A B C D E

ZZZ ZZZ1 ZZZ2 ZZZ3

1 1

PCB LA-5081P LS-5081P LS-5082P

DAZ@ DAZ@ DAZ@

2 KIWA5/A6 2

Schematics Document
Mobile Penryn uFCPGA with Intel
3

Cantiga_GM/PM+ICH9-M core logic 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWAX_LA-5081P
Date: Tuesday, April 28, 2009 Sheet 1 of 51
A B C D E
 A B C D E

ZZZ
Compal confidential
File Name : POWER Board CAP SENSE LEDs Board
PCB KIWA5 LA-5081P LS-5081P/5082P

VRAM
1 64*16 Mobile Penryn 1

DDRII uFCPGA-478 CPU

page20,21
PCI-E X16 Clock Gen.
NV10M-GS page5,6,7 SLG8SP556VTR
ICS9LPRS387AKLFT
40nmpage16,17,18,19 H_A#(3..35)
FSB
page22

H_D#(0..63) 667/800/1066MHz

HDMI Parade 8101T PCI-E DDR3 -800

CONN ASM 1442T DDR3-SO-DIMM X2
page23
page23
Intel Cantiga GMCH DDR3-1066 BANK 0, 1, 2, 3 page 14,15

CRT & TV OUT PCBGA 1329 Dual Channel

LVDS I/F
page25
page 8,9,10,11,12,13
2 2
LVDS
Connector page24 DMI C-Line
AMP&Audio Jack
AZALIA page35

PCI Express 6*PCI-E BUS 12*USB2.0

Mini card Slotpage30
1 Intel ICH9-M Audio Codec
mBGA-676 CX20561
page34

New Card USB 2.0 BUS

4*SATA serial Key component
page30 page27,28,29,30 Manufacturer
Compal P/N
R1 Desc
BCM5906 Card Reader CMOS Camera Northbridge
10/100/LAN Intel / Cantiga PM45
page31 RTS 5159 LPC BUS page39 SA00002JJM0
page37
S IC AC82PM45 QV11 A1 FCBGA 1329 PM C38
3 3
BlueTooth Conn Intel / Cantiga GM 45
page39 SA00002JTD0
EC S IC AC82GM45 SLB94 B3 FCBGA1329 GM C38!

RJ45 CONN Card reader(XD/SD USB conn X3

page32 MMC/MS/MS-Pro ENE KB926 page39
SouthBridge
Intel / ICH9M
page36 SA00002JH90
HD SD) page37 S IC AF82801IBM SLB8Q A3 676P ICH9M C38! (MP)

VGA Chip
Nvidia / N10M
Int.KBD SA00002V810
page38
S IC N10M-GE1-S-U2(H) BGA 533P C38
SATA HDD
BIOS page39
Connector page33 VRAM
Touch Pad DDR2/512MB
SA00002MF00 (14")
page39 S IC D2 64M16/500 HYB18T1G161C2F-20
SATA CDROM
Connector page33 SA00002UH00 (15.6")
S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 2 of 51
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 A B C D E

DDR3 Voltage Rails

power
plane

+5VALW +1.5V +5VS

B+ +3VS
1 1
+3VALW +1.5VS
+0.75VS
State +VCCP
+CPU_CORE
+VGA_CORE
+1.8VS

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
2 2
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
SMBUS, SPI and I2C Control Table

SERIAL NEW CLK CAP Mini Mini THERMAL THERMAL

SOURCE HDMI LVDS CRT HDCP EEPROM BATT SENSOR SENSOR
CARD GEN sensor CARD1 CARD2 (VGA) (CPU)

EC_SMB_CK1
EC_SMB_DA1
KB926 X X X X X X X X X X V X X
EC_SMB_CK2
EC_SMB_DA2
KB926 X X X X X X X V X X X V V
ICH_SMBCLK
ICH_SMBDAT ICH9 X X X X X V V X V V X X X
LVDS_SCL
3
LVDS_SDA Cantiga
X V X X X X X X X X X X X 3

GMCH_CRT_CLK
GMCH_CRT_DAT Cantiga
X X V X X X X X X X X X X
HDMICLK_NB
HDMIDAT_NB Cantiga
V X X X X X X X X X X X X
VGA_DDCCLK
VGA_DDCDATA N10M X X V X X X X X X X X X X
VGA_LVDS_SCL
VGA_LVDS_DAT N10M X V X X X X X X X X X X X
VGA_HDMI_SCL
VGA_HDMI_DAT
(55nm) N10M
V X X X X X X X X X X X X
HDCP_SMB_CK1
HDCP_SMB_DA1 N10M X X X V X X X X X X X X X
IFPC_AUX
IFPC_AUX_N
(40nm)
N10M V X X X X X X X X X X X X
4 4

FSEL#SPICS#
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI
KB926 X X X X V X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 3 of 51
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 A B C D E

VGA and DDR2 Voltage Rails (N10M) EDP at Tj = 97C*

Power Supply Rail NB10M-GS N10M-GE1-S
(V) GDDR3 DDR2 GDDR3 DDR2
NVVDD Variable 11.22A 10.87A 13.56A 13.47A
FB_DLLAVDD 1.1 25mA 25mA
power FB_PLLAVDD 1.1 10mA 10mA
plane +3VS IFPC_IOVDD 1.1 385mA 180mA
1 1

+VGA_CORE IFPD_IOVDD 1.1 385mA 180mA

+1.1VS IFPE_IOVDD 1.1 385mA 180mA
+1.8VS IFPF_IOVDD 1.1 385mA 180mA
PEX_IOVDD/Q 1.1 1550mA 1550mA
PEX_PLLVDD 1.1 165mA 65mA
State
PLLVDD 1.1 55mA 30mA
SP_PLLVDD 1.1 25mA 10mA
VID_PLLVDD 1.1 50mA 25mA
TOTAL 1.1 3.425A 2.435A

FBVDD/Q 1.8 2.24A 1.65A 2.24A 1.75A

S0 IFPA_IOVDD 1.8 50mA 50mA
O
IFPB_IOVDD 1.8 50mA 50mA
S1 IFPAB_PLLVDD 1.8 100mA 75mA
O
IFPCD_PLLVDD 1.8 160mA 80mA
S3 IFPEF_PLLVDD 1.8 160mA 80mA
2
X TOTAL 1.8 2.76A 2.17A 2.575A 2.085A 2

S5 S4/AC
X DACA_VDD 3.3 110mA 110mA
DACB_VDD 3.3 125mA 125mA
S5 S4/ Battery only
X DACC_VDD 3.3 110mA 110mA
MIOA_VDDQ 3.3 10mA 10mA
S5 S4/AC & Battery
don't exist X MIOB_VDDQ 3.3 10mA 10mA
VDD33 3.3 80mA 80mA
TOTAL 3.3 0.445A 0.445A

POWER SQUENCE
The ramp time for any rail must be more than 40us

3 3

(+3VS) VDD33

PEX_VDD can ramp up any time

(1.1VS) PEX_VDD
tNVVDD>=0

(+VGA_CORE) NVVDD
tNV-FB

tFBVDDQ>=0

4
(1.8VS) FBVDDQ 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 4 of 51
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 5 4 3 2 1

XDP Reserve +3VS

XDP_DBRESET# 1 2 @ 1K_0402_5%
R43
+VCCP

XDP_TDI R11 1 2 54.9_0402_1%

D XDP_TMS R14 1 2 54.9_0402_1% D

CONN@ +VCCP XDP_TDO R12 1 2 54.9_0402_1%

(8) H_A#[3..16]
JCPUA
H_A#3 J4 H1 H_ADS# @
A[3]# ADS# H_ADS# (8)

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# (8)
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# (8)

1
H_A#6 K5 R83
H_A#7 A[6]# H_DEFER# 56_0402_5%
M3 A[7]# DEFER# H5 H_DEFER# (8)
H_A#8 N2 F21 H_DRDY# XDP_TRST# R16 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# (8)
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# (8)
H_A#10 N3 XDP_TCK R15 1 2 54.9_0402_1%

2
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# (8)
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# (27)
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# (8)
H_ADSTB#0
(8) H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET#
EMC1402 SA00001Z700
RESET# H_RESET# (8)
(8) H_REQ#0
H_REQ#0
H_REQ#1
K3 REQ[0]# RS[0]# F3 H_RS#0
H_RS#1
H_RS#0 (8) +3VS
ADT7421ARMZ SA00001UN00
(8) H_REQ#1 H2 REQ[1]# RS[1]# F4 H_RS#1 (8)
H_REQ#2 K2 G3 H_RS#2 +3VS
(8) H_REQ#2 REQ[2]# RS[2]# H_RS#2 (8)
H_REQ#3 J3 G2 H_TRDY#
(8) H_REQ#3 REQ[3]# TRDY# H_TRDY# (8)

2
H_REQ#4 L1
(8) H_REQ#4 REQ[4]#
G6 H_HIT# 1 R95

0.1U_0402_16V4Z
(8) H_A#[17..35] HIT# H_HIT# (8)
H_A#17 Y2 E4 H_HITM# 10K_0402_5%
A[17]# HITM# H_HITM# (8) C89
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0 U5
R3 AD4

1
A[19]# BPM[0]# 2
ADDR GROUP_1

C H_A#20 W6 AD3 XDP_BPM#1 C

H_A#21 A[20]# BPM[1]# XDP_BPM#2
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3 1 8 EC_SMB_CK2 EC_SMB_CK2 (16,36)
H_A#23 A[22]# BPM[3]# XDP_BPM#4 VDD SMCLK
U1 AC2
XDP/ITP SIGNALS

H_A#24 A[23]# PRDY# XDP_BPM#5 H_THERMDA EC_SMB_DA2

R4 A[24]# PREQ# AC1 2 DP SMDATA 7 EC_SMB_DA2 (16,36)
H_A#25 T5 AC5 XDP_TCK C95
H_A#26 A[25]# TCK XDP_TDI H_THERMDC
T3 A[26]# TDI AA6 1 2 3 DN ALERT# 6
H_A#27 W2 AB3 XDP_TDO 2200P_0402_50V7K
A[27]# TDO
H_A#28 W5 AB5 XDP_TMS 2200p change to THERM# 4 5
H_A#29 A[28]# TMS XDP_TRST# THERM# GND
Y4 A[29]# TRST# AB6 1000p for ADT7421
H_A#30 U2 C20 XDP_DBRESET# R94
A[30]# DBR# XDP_DBRESET# (28)
H_A#31 V4 +3VS 1 2
H_A#32 A[31]# 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
W3 A[32]# 2 1 +VCCP
H_A#33 AA4 A[33]# THERMAL R84 68_0402_5% Address:100_1100
H_A#34 AB2 H_PROCHOT#
A[34]# H_PROCHOT#
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
(8) H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
(27) H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
(27) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (8,27)
H_IGNNE# C4
(27) H_IGNNE# IGNNE#
H_STPCLK# D5
G990 SA00002GW00
(27) H_STPCLK# STPCLK#
H_INTR C6 H CLK APL5605 SA00001Z900
(27)
(27)
H_INTR
H_NMI
H_NMI
H_SMI#
B4
A3
LINT0
LINT1 BCLK[0] A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK (22)
RT9027 SA000022J00
FAN1 Conn
(27) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (22)
M4 +5VS +5VS
RSVD[01] C594 10U_0805_10V4Z
B
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, B
T2 RSVD[03] 1 2
Trace width / Spacing = 10 / 10 mil

1
V3 RSVD[04]
B2 D17
RESERVED

RSVD[05] U24 @ 1SS355TE-17_SOD323-2

RSVD pins on the CPU D2 RSVD[06] FAN solution RC (R=1Kohm,C=0.1uF)
should be left as NO D22 RSVD[07] 1 VEN GND 8
D3 2 7 D16

2
CONNECT RSVD[08] +VCC_FAN1 VIN GND @ BAS16_SOT23-3
F6 RSVD[09] 3 VO GND 6
EN_FAN1 1 2 EN_FAN1_R 4 5 1 2
(36) EN_FAN1 VSET GND
R667 G990P11U_SO8
1K_0402_5% 1 C595
Penryn <BOM Structure> 1U_0603_10V4Z
C810 1 2
0.1U_0402_16V4Z
2 +3VS C597
0.1U_0402_16V4Z
1 2

1
R469
10K_0402_5%
40mil JP13

2
+VCC_FAN1 1 1
(36) FAN_SPEED1 2 2
3 3
1
C596 4
1000P_0402_50V7K GND
5 GND
A 2 A
E&T_3801-F03N-01R

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 5 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
CONN@
JCPUC
(8) H_D#[0..15] CONN@ A7 AB20
H_D#[32..47] (8) VCC[001] VCC[068]
JCPUB A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]

DATA GRP 2
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
H_DSTBN#0 J26 Y26 H_DSTBN#2 C9 AE10
(8) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (8) VCC[019] VCC[086]
H_DSTBP#0 H26 AA26 H_DSTBP#2 C10 AE12
(8) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (8) VCC[020] VCC[087]
H_DINV#0 H25 U22 H_DINV#2 C12 AE13
(8) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (8) VCC[021] VCC[088]
(8) H_D#[16..31] H_D#[48..63] (8) C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
D[21]# D[53]# VCC[029] VCC[096]

DATA GRP 3
H_D#22 L22 AD20 H_D#54 D15 AF15
D[22]# D[54]# VCC[030] VCC[097]
H_D#23 M23 D[23]# D[55]# AE22 H_D#55 D17 VCC[031] VCC[098] AF17 For testing purpose only
H_D#24 P25 AF23 H_D#56 D18 AF18
C H_D#25 D[24]# D[56]# H_D#57 VCC[032] VCC[099] +VCCP C
P23 D[25]# D[57]# AC25 E7 VCC[033] VCC[100] AF20
H_D#26 P22 AE21 H_D#58 E9 R47 0_0402_5%
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 2 1
H_D#28 R24 AC22 H_D#60 E12 V6 2 1
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02] R8 0_0402_5%
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6
H_D#30 T25 AF22 H_D#62 E15 K6
H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E18 J21
(8) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (8) VCC[040] VCCP[06]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E20 K21
(8) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (8) VCC[041] VCCP[07]
H_DINV#1 N24 AC20 H_DINV#3 F7 M21
(8) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (8) VCC[042] VCCP[08]
F9 VCC[043] VCCP[09] N21
+CPU_GTLREF AD26 R26 COMP0 R63 1 2 27.4_0402_1% F10 N6
R45 GTLREF COMP[0] VCC[044] VCCP[10]
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R64 1 2 54.9_0402_1% F12 VCC[045] VCCP[11] R21
R46 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R10 1 2 27.4_0402_1% F14 R6
T16 TEST3 TEST2 COMP[2] COMP3 R9 1 54.9_0402_1% VCC[046] VCCP[12]
C24 TEST3 COMP[3] Y1 2 F15 VCC[047] VCCP[13] T21
T15 TEST4 AF26 TEST4 F17 VCC[048] VCCP[14] T6 Near pin B26
T14 TEST5 AF1 E5 H_DPRSTP#_R F18 V21
T17 TEST6 TEST5 DPRSTP# H_DPSLP# VCC[049] VCCP[15]
A26 TEST6 DPSLP# B5 H_DPSLP# (27) F20 VCC[050] VCCP[16] W21
T10 TEST7 C3 D24 H_DPW R# AA7 20mils
TEST7 DPWR# H_DPW R# (8) VCC[051]
CPU_BSEL0 B22 D6 H_PW RGOOD AA9 B26
(22) CPU_BSEL0 BSEL[0] PWRGOOD H_PW RGOOD (27) VCC[052] VCCA[01] +1.5VS
Trace Close CPU < 0.5' CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26

0.01U_0402_16V7K
(22) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (8) VCC[053] VCCA[02]
CPU_BSEL2 C21 AE6 H_PSI# AA12

10U_0805_10V4Z
(22) CPU_BSEL2 BSEL[2] PSI# H_PSI# (49) VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 (49)
Penryn AA15 AF5 1 1
VCC[056] VID[1] CPU_VID1 (49)
Width=4 mil , AA17 VCC[057] VID[2] AE5 CPU_VID2 (49)

C599

C598
R1089 0_0402_5% AA18 AF4
Spacing: 15mil VCC[058] VID[3] CPU_VID3 (49)
H_DPRSTP#_R 2 1 H_DPRSTP# AA20 AE3
(8) H_DPRSTP#_R H_DPRSTP# (27,49) VCC[059] VID[4] CPU_VID4 (49) 2 2
(55Ohm) AB9 AF3
0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

VCC[060] VID[5] CPU_VID5 (49)

B
1 TRACE CLOSELY CPU < 0.5' AC10 VCC[061] VID[6] AE2 CPU_VID6 (49) B
AB10 VCC[062]
1CPU_BSEL0 1CPU_BSEL1 1CPU_BSEL2 C1162 COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB12 VCC[063]
68P_0402_50V8J AB14 AF7 VCCSENSE
2 COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) VCC[064] VCCSENSE VCCSENSE (49)
C1163

C1164

C1165

AB15 VCC[065]
AB17 VCC[066]
2 2 2 @ VSSSENSE
@ @ @
3/17 change to 68P AB18 VCC[067] VSSSENSE AE7 VSSSENSE (49)
Penryn
.
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+VCCP
FSB BCLK BSEL2 BSEL1 BSEL0 Length match within 25 mils. +CPU_CORE
1

The trace width/space/other is R23

100_0402_1%
533 133 0 0 1
R471 16/7/25. 1 2 VCCSENSE
1K_0402_1%
667 166 0 1 1 R24
2

Layout note: Z0=55 ohm +CPU_GTLREF 100_0402_1%

1 2 VSSSENSE
0.5" max for GTLREF.
800 200 0 1 0 Layout Note:
1

Route VCCSENSE and VSSSENSE traces at

R470 1067 266 0 0 0 27.4 Ohms with 50 mil spacing.
2K_0402_1%
Place PU and PD within 1 inch of CPU.
2

Length matched to within 25 mils.

A Close to CPU pin A

within 500mils.
Close to CPU pin AD26
within 500mils.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

CONN@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
+CPU_CORE
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
D AF2 VSS[008] VSS[089] T1 1 1 1 1 1 1 1 1 D
B6 VSS[009] VSS[090] T4
B8 T23 Place these capacitors on L8 C13 C39 C36 C30 C27 C19 C14 C12
VSS[010] VSS[091] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B11 VSS[011] VSS[092] T26
2 2 2 2 2 2 2 2
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
+CPU_CORE
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25 1 1 1 1 1 1 1 1
C14 VSS[020] VSS[101] W1
C16 W4 Place these capacitors on L8 C28 C24 C40 C37 C31 C26 C20 C15
VSS[021] VSS[102] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C19 VSS[022] VSS[103] W23
2 2 2 2 2 2 2 2
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
+CPU_CORE
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
D13 VSS[030] VSS[111] AA8 1 1 1 1 1 1 1 1
D16 VSS[031] VSS[112] AA11
D19 AA14 Place these capacitors on L8 C583 C585 C586 C589 C591 C593 C582 C584
VSS[032] VSS[113] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D23 VSS[033] VSS[114] AA16
2 2 2 2 2 2 2 2
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
C E8 AB1 C
VSS[037] VSS[118] +CPU_CORE
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13 1 1 1 1 1 1 1 1
E21 VSS[042] VSS[123] AB16
E24 AB19 Place these capacitors on L8 C588 C587 C590 C592 C35 C29 C25 C33
VSS[043] VSS[124] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
F5 VSS[044] VSS[125] AB23
2 2 2 2 2 2 2 2
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2
F22
VSS[050] VSS[131] AC14
AC16
Mid Frequence Decoupling
VSS[051] VSS[132]
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
+CPU_CORE
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 AD19

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
VSS[061] VSS[142]
J5 AD22
J22
J25
VSS[062]
VSS[063]
VSS[143]
VSS[144] AD25
AE1
1 1 1 @ 1 ESR <= 1.5m ohm
VSS[064] VSS[145] + + + +
Capacitor > 1980uF

C47

C17

C16
K1 VSS[065] VSS[146] AE4 North Side Secondary
B B

C41
K4 VSS[066] VSS[147] AE8 South Side Secondary
K23 VSS[067] VSS[148] AE11
2 2 2 2
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 AF21 Delete "REMOVE?" 0113 +VCCP
VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
VSS[163] AF25
1
Penryn 1 1 1 1 1 1
. C8 + Place these inside
C11 C10 C51 C50 C48 C9 socket cavity on L8
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 7 of 51
5 4 3 2 1
 5 4 3 2 1

U26B
(6) H_D#[0..63] H_A#[3..35] (5)
U26A T69 M36 AP24 M_CLK_DDR0 M_CLK_DDR0 (14)
H_A#3 RSVD1 SA_CK_0 M_CLK_DDR1
A14 T70 N36 AT21 M_CLK_DDR1 (14)
H_D#0 H_A#_3 H_A#4 RSVD2 SA_CK_1 M_CLK_DDR2
F2 C15 T58 R33 AV24 M_CLK_DDR2 (15)
H_D#1 H_D#_0 H_A#_4 H_A#5 +1.5V RSVD3 SB_CK_0 M_CLK_DDR3
G8 F16 T33 AU20 M_CLK_DDR3 (15)

0.01U_0402_16V7K
T66

2.2U_0603_6.3V4Z
H_D#_1 H_A#_5 RSVD4 SB_CK_1

COMPENSATION
H_D#2 F8 H13 H_A#6 T23 AH9
H_D#3 H_D#_2 H_A#_6 H_A#7 RSVD5 M_CLK_DDR#0
E6 C18 2 2 T25 AH10 AR24 M_CLK_DDR#0 (14)
H_D#_3 H_A#_7 RSVD6 SA_CK#_0

1
H_D#4 G2 M16 H_A#8 T27 AH12 AR21 M_CLK_DDR#1
H_D#_4 H_A#_8 RSVD7 SA_CK#_1 M_CLK_DDR#1 (14)
H_D#5 H_A#9 R126 M_CLK_DDR#2

C641
H6 J13 T30 AH13 AU24 M_CLK_DDR#2 (15)
H_D#_5 H_A#_9 RSVD8 SB_CK#_0

C640
H_D#6 H2 P16 H_A#10 T26 K12 AV20 M_CLK_DDR#3
H_D#_6 H_A#_10 1 1 RSVD9 SB_CK#_1 M_CLK_DDR#3 (15)
H_D#7 F6 R16 H_A#11 1K_0402_1% T62 AL34
H_D#8 H_D#_7 H_A#_11 H_A#12 RSVD10 DDR_CKE0_DIMMA +1.5V
D4 N17 T61 AK34 BC28 DDR_CKE0_DIMMA (14)

2
H_D#9 H_D#_8 H_A#_12 H_A#13 SMRCOMP_VOH RSVD11 SA_CKE_0 DDR_CKE1_DIMMA
H3 M13 T67 AN35 AY28 DDR_CKE1_DIMMA (14)
H_D#10 H_D#_9 H_A#_13 H_A#14 RSVD12 SA_CKE_1 DDR_CKE2_DIMMB
M9 E17 T68 AM35 AY36 DDR_CKE2_DIMMB (15)
H_D#_10 H_A#_14 RSVD13 SB_CKE_0

1
H_D#11 M11 P17 H_A#15 T44 T24 BB36 DDR_CKE3_DIMMB
H_D#_11 H_A#_15 RSVD14 SB_CKE_1 DDR_CKE3_DIMMB (15)
H_D#12 J1 F17 H_A#16 R501
H_D#13 H_D#_12 H_A#_16 H_A#17 3.01K_0402_1% DDR_CS0_DIMMA#
J2 G20 BA17 DDR_CS0_DIMMA# (14)
H_D#_13 H_A#_17 SA_CS#_0

2
D D
H_D#14 N12 B19 H_A#18 NA lead free AY16 DDR_CS1_DIMMA#
H_D#_14 H_A#_18 SA_CS#_1 DDR_CS1_DIMMA# (14)
H_D#15 J6 J16 H_A#19 T56 B31 AV16 DDR_CS2_DIMMB# R125
DDR_CS2_DIMMB# (15)

2
H_D#16 H_D#_15 H_A#_19 H_A#20 SMRCOMP_VOL RSVD15 SB_CS#_0 DDR_CS3_DIMMB#
P2 E20 T84 B2 AR13 DDR_CS3_DIMMB# (15) 80.6_0402_1%
H_D#_16 H_A#_20 RSVD16 SB_CS#_1

DDR CLK/ CONTROL/

H_D#17 L2 H16 H_A#21 T83 M1
H_D#_17 H_A#_21 RSVD17

RSVD
H_D#18 R2 J20 H_A#22 BD17 M_ODT0 M_ODT0 (14)

0.01U_0402_16V7K

1
2.2U_0603_6.3V4Z
H_D#19 H_D#_18 H_A#_22 H_A#23 R500 SA_ODT_0 M_ODT1
N9 L17 1 1 AY17 M_ODT1 (14)
H_D#20 H_D#_19 H_A#_23 H_A#24 SA_ODT_1 M_ODT2
L6 A17 T40 AY21 BF15 M_ODT2 (15)
H_D#21 H_D#_20 H_A#_24 H_A#25 1K_0402_1% RSVD20 SB_ODT_O M_ODT3

C635
H_D#22
M5
H_D#_21 H_A#_25
B17
H_A#26 SB_ODT_1
AY13 M_ODT3 (15) 20mil

C636
J3 L16

2
H_D#23 H_D#_22 H_A#_26 H_A#27 2 2 SMRCOMP
N2
H_D#_23 H_A#_27
C21
SM_RCOMP
BG22 For Crestline: 20ohm
H_D#24 R1 J17 H_A#28 T87 BG23 BH21 SMRCOMP# R497 1 2 80.6_0402_1% For Calero: 80.6ohm
H_D#25 H_D#_24 H_A#_28 H_A#29 RSVD22 SM_RCOMP#
N5
H_D#_25 H_A#_29
H20 T88 BF23
RSVD23 For Cantiga: 80.6ohm
H_D#26 N6 B18 H_A#30 T34 BH18 BF28 SMRCOMP_VOH
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD24 SM_RCOMP_VOH SMRCOMP_VOL R483 1
P13 K17 T35 BF18 BH28 2 0_0402_5% 1.5V_PGOOD (47)
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD25 SM_RCOMP_VOL
N8 B20
H_D#29 H_D#_28 H_A#_32 H_A#33 +DDR_MCH_REF
L7
H_D#_29 H_A#_33
F21
SM_VREF
AV42 Delete "DDR3_SM_PWROK" 0113
H_D#30 N10 K21 H_A#34 AR36 SM_PWROK R148 1 @ 2 10K_0402_5%
H_D#31 H_D#_30 H_A#_34 H_A#35 SM_PWROK SM_REXT
M3 L20 BF17 1 2
H_D#32 H_D#_31 H_A#_35 SM_REXT TP_SM_DRAMRST# R111
Y3 BC36 SM_DRAMRST# (14,15)
H_D#33 H_D#_32 H_ADS# SM_DRAMRST# 499_0402_1%
AD14 H12 H_ADS# (5)
H_D#34 H_D#_33 H_ADS# H_ADSTB#0
H_D#35
Y6
H_D#_34 H_ADSTB#_0
B16
H_ADSTB#1
H_ADSTB#0 (5)
CLK_MCH_DREFCLK
DDR3
Y10 G17 H_ADSTB#1 (5) B38 CLK_MCH_DREFCLK (22)
H_D#36 H_D#_35 H_ADSTB#_1 H_BNR# DPLL_REF_CLK CLK_MCH_DREFCLK#
Y12 A9 H_BNR# (5) A38 CLK_MCH_DREFCLK# (22)
H_D#_36 H_BNR# DPLL_REF_CLK#
HOST

H_D#37 Y14 F11 H_BPRI# E41 MCH_SSCDREFCLK

H_D#_37 H_BPRI# H_BPRI# (5) DPLL_REF_SSCLK MCH_SSCDREFCLK (22)
H_D#38 Y7 G12 H_BR0# F41 MCH_SSCDREFCLK#
H_D#_38 H_BREQ# H_BR0# (5) DPLL_REF_SSCLK# MCH_SSCDREFCLK# (22)
H_D#39 H_DEFER#

CLK
W2 E9 H_DEFER# (5)
H_D#40 H_D#_39 H_DEFER# H_DBSY# CLK_MCH_3GPLL
AA8 B10 H_DBSY# (5) F43 CLK_MCH_3GPLL (22)
H_D#41 H_D#_40 H_DBSY# CLK_MCH_BCLK PEG_CLK CLK_MCH_3GPLL#
Y9 AH7 CLK_MCH_BCLK (22) E43 CLK_MCH_3GPLL# (22)
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# PEG_CLK#
AA13 AH6 CLK_MCH_BCLK# (22)
H_D#43 H_D#_42 HPLL_CLK# H_DPWR#
AA9 J11 H_DPWR# (6)
H_D#44 H_D#_43 H_DPWR# H_DRDY#
AA11 F9 H_DRDY# (5)
H_D#45 H_D#_44 H_DRDY# H_HIT# DMI_TXN0
AD11 H9 H_HIT# (5) AE41 DMI_TXN0 (28)
H_D#46 H_D#_45 H_HIT# H_HITM# DMI_RXN_0 DMI_TXN1
AD10 E12 H_HITM# (5) AE37 DMI_TXN1 (28)
H_D#47 H_D#_46 H_HITM# H_LOCK# DMI_RXN_1 DMI_TXN2
AD13 H11 H_LOCK# (5) AE47 DMI_TXN2 (28)
H_D#48 H_D#_47 H_LOCK# H_TRDY# DMI_RXN_2 DMI_TXN3
AE12 C9 H_TRDY# (5) AH39 DMI_TXN3 (28)
H_D#49 H_D#_48 H_TRDY# DMI_RXN_3
AE9
H_D#50 H_D#_49 DMI_TXP0
AA2 AE40 DMI_TXP0 (28)
H_D#51 H_D#_50 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
C AD8 (22) MCH_CLKSEL0 T25 AE38 DMI_TXP1 (28)
C
H_D#52 H_D#_51 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AA3 (22) MCH_CLKSEL1 R25 AE48 DMI_TXP2 (28)
H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
AD3 J8 H_DINV#0 (6) (22) MCH_CLKSEL2 P25 AH40 DMI_TXP3 (28)
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 CFG_2 DMI_RXP_3
AD7 L3 H_DINV#1 (6) P20
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 CFG_3 DMI_RXN0
AE14 Y13 H_DINV#2 (6) P24 AE35 DMI_RXN0 (28)
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1

DMI
AF3 Y1 H_DINV#3 (6) CFG5 C25 AE43 DMI_RXN1 (28)
H_D#57 H_D#_56 H_DINV#_3 CFG6 CFG_5 DMI_TXN_1 DMI_RXN2
AC1 T48 N24 AE46 DMI_RXN2 (28)
H_D#58 H_D#_57 H_DSTBN#0 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3
AE3 L10 H_DSTBN#0 (6) T47 M24 AH42 DMI_RXN3 (28)
H_D#_58 H_DSTBN#_0 CFG_7 DMI_TXN_3

CFG
H_D#59 AC3 M7 H_DSTBN#1 T45 CFG8 E21
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (6) CFG_8
H_D#60 AE11 AA5 H_DSTBN#2 T41 CFG9 C23 AD35 DMI_RXP0
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (6) CFG_9 DMI_TXP_0 DMI_RXP0 (28)
H_D#61 AE8 AE6 H_DSTBN#3 T50 CFG10 C24 AE44 DMI_RXP1
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (6) CFG_10 DMI_TXP_1 DMI_RXP1 (28)
H_D#62 AG2 T49 CFG11 N21 AF46 DMI_RXP2
H_D#_62 CFG_11 DMI_TXP_2 DMI_RXP2 (28)
H_D#63 AD6 L9 H_DSTBP#0 T39 CFG12 P21 AH43 DMI_RXP3
H_D#_63 H_DSTBP#_0 H_DSTBP#0 (6) CFG_12 DMI_TXP_3 DMI_RXP3 (28)
M8 H_DSTBP#1 T43 CFG13 T21
H_DSTBP#_1 H_DSTBP#1 (6) CFG_13
AA6 H_DSTBP#2 +3VS T38 CFG14 R20
H_DSTBP#_2 H_DSTBP#2 (6) CFG_14
H_SWNG C5 AE5 H_DSTBP#3 T37 CFG15 M20
H_SWING H_DSTBP#_3 H_DSTBP#3 (6) CFG_15
H_RCOMP E3 T46 CFG16 L21
H_RCOMP H_REQ#0 CFG17 CFG_16
B15 H_REQ#0 (5) T42 H21
H_REQ#_0 CFG_17
1

K13 H_REQ#1 CFG18 P29

GRAPHICS VID
H_REQ#_1 H_REQ#1 (5) T55 CFG_18
F13 H_REQ#2 R206 R217 T53 CFG19 R28
H_REQ#_2 H_REQ#2 (5) CFG_19
B13 H_REQ#3 10K_0402_5% 10K_0402_5% T54 CFG20 T28 B33
H_REQ#_3 H_REQ#3 (5) CFG_20 GFX_VID_0
(5) H_RESET# H_RESET# C12 B14 H_REQ#4 B32 T90 PAD MCH_HDA_BCLK
H_CPURST# H_REQ#_4 H_REQ#4 (5) GFX_VID_1
(6) H_CPUSLP# H_CPUSLP# E11 G33 T89 PAD connect to power CPU_CORE
2

H_CPUSLP# H_RS#0 PM_EXTTS#0 GFX_VID_2 T65 PAD

B6 H_RS#0 (5) F33 1
H_RS#_0 H_RS#1 PM_BMBUSY# GFX_VID_3 T64 PAD
F12 H_RS#1 (5) (28) PM_BMBUSY# R29 E33
H_VREF H_RS#_1 H_RS#2 PM_EXTTS#1 H_DPRSTP#_R PM_SYNC# GFX_VID_4 T63 PAD C646
A11 C8 H_RS#2 (5) (6) H_DPRSTP#_R B7
H_AVREF H_RS#_2 PM_EXTTS#0 PM_DPRSTP# 10P_0402_50V8J
B11 (14,15) PM_EXTTS#0 N33
H_DVREF PM_EXT_TS#_0 2

PM
PM_EXTTS#1 P32 @
PM_EXTTS#1 PM_EXT_TS#_1
GM45@ CANTIGA ES_FCBGA1329 PM_POK_R AT40 C34 T91
PLT_RST#_R PWROK GFX_VR_EN
AT11
H_THERMTRIP# RSTIN# +VCCP
(5,27) H_THERMTRIP# T20
DPRSLPVR THERMTRIP#
(28,49) DPRSLPVR R32
DPRSLPVR
layout note: For AMT function

1
Route H_SCOMP and H_SCOMP# with trace width BG48 AH37 CL_CLK0 CL_CLK0 (28) R143
NC_1 CL_CLK CL_DATA0
spacing and impedance (55 ohm) same as FSB data traces BF48
NC_2 CL_DATA
AH36 CL_DATA0 (28)

ME
BD48 AN36 1K_0402_1%
NC_3 CL_PWROK M_PWROK (28)
2 1 PM_POK_R BC48 AJ35 CL_RST#
(28,36) ICH_POK CL_RST# (28)

2
B
R177 0_0402_5% NC_4 CL_RST# CL_VREF B
BH47 AH34
0309 add NC_5 CL_VREF
Layout Note: (28,49) VGATE 2 1 BG47
NC_6
R178 @ 0_0402_5% BE47 0.1U_0402_16V4Z 1
H_RCOMP / H_VREF / H_SWNG 1 2 PLT_RST#_R BH46
NC_7
N28 T52 R147
(16,26,30,31) PLT_RST# NC_8 DDPC_CTRLCLK

NC
trace width and spacing is 10/20 R103 100_0402_5% BF46 M28 T51 C238 499_0402_1%
NC_9 DDPC_CTRLDATA HDMICLK_NB
BG45 G36 HDMICLK_NB (23)
NC_10 SDVO_CTRLCLK HDMIDAT_NB 2
BH44 E36 HDMIDAT_NB (23)
NC_11 SDVO_CTRLDATA MCH_CLKREQ#
BH43 K36 MCH_CLKREQ# (22)
NC_12 CLKREQ#

MISC
BH6 H36 MCH_ICH_SYNC#
+VCCP NC_13 ICH_SYNC# MCH_ICH_SYNC# (28)
BH5
+VCCP NC_14
BG4 TSATN# (36)
NC_15
BH3 B12 1 2 +VCCP
NC_16 TSATN#
Layout Note: BF3
1K_0402_1%

221_0603_1%

NC_17 R105 56_0402_5%

1

V_DDR_MCH_REF BH2
+1.5V NC_18
R482

BG2
trace width and NC_19 MCH_HDA_BCLK R80 GM_HDMI@ 33_0402_5%
R493

BE2 B28 1 2 HDA_BITCLK_CODEC (16,27,34)

NC_20 HDA_BCLK
spacing is 20/20. BG1
NC_21 HDA_RST#
B30 MCH_HDA_RST# R82 GM_HDMI@ 1 2 0_0402_5% HDA_RST_CODEC# (16,27,34)
1

0.1U_0402_16V4Z BF1 B29 MCH_HDA_SDIN R79 GM_HDMI@ 1 2 33_0402_5%

HDA_SDIN0 (27)
2

H_VREF H_RCOMP H_SWNG R185 NC_22 HDA_SDI MCH_HDA_SDOUT R85 GM_HDMI@ 0_0402_5%
BD1 C29 1 2 HDA_SDOUT_CODEC (16,27,34)
NC_23 HDA_SDO MCH_HDA_SYNC R81 GM_HDMI@ 0_0402_5%
BC1 A28 1 2

HDA
10K_0402_5% NC_24 HDA_SYNC HDA_SYNC_CODEC (16,27,34)
F1
24.9_0402_1%

0.1U_0402_16V4Z

NC_25
1

A47 0113
2K_0402_1%

100_0402_1%

1 1
2

+DDR_MCH_REF NC_26
+DDR_MCH_REF
R89

GM45@ CANTIGA ES_FCBGA1329

R488

C623

R484

C616

Notice: Please check HDA power rail to select HDA controller.

0.1U_0402_16V4Z

2 2 R162
1
2

10K_0402_5%
C273

2
within 100 mils from NB Near B3 pin

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/6)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

D D

(14) DDR_A_D[0..63] (15) DDR_B_D[0..63]

U26D U26E
DDR_A_D0 AJ38 BD21 DDR_A_BS#0 DDR_B_D0 AK47 BC16 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 (14) SB_DQ_0 SB_BS_0 DDR_B_BS#0 (15)
DDR_A_D1 AJ41 BG18 DDR_A_BS#1 DDR_B_D1 AH46 BB17 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 (14) SB_DQ_1 SB_BS_1 DDR_B_BS#1 (15)
DDR_A_D2 AN38 AT25 DDR_A_BS#2 DDR_B_D2 AP47 BB33 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 (14) SB_DQ_2 SB_BS_2 DDR_B_BS#2 (15)
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# (14) AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# (14) SB_DQ_5 SB_RAS# DDR_B_RAS# (15)
DDR_A_D6 AM44 AY20 DDR_A_W E# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_W E# (14) SB_DQ_6 SB_CAS# DDR_B_CAS# (15)
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_W E#
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_W E# (15)
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
SA_DQ_12 DDR_A_DM[0..7] (14) SB_DQ_12
DDR_A_D13 AN39 AM37 DDR_A_DM0 DDR_B_D13 AR47
DDR_A_D14 SA_DQ_13 SA_DM_0 DDR_A_DM1 DDR_B_D14 SB_DQ_13
AU44 SA_DQ_14 SA_DM_1 AT41 BA47 SB_DQ_14 DDR_B_DM[0..7] (15)
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
C DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4 C
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] (14) SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] (15)
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0

MEMORY
DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48

DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 DDR_A_DQS#[0..7] (14) BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D34 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 BH11 SB_DQ_34 DDR_B_DQS#[0..7] (15)
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0

SYSTEM
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM

DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1

DDR_A_D37 SA_DQ_36 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
AV13 SA_DQ_37 SA_DQS#_4 AY12 BF11 SB_DQ_37 SB_DQS#_2 BH41
DDR_A_D38 BD12 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
DDR_A_D39 SA_DQ_38 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
BC12 SA_DQ_39 SA_DQS#_6 AU9 BG7 SB_DQ_39 SB_DQS#_4 BG9
DDR_A_D40 BB9 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 BC2 DDR_B_DQS#5
DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
BA9 SA_DQ_41 BC6 SB_DQ_41 SB_DQS#_6 AT2
DDR_A_D42 AU10 DDR_B_D42 AY3 AN5 DDR_B_DQS#7
SA_DQ_42 DDR_A_MA[0..14] (14) SB_DQ_42 SB_DQS#_7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] (15)
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDR_A_D48 DDR_A_MA4 DDR_B_D48 DDR_B_MA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDR_A_D49 AV7 BA24 DDR_A_MA5 DDR_B_D49 AU3 AW25 DDR_B_MA4
DDR_A_D50 SA_DQ_49 SA_MA_5 DDR_A_MA6 DDR_B_D50 SB_DQ_49 SB_MA_4 DDR_B_MA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDR_A_D51 AN8 BG27 DDR_A_MA7 DDR_B_D51 AN2 AU28 DDR_B_MA6
DDR_A_D52 SA_DQ_51 SA_MA_7 DDR_A_MA8 DDR_B_D52 SB_DQ_51 SB_MA_6 DDR_B_MA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDR_A_D53 AU6 AW24 DDR_A_MA9 DDR_B_D53 AV1 AT33 DDR_B_MA8
DDR_A_D54 SA_DQ_53 SA_MA_9 DDR_A_MA10 DDR_B_D54 SB_DQ_53 SB_MA_8 DDR_B_MA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDR_A_D55 AN10 BG26 DDR_A_MA11 DDR_B_D55 AR1 BB16 DDR_B_MA10
DDR_A_D56 SA_DQ_55 SA_MA_11 DDR_A_MA12 DDR_B_D56 SB_DQ_55 SB_MA_10 DDR_B_MA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDR_A_D57 AM5 BH17 DDR_A_MA13 DDR_B_D57 AL2 AY33 DDR_B_MA12
DDR_A_D58 SA_DQ_57 SA_MA_13 DDR_A_MA14 DDR_B_D58 SB_DQ_57 SB_MA_12 DDR_B_MA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDR_A_D59 AJ8 DDR_B_D59 AH1 AU33 DDR_B_MA14
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDR_A_D61 AM13 DDR_B_D61 AM3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDR_A_D63 AJ12 DDR_B_D63 AJ3
SA_DQ_63 SB_DQ_63
GM45@ CANTIGA ES_FCBGA1329 GM45@ CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (2/6)-DDRII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

000 = FSB 1066MHz
CFG[2:0] FSB Freq select
010 = FSB 800MHz
011 = FSB 667MHz
+3VS R91 1 GM@ 2 2.2K_0402_5% LVDS_SCL Others = Reserved
R90 1 2 2.2K_0402_5% LVDS_SDA PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15] (16)
GM@
PCIE_MTX_C_GRX_P[0..15] CFG[4:3] Reserved
PCIE_MTX_C_GRX_P[0..15] (16)
PCIE_GTX_C_MRX_N[0..15] 0 = DMI x 2
D PCIE_GTX_C_MRX_N[0..15] (16) D
CFG5 (DMI select) 1 = DMI x 4
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P[0..15] (16) *
0 = The iTPM Host Interface is enable
CFG6
1 = The iTPM Host Interface is disable
Place the resistor within 500mils 0 =(TLS)chiper suite with no confidentiality
*
CFG7 (Intel Management
(1.27mm)of the (G)MCH 1 =(TLS)chiper suite with confidentiality
Engine Crypto strap)
U26C
PEGCOMP trace width
and spacing is 20/25 mils. CFG8 Reserved
L32 +VCC_PEG
T1 L_BKLT_CTRL
GMCH_ENBKL G32 T37 49.9_0402_1%
(24) GMCH_ENBKL L_BKLT_EN PEG_COMPI
+3VS R213 1 2 10K_0402_5% M32 T36 PEGCOMP R1631 2 CFG9 0 = Reverse Lane,15->0, 14->1
R159 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% M33 L_CTRL_DATA
(24) LVDS_SCL LVDS_SCL K33 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
LVDS_SDA L_DDC_CLK PCIE_GTX_C_MRX_N0
J33 H44 Please check Power
(24) LVDS_SDA
(24) GM_ENVDD GM_ENVDD M29
L_DDC_DATA
L_VDD_EN
PEG_RX#_0
PEG_RX#_1 J46
L44
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
source if want
0 = Enable
*
PEG_RX#_2 PCIE_GTX_C_MRX_N3 support IAMT
1 2 C44 LVDS_IBG PEG_RX#_3 L40 CFG10 (PCIE Lookback enable)
R167 2.37K_0402_1% B43 N41 PCIE_GTX_C_MRX_N4 1 = Disable
For Cantiga:2.37kohm E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_4
PEG_RX#_5 P48
N44
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6 CFG11 Reserved
*
For Crestline:2.4kohm LVDS_VREFL PEG_RX#_6
T43 PCIE_GTX_C_MRX_N7
LVDS_ACLK# PEG_RX#_7 PCIE_GTX_C_MRX_N8
For Calero: 1.5Kohm (24) LVDS_ACLK# C41 LVDSA_CLK# PEG_RX#_8 U43 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDS_ACLK C40 Y43 PCIE_GTX_C_MRX_N9 01 = XOR Mode Enabled
(24) LVDS_ACLK LVDSA_CLK PEG_RX#_9
B37 Y48 PCIE_GTX_C_MRX_N10 10 = All Z Mode Enabled
LVDSB_CLK# PEG_RX#_10 PCIE_GTX_C_MRX_N11
Note: All LVDS data A37 Y36 11 = Normal Operation (Default)
LVDSB_CLK PEG_RX#_11
*

LVDS
signals/and it's compliments AA43 PCIE_GTX_C_MRX_N12
C LVDS_A0# PEG_RX#_12 PCIE_GTX_C_MRX_N13 C
should be routed (24) LVDS_A0# H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 CFG[15:14] Reserved
LVDS_A1# E46 AC47 PCIE_GTX_C_MRX_N14
Differentially (24) LVDS_A1# LVDSA_DATA#_1 PEG_RX#_14
LVDS_A2# G40 AD39 PCIE_GTX_C_MRX_N15
(24) LVDS_A2# LVDSA_DATA#_2 PEG_RX#_15
T93 A40 LVDSA_DATA#_3 CFG16 (FSB Dynamic ODT) 0 = Disabled
H43 PCIE_GTX_C_MRX_P0
LVDS_A0 PEG_RX_0 PCIE_GTX_C_MRX_P1
H48 J44 1 = Enabled
Layout Note: Place 150
(24) LVDS_A0
(24) LVDS_A1
LVDS_A1
LVDS_A2
D45
F40
LVDSA_DATA_0
LVDSA_DATA_1
PEG_RX_1
PEG_RX_2 L43
L41
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
*

GRAPHICS
(24) LVDS_A2 LVDSA_DATA_2 PEG_RX_3
Ohmtermination resistors T94 B40 N40 PCIE_GTX_C_MRX_P4 CFG[18:17] Reserved
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
P47
close to GMCH PEG_RX_5 PCIE_GTX_C_MRX_P6
A41 LVDSB_DATA#_0 PEG_RX_6 N43
H38 T42 PCIE_GTX_C_MRX_P7 CFG19 (DMI Lane Reversal) 0 = Normal Operation
T72
G37
J37
LVDSB_DATA#_1
LVDSB_DATA#_2
PEG_RX_7
PEG_RX_8 U42
Y42
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9 (Lane number in Order)
*
R121 R122 R127 LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
B42 Y37 PCIE_GTX_C_MRX_P11 1 = Reverse Lane
LVDSB_DATA_0 PEG_RX_11 PCIE_GTX_C_MRX_P12
G38 LVDSB_DATA_1 PEG_RX_12 AA42
PM@ PM@ PM@ F37 AD36 PCIE_GTX_C_MRX_P13
T73 K37
LVDSB_DATA_2
LVDSB_DATA_3
PEG_RX_13
PEG_RX_14 AC48
AD40
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
PCI-EXPRESS
PEG_RX_15
0_0402_5% 0_0402_5% 0_0402_5% 1 = PCIE/SDVO are operating simu.
J41 PCIE_MTX_GRX_N0 C277 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
GM@ PEG_TX#_0 PCIE_MTX_GRX_N1 C303 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
PEG_TX#_1 M46 1 2
R127 2 1 75_0402_5% TVA_DAC TVA_DAC F25 M47 PCIE_MTX_GRX_N2 C317 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
TVB_DAC TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C315 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
H25 TVB_DAC PEG_TX#_3 M40 1 2
R121 2 GM@ 1 75_0402_5% TVB_DAC TVC_DAC K25 M42 PCIE_MTX_GRX_N4 C325 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C343 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 R48 1 2
TV

R122 2 1 75_0402_5% TVC_DAC H24 N38 PCIE_MTX_GRX_N6 C358 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6
GM@ TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C349 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
PEG_TX#_7 T40 1 2
U37 PCIE_MTX_GRX_N8 C368 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
R132 R123 R124 PEG_TX#_8 PCIE_MTX_GRX_N9 C354 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N9
PEG_TX#_9 U40 1 2
B C31 Y40 PCIE_MTX_GRX_N10 C371 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10 B
TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C356 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 1 2
PM@ PM@ PM@ AA37 PCIE_MTX_GRX_N12 C372 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C364 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
PEG_TX#_13 AA40 1 2
AD43 PCIE_MTX_GRX_N14 C375 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C348 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
0_0402_5% 0_0402_5% 0_0402_5% PEG_TX#_15 AC46 1 2

1 GM@ 2 GMCH_CRT_R GMCH_CRT_B E28 J42 PCIE_MTX_GRX_P0 C271 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
(25) GMCH_CRT_B CRT_BLUE PEG_TX_0
R132 150_0402_1% L46 PCIE_MTX_GRX_P1 C296 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
GMCH_CRT_G GMCH_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 PCIE_MTX_C_GRX_P2
1 GM@ 2 (25) GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 C314 1 2 PM@ 0.1U_0402_10V7K
R124 150_0402_1% M39 PCIE_MTX_GRX_P3 C311 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PEG_TX_3
VGA

1 GM@ 2 GMCH_CRT_B GMCH_CRT_R J28 M43 PCIE_MTX_GRX_P4 C322 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
(25) GMCH_CRT_R CRT_RED PEG_TX_4
R123 150_0402_1% R47 PCIE_MTX_GRX_P5 C336 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
PEG_TX_5 PCIE_MTX_GRX_P6 C352 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
G29 CRT_IRTN PEG_TX_6 N37 1 2
T39 PCIE_MTX_GRX_P7 C344 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
GMCH_CRT_CLK H32 PEG_TX_7 PCIE_MTX_GRX_P8 C363 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
(25) GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8 U36 1 2
(25) GMCH_CRT_DATA GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C346 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
CRT_DDC_DATA PEG_TX_9 PCIE_MTX_GRX_P10 C366 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
(25) GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39 1 2
R203 GM@ 33_0402_1% E29 Y46 PCIE_MTX_GRX_P11 C351 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C367 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
20mil PEG_TX_12 AA36 1 2
AA39 PCIE_MTX_GRX_P13 C359 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
PEG_TX_13 PCIE_MTX_GRX_P14 C373 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
(25) GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2
R204 GM@ 33_0402_1% AD46 PCIE_MTX_GRX_P15 C347 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PEG_TX_15
1

R139 R140 CANTIGA ES_FCBGA1329

0_0402_5% 0_0402_5% R138 GM45@ PCIE_MTX_GRX_P3 C670 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_CLK (23)
PM@ PM@ PCIE_MTX_GRX_N3 C674 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_CLK# (23)
1.02K_0402_1% PCIE_MTX_GRX_P2 C669 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_DATA0 (23)
2

PCIE_MTX_GRX_N2 C673 1 2 GM_HDMI@

0.1U_0402_10V7K TMDS_B_DATA0# (23)
PCIE_MTX_GRX_P1 C662 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_DATA1 (23)
A GM@ R138 PCIE_MTX_GRX_N1 C663 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_DATA1# (23) A
For Cantiga:1.02kohm PCIE_MTX_GRX_P0 C658 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_DATA2 (23)
For Crestline:1.3kohm PCIE_MTX_GRX_N0 C661 1 2 GM_HDMI@
0.1U_0402_10V7K TMDS_B_DATA2# (23)
For Calero: 255ohm PM@
PCIE_GTX_C_MRX_P3 R640 1 2 0_0402_5% TMDS_B_HPD# (23)
GM@
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_DAC_CRT
R120
1 2
+VCCP
VCC_AXF: 321.35mA

0.022U_0402_16V7K
0_0603_5%
(10UF*1, 1UF*1)

0.1U_0402_16V4Z

10U_0805_10V4Z
GM@ U26H
+1.05VS_DPLLA
1 1 1 R151 +VCCP

C644
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +V1.05VS_AXF

C206

C213
GM@ GM@ @ U13 1 2 +VCCP
VTT_1

4.7U_0805_10V4Z

0.1U_0402_16V4Z
+3VS_DAC_CRT B27 T13 1
2 2 2 VCCA_CRT_DAC_1 VTT_2

220U_D2_4VM

10U_0805_10V4Z
A26 U12 1 MCK3225151YZF 1210 1 2
VCCA_CRT_DAC_2 VTT_3

10U_0805_10V4Z

1U_0603_10V4Z
T12 +
VTT_4 1 1
GM@

C278
C747

C265
VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1) U11 C278 R495
VTT_5

C275
T11 1 1 0_0603_5%
VTT_6 2 2

C629

C631
CRT
+3VS_DAC_BG A25 U10
VCCA_DAC_BG VTT_7 2 2
T10
+3VS +3VS_DAC_BG VTT_8 GM@ GM@
D B25 U9 D
VSSA_DAC_BG VTT_9 2 2
VTT_10 T9
1R115 2 VTT_11 U8 +1.05VS_DPLLA 0_0402_5%
0.022U_0402_16V7K
0_0603_5% T8 PM@ VCC_SM_CK: 119.85mA
VTT_12 +1.05VS_DPLLB: 64.8mA
0.1U_0402_16V4Z

10U_0805_10V4Z

4.7U_0805_10V4Z
GM@

VTT
F47 U7
+1.05VS_DPLLA VCCA_DPLLA VTT_13 (470UF*1, 0.1UF*1) (10UF*1, 0.1UF*1)

C126
1 1 GM@ 1 T7 1 1
VTT_14
C639

+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6 +1.5V_SM_CK

+1.05VS_DPLLB
C637

C638

C136
GM@ GM@ T6 +1.5V
VTT_16 R191

PLL
AD1 U5 R496

0.47U_0402_6.3V6K
2 2 2 +1.05VS_HPLL VCCA_HPLL VTT_17 2 2
VTT_18 T5 1 2 +VCCP 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 V3 0_0805_5%
VCCA_MPLL VTT_19

10U_0805_10V4Z
U3 MCK3225151YZF 1210 1
+1.8V_TXLVDS VTT_20

C627
V2 1 1 C312 1
VTT_21 GM@

C312

C628
A PEG A LVDS
J48 U2
VCCA_LVDS VTT_22

C310
1 T2
1000P_0402_50V7K VTT_23 2
J47 VSSA_LVDS VTT_24 V1
@ C300 U1 2 2 2
C637 C206 VTT_25 GM@ GM@
2
+1.5VS_PEG_BG: 0.414mA AD48 VCCA_PEG_BG 0_0402_5%
PM@
(0.1UF*1) +1.5VS_PEG_BG
R166 20 mils
+1.05VS_HPLL
+1.5VS 2 1 AA48
VCCA_PEG_PLL +1.05VS_HPLL: 24mA
0_0402_5% 0_0402_5% 0_0603_5% +1.05VS_PEGPLL
PM@ PM@ 1 R474 (4.7UF*1, 0.1UF*1) +1.5VS_TVDAC +1.5VS
C301 R136
2 1 +VCCP
MBK2012121YZF_0805 2 1
0.1U_0402_16V4Z C180 0_0603_5%
2 POWER

0.022U_0402_16V7K

0.1U_0402_16V4Z

10U_0805_10V4Z
AR20 1 1 GM@
VCCA_SM_1 C609 C604
AP20 1 1 1
+1.05VS_A_SM VCCA_SM_2
AN20 VCCA_SM_3
+VCCP

C180

C195

C198
R108 AR17 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
VCCA_SM_4 2 2

A SM
1 2 AP17 VCCA_SM_5 VCCD_TVDAC: 58.696mA
VCCA_SM:720mA 1 0_0805_5% AN17 B22 0_0402_5% GM@ 2 2 2
VCCA_SM_6 VCC_AXF_1 +V1.05VS_AXF (0.1UF*1, 0.01UF*1)

AXF
1 1 1 AT16 B21 PM@
(22UF*2, 4.7UF*1, 1UF*1) + C87 4.7U_0805_10V4Z C102 AR16
VCCA_SM_7 VCC_AXF_2
A21
C605 C96 VCCA_SM_8 VCC_AXF_3 GM@ GM@
AP16
220U_D2_4VY_R15M 10U_0805_10V4Z 1U_0603_10V4Z VCCA_SM_9
C C
@ 2 2 2 2

VCC_SM_CK_1 BF21 +1.5V_SM_CK +1.05VS_MPLL +1.8V_TXLVDS

SM CK
+1.05VS_A_SM_CK VCC_SM_CK_2 BH20 1.05VS_MPLL: 139.2mA 40 mils
VCCA_SM_CK: 220mA BG20 R473
R134 VCC_SM_CK_3
BF20
(22UF*1, 0.1UF*1) R208
(22UF*1, 2.2UF*1, 0.1UF*1) 2 1 AP28
VCC_SM_CK_4
2 1 1000P_0402_50V7K 2 1
VCCA_SM_CK_1 +VCCP +1.8VS
1U_0402_6.3V4Z

1U_0603_10V4Z

0_0603_5% AN28 MBK2012121YZF_0805 0_0603_5%

VCCA_SM_CK_2
10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
AP25 C299 GM@ +1.8V_TXLVDS: 118.8mA
VCCA_SM_CK_3
1 1 1 1 AN25 +1.8V_TXLVDS 1 1 1 1 (22UF*1, 1000PF*1)
VCCA_SM_CK_4
C194

C214

C370
AN24 K47 C608 C603 C299
VCCA_SM_CK_5 VCC_TX_LVDS
C211

A CK
GM@ GM@
C210

AM28
VCCA_SM_CK_NCTF_1 +3VS_HV 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
AM26
2 2 2 2 VCCA_SM_CK_NCTF_2 2 2 2 2

0.1U_0402_16V4Z
AM25 <BOM Structure>
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4 VCC_HV_1
C35 1 0_0402_5%
AM24 B35 PM@
VCCA_SM_CK_NCTF_5 VCC_HV_2

C649
HV
AL24 A35
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23
VCCA_SM_CK_NCTF_7 2
AL23
VCCA_SM_CK_NCTF_8
+3VS_TVDAC: 40mA VCC_PEG_1
V48 +VCC_PEG +VCCP
(0.1UF*1, 0.01UF*1 for VCC_PEG_2
U48
+1.05VS_PEGPLL
+1.5VS_PEG_PLL: 50mA +VCC_PEG

PEG
VCC_PEG_3 V47 (0.1UF*1)
GM@ each DAC) U47 L1
+3VS R117 +3VS_TVDAC VCC_PEG_4 BLM18PG121SN1D_0603
+3VS_TVDAC B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
1 2 A24 2 1 +VCCP
+1.5VS_HDA VCCA_TV_DAC_2

10U_0805_10V4Z
TV 1

0.1U_0402_16V4Z

220U_D2_4VM
0_0603_5% GM_HDMI@ 1

C339

C323
R1 +
1 1 1 1

C342
C181 C171 +1.5VS 1 2 A32 AH48 +VCC_DMI C355
VCC_HDA VCC_DMI_1
HDA

0.022U_0402_16V7K 0.1U_0402_16V4Z AF48

VCC_DMI_2 2 2
0.1U_0402_16V4Z

DMI
0_0603_5% AH47 VCC_DMI: 456mA 2.2U_0603_6.3V4Z
VCC_DMI_3
1

2 2 2 2
VCC_HDA: 50mA 1 VCC_DMI_4
AG47
(0.1UF*1) <BOM Structure>
C1

C181 GM@ GM@ R2 0316 add

(0.1UF*1) M25
0_0402_5% +1.5VS_TVDAC VCCD_TVDAC
PMIGM_NOHDMI@ GM_HDMI@
D TV/CRT

2
B +1.5VS_QDAC L28 20mils B
2

VCCD_QDAC
+VCCP
0_0402_5% +1.05VS_HPLL AF1
VCCD_HPLL
PM@ A8 +VCC_DMI
VTTLF1 R202
+1.05VS_PEGPLL AA47 L1
VCCD_PEG_PLL VTTLF2 +VCCP_D
VTTLF

AB2 2 1
VTTLF3 0_0805_5%

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
+1.8V_LVDS M38 1 1 1
VCCD_LVDS_1
LVDS

L37 D1 @ R158 @ R157 1 1 1

VCCD_LVDS_2
C94

C611

C618

C337

C353

C795
+VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
2 2 2 CH751H-40PT_SOD323-2
GM45@ CANTIGA ES_FCBGA1329 2 2 2
+3VS
U26 U26
0316 add

GL40 PM
GL40@ PM@

VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA

+1.5VS_QDAC (0.1UF*1, 0.01UF*1) +1.8V_LVDS (1UF*1)
R142
R137
2 1 +1.5VS
1U_0402_6.3V4Z

10U_0805_10V4Z

0_0603_5% 2 1 +1.8VS
0.1U_0402_16V4Z

10U_0805_10V4Z

0_0603_5%
1U_0603_10V4Z

1 1 1 1 1 GM@
C237
C208

C207

C221

C226

A A
GM@
2 2 2 2 2 GM@
GM@
C208 GM@ C237

0.01U_0402_16V7K 0_0603_5%
PM@ PM@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (4/6)-VCC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom KIWAX_LA-5081P 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 11 of 51
5 4 3 2 1
 5 4 3 2 1

U26F
+AXG_CORE

Check : power
1782mA VCC_AXG_NTCF_1 W28
AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
VCC_SM_2 VCC_AXG_NCTF_3
+1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
BG32
VCC_SM_4 VCC_AXG_NCTF_5
W25 1 C197 1 C129 1 C99

10U_0805_10V4Z

0.01U_0402_16V7K
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
+VCCP

220U_D2_4VM_R15
1 BD32 W24
U26G VCC_SM_6 VCC_AXG_NCTF_7 GM@ GM@ GM@
1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
2 2 2

C177

C643

C645
D + BB32 W23 D
VCC_SM_8 VCC_AXG_NCTF_9

VCC
AG34 VCC_1 BA32 VCC_SM_9 VCC_AXG_NCTF_10 V23
AC34 AY32 AM21 0.22U_0402_10V4Z
VCC_2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_11
AB34 AW32 AL21
VCC_3 VCC_SM_11 VCC_AXG_NCTF_12
AA34 AV32 AK21
VCC_4 VCC_SM_12 VCC_AXG_NCTF_13
Y34 VCC_5 AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21
V34 AT32 V21 C99

VCC CORE

SM
VCC_6 VCC_SM_14 VCC_AXG_NCTF_15
U34 VCC_7 AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21
AM33 VCC_8 AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20
AK33 AN32 AK20
VCC_9 VCC_SM_17 VCC_AXG_NCTF_18
AJ33 VCC_10 BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AG33 BG31 U20

VCC_11 VCC_SM_19 VCC_AXG_NCTF_20
10U_0805_10V4Z

AF33 VCC_12 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 0_0603_5%

1 1 1 1 BG30 AL19 PM@
VCC_SM_21 VCC_AXG_NCTF_22
C193

C175

C220

BH29 AK19
VCC_SM_22 VCC_AXG_NCTF_23
C178

BG29 AJ19
VCC_SM_23 VCC_AXG_NCTF_24
AE33 VCC_13 BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
2 2 2 2 AC33 BD29 AG19
VCC_14 VCC_SM_25 VCC_AXG_NCTF_26
AA33 VCC_15 BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
Y33 BB29 AE19
VCC_16 VCC_SM_27 VCC_AXG_NCTF_28
W33 BA29 AB19
VCC_17 VCC_SM_28 VCC_AXG_NCTF_29

POWER
V33 AY29 AA19
VCC_18 VCC_SM_29 VCC_AXG_NCTF_30

GFX NCTF
U33 VCC_19 AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19
AH28 VCC_20 AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19
AF28 AU29 V19
VCC_21 VCC_SM_32 VCC_AXG_NCTF_33
AC28 VCC_22 AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19
AA28 AR29 AM17
VCC_23 VCC_SM_34 VCC_AXG_NCTF_35
AJ26 AP29 AK17
VCC_24 VCC_SM_35 VCC_AXG_NCTF_36
AG26 VCC_25 VCC_AXG_NCTF_37 AH17
AE26 VCC_26 VCC_AXG_NCTF_38 AG17
AC26 AF17
VCC_27 +VCCP VCC_AXG_NCTF_39
AH25 BA36 AE17
C VCC_28 +VCCP +AXG_CORE VCC_SM_36/NC VCC_AXG_NCTF_40 C
AG25 VCC_29 BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17

VCC
AF25 @ BD16 AB17
VCC_30 J4 VCC_SM_38/NC VCC_AXG_NCTF_42
AG24 AM32 BB21 Y17
VCC_31 VCC_NCTF_1 VCC_SM_39/NC VCC_AXG_NCTF_43
AJ23 VCC_32 VCC_NCTF_2 AL32 1 1 2 2 AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17
AH23 VCC_33 VCC_NCTF_3 AK32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
AF23 AJ32 AT13 AM16
VCC_34 VCC_NCTF_4 JUMP_43X118 VCC_SM_42/NC VCC_AXG_NCTF_46
T32 VCC_35 VCC_NCTF_5 AH32 VCC_AXG_NCTF_47 AL16
AG32 AK16

POWER
VCC_NCTF_6 VCC_AXG_NCTF_48
VCC_NCTF_7 AE32 VCC_AXG_NCTF_49 AJ16
AC32 AH16
VCC_NCTF_8 VCC_AXG_NCTF_50
VCC_NCTF_9 AA32 VCC_AXG_NCTF_51 AG16
Y32 AF16
VCC_NCTF_10 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16
U32 AE25 AC16
VCC_NCTF_12 VCC_AXG_2 VCC_AXG_NCTF_54
AM30 AB25 AB16
VCC_NCTF_13 +AXG_CORE VCC_AXG_3 VCC_AXG_NCTF_55
AL30 AA25 AA16
VCC_NCTF_14 VCC_AXG_4 VCC_AXG_NCTF_56
AK30 AE24 Y16
VCC_NCTF_15 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG_5 VCC_AXG_NCTF_57
AH30 AC24 W16
VCC_NCTF_16 VCC_AXG_6 VCC_AXG_NCTF_58
AG30 AA24 V16
VCC_NCTF_17 VCC_AXG_7 VCC_AXG_NCTF_59
VCC_NCTF_18 AF30 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16
AE30 GM@ 1 GM@ GM@ 1 GM@ 1 GM@ 1 AE23
VCC_NCTF_19 C149 C84 + C104 C157 C167 VCC_AXG_9
AC30 AC23
NCTF

VCC_NCTF_20 VCC_AXG_10
AB30 AB23
VCC_NCTF_21 1U_0603_10V4Z VCC_AXG_11
AA30 AA23
VCC_NCTF_22 2 2 2 2 2 VCC_AXG_12
Y30 AJ21
VCC_NCTF_23 VCC_AXG_13
W30 AG21
VCC_NCTF_24 220U_D2_4VM_R15 10U_0805_10V4Z VCC_AXG_14
VCC_NCTF_25 V30 AE21 VCC_AXG_15
U30 AC21
VCC_NCTF_26 VCC_AXG_16
VCC

AL29 AA21
VCC_NCTF_27 VCC_AXG_17
AK29 Y21
VCC_NCTF_28 VCC_AXG_18

VCC
AJ29 AH20
VCC_NCTF_29 VCC_AXG_19
AH29 AF20
B VCC_NCTF_30 C157 VCC_AXG_20 B
VCC_NCTF_31 AG29 AE20 VCC_AXG_21
VCC_NCTF_32 AE29 AC20 VCC_AXG_22
AC29 AB20
VCC_NCTF_33 VCC_AXG_23
AA29 AA20

GFX
VCC_NCTF_34 VCC_AXG_24
Y29 T17
VCC_NCTF_35 VCC_AXG_25
W29 T16
VCC_NCTF_36 VCC_AXG_26
VCC_NCTF_37
V29 0_0805_5% AM15
VCC_AXG_27
AL28 PM@ AL15
VCC_NCTF_38 VCC_AXG_28
AK28 AE15
VCC_NCTF_39 VCC_AXG_29
VCC_NCTF_40 AL26 AJ15 VCC_AXG_30
VCC_NCTF_41 AK26 AH15 VCC_AXG_31
AK25 AG15
VCC_NCTF_42 VCC_AXG_32
VCC_NCTF_43 AK24 AF15 VCC_AXG_33
AK23 AB15
VCC_NCTF_44 VCC_AXG_34
AA15 VCC_AXG_35
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40
U14 AV44 VCCSM_LF1

VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
AM40 VCCSM_LF3
VCC_SM_LF3
GM45@ CANTIGA ES_FCBGA1329
VCC_SM_LF4 AV21 VCCSM_LF4
AY5 VCCSM_LF5
VCC_SM_LF5
T32 AJ14 AM10 VCCSM_LF6
VCC_AXG_SENSE VCC_SM_LF6
T31 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7

C121 0.1U_0402_16V4Z

C114 0.1U_0402_16V4Z

C101 0.22U_0402_10V4Z

C159 0.22U_0402_10V4Z

C264 0.47U_0402_6.3V6K

C243 1U_0402_6.3V4Z

C297 1U_0402_6.3V4Z
1 1 1 1 1 1 1

2 2 2 2 2 2 2
A A
GM45@ CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (5/6)-VCC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 12 of 51
5 4 3 2 1
 5 4 3 2 1

U26I U26J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 B36 AH21 AU7
VSS_7 VSS_106 VSS_205 VSS_303
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 AA35 AB21 AJ7
VSS_9 VSS_108 VSS_207 VSS_305
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 U35 M21 AA7
VSS_11 VSS_110 VSS_209 VSS_307
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 AF34 AW20 AV6
VSS_16 VSS_115 VSS_214 VSS_312
BA46 AE34 AT20 AT6
VSS_17 VSS_116 VSS_215 VSS_313
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 B34 AG20 M6
VSS_19 VSS_118 VSS_217 VSS_315
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 BC33 K20 AH5
VSS_22 VSS_121 VSS_220 VSS_318
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 AV33 C20 Y5
VSS_24 VSS_123 VSS_222 VSS_320
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 AL33 BG19 J5
VSS_26 VSS_125 VSS_224 VSS_322
BF44 AH33 A18 H5
VSS_27 VSS_126 VSS_225 VSS_323
AH44 AB33 BG17 F5
VSS_28 VSS_127 VSS_226 VSS_324
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 L33 AW17
VSS_30 VSS_129 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 N32 R17 AV3
VSS_32 VSS_131 VSS_230 VSS_328
T44 K32 M17 AL3
VSS_33 VSS_132 VSS_231 VSS_329
M44 F32 H17 R3
VSS_34 VSS_133 VSS_232 VSS_330
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 AN29 BA16 BA2
VSS_37 VSS_136 VSS_235 VSS_333
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 N29 AU16 AU2
VSS_39 VSS_138 VSS_237 VSS_335
J43 K29 AN16 AR2
VSS_40 VSS_139 VSS_238 VSS_336
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 BG28 E16 AF2
C VSS_44 VSS_143 VSS_242 VSS_340 C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 BA28 AC15 AD2
VSS_46 VSS_145 VSS_244 VSS_342
AE42 AV28 W15 AC2
VSS_47 VSS_146 VSS_245 VSS_343
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
VSS_50 VSS_149 VSS_248 VSS_346
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
VSS_52 VSS_151 VSS_250 VSS_348
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 Y28 BA13 H1
VSS_54 VSS_153 VSS_252 VSS_350
AA41 VSS_55 VSS_154 P28
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 F28 AJ13 U25
VSS_58 VSS_157 VSS_256 VSS_353
M41 C28 AE13 U29
VSS_59 VSS_158 VSS_257 VSS_354
G41 BF26 N13
VSS_60 VSS_159 VSS_258
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
VSS_62 VSS_161 VSS_260 VSS_NCTF_2
BB40 AB26 E13 V32
VSS_63 VSS_162 VSS_261 VSS_NCTF_3
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 C26 AV12 AM29
VSS_65 VSS_164 VSS_263 VSS_NCTF_5
H40 B26 AT12 AF29
VSS_66 VSS_165 VSS_264 VSS_NCTF_6
E40 BH25 AM12 AB29
VSS_67 VSS_166 VSS_265 VSS_NCTF_7
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 BB25 J12 U23
VSS_69 VSS_168 VSS_267 VSS_NCTF_9
AJ39 AV25 A12 AL20
VSS_70 VSS_169 VSS_268 VSS_NCTF_10
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 AJ25 BB11 AC19
VSS_72 VSS_171 VSS_270 VSS_NCTF_12
L39 AC25 AY11 AL17
VSS_73 VSS_172 VSS_271 VSS_NCTF_13
B39 Y25 AN11 AJ17
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 N25 AH11 AA17
VSS_75 VSS_174 VSS_273 VSS_NCTF_15
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 AD12 BG10 A48
VSS_81 VSS_180 VSS_279 VSS_SCB_3
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 AT24 AT10 A3
VSS_83 VSS_182 VSS_281 VSS_SCB_5
T38 AJ24 AJ10
VSS_84 VSS_183 VSS_282
J38 AH24 AE10
VSS_85 VSS_184 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 A23 B47
VSS_99 VSS_198 NC_37
VSS_199 AJ6 NC_38 A46
F48
GM45@ CANTIGA ES_FCBGA1329 NC_39
E48
NC_40
NC_41 C48
B48
NC_42

GM45@ CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH (6/6)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 13 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

+V_DDR3_DIMM_REF
(9) DDR_A_DQS#[0..7]

(9) DDR_A_D[0..63] JP17

1 VREF_DQ VSS1 2
+1.5V 3 4 DDR_A_D4
(9) DDR_A_DM[0..7] DDR_A_D0 VSS2 DQ4 DDR_A_D5
5 DQ0 DQ5 6
(9) DDR_A_DQS[0..7] DDR_A_D1 7 8
DQ1 VSS3

1
9 10 DDR_A_DQS#0
R625 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
(9) DDR_A_MA[0..14] 11 12
100_0402_1% DM0 DQS0
13 VSS5 VSS6 14
<BOM Structure>+V_DDR3_DIMM_REF DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18

2
D DQ3 DQ7 D
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
0.1U_0402_16V4Z
DDR_A_D9 23 24 DDR_A_D13
R626 DQ9 DQ13
1 25 26
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 28
DQS#1 DM1

C755
100_0402_1%
<BOM Structure> DDR_A_DQS1 29 30 SM_DRAMRST#
DQS1 RESET# SM_DRAMRST# (8,15)
31 32

2
2 DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 48
DQS2 VSS17 DDR_A_D22
49 50
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_A_DQS#3
61 62
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 72
VSS25 VSS26

Layout Note: DDR_CKE0_DIMMA DDR_CKE1_DIMMA

(8) DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA (8)
Place near JP4 75
CKE0 CKE1
76
C VDD1 VDD2 C
77 NC1 A15 78
DDR_A_BS2 79 80 DDR_A_MA14
(9) DDR_A_BS#2 BA2 A14
Layout Note: Place these 4 Caps near Command 81
VDD3 VDD4
82
DDR_A_MA12 83 84 DDR_A_MA11
and Control signals of DIMMA DDR_A_MA9 85
A12/BC# A11
86 DDR_A_MA7
A9 A7
87 88
+1.5V DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
A3 A2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1 1 1 1 1 1 1 1 1 1 99 100
VDD9 VDD10
C750

C752

C749

C753
C766

C768

C767

C763

C764

C765

+ C787 M_CLK_DDR0 101 102 M_CLK_DDR1

470U_D2_2.5VM_R15 (8) M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 (8)
103 104 M_CLK_DDR#1 (8)
(8) M_CLK_DDR#0 CK0# CK1#
@ 105 106
2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS#1 (9)
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
(9) DDR_A_BS#0 109 110 DDR_A_RAS# (9)
BA0 RAS#
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114 DDR_CS0_DIMMA# (8)
(9) DDR_A_WE# DDR_A_CAS# WE# S0# M_ODT0
(9) DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 (8)
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1 +V_DDR3_DIMM_REF
119 120 M_ODT1 (8)
DDR_CS1_DIMMA# A13 ODT1
121 122
(8) DDR_CS1_DIMMA# S1# NC2 R623
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMA
125 126 1 2
NCTEST VREF_CA
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36 0_0402_5%
Layout Note: DDR_A_D33
129 DQ32 DQ36 130
DDR_A_D37
131 132
Place near JP4.203 & JP4.204 133
DQ33 DQ37
134
VSS29 VSS30

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_A_D38
139 140
VSS32 DQ38

C785

C751
B DDR_A_D34 DDR_A_D39 B
141 DQ34 DQ39 142
+0.75VS DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2
145 146
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

151 152 DDR_A_DQS#5

DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
2 2 2 2 1 155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
1 1 1 1 2
C778

C779

C776

C777

C762

DDR_A_D48 163 164 DDR_A_D52

DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 DQS#6 DM6 170
DDR_A_DQS6 171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R627 2 195 196
10K_0402_5% VSS51 VSS52 PM_EXTTS#0
197 198 PM_EXTTS#0 (8,15)
SA0 EVENT# CLK_SMBDATA
+3VS 199 200 CLK_SMBDATA (15,22)
VDDSPD SDA CLK_SMBCLK
201 202 CLK_SMBCLK (15,22)
SA1 SCL
2.2U_0603_6.3V4Z

1 1 203 VTT1 VTT2 204 +0.75VS

1
10K_0402_5%

A A
0.1U_0402_16V4Z

C754
C784 205 206
G1 G2
R628

2 2 FOX_AS0A626-U2RN-7F
ME@
DDR3 SO-DIMM A
REVERSE
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 14 of 51
5 4 3 2 1
 5 4 3 2 1

(9) DDR_B_DQS#[0..7] +1.5V +1.5V

(9) DDR_B_D[0..63]
+V_DDR3_DIMM_REF

(9) DDR_B_DM[0..7] JP16

(9) DDR_B_DQS[0..7] 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
(9) DDR_B_MA[0..14] 5 6
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS3 8
9 10 DDR_B_DQS#0
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
D DDR_B_D3 DDR_B_D7 D
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 DQS#1 DM1 28
DDR_B_DQS1 29 30 SM_DRAMRST#
DQS1 RESET# SM_DRAMRST# (8,14)
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 44
DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 46
DDR_B_DQS2 DQS#2 DM2
Layout Note: 47
DQS2 VSS17
48
DDR_B_D22
49 VSS18 DQ22 50
Place near JP5 DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
Layout Note: Place these 4 Caps near Command 55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
and Control signals of DIMMA 57 58
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
+1.5V DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 71 72
VSS25 VSS26
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1 1 1 1 1 1 1 1 1 1
C756

C757

C760

C759
C771

C775

C772

C769

C774

C773

+ C788
470U_D2_2.5VM_R15
@ DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
C 2 2 2 2 2 2 2 2 2 2 2 (8) DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB (8) C
75 VDD1 VDD2 76
77 78
DDR_B_BS2 NC1 A15 DDR_B_MA14
(9) DDR_B_BS#2 79 80
BA2 A14
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
Layout Note: DDR_B_MA1
95 A3 A2 96
DDR_B_MA0
97 98
Place near JP5.203 & JP5.204 99
A1 A0
100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
101 102 M_CLK_DDR3 (8)
(8) M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
103 104 M_CLK_DDR#3 (8)
(8) M_CLK_DDR#2 CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS#1 (9)
+0.75VS DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
(9) DDR_B_BS#0 109 110 DDR_B_RAS# (9)
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB#
113 WE# S0# 114 DDR_CS2_DIMMB# (8)
(9) DDR_B_WE# DDR_B_CAS# M_ODT2
(9) DDR_B_CAS# 115 116 M_ODT2 (8)
CAS# ODT0
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3 +V_DDR3_DIMM_REF
119 120 M_ODT3 (8)
DDR_CS3_DIMMB# A13 ODT1
2 2 2 2 1 121 122
(8) DDR_CS3_DIMMB# S1# NC2 R624
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB
125 126 1 2 0_0402_5%
NCTEST VREF_CA
127 VSS27 VSS28 128
1 1 1 1 2
C780

C781

C783

C782

C770

DDR_B_D32 129 130 DDR_B_D36

DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134
VSS29 VSS30

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z
DDR_B_DQS#4 135 136 DDR_B_DM4
DDR_B_DQS4 DQS#4 DM4
137 138 1 1
B DQS4 VSS31 DDR_B_D38 B
139 VSS32 DQ38 140

C786

C758
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 DQ42 DQ46 158
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 DQ58 DQ62 192
DDR_B_D59 DDR_B_D63
1 R630 2
193
195
DQ59
VSS51
DQ63
VSS52
194
196 same with intel DDR3 CRB connection
10K_0402_5% 197 198 PM_EXTTS#0
SA0 EVENT# PM_EXTTS#0 (8,14)
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBCLK CLK_SMBDATA (14,22)
201 SA1 SCL 202 CLK_SMBCLK (14,22)
A A
0.1U_0402_16V4Z

1 2 203 204
1
R629
10K_0402_5% 205
VTT1 VTT2
206
+0.75VS
DDR3 SO-DIMM B
2
C761 G1 G2
FOX_AS0A626-UARN-7F
REVERSE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 15 of 51
5 4 3 2 1
 5 4 3 2 1

GPU_VID1 GPU_VID0 VGA_CORE P-State

3/17 N10M-GS: VGA_CORE:1.0V GPIO6/5--->1/1 10,12
U59A 0 0 0.9V
0 VGA_CRT_R R933 1 PM@ 2 150_0402_1%
PCIE_MTX_C_GRX_P0 AE12 Part 1 of 5 N1
1 1 1.20V VGA_CRT_G R934 1 PM@ 2 150_0402_1%
PCIE_MTX_C_GRX_N0 PEX_RX0 GPIO0 VGA_CRT_B
PCIE_MTX_C_GRX_N[0..15]
AF12 PEX_RX0_N GPIO1 G1 HDMI_DETECT_VGA (23) 0 1 1.09V 8 R935 1 PM@ 2 150_0402_1%
PCIE_MTX_C_GRX_P1 AG12 C1 NV_INVTPWM
(10) PCIE_MTX_C_GRX_N[0..15] PEX_RX1 GPIO2 PAD T157
PCIE_MTX_C_GRX_N1 AG13 M2 VGA_ENVDD
PCIE_MTX_C_GRX_P[0..15] PEX_RX1_N GPIO3 VGA_ENVDD (24)
PCIE_MTX_C_GRX_P2 AF13 M3 VGA_ENBKL
(10) PCIE_MTX_C_GRX_P[0..15] PEX_RX2 GPIO4 VGA_ENBKL (24)
PCIE_MTX_C_GRX_N2 AE13 K3 1 2 GPU_VID1
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P3 PEX_RX2_N GPIO5 GPU_VID0 GPU_VID1 (48)
AE15 K2 R936
1 PM@ 2 0_0402_5%
(10) PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N3 PEX_RX3 GPIO6 GPU_VID0 (48)
AF15 J2 R937 PM@ 0_0402_5%
PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P4 PEX_RX3_N GPIO7
AG15 C2

GPIO
(10) PCIE_GTX_C_MRX_P[0..15] PEX_RX4 GPIO8
PCIE_MTX_C_GRX_N4
D PCIE_MTX_C_GRX_P5
AG16
AF16
PEX_RX4_N GPIO9 M1
D2 VGA_GPIO11
For N10M 40NM D
PCIE_MTX_C_GRX_N5 PEX_RX5 GPIO10 VGA_GPIO11 VGA_GPIO14 +3VS
AE16 PEX_RX5_N GPIO11 D1

1
PCIE_MTX_C_GRX_P6 AE18 J3
PEX_RX6 GPIO12

1
PCIE_MTX_C_GRX_N6 AF18 J1 R939
PCIE_MTX_C_GRX_P7 PEX_RX6_N GPIO13 VGA_GPIO14 R940
AG18 K1 10K_0402_5%
PCIE_MTX_C_GRX_N7 PEX_RX7 GPIO14 10K_0402_5%
AG19 PEX_RX7_N GPIO15 F3 40NM@
PCIE_MTX_C_GRX_P8 AF19 G3 40NM@ 55NM_HDMI@
C928

2
PEX_RX8 GPIO16

1
PCIE_MTX_C_GRX_N8 AE19 G2 1 2 0.1U_0402_16V4Z
PAD T158

2
PCIE_MTX_C_GRX_P9 PEX_RX8_N GPIO17 R941 R942 R943
AE21 PEX_RX9 GPIO18 F1
PCIE_MTX_C_GRX_N9 AF21 F2 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5%
PCIE_MTX_C_GRX_P10 PEX_RX9_N GPIO19 @ U60
AG21 PEX_RX10 PM@ PM@
PCIE_MTX_C_GRX_N10 AG22 AD2 VGA_HSYNC 8 1
VGA_HSYNC (25)

2
PCIE_MTX_C_GRX_P11 PEX_RX10_N DACA_HSYNC VGA_VSYNC VCC A0
AF22 PEX_RX11 DACA_VSYNC AD1 VGA_VSYNC (25) 7 WP A1 2

DACA
PCIE_MTX_C_GRX_N11 AE22 HDCP_SMB_CK1 6 3
PCIE_MTX_C_GRX_P12 PEX_RX11_N VGA_CRT_R HDCP_SMB_DAI SCL A2
AE24 AE2 VGA_CRT_R (25) 5 4
PCIE_MTX_C_GRX_N12 PEX_RX12 DACA_RED VGA_CRT_B SDA GND
PCIE_MTX_C_GRX_P13
AF24
AG24
PEX_RX12_N DACA_BLUE
AD3
AE3 VGA_CRT_G
VGA_CRT_B (25)
VGA_CRT_G (25)
CRT OUT AT24C16AN-10SU-2.7_SO8
PCIE_MTX_C_GRX_N13 PEX_RX13 DACA_GREEN 55NM_HDMI@
AF25
PCIE_MTX_C_GRX_P14 PEX_RX13_N DACA_VREF
AG25 PEX_RX14 DACA_VREF AF1 2 1 PM@

1
PCIE_MTX_C_GRX_N14 AG26 AE1 DACA_RSET C929 0.1U_0402_16V4Z R944
PCIE_MTX_C_GRX_P15 PEX_RX14_N DACA_RSET R946
AF27 2.2K_0402_5%
PCIE_MTX_C_GRX_N15 PEX_RX15 R945 PM@ 124_0402_1% 100K_0402_1% 55NM_HDMI@
AE27 D6 @
PEX_RX15_N DACB_CSYNC
PCIE_GTX_C_MRX_P0 C930 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P0 AD10 F7 +3VS

DACB

2
PCIE_GTX_C_MRX_N0 C931 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N0 PEX_TX0 DACB_RED
1 2 AD11 E6
PCIE_GTX_C_MRX_P1 C932 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P1 PEX_TX0_N DACB_BLUE
1 2 AD12 PEX_TX1 DACB_GREEN E7
PCIE_GTX_C_MRX_N1 C933 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N1 AC12
PCIE_GTX_C_MRX_P2 C934 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P2 PEX_TX1_N PM@ 2.2K_0402_5%
1 2 AB11
PCIE_GTX_C_MRX_N2 C935 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N2 PEX_TX2 VGA_LVDS_SCL_C R947 2
1 2 AB12 PEX_TX2_N DACB_VREF G6 1
PCIE_GTX_C_MRX_P3 C936 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P3 AD13 F8 VGA_LVDS_SDA_C R948 2 1 Device ID
PCIE_GTX_C_MRX_N3 C937 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N3 PEX_TX3 DACB_RSET PM@ 2.2K_0402_5%
1 2 AD14
PCIE_GTX_C_MRX_P4 PCIE_GTX_MRX_P4 PEX_TX3_N
C
C938 PM@ 1 2 0.1U_0402_10V7K AD15
PEX_TX4 DACC_HSYNC
U6 NB9M-GS 0x06E9 C
PCIE_GTX_C_MRX_N4 C939 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N4 AC15 U4
PCIE_GTX_C_MRX_P5 PCIE_GTX_MRX_P5 PEX_TX4_N DACC_VSYNC
C940 PM@ 1 2 0.1U_0402_10V7K AB14
PEX_TX5 N10M-GE1-S
PCIE_GTX_C_MRX_N5 C941 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N5 AB15 T5 0x6EC

DACC
PCIE_GTX_C_MRX_P6 C942 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P6 AC16
PEX_TX5_N DACC_RED
R4 +3VS (55nm)

PCI EXPRESS
PCIE_GTX_C_MRX_N6 C943 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N6 PEX_TX6 DACC_BLUE VGA_HDMI_SCL_R R949 40NM@ 2.2K_0402_5%
1 2 AD16 PEX_TX6_N DACC_GREEN T4
PCIE_GTX_C_MRX_P7 C944 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P7 AD17
PCIE_GTX_C_MRX_N7 C945 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N7 PEX_TX7 VGA_HDMI_SDA_R R950 40NM@ 2.2K_0402_5%
1 2 AD18 PEX_TX7_N DACC_VREF R6
PCIE_GTX_C_MRX_P8 C946 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P8 AC18 V6
PCIE_GTX_C_MRX_N8 C947 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N8 PEX_TX8 DACC_RSET
1 2 AB18 PEX_TX8_N
PCIE_GTX_C_MRX_P9 C948 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P9 AB19
PCIE_GTX_C_MRX_N9 C949 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N9 PEX_TX9
1 2 AB20 PEX_TX9_N
PCIE_GTX_C_MRX_P10 C950 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P10 AD19 R1 VGA_DDCCLK_C 0_0402_5%
PCIE_GTX_C_MRX_N10 C951 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N10 PEX_TX10 I2CA_SCL VGA_DDCDATA_C R951 55NM_HDMI@
1 2 AD20 PEX_TX10_N I2CA_SDA T3
PCIE_GTX_C_MRX_P11 C952 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P11 AD21 R2 VGA_HDMI_SCL_R 1 2 VGA_HDMI_SCL
PEX_TX11 I2CB_SCL VGA_HDMI_SCL (17,23)
PCIE_GTX_C_MRX_N11 C953 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N11 AC21 R3 VGA_HDMI_SDA_R 1 2 VGA_HDMI_SDA
PEX_TX11_N I2CB_SDA +3VS VGA_HDMI_SDA (17,23)
PCIE_GTX_C_MRX_P12 C954 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_P12 AB21 A2 VGA_LVDS_SCL_C R952 55NM_HDMI@
PCIE_GTX_C_MRX_N12 C955 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N12 PEX_TX12 I2CC_SCL VGA_LVDS_SDA_C 0_0402_5%
1 2 AB22 B1
PCIE_GTX_C_MRX_P13 C956 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P13 PEX_TX12_N I2CC_SDA I2CD_SCL R953 1 2.2K_0402_5% PM@
1 2 AC22 I2C N2 2
PCIE_GTX_C_MRX_N13 C957 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N13 PEX_TX13 I2CD_SCL I2CD_SDA R955 1 2.2K_0402_5% PM@
1 2 AD22 N3 2
PCIE_GTX_C_MRX_P14 C958 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P14 PEX_TX13_N I2CD_SDA I2CE_SCL R956 1 2.2K_0402_5% PM@
1 2 AD23 PEX_TX14 I2CE_SCL Y6 2
PCIE_GTX_C_MRX_N14 C959 PM@ 1 2 0.1U_0402_10V7K PCIE_GTX_MRX_N14 AD24 W6 I2CE_SDA R957 1 2 2.2K_0402_5% PM@
PCIE_GTX_C_MRX_P15 C960 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_P15 PEX_TX14_N I2CE_SDA HDCP_SMB_CK1
1 2 AE25 A3
PCIE_GTX_C_MRX_N15 C961 PM@ 0.1U_0402_10V7K PCIE_GTX_MRX_N15 PEX_TX15 I2CH_SCL HDCP_SMB_DAI
1 2 AE26 A4
PEX_TX15_N I2CH_SDA EC_SMB_CK2
T1 EC_SMB_CK2 (5,36)
CLK_PCIE_VGA I2CS_SCL EC_SMB_DA2
(22) CLK_PCIE_VGA AB10 T2 EC_SMB_DA2 (5,36)
CLK_PCIE_VGA# PEX_REFCLK I2CS_SDA
(22) CLK_PCIE_VGA# AC10
PEX_REFCLK_N
AF10
PEX_TSTCLK_OUT JTAG_TCK
1 2 AE10 AF3 PAD T159
R958 200_0402_5% @ PEX_TSTCLK_OUT_N JTAG_TCK JTAG_TDI L23 PM@ MBK1608121YZF_0603
AG4
TEST

JTAG_TDI PAD T160

1 2 AG10 AE4 JTAG_TDO VGA_DDCCLK_C 1 2
PEX_TERMP JTAG_TDO PAD T161 VGA_DDCCLK (25)
R959 2.49K_0402_1% PM@ AF4 JTAG_TMS VGA_DDCDATA_C 1 2
B JTAG_TMS PAD T162 VGA_DDCDATA (25) B
(8,26,30,31) PLT_RST# PLT_RST# AD9 AG3 JTAG_TRST_N 1 2 10K_0402_5% L24 PM@ MBK1608121YZF_0603
PEX_RST_N JTAG_TRST_N TESTMODE
TESTMODE AD25 1R960 PM@
2 PM@ MBK1608121YZF_0603
1 2 10K_0402_5% R961 PM@ 10K_0402_5% VGA_LVDS_SCL_C L25 1 2 VGA_LVDS_SCL (24)
@ R962 VGA_LVDS_SDA_C 1 2 VGA_LVDS_SDA (24)
OSC_SPREAD D11 F9 SPDIF_IN PAD T163 L26 PM@ MBK1608121YZF_0603
OSC_OUT XTAL_SSIN SPDIF +VGASENSE
1 2 E9 W15 1 2 +VGASENSE (17,48)
@ R963 22_0402_5% XTAL_OUTBUFF VDD_SENSE R964 55NM@ 0_0402_5% 1 1 1 1
XTALOUT E10 C962
C963 C964 C965
CLK
HDA

XTAL_OUT
1

XTALIN D10 C6 VGA_HDA_RST_CODEC# R965 1 55NM_HDMI@

2 0_0402_5% HDA_RST_CODEC# PM@
PM@ PM@ PM@
XTAL_IN HDA_RST_N HDA_RST_CODEC# (8,27,34)
R966 R967 A6 HDA_SDIN1_R R968 1 55NM_HDMI@
2 10_0402_5% 12P_0402_50V8J 12P_0402_50V8J
HDA_SDI VGA_HDA_SDOUT_CODECR969 HDA_SDOUT_CODEC HDA_SDIN1 (27) 2 2 2 2
10K_0402_5% 10K_0402_5% B6 1 55NM_HDMI@
2 0_0402_5%
HDA_SDO HDA_SDOUT_CODEC (8,27,34)
PM@ PM@ B7 VGA_HDA_SYNC_CODEC R970 1 55NM_HDMI@
2 0_0402_5% HDA_SYNC_CODEC 12P_0402_50V8J 12P_0402_50V8J
HDA_SYNC VGA_HDA_BITCLK_CODECR971 HDA_BITCLK_CODEC HDA_SYNC_CODEC (8,27,34)
A7 1 55NM_HDMI@
2 HDA_BITCLK_CODEC (8,27,34)
2

HDA_BCLK 33_0402_5%

1
NB9M-GS_BGA533
If External Spread Spectrum not stuff than stuff resistor 55NM@ R972
@ 33_0402_5%
External Spread Spectrum

1
C966 U61
Y7 1 6
@ 22P_0402_50V8J REFOUT VSS @
3 4
OUT GND 2
2 XOUT MODOUT 5 1 2 OSC_SPREAD
2 1 R973 22_0402_5%
GND IN OSC_OUT 3 4 +3VS
27MHZ_16PF_X7S027000BG1H-U XIN/CLKIN VDD
1 PM@ 1
EMI 2
@ ASM3P2872AF-06OR_TSOT-23-6
A C967 C968 C969 A
20P_0402_50V8 20P_0402_50V8 0.1U_0402_16V4Z
PM@ 2 2 PM@ 1
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M PCIE,LVDS,GPIO,CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

FBAD[0..63]
FBAD[0..63] (20,21)
FBAA[0..13]
FBAA[0..13] (20,21)
FBBA[2..5]
FBBA[2..5] (21)
FBADQM#[0..7]
FBADQM#[0..7] (20,21)
FBADQS[0..7]
FBADQS[0..7] (20,21)
FBADQS#[0..7]
FBADQS#[0..7] (20,21)
D D

CKE cs0ODT
For N10M
R131 & R132 Pull-down for initialization
CKE & RESET/ODT U59C
U59B +3VS
FBAD0 D21 F26 FBAA4 VGA_LVDS_ACLK AC4 Part 3 of 5 C15
FBAD1 FBA_D0 Part 2 of 5 FBA_CMD0 FBA_RAS# (24) VGA_LVDS_ACLK VGA_LVDS_ACLK# AD4 IFPA_TXC NC
C22 J24 FBA_RAS# (20,21) (24) VGA_LVDS_ACLK# D15
FBAD2 FBA_D1 FBA_CMD1 FBAA5 VGA_LVDS_A0 IFPA_TXC_N NC +1.1VS
B22 FBA_D2 FBA_CMD2 F25 (24) VGA_LVDS_A0 V5 IFPA_TXD0 NC E15 1 2+VGASENSE +VGASENSE (16,48)
FBAD3 A22 M23 FBA_BA1 VGA_LVDS_A0# V4 F6 R974 40NM@ 0_0402_5%
FBAD4 FBA_D3 FBA_CMD3 FBBA2 FBA_BA1 (20,21) (24) VGA_LVDS_A0# VGA_LVDS_A1 IFPA_TXD0_N NC +FB_PLLAVDD
C24 N27 (24) VGA_LVDS_A1 AA5 J5
FBAD5 FBA_D4 FBA_CMD4 FBBA4 VGA_LVDS_A1# IFPA_TXD1 NC FBA_CS0#
B25 M27 (24) VGA_LVDS_A1# AA4 J22 FBA_CS0# (20)

NC
FBA_D5 FBA_CMD5 IFPA_TXD1_N NC

2
FBAD6 A25 K26 FBBA3 VGA_LVDS_A2 W4 L22 FBA_ODT
FBAD7 FBA_D6 FBA_CMD6 FBB_CKE (24) VGA_LVDS_A2 VGA_LVDS_A2# IFPA_TXD2 NC FBA_ODT (20)
A26 J25 Y4 T6 R975 R976
FBA_D7 FBA_CMD7 FBB_CKE (21) (24) VGA_LVDS_A2# IFPA_TXD2_N NC
FBAD8 D22 J27 FBB_CS0# AB4 AA6 40NM@ 0_0402_5% 0_0402_5%
FBA_D8 FBA_CMD8 FBB_CS0# (20,21) IFPA_TXD3 NC

1
FBAD9 E22 G23 FBAA11 AB5 AC19 R978 1 2 40NM@ @
FBAD10 FBA_D9 FBA_CMD9 FBA_CAS# R118 IFPA_TXD3_N NC 0_0402_5%
E24 G26 FBA_CAS# (20,21) AE9

1
FBAD11 FBA_D10 FBA_CMD10 FBA_WE# 10K_0402_5% NC
D24 J23 FBA_WE# (20,21) AB3 AG9
FBAD12 FBA_D11 FBA_CMD11 FBA_BA0 40NM@ IFPB_TXC NC
D26 FBA_D12 FBA_CMD12 M25 FBA_BA0 (20,21) AB2 IFPB_TXC_N
FBAD13 D27 K27 FBBA5 W1

2
FBAD14 FBA_D13 FBA_CMD13 FBAA12 IFPB_TXD4 STRAP0
C27 G25 V1 C7

STRAP
FBA_D14 FBA_CMD14 IFPB_TXD4_N STRAP0 STRAP0 (19)
FBAD15 B27 L24 FB_ODT W3 B9 STRAP1
FBAD16 FBA_D15 FBA_CMD15 FBAA7 FB_ODT (20,21) IFPB_TXD5 STRAP1 STRAP2 STRAP1 (19)
D16 K23 W2 A9 STRAP2 (19)
FBAD17 FBA_D16 FBA_CMD16 FBAA10 IFPB_TXD5_N STRAP2
E16 K24 AA2
FBAD18 FBA_D17 FBA_CMD17 FBA_CKE IFPB_TXD6
D17 FBA_D18 FBA_CMD18 G22 FBA_CKE (20,21) AA3 IFPB_TXD6_N
FBAD19 F18 K25 FBAA0 AB1 F10
FBA_D19 FBA_CMD19 IFPB_TXD7 STARP_REF_MIOB

1
FBAD20 D20 H22 FBAA9 AA1 F11
FBA_D20 FBA_CMD20 IFPB_TXD7_N STARP_REF_3V3

1
FBAD21 F20 M26 FBAA6 R119
C FBAD22 FBA_D21 FBA_CMD21 FBAA2 10K_0402_5% R982 R983 C
E21 FBA_D22 FBA_CMD22 H24
FBAD23 F21 F27 FBAA8 PM@ (23) VGA_HDMI_TX2 VGA_HDMI_TX2+ P4 40.2K_0402_1% 40.2K_0402_1%
FBAD24 FBA_D23 FBA_CMD23 FBAA3 VGA_HDMI_TX2- IFPC_L0 PM@ PM@
C16 J26 (23) VGA_HDMI_TX2# N4 N5 PAD T164

2
FBAD25 FBA_D24 FBA_CMD24 FBAA1 VGA_HDMI_TX1+ IFPC_L0_N BUFRST_N

GENERAL
B18 G24 M5
MEMORY INTERFACE

(23) VGA_HDMI_TX1

2
FBAD26 FBA_D25 FBA_CMD25 VGA_HDMI_TX1- IFPC_L1
C18 G27 M4 D8

LVDS/TMDS
FBA_D26 FBA_CMD26 (23) VGA_HDMI_TX1# IFPC_L1_N THERMDN PAD T165
FBAD27 D18 M24 FBA_BA2 VGA_HDMI_TX0+ L4
FBA_D27 FBA_CMD27 FBA_BA2 (20,21) (23) VGA_HDMI_TX0 IFPC_L2
FBAD28 C19 K22 FBB_ODT (23) VGA_HDMI_TX0# VGA_HDMI_TX0- K4 D9 PAD
FBA_D28 FBA_CMD28 FBB_ODT (21) IFPC_L2_N THERMDP T167
FBAD29 C21 VGA_HDMI_CLK+ H4
FBA_D29 (23) VGA_HDMI_CLK IFPC_L3
FBAD30 B21 D23 FBADQM#0 VGA_HDMI_CLK- J4
FBA_D30 FBA_DQM0 (23) VGA_HDMI_CLK# IFPC_L3_N
FBAD31 A21 C26 FBADQM#1
FBAD32 FBA_D31 FBA_DQM1 FBADQM#2
P22 FBA_D32 FBA_DQM2 D19 F5 IFPE_L0 ROM_CS_N B10
FBAD33 P24 B19 FBADQM#3 F4
FBAD34 FBA_D33 FBA_DQM3 FBADQM#4 IFPE_L0_N ROM_SCLK

SERIAL
R23 FBA_D34 FBA_DQM4 T24 E4 IFPE_L1 ROM_SCLK C9 ROM_SCLK (19)
FBAD35 R24 T26 FBADQM#5 FB_ODT D5
FBAD36 FBA_D35 FBA_DQM5 FBADQM#6 FBB_ODT IFPE_L1_N ROM_SI
T23 AA23 C3 A10 ROM_SI (19)
FBAD37 FBA_D36 FBA_DQM6 FBADQM#7 FBA_ODT IFPE_L2 ROM_SI
U24 AB27 C4
FBAD38 FBA_D37 FBA_DQM7 IFPE_L2_N ROM_SO
V23 B3 C10 ROM_SO (19)
FBA_D38 IFPE_L3 ROM_SO

R130 1

R129 1

R128 1
10K_0402_5%

10K_0402_5%

10K_0402_5%
FBAD39 V24 B24 FBADQS#0 B4
FBAD40 FBA_D39 FBA_DQS_RN0 FBADQS#1 IFPE_L3_N
N25 D25
FBAD41 FBA_D40 FBA_DQS_RN1 FBADQS#2
N26 FBA_D41 FBA_DQS_RN2 E18 IFPE_AUX_N D4
FBAD42 R25 A18 FBADQS#3 40NM@ 55NM@ R985 1 2 @ 1K_0402_5% AB6 D3
FBAD43 FBA_D42 FBA_DQS_RN3 FBADQS#4 R986 1 IFPAB_RSET IFPE_AUX IFPC_AUX_N
R26 R22 2 @ 1K_0402_5% M6 G5

2
FBAD44 FBA_D43 FBA_DQS_RN4 FBADQS#5 R987 1 1K_0402_5% IFPE_RSET IFPC_AUX_N IFPC_AUX
T25 R27 2 R5 G4
FBAD45 FBA_D44 FBA_DQS_RN5 FBADQS#6 PM@ IFPC_RSET IFPC_AUX
V26 Y24
FBAD46 FBA_D45 FBA_DQS_RN6 FBADQS#7 40NM@
V25 AA27
FBAD47 FBA_D46 FBA_DQS_RN7 NB9M-GS_BGA533
V27
FBAD48 FBA_D47 FBADQS0 55NM@
FBAD49
V22
W22
FBA_D48
FBA_D49
FBA_DQS_WP0
FBA_DQS_WP1
A24
C25 FBADQS1 +1.8VS for GT21x request
FBAD50 W23 E19 FBADQS2
FBAD51 FBA_D50 FBA_DQS_WP2 FBADQS3
W24 A19
FBA_D51 FBA_DQS_WP3

1
FBAD52 AA22 T22 FBADQS4
FBAD53 FBA_D52 FBA_DQS_WP4 FBADQS5 R988 +3VS
AB23 T27
B FBAD54 FBA_D53 FBA_DQS_WP5 FBADQS6 1.3K_0402_1% B
AB24 FBA_D54 FBA_DQS_WP6 AA24
FBAD55 AC24 AA26 FBADQS7 @
FBAD56 FBA_D55 FBA_DQS_WP7
W25
1.27V~0.9V

2
FBAD57 FBA_D56 FB_VREF1 10mil
W26 FBA_D57 FB_VREF A16

2
FBAD58 W27
FBAD59 FBA_D58 R989
AA25 F24 FBACLK0 (20)
FBA_D59 FBA_CLK0

1
FBAD60 AB25 F23 1 4.7K_0402_5%
FBAD61 FBA_D60 FBA_CLK0_N FBACLK0# (20)
AB26 C970 R991 40NM_HDMI@
FBA_D61

2
FBAD62 AD26 N24 0.01U_0402_16V7K 1.3K_0402_1%
FBACLK1 (21)

1
FBAD63 FBA_D62 FBA_CLK1 @ @ Q42A 40NM_HDMI@
AD27 FBA_D63 FBA_CLK1_N N23 FBACLK1# (21) +1.8VS 2 IFPC_AUX 1 6 VGA_HDMI_SCL (16,23)
2
M22 FBA_DEBUG 1 2
FBA_DEBUG R992 60.4_0402_1% 2N7002DW-T/R7_SOT363-6
NB9M-GS_BGA533 PM@
55NM@
2N7002DW-T/R7_SOT363-6
IFPC_AUX_N 4 3 VGA_HDMI_SDA (16,23)
Q42B 40NM_HDMI@

5
2
R993
4.7K_0402_5%
40NM_HDMI@

1
+3VS

A A

5V PULL UP IN CONNECTER SIDE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M Memory
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 17 of 51
5 4 3 2 1
 5 4 3 2 1

FOR N10M 40NM , 1.1VS needs to be changed to 1.05VS

PLACE NEAR BGA +1.8VS

+VGA_CORE 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U 6.3V K X5R 0603

13.56A NEAR BALL U59D C971

1
C972
1
C973
1
C974
1 1
C975 C976
1
@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J9 A13 PM@ PM@ PM@ PM@ PM@
VDD FBVDDQ 2 2 2 2 2 2
D 1 J10 VDD FBVDDQ B13 D

220U_D2_4VM
1 1 1 1 1 1 J12 C13 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U 6.3V K X5R 0603
+ C978 C979 C980 C981 C982 C983 VDD FBVDDQ
J13 VDD FBVDDQ D13

C977
L9 VDD FBVDDQ D14
PM@ PM@ PM@ PM@ PM@ PM@ PM@ M9 E13
2 2 2 2 2 2 2 VDD Part 4 of 5 FBVDDQ
M11
M17
VDD
VDD
FBVDDQ
FBVDDQ
F13
F14 PLACE BELOW GPU FBAVDDQ=2.24A +1.8VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z N9 F15
VDD FBVDDQ 4700P_0402_25V7K 4700P_0402_25V7K 1U_0603_10V4Z
N11 VDD FBVDDQ F16
N12 VDD FBVDDQ F17 1 1 1 1 1 1
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K N13 F19 C984 C985 C986 C987 C988 C989
VDD FBVDDQ
N14 VDD FBVDDQ F22
1 1 1 1 1 1 N15 H23 PM@ PM@ PM@ PM@ PM@ PM@
VDD FBVDDQ 2 2 2 2 2 2
N16 VDD FBVDDQ H26
C990 C991 C992 C993 C994 C995 N17 J15 4700P_0402_25V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z
PM@ PM@ PM@ PM@ PM@ PM@ VDD FBVDDQ +1.8VS
N19 VDD FBVDDQ J16
2 2 2 2 2 2 P11 J18 4700P_0402_25V7K 0.022U_0402_16V7K 1U_0603_10V4Z
0.47U_0402_6.3V6K VDD FBVDDQ
P12 VDD FBVDDQ J19 1 1 1 1 1
P13 L19 C996 C997 C998 C999 C1000
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K VDD FBVDDQ
P14 VDD FBVDDQ L23
P15 L26 PM@ PM@ PM@ PM@ PM@
VDD FBVDDQ 2 2 2 2 2
P16 VDD FBVDDQ M19
P17 N22 4700P_0402_25V7K 0.1U_0402_16V4Z

POWER
4.7U 6.3V K X5R 0603 VDD FBVDDQ
R9 VDD FBVDDQ U22
R11 VDD FBVDDQ Y22
1 1 R12 VDD
C1001 C1002
PM@ PM@ NEAR BGA R13
R14
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ
AG6
AF6 0.1U_0402_16V4Z 0.47U_0402_6.3V6K
+1.1VS
R15 VDD PEX_IOVDDQ AE6 1 1 1 1
2 2 R16
R17
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ
AD6
AC13 C1003 C1004 C1005 C1006 PEX_IOVDDQ=1.6A
4.7U 6.3V K X5R 0603 PM@ PM@ PM@ PM@
C
T9
T11
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ
AC7
AB17 2 2 2 2 PEX_IOVDD=500mA C
0.1U_0402_16V4Z 0.47U_0402_6.3V6K
T17
U9
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ
AB16
AB13 PEX_PLLVDD=100mA
U19 VDD PEX_IOVDDQ AB9
+3VS W9 AB8 1U_0402_6.3V4Z 10U_0805_10V4Z
VDD PEX_IOVDDQ

NEAR BGA NEAR BALL

W 10
W 12
VDD
VDD
PEX_IOVDDQ
PEX_IOVDD
AB7
AG7
1
NEAR BALL 1 1 1
0.1U_0402_16V4Z W 13 AF7 C1007 C1008 C1009 C1010
VDD PEX_IOVDD PM@ PM@ PM@ PM@
80mA 2 1 1 W 18
W 19
VDD
VDD
PEX_IOVDD
PEX_IOVDD
AE7
AD8 2 2 2 2
C1011 C1012 C1013 AD7 4.7U 6.3V K X5R 0603 10U_0805_10V4Z
PM@ PM@ PM@ PEX_IOVDD
A12 VDD33 PEX_IOVDD AC9
1 2 2 B12
1U_0603_10V4Z 0.1U_0402_16V4Z VDD33
C12 VDD33
D12 AF9 +PEX_PLLVDD MBK1608121YZF_0603
VDD33 PEX_PLLVDD +1.1VS_PLL 0.1U_0402_16V4Z 1U_0402_6.3V6K +1.1VS
E12 VDD33 VID_PLLVDD K6 2 1
L27 PM@
12~16mil
NEAR BALL PLLVDD=65mA
F12 VDD33 SP_PLLVDD L6 1 1 1 1 1
PLLVDD K5
+IFPA_IOVDD C1014 C1015 C1016 C1017 C1018
+1.8VS L28 +IFPB_IOVDD
V3
V2
IFPA_IOVDO
IFPB_IOVDD FB_PLLAVDD R19 +FB_PLLAVDD
2
PM@
2
PM@
2
PM@
2
PM@
2
PM@ SP_PLLVDD=25mA
MBK1608121YZF_0603 +IFPC_IOVDD
1 2 4700P_0402_25V7K 470P_0402_50V7K
12~16mil 10K_0402_5% R994
J6 IFPC_IOVDD
T19 +FB_DLLAVDD 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K VID_PLLVDD=50mA
PM@ FB_DLLAVDD
1 1 2 1 PM@ H6 IFPE_IOVDD
AG2 +DACA_VDD
C1019 C1020 C1021 +IFPAB_PLLVDD DACA_VDD +DACB_VDD
AD5 IFPAB_PLLVDD DACB_VDD D7 1 PM@ 2
PM@ PM@ PM@ +IFPC_PLLVDD P6 W5 +DACC_VDD R9951 2 10K_0402_5%
2 2 IFPC_PLLVDD DACC_VDD
2 1 PM@ N6 IFPE_PLLVDD
R996 @ 10K_0402_5%
4.7U 6.3V K X5R 0603 10K_0402_5% R997 +FB_PLLAVDD +1.1VS
110mA FB_CAL_PD_VDDQ B15 1 2 R998 +1.8VS
PM@ 30.1_0402_1% L30
NEAR BGA NEAR BALL +FB_PLLAVDD 0.1U_0402_16V4Z 1 2
B NB9M-GS_BGA533 MBK1608121YZF_0603 B
+1.8VS L31 55NM@ PM@
1 1 1
MBK1608121YZF_0603 +1.1VS
1 2 4700P_0402_25V7K 470P_0402_50V7K C1022 C1023 C1024
PM@ 1 1 L32 PM@ PM@ PM@
+PEX_PLLVDD 0.1U_0402_16V4Z 10U_0805_10V4Z 1 2 2 2 2
C1025 C1026 C1027 1 1 1 1 MBK1608121YZF_0603
1U_0402_6.3V4Z
PM@ PM@ PM@ PM@ 0.01U_0402_16V7K 4.7U 6.3V K X5R 0603
2 2
C1030

C1028 C1029 C1031

4.7U 6.3V K X5R 0603 PM@ PM@ PM@ PM@ L34
2 2 2 2 +FB_DLLAVDD 0.1U_0402_16V4Z 1 2
0.01U_0402_16V7K MBK1608121YZF_0603
1 1 1 PM@

IFPC_PLLVDD: please add option to support NEAR BALL NEAR BGA C1032 C1033 C1034
PM@ PM@ PM@
both 1.8V (for G9X) and 3.3V(for GT21X) 2 2 2

0.01U_0402_16V7K 4.7U 6.3V K X5R 0603

+1.8VS L35 R996
MBK1608121YZF_0603
4700P_0402_25V7K +IFPC_PLLVDD

+3VS
1
55NM_HDMI@
2
260mAL36NEAR BGA
+1.8VS
37.4_0402_1%
1 1 MBK1608121YZF_0603 40NM@ L38
C1035 C1036 55NM@ MBK1608121YZF_0603 +3VS
L37 PM_HDMI@ PM_HDMI@ C1036 1 2 4700P_0402_25V7K +IFPAB_PLLVDD PM@
+DACA_VDD 4700P_0402_25V7K 4.7U 6.3V K X5R 0603 2
1 2
40NM_HDMI@ 2 2
+1.1VS
1 1
NEAR BALL 1

MBK1608121YZF_0603 0_0402_5% C1037 C1038

+1.1VS 4.7U 6.3V K X5R 0603 PM_NOHDMI@ L39
2
PM@
2
PM@ 110mA 1
C1039
1
C1040
1
C1041
L40 1 2 PM@ PM@ PM@
A MBK1608121YZF_0603 40NM@ 4.7U 6.3V K X5R 0603 A
PM_HDMI@ MBK1608121YZF_0603 2 2 2
1 2 4700P_0402_25V7K +IFPC_IOVDD
IFPAB_PLLVDD: please add option to support 470P_0402_50V7K
1 1 1
NEAR BGA C1042 C1043 C1044 both 1.8V(for G9X) and 1.05V(for GT21X)
PM_HDMI@ PM_HDMI@ PM_HDMI@ C1044
2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5% Issued Date 2009/04/23 Deciphered Date 2010/05 Title
4.7U 6.3V K X5R 0603 470P_0402_50V7K PM_NOHDMI@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB10M Power
Size Document Number Rev
NEAR BALL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

A total of 8 signals are required for GB1 strapping this includes

2 reference signals
6 physical strapping pins
4 logical strapping bits
U59E A total of 24 logical strapping bits are available
B2 U2
GND Part 5 of 5 GND
B5 GND GND U5
B8 U11
GND GND
B11 GND GND U12
B14 U13
GND GND +3VS
B17 GND GND U14
D D
B20 GND GND U15
B23 GND GND U16
B26 GND GND U17
E2 U23
GND GND

1
E5 U26
GND GND
E8 GND GND V9 R148 pop 25K ohm R999 R1000 R1001 R1002 R1003 R1004

10K_0402_1%

10K_0402_5%

45.3K_0402_1%
E11 V19 @ @ PM@ @ @ 55NM@
GND GND when use N10M-GE1-S(55nm)

4.99K_0402_1%
E14 W11 R999
GND GND

10K_0402_5%

2K_0402_5%
E17 W14

2
GND GND
E20 W17
GND GND STRAP2
E23 GND GND Y2 (17) STRAP2 24.9K_0402_1%
E26 Y5 STRAP1 55NM@
GND GND (17) STRAP1 STRAP0
H2 GND GND Y23 (17) STRAP0
H5 Y26 ROM_SCLK
GND GND (17) ROM_SCLK ROM_SI
J11 AC2 (17) ROM_SI
GND GND ROM_SO
J14 AC5 (17) ROM_SO
GND GND
J17 GND GND AC6
K9 AC8
GND GND

1
K19 GND GND AC11
L2 AC14 R1005 R1006 R1007 R1008 R1009 R1010
GND GND @ 40NM@ @ 55NM@ X76@ 40NM@
L5 AC17
GND GND

10K_0402_5%

35K_0402_1%

10K_0402_5%

15K_0402_1%

20K_0402_1%

10K_0402_1%
GND
L11 AC20
GND GND
L12 AC23

2
GND GND
L13 GND GND AC26
L14 AF2 R1002 R1005
GND GND
L15 GND GND AF5
L16 AF8
GND GND R1006
L17
GND GND
AF11 15K_0402_1% 24.9K_0402_1%
M12 AF14 40NM@ 40NM@
GND GND
M13 GND GND AF17
M14
GND GND
AF20 10K_0402_5%
M15 AF23 55NM@
C GND GND R1012 C
M16 GND GND AF26
P2 T16
GND GND
P5
P9
GND
GND
GND
GND
T15
T14 44.2_0402_1% GB1 Family GPU Strap Qptions X76
P19 40NM@
GND R1011 1 PM@
P23 W16 2 0_0402_5%
GND GND_SENSE
P26 GND GPU FB Memory (DDR2) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
T12 A15 R1012 1 55NM@ 2 30.1_0402_1%
GND FB_CAL_PU_GND R1013
T13 GND
FB_CAL_TERM_GND
B16 R1013 1 2 40.2_0402_1% 64Mx16 PU 5K PD 15K PD 20K PU 25K PD 10K PU 45K
@ Samsung
40.2_0402_1%
NB9M-GS_BGA533 40NM@
55NM@

N10M-GE1-S 64Mx16 PU 5K PD 15K PD 5K PU 25K PD 10K PU 45K

Memory/PKG FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND (0x6EC) Hynix
55nm
DDR2 30.1ohm 30.1ohm NC
GDDR3 33.2ohm 44.2ohm 40.2ohm 64Mx16 PU 5K PD 15K PD 15K PU 25K PD 10K PU 45K
Qimonda
To update for NV PUN-03304-001_V06 (2008/4/01) 4/23 update strap1 10K to 35K
according to N10M latest PUN
GPU FB Memory (DDR2) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0

64Mx16 PD 10K PD 15K PD 10K PU 10K PD 35K PU 45K

B
Samsung B
U59

NB10M-GS-S
40NM@ N10M-GS 64Mx16 PD 10K PD 15K PD 5K PU 10K PD 35K PU 45K
(0x6EC) Hynix
40nm

64Mx16 PD 10K PD 15K PD 15K PU 10K PD 35K PU 45K

Qimonda

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

U6 U28
FBA_BA0 L2 B9 FBAD7 FBA_BA0 L2 B9 FBAD25
FBA_BA1 BA0 DQ15 FBAD3 FBA_BA1 BA0 DQ15 FBAD29
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD4 D9 FBAD24
FBAA12 DQ13 FBAD0 FBAA12 DQ13 FBAD31
R2 D1 R2 D1
FBAA11 A12 DQ12 FBAD1 FBAA11 A12 DQ12 FBAD28
P7 A11 DQ11 D3 P7 A11 DQ11 D3
FBAA10 M2 D7 FBAD6 FBAA10 M2 D7 FBAD27
FBAA9 A10/AP DQ10 FBAD2 FBAA9 A10/AP DQ10 FBAD30
P3 A9 DQ9 C2 P3 A9 DQ9 C2
FBAA8 P8 C8 FBAD5 FBAA8 P8 C8 FBAD26
FBAA7 A8 DQ8 FBAD10 FBAA7 A8 DQ8 FBAD18
P2 F9 P2 F9
FBAA6 A7 DQ7 FBAD15 FBAA6 A7 DQ7 FBAD23
N7 A6 DQ6 F1 N7 A6 DQ6 F1
FBAA5 N3 H9 FBAD8 FBAA5 N3 H9 FBAD17
FBAA4 A5 DQ5 FBAD13 FBAA4 A5 DQ5 FBAD21
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBAA3 N2 H3 FBAD12 FBAA3 N2 H3 FBAD19
FBAA2 A3 DQ3 FBAD9 FBAA2 A3 DQ3 FBAD16
M7 A2 DQ2 H7 M7 A2 DQ2 H7
D FBAA1 M3 G2 FBAD14 FBAA1 M3 G2 FBAD22 FBBA[2..5] D
FBAA0 A1 DQ1 FBAD11 FBAA0 A1 DQ1 FBAD20 (17,21) FBBA[2..5]
M8 A0 DQ0 G8 M8 A0 DQ0 G8
FBAD[0..63]
FBACLK0# FBACLK0# (17,21) FBAD[0..63]
K8 A9 K8 A9
FBACLK0 CK VDDQ1 FBACLK0 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C3 C3 FBAA[0..12]
FBA_CKE VDDQ3 FBA_CKE VDDQ3 (17,21) FBAA[0..12]
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7
VDDQ5 C9 VDDQ5 C9
E9 E9 FBADQS[0..7]
VDDQ6 +1.8VS VDDQ6 +1.8VS (17,21) FBADQS[0..7]
VDDQ7 G1 VDDQ7 G1
FBACS0#_V L8 G3 FBACS0#_V L8 G3
CS VDDQ8 CS VDDQ8 FBADQS#[0..7]
VDDQ9 G7 VDDQ9 G7 (17,21) FBADQS#[0..7]
FBA_WE# K3 G9 1 FBA_WE# K3 G9
WE VDDQ10 WE VDDQ10
FBA_RAS# K7 A1 C184 + PM@ FBA_RAS# K7 A1 FBADQM#[0..7]
RAS VDD1 RAS VDD1 (17,21) FBADQM#[0..7]
E1 220U_D2_4VM_R15 E1
FBA_CAS# VDD2 FBA_CAS# VDD2
L7 J9 L7 J9
CAS VDD3 2 CAS VDD3 FBA_BA0
VDD4 M9 VDD4 M9 (17,21) FBA_BA0
FBADQM#1 F3 R1 FBADQM#2 F3 R1
FBADQM#0 LDM VDD5 FBADQM#3 LDM VDD5 FBA_BA1
B3 B3 (17,21) FBA_BA1
UDM UDM
J1 J1
VDDL VDDL
VSSDL J7 1 1 VSSDL J7 1 1
FBAODT_V K9 C630 C617 FBAODT_V K9 C92 C98
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBA_CKE
(17,21) FBA_CKE
PM@ PM@ PM@ PM@
+1.8VS FBADQS1 F7 2 2 FBADQS2 F7 2 2 FBA_RAS#
FBADQS#1 LDQS FBADQS#2 LDQS (17,21) FBA_RAS#
E8 A7 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBA_CAS#
VSSQ2 B2 VSSQ2 B2 (17,21) FBA_CAS#
VSSQ3 B8 VSSQ3 B8
1

D2 D2 FBA_WE#
FBADQS0 VSSQ4 FBADQS3 VSSQ4 (17,21) FBA_WE#
R480 B7 D8 B7 D8
C +VRAM_VREFA 1K_0402_1% FBADQS#0 UDQS VSSQ5 +VRAM_VREFA FBADQS#3 UDQS VSSQ5 C
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
PM@ F2 F2
VSSQ7 VSSQ7 FBABA2
F8 F8 (17,21) FBA_BA2
2

VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
(SSTL-1.8) VREF = .5*VDDQ H8 (SSTL-1.8) VREF = .5*VDDQ H8
VSSQ10 VSSQ10
1

1 C613 A2
NC#A2
PM@ 1 A2
NC#A2
R479 0.047U_0402_16V4Z E2 A3 C91 E2 A3
1K_0402_1% PM@ FBABA2 NC#E2 VSS1 0.047U_0402_16V4Z FBABA2 NC#E2 VSS1
L1 E3 L1 E3
BA2 VSS2 BA2 VSS2
PM@ Close to U6 R3 NC#R3 VSS3 J3 Close to U28 R3 NC#R3 VSS3 J3
2 R7 N1 2 R7 N1
2

NC#R7 VSS4 NC#R7 VSS4 FBA_ODT FBAODT_V

R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 (17) FBA_ODT 1 R196 2
0_0402_5%
40NM@
HYB18T1G161C2F-20_PG-TFBGA84 HYB18T1G161C2F-20_PG-TFBGA84 FB_ODT 1 R193 2
(17,21) FB_ODT
X76@ X76@ 0_0402_5%
55NM@

FBA_CS0# 1 R194 2 FBACS0#_V

(17) FBA_CS0#
0_0402_5%
DDR2 BGA MEMORY DDR2 BGA MEMORY 40NM@
FBB_CS0# 1 R195 2
(17,21) FBB_CS0#
0_0402_5%
+1.8VS 55NM@
+1.8VS
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 C110 C113 C130 C137 C143 C103 C100 C158 Close to U5
C621 C622 C624 C626 C625 C619 C620 C615 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ FBACLK0
(17) FBACLK0
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

1
B B
R104
475_0402_1%

R104 55NM@

2
220_0402_1% FBACLK0#
(17) FBACLK0#
40NM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

U29 U7
FBA_BA0 L2 B9 FBAD40 FBA_BA0 L2 B9 FBAD39
FBA_BA1 BA0 DQ15 FBAD45 FBA_BA1 BA0 DQ15 FBAD34
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 FBAD41 D9 FBAD38
FBAA12 DQ13 FBAD46 FBAA12 DQ13 FBAD35
R2 D1 R2 D1
FBAA11 A12 DQ12 FBAD47 FBAA11 A12 DQ12 FBAD32
P7 A11 DQ11 D3 P7 A11 DQ11 D3
FBAA10 M2 D7 FBAD43 FBAA10 M2 D7 FBAD36
FBAA9 A10/AP DQ10 FBAD44 FBAA9 A10/AP DQ10 FBAD33
P3 A9 DQ9 C2 P3 A9 DQ9 C2
FBAA8 P8 C8 FBAD42 FBAA8 P8 C8 FBAD37
FBAA7 A8 DQ8 FBAD61 FBAA7 A8 DQ8 FBAD55
P2 F9 P2 F9
FBAA6 A7 DQ7 FBAD62 FBAA6 A7 DQ7 FBAD51
N7 A6 DQ6 F1 N7 A6 DQ6 F1
FBBA5 N3 H9 FBAD58 FBBA5 N3 H9 FBAD52 FBAD[0..63]
FBBA4 A5 DQ5 FBAD56 FBBA4 A5 DQ5 FBAD50 (17,20) FBAD[0..63]
N8 A4 DQ4 H1 N8 A4 DQ4 H1
FBBA3 N2 H3 FBAD59 FBBA3 N2 H3 FBAD49
FBBA2 A3 DQ3 FBAD57 FBBA2 A3 DQ3 FBAD54 FBAA[0..12]
M7 A2 DQ2 H7 M7 A2 DQ2 H7 (17,20) FBAA[0..12]
D FBAA1 FBAD63 FBAA1 FBAD48 D
M3 A1 DQ1 G2 M3 A1 DQ1 G2
FBAA0 M8 G8 FBAD60 FBAA0 M8 G8 FBAD53
A0 DQ0 A0 DQ0 FBBA[2..5]
(17) FBBA[2..5]
FBACLK1# K8 A9 FBACLK1# K8 A9
FBACLK1 CK VDDQ1 FBACLK1 CK VDDQ1 FBADQS[0..7]
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 (17,20) FBADQS[0..7]
C3 C3
FBB_CKE_V VDDQ3 FBB_CKE_V VDDQ3
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7
C9 C9 FBADQS#[0..7]
VDDQ5 VDDQ5 (17,20) FBADQS#[0..7]
E9 E9
VDDQ6 +1.8VS VDDQ6 +1.8VS
VDDQ7 G1 VDDQ7 G1
FBB_CS0# L8 G3 FBB_CS0# L8 G3 FBADQM#[0..7]
CS VDDQ8 CS VDDQ8 (17,20) FBADQM#[0..7]
VDDQ9 G7 VDDQ9 G7
FBA_WE# K3 G9 FBA_WE# K3 G9
WE VDDQ10 WE VDDQ10 FBA_BA0
(17,20) FBA_BA0
FBA_RAS# K7 A1 FBA_RAS# K7 A1
RAS VDD1 RAS VDD1 FBA_BA1
VDD2 E1 VDD2 E1 (17,20) FBA_BA1
FBA_CAS# L7 J9 FBA_CAS# L7 J9
CAS VDD3 CAS VDD3
VDD4 M9 VDD4 M9
FBADQM#7 F3 R1 FBADQM#6 F3 R1
FBADQM#5 LDM VDD5 FBADQM#4 LDM VDD5
B3 B3
UDM UDM
J1 J1
VDDL VDDL FBA_RAS#
VSSDL J7 1 1 VSSDL J7 1 1 (17,20) FBA_RAS#
FBBODT_V K9 C305 C224 FBBODT_V K9 C654 C655
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBA_CAS#
(17,20) FBA_CAS#
PM@ PM@ PM@ PM@
FBADQS7 F7 2 2 FBADQS6 F7 2 2 FBA_WE#
+1.8VS FBADQS#7 LDQS FBADQS#6 LDQS (17,20) FBA_WE#
E8 A7 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBB_CS0#
VSSQ2 B2 VSSQ2 B2 (17,20) FBB_CS0#
VSSQ3 B8 VSSQ3 B8
1

D2 D2 FBA_BA2
FBADQS5 VSSQ4 FBADQS4 VSSQ4 (17,20) FBA_BA2
R184 B7 D8 B7 D8
C +VRAM_VREFB 1K_0402_1% FBADQS#5 UDQS VSSQ5 +VRAM_VREFB FBADQS#4 UDQS VSSQ5 C
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
PM@ F2 F2
VSSQ7 VSSQ7
F8 F8
2

VSSQ8 VSSQ8
J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
(SSTL-1.8) VREF = .5*VDDQ H8 H8
VSSQ10 VSSQ10
1

(SSTL-1.8) VREF = .5*VDDQ

1 C319 A2
NC#A2 1 A2
NC#A2
R190 0.047U_0402_16V4Z E2 A3 C672 E2 A3
1K_0402_1% PM@ FBA_BA2 NC#E2 VSS1 0.047U_0402_16V4Z FBA_BA2 NC#E2 VSS1
L1 E3 L1 E3
BA2 VSS2 BA2 VSS2
PM@ Close to U29 R3 NC#R3 VSS3 J3 PM@ R3 NC#R3 VSS3 J3
2 R7 N1 Close to U7 2 R7 N1
2

NC#R7 VSS4 NC#R7 VSS4 FBB_ODT FBBODT_V

R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 (17) FBB_ODT 1 R198 2
0_0402_5%
40NM@
HYB18T1G161C2F-20_PG-TFBGA84 HYB18T1G161C2F-20_PG-TFBGA84 FB_ODT 1 R197 2
(17,20) FB_ODT
X76@ X76@ 0_0402_5%
55NM@

FBA_CKE 1 R199 2 FBB_CKE_V

(17,20) FBA_CKE
DDR2 BGA MEMORY 0_0402_5%
DDR2 BGA MEMORY 55NM@
FBB_CKE 1 R200 2
(17) FBB_CKE
0_0402_5%
40NM@
+1.8VS FBACLK1
+1.8VS (17) FBACLK1
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 C668 C666 C665 C659 C656 C647 C642 C667

1
C272 C234 C225 C304 C269 C263 C239 C233 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ R154
2 2 2 2 2 2 2 2 475_0402_1%
2 2 2 2 2 2 2 2 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 55NM@
B 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K B

2
FBACLK1#
(17) FBACLK1#
Close to U7

R154

220_0402_1%
40NM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 21 of 51
5 4 3 2 1
 5 4 3 2 1

+3VSM_CK505 +3VS
FSC FSB FSA CPU SRC PCI REF DOT_96 USB
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS R668 1 2 0_0805_5%
1 1 1 1 1 1 1
R669 1 2 0_0402_5% @ @
0 0 0 266 100 33.3 14.318 96.0 48.0 C811 C812 C813 C814 C815 C816 C817
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R670 R671
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
0 0 1 133 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6
+1.5VS R672 1 2 @ 0_0805_5% (28,30) ICH_SMBDATA 6 1 CLK_SMBDATA
+VDD_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 @ Q1A
+VCCP R673 1 2 0_0805_5%

2
1 1 1 1 1 1 1 +3VS
D D
0 1 1 166 100 33.3 14.318 96.0 48.0

5
C818 C819 C820 C821 C822 C823 C824
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ Q1B
2 2 2 2 2 2 2
1 0 0 333 100 33.3 14.318 96.0 48.0 (28,30) ICH_SMBCLK 3 4 CLK_SMBCLK

2N7002DW-T/R7_SOT363-6
1 0 1 100 100 33.3 14.318 96.0 48.0 SA000020K00 (Silego : SLG8SP556VTR )
<BOM Structure>
1 1 0 400 100 33.3 14.318 96.0 48.0 SA000020H00 (ICS : ICS9LPRS387AKLFT)
<BOM Structure> R674 1 2 0_0402_5%

+3VSM_CK505 U30
1 1 1 Reserved 9 CLK_SMBDATA
SDA CLK_SMBDATA (14,15)
55
VDD_SRC CLK_SMBCLK
10
SCL CLK_SMBCLK (14,15)
6
VDD_REF
+VCCP 12 71 CLK_CPU_BCLK
VDD_PCI CPU_0 CLK_CPU_BCLK (5)
72 70 CLK_CPU_BCLK#
VDD_CPU CPU_0# CLK_CPU_BCLK# (5)
2

@ 19 68 CLK_MCH_BCLK
VDD_48 CPU_1 CLK_MCH_BCLK (8)
R675
56_0402_5% 27 67 CLK_MCH_BCLK#
+VDD_CK505 VDD_PLL3 CPU_1# CLK_MCH_BCLK# (8)
1

FSA R680 2 1 2.2K_0402_5% R676 1 2 1K_0402_5% MCH_CLKSEL0 (8)

66 24 R_CLK_DOT R677 1 2 GM@ 0_0402_5%
VDD_CPU_IO SRC_0/DOT_96 CLK_MCH_DREFCLK (8)
R678 1 2 0_0402_5% R681 1 2 PM@ 0_0402_5%
(6) CPU_BSEL0 CLK_PCIE_VGA (16)
31 25 R_CLK_DOT# R682 1 2 GM@ 0_0402_5%
CLK_MCH_DREFCLK# (8)
1

VDD_PLL3_IO SRC_0#/DOT_96# R683 PM@ 0_0402_5%

1 2 CLK_PCIE_VGA# (16)
@ 62
C R679 VDD_SRC_IO C
28 MCH_SSCDREFCLK (8)
1K_0402_5% LCDCLK/27M
52
VDD_SRC_IO
29 MCH_SSCDREFCLK# (8) SRC PORT LIST
2

LCDCLK#/27M_SS
23
VDD_IO

R684 1
CARD@
2 12_0402_5%
38
VDD_SRC_IO SRC_2
32 CLK_MCH_3GPLL
CLK_MCH_3GPLL (8) PORT DEVICE
+VCCP (37) CLK_48M_CR 33 CLK_MCH_3GPLL#
SRC_2# CLK_MCH_3GPLL# (8)
R685 1 2 12_0402_5% FSA 20
SRC0 MCH_DREFCLK
1

(28) CLK_48M_ICH USB_0/FS_A CLK_PCIE_EXP

@ FSB 2
SRC_3
35 CLK_PCIE_EXP (30) SRC2 MCH_3GPLL
R686 FS_B/TEST_MODE CLK_PCIE_EXP#
1K_0402_5% R687 1 2 33_0402_5% FSC 7
SRC_3#
36 CLK_PCIE_EXP# (30) SRC3 PCIE_EXP#
(28) CLK_14M_ICH REF_0/FS_C/TEST_
SRC4
2

FSB R688 1 2 1K_0402_5% R689 1 2 @ 33_0402_5% 8 39 CLK_PCIE_WLAN2 T153

MCH_CLKSEL1 (8) (38) CLK_14M_SIO REF_1 SRC_4

(6) CPU_BSEL1
R690 1 2 0_0402_5% 40 CLK_PCIE_WLAN2# T154
SRC6 PCIE_WLAN
CK_PWRGD SRC_4#
1
CKPWRGD/PD# SRC7 PCIE_WLAN1
1

(28) CK_PWRGD
@ CLK_PCIE_WLAN
R691
11
NC SRC_6
57 T155 SRC8
0_0402_5% CLK_PCIE_WLAN#
SRC_6#
56 T156 SRC9 PCIE_LAN
2

PM_STP_CPU#
(28) H_STP_CPU#
53
CPU_STOP#
61 CLK_PCIE_WLAN1
CLK_PCIE_WLAN1 (30)
SRC10 PCIE_ICH
PM_STP_PCI# SRC_7
(28) H_STP_PCI#
54
PCI_STOP#
60 CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1# (30)
SRC11 PCIE_SATA
+VCCP SRC_7#
CLK_XTAL_IN 5
XTAL_IN
64
SRC_8/CPU_ITP
1

CLK_XTAL_OUT 4 +3VS
B @ XTAL_OUT B
63
R692 SRC_8#/CPU_ITP# SATA_CLKREQ#_R R693 10K_0402_5%
2 1
1K_0402_5% EXP_CLKREQ# R694 2 1 10K_0402_5%
13 44 CLK_PCIE_LAN WLAN_CLKREQ1# R695 2 1 10K_0402_5%
CLK_PCIE_LAN (31)
2

R696 1 PCI_1 SRC_9

FSC 2 10K_0402_5% R697 1 2 1K_0402_5% MCH_CLKSEL2 (8)
MCH_CLKREQ#_R R698 2 1 10K_0402_5%
R700 1 2 @ 33_0402_5% PCI2_TME 14 45 CLK_PCIE_LAN# CLKREQ_LAN# R701 2 1 10K_0402_5%
(38) CLK_PCI_DB PCI_2 SRC_9# CLK_PCIE_LAN# (31)
R699 1 2 0_0402_5% WLAN_CLKREQ# R702 2 1 10K_0402_5%
(6) CPU_BSEL2
15 WLAN_CLKREQ2# R703 2@ 1 10K_0402_5%
1

PCI_3 CLK_PCIE_ICH @
50 CLK_PCIE_ICH (28)
@ R705 1 33_0402_5% PCI4_SEL SRC_10
2 16
R704
(36) CLK_PCI_LPC PCI_4/SEL_LCDCL
51 CLK_PCIE_ICH# REQ PORT LIST
SRC_10# CLK_PCIE_ICH# (28)
0_0402_5% R706 1 2 33_0402_5% ITP_EN 17
(26) CLK_PCI_ICH PCIF_5/ITP_EN
PORT DEVICE
2

48 CLK_PCIE_SATA
SRC_11 CLK_PCIE_SATA (27)
18
VSS_PCI SRC_11#
47 CLK_PCIE_SATA#
CLK_PCIE_SATA# (27) REQ_3# PCIE_EXP#
3
VSS_REF REQ_4# PCIE_WLAN2
+3VS +3VS +3VS EXP_CLKREQ#
22
VSS_48 CLKREQ_3#
37 EXP_CLKREQ# (30) REQ_6# PCIE_WLAN
CLK_48M_CR WLAN_CLKREQ2#
26
VSS_IO CLKREQ_4#
41 WLAN_CLKREQ2# REQ_7# PCIE_WLAN1
1

@ PM@ CLK_48M_ICH WLAN_CLKREQ#

R707 R708 R709
69
VSS_CPU CLKREQ_6#
58 WLAN_CLKREQ# REQ_9# PCIE_LAN
10K_0402_5% 10K_0402_5% 10K_0402_5% CLK_14M_ICH WLAN_CLKREQ1#
30
VSS_PLL3 CLKREQ_7#
65 WLAN_CLKREQ1# (30) REQ_10#
2

ITP_EN PCI4_SEL PCI2_TME C825 22P_0402_50V8J CLK_XTAL_IN CLK_14M_SIO CLKREQ_LAN#

34
VSS_SRC CLKREQ_9#
43 CLKREQ_LAN# (31) REQ_11# PCIE_SATA
C826

C829

C827

C830
1

GM@ @ Y4
1 1 1 1 59
VSS_SRC SLKREQ_10#
49 REQ_A# MCH_3GPLL
R710 R711 R712 14.31818MHZ_16PF_DSX840GA @ @ @ @ 42 46 SATA_CLKREQ#_R
A VSS_SRC CLKREQ_11# SATA_CLKREQ# (28) A
10K_0402_5% 10K_0402_5% 10K_0402_5%
2

2 2 2 2
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

C828 22P_0402_50V8J CLK_XTAL_OUT 73 21 MCH_CLKREQ#_R

MCH_CLKREQ# (8)
2

VSS USB_1/CLKREQ_A#

Routing the trace at least 10mil SLG8SP556VTR_QFN72_10X10

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# Security Classification Compal Secret Data Compal Electronics, Inc.
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# place CAPs near Resistors of U10 Issued Date 2009/04/23 Deciphered Date 2010/05 Title
Pin28/29 : LCDCLK / LCDCLK# For 3G RF noise . Clock Generator CK505
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 = Pin24/25 : SRC_0 / SRC_0# Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
Pin28/29 : 27M/27M_SS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 22 of 51
5 4 3 2 1
 5 4 3 2 1

U31 +3VS +3VS

+3VS
P/N:SA00002D700 (8101T)

1
10/30 update PS8171 co-lay circuit 1 1 1 1 GM_NOHDMI@
GM_HDMI@ GM_HDMI@ GM_HDMI@ GM_HDMI@ R715
P/N:SA00001U920 (CH7318C)

1
4/14 update 1442T co-lay circuit C831 C832 C833 C834 20K_0402_1%
@ S IC ASM1442T 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
R716 1442T@ U31 2 2 2 2

2
+3VS 0_0402_5% TMDS_B_HPD#
For 8171 For 8171

1
25 12/30
OE# @

2
12/30 +3VS +3VS 4/14 update 1442T@ 2 R727 R718
1442T@ HDMICLK_R VCC APD R912 7.5K_0402_1%
28 SCL_SINK VCC 11
2

2
D R719 D
15 0_0402_5%

2
VCC

1
R722 R724 0_0402_5% HDMIDAT_R 29 21 12/30
SDA_SINK VCC 8101TI1442T@
4.7K_0402_5% 4.7K_0402_5% R717 26 R913

1
VCC EMI1
33 2 1
8101T@ @ 4.7K_0402_5%
HDMI_DETECT 30
VCC
40 4.7K_0402_5% 3.01K_0402_1%
Reserved for CH7318C
GM_HDMI@
1

1 HPD_SINK VCC
4/14 update 8101T@ 46 8171@ 1442T@

2
PC1 PC0 VCC
32
DDC_EN

1
12/30 +3VS
2

@ R721 1 2 8171@ 4.7K_0402_5% 34 4 PC1

CFG0 PC1 PC0
R914 R915 R720 R723 1 2 @ 4.7K_0402_5% 35
CFG1 3
PC0 internal 1.2k for CH7318C
4.7K_0402_5% 4.7K_0402_5% 0_0402_5% internal pull down pull down

1
@ 8171@ 8101T@

2
R725 R726 6 R727 1 2 499_0402_1% GM@ GM@
1

REXT 4/14 update 8101T@ R728 R729

4.7K_0402_5% 4.7K_0402_5% 7 TMDS_B_HPD# 2.2K_0402_5% 2.2K_0402_5%
1442T@ @ HPD# TMDS_B_HPD# (10)

2
4/14 update 1442T@ 8
SDA HDMIDAT_NB (8)
9 HDMICLK_NB (8)
SCL
PIN NUM 8101T 8171 2 1
4.7K_0402_5% R1095 1442T@
PIN1 GND ASQ0 10 8171@ C835 1 2 PM_HDMI@
0.1U_0402_16V7K HDMI_CLK-
RT_EN# (17) VGA_HDMI_CLK# HDMI_CLK+
1 C836 1 2 PM_HDMI@
0.1U_0402_16V7K
4.7U_0805_10V4Z (17) VGA_HDMI_CLK
PIN3 PC0 PEQ
48 13 HDMI_CLK+ C925 C837 1 2 PM_HDMI@
0.1U_0402_16V7K HDMI_TX0-
(10) TMDS_B_CLK IN_D4+ OUT_D4+ HDMI_CLK- (17) VGA_HDMI_TX0# HDMI_TX0+
PIN4 PC1 PIO (10) TMDS_B_CLK# 47
IN_D4- OUT_D4-
14
2 (17) VGA_HDMI_TX0
C838 1 2 PM_HDMI@
0.1U_0402_16V7K

PIN7 HPD# HPDX 45 16 HDMI_TX0+ C839 1 2 PM_HDMI@

0.1U_0402_16V7K HDMI_TX1-
(10) TMDS_B_DATA0 IN_D3+ OUT_D3+ (17) VGA_HDMI_TX1#
44 17 HDMI_TX0- C840 1 2 PM_HDMI@
0.1U_0402_16V7K HDMI_TX1+
12/30 (10) TMDS_B_DATA0# IN_D3- OUT_D3- (17) VGA_HDMI_TX1
PIN10 RE_EN# CEXT
42 19 HDMI_TX1+ C841 1 2 PM_HDMI@
0.1U_0402_16V7K HDMI_TX2-
C (10) TMDS_B_DATA1 IN_D2+ OUT_D2+ HDMI_TX1- (17) VGA_HDMI_TX2# HDMI_TX2+ C
PIN11 VCC APD (10) TMDS_B_DATA1# 41 IN_D2- OUT_D2- 20 (17) VGA_HDMI_TX2
C842 1 2 PM_HDMI@
0.1U_0402_16V7K

PIN12 GND ASQ1 (10) TMDS_B_DATA2 39 22 HDMI_TX2+

IN_D1+ OUT_D1+ HDMI_TX2- 12/30
(10) TMDS_B_DATA2# 38 IN_D1- OUT_D1- 23
PIN27 GND EMI0 +3VS
R916 8171@
PIN33 VCC EMI1 12/30 1 2
For 8171 L41 PM_HDMI@MBK1608121YZF_0603
ASQ0 4.7K_0402_5% HDMIDAT_R
PIN34 DDCBUF_EN DDCBUF
For 8171 net name: GND
1
5
(16,17) VGA_HDMI_SDA 1
1
2
2 HDMICLK_R
GND (16,17) VGA_HDMI_SCL
EMI0, EMI1 12 ASQ1 1 R917 2 8171@ L42 PM_HDMI@MBK1608121YZF_0603
GND
PIN35 CFG PRE GND 18 4.7K_0402_5% place those component

2
ASQ0, ASQ1 GND
24 1 1
GND 27 EMI0 R918 near JP? C1156 C1157
APD GND
31 0_0402_5% for NV request
36 8101TI1442T@ PM_HDMI@ PM_HDMI@
GND

2
2 2
37 0515

1
GND R919 12P_0402_50V8J 12P_0402_50V8J
43
TMDS pull down (500ohm) resistors for ATI M92-S2 XT GND
49 0_0402_5%
PAD
R731 1 499_0402_1% 8101TI1442T@ +5VS
HDMI_CLK+_CONN 2 8101T@ PS8101TQFN48G_QFN48_7X7

1
PM_HDMI@
HDMI_CLK-_CONN R730 1 499_0402_1% For 8171 +3VS +3VS 12/30
2 For 8171

2
PM_HDMI@ 12/30 +5VS
HDMI_TX0+_CONN R733 1 2 499_0402_1% R922 HDMI@ +5VS_HDMI
PM_HDMI@ R920 8101TI1442T@ R921 @ R738 D18

2
HDMI_TX0-_CONN R732 1 2 499_0402_1% APD 1 2 ASQ0 1 2 @ 0_0805_5% RB491D_SC59-3
PM_HDMI@ 0_0402_5% 4.7K_0402_5% +5VS_HDMI 1

1
2

HDMI_TX1+_CONN R735 1 2 499_0402_1% PM_HDMI@ 2

PM_HDMI@ 2N7002_SOT23-3 R923 R922 C845
1

2
HDMI_TX1-_CONN R734 1 499_0402_1% D 0.1U_0402_16V4Z
2 4.7K_0402_5% 0_0402_5% 4.7K_0402_5% 2 HDMI@
PM_HDMI@ Q2
2 +3VS 8171@ 8101TI1442T@ 8171@ @ HDMI@ HDMI@

1
HDMI_TX2+_CONN R737 1 2 499_0402_1% G D20 R742 R743
1

1
2

B PM_HDMI@ 12/30 BAT54S-7-F_SOT23-3 2.2K_0402_5% 2.2K_0402_5% B

S
3

HDMI_TX2-_CONN R736 1 2 499_0402_1% R741 GM_HDMI@ JHDMI1

1
PM_HDMI@ 100K_0402_5% HDMI_DETECT 1 2 19
R744 0_0402_5% HP_DET
NEAR CONNECTOR @
PM_HDMI@
18
17
+5V
1

R1078 L43 HDMIDAT_R DDC/CEC_GND

16
WCM-2012-900T_4P HDMICLK_R SDA
(16) HDMI_DETECT_VGA 1 2 1 2 1 2 15
HDMI_CLK- HDMI_CLK-_CONN 1K_0402_1% FBML10160808121LMT_0603 R745 0_0402_5% SCL
4
3 3
14
4 Reserved
1

PM_HDMI@ PM_HDMI@ 13
@ PM_HDMI@ HDMI_CLK-_CONN CEC
2 12 CK- GND 20
HDMI_CLK+ 1 2 HDMI_CLK+_CONN D45 R1079 C267 11 21
1 2 RB751V_SOD323 10K_0402_1% PM_HDMI@ HDMI_CLK+_CONN CK_shield GND
10 22
L2PM_HDMII8101T@ 330P_0402_50V7K HDMI_TX0-_CONN CK+ GND
9 23
2

1 D0- GND
8
WCM-2012-900T_4P HDMI_TX0+_CONN D0_shield
7 D0+
HDMI_TX0- 4 HDMI_TX0-_CONN HDMI_TX1-_CONN
3 3
6
4 D1-
5
HDMI_TX1+_CONN D1_shield
4
HDMI_TX0+ HDMI_TX0+_CONN HDMI_TX2-_CONN D1+
1
2 2
3
1 D2-
2
L3PM_HDMII8101T@ HDMI_TX2+_CONN D2_shield
1
D2+
WCM-2012-900T_4P SUYIN_100042MR019S153ZL
HDMI_TX1- 4 HDMI_TX1-_CONN ME@
4 3 3 +5VS +5VS

HDMI_TX1+ 1 HDMI_TX1+_CONN
1 2 2 3 3
L4PM_HDMII8101T@ 1 HDMIDAT_R 1 HDMICLK_R

WCM-2012-900T_4P 2 @ 2 @
HDMI_TX2- 4 HDMI_TX2-_CONN D21 D22
A 4 3 3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 A
KIWB3/B4_LA4551P
HDMI_TX2+ 1 2 HDMI_TX2+_CONN
1 2
L5PM_HDMII8101T@

HDMI_CLK+ R751 1 1442T@ 2 0_0402_5% HDMI_CLK+_CONN

HDMI_CLK- R752 1 1442T@ 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+ R753 1 1442T@ 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics, Inc.
HDMI_TX0- R754 1 1442T@ 2 0_0402_5% HDMI_TX0-_CONN 2009/04/23 2010/05 Title
HDMI_TX1+ HDMI_TX1+_CONN
Issued Date Deciphered Date
R755 1 1442T@ 2 0_0402_5%
HDMI_TX1- R756 1 1442T@ 2 0_0402_5% HDMI_TX1-_CONN Level Shiftter_PS8101T
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+ R757 1 1442T@ 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2- R758 1 1442T@ 2 0_0402_5% HDMI_TX2-_CONN Custom KIWAX_LA-5081P 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 23 of 51
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD +5VALW

+3VS
W=60mils

1
R759 R760
150_0603_1% 100K_0402_5%

1 2

3
D D R761 220K_0402_5%
S
D
G
2 1 2 2
Q3 G
2N7002_SOT23 S SI2301BDS-T1-E3_SOT23-3

C851 0.1U_0402_16V4Z
DTC124EK 1
Q4 D

OUT

1
2 1 2 2 +LCDVDD
(10) GM_ENVDD IN
R230 GM@ 0_0402_5% Q5 W=60mils

GND
(16) VGA_ENVDD 2 1 DTC124EKAT146_SC59-3
R231 PM@ 0_0402_5%

3
INVT_PWM
+3VS
DAC_BRIG

1
DISPOFF#
R762

4.7K_0402_5% 1 1 1
D23
C852 C853 C854

2
BKOFF# 1 2 DISPOFF#
(36) BKOFF#
470P_0402_50V7K
CH751H-40PT_SOD323-2 2 2 2
2 1 ENBKL 470P_0402_50V7K 470P_0402_50V7K
(10) GMCH_ENBKL ENBKL (36)
R763 GM@ 0_0402_5%
(16) VGA_ENBKL 2 1

2
R764 PM@ 0_0402_5% @ @ @
R765
C C
100K_0402_1% For EMI

LCD/PANEL BD. Conn.

1
change from 10K to 100K
5/8 by checklist
LCD/PANEL BD. Conn. FOR DIS
FOR UMA

280mA (60 MIL) +LEDVDD

B+ 2 1
L7 1
FBMA-L11-201209-221LMA30T_0805C855
400mA
4.7U_0805_25V6-K
2

B B

+LCDVDD_L +LCDVDD_L

JLVDS1 JLVDS2
FBMA-L11-201209-221LMA30T_0805 2 1 +LEDVDD 2 1 +LEDVDD
L6 +LCDVDD_L 2 1 +LCDVDD_L 2 1
+LCDVDD 2 1 4 4 3 3 4 4 3 3
(60 MIL) 6 6 5 5 6 6 5 5
8 7 +3VS 8 7 +3VS
8 7 DAC_BRIG 8 7 DAC_BRIG
1 1 +3VS 10 10 9 9 DAC_BRIG (36) +3VS 10 10 9 9 DAC_BRIG (36)
C49 C46 12 11 12 11
12 11 INVT_PWM (36) 12 11 INVT_PWM (36)
14 13 DISPOFF# 14 13 DISPOFF#
4.7U_0805_10V4Z 0.1U_0402_16V4Z LVDS_ACLK# 14 13 VGA_LVDS_ACLK# 14 13
(10) LVDS_ACLK# 16 15 (17) VGA_LVDS_ACLK# 16 15
2 2 LVDS_ACLK 16 15 VGA_LVDS_ACLK 16 15
(10) LVDS_ACLK 18 17 (17) VGA_LVDS_ACLK 18 17
LVDS_A0# 18 17 VGA_LVDS_A0# 18 17
(10) LVDS_A0# 20 19 (17) VGA_LVDS_A0# 20 19
LVDS_A0 20 19 VGA_LVDS_A0 20 19
(10) LVDS_A0 22 21 (17) VGA_LVDS_A0 22 21
LVDS_A1# 22 21 VGA_LVDS_A1# 22 21
(10) LVDS_A1# 24 23 (17) VGA_LVDS_A1# 24 23
LVDS_A1 24 23 VGA_LVDS_A1 24 23
(10) LVDS_A1 26 25 (17) VGA_LVDS_A1 26 25
LVDS_A2# 26 25 LVDS_SDA VGA_LVDS_A2# 26 25 VGA_LVDS_SDA
(10) LVDS_A2# 28 28 27 27 LVDS_SDA (10) (17) VGA_LVDS_A2# 28 28 27 27 VGA_LVDS_SDA (16)
LVDS_A2 30 29 LVDS_SCL VGA_LVDS_A2 30 29 VGA_LVDS_SCL
(10) LVDS_A2 30 29 LVDS_SCL (10) (17) VGA_LVDS_A2 30 29 VGA_LVDS_SCL (16)
32 31 32 31
GNDGND GNDGND

ACES_87142-3041 ACES_87142-3041
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 24 of 51
5 4 3 2 1
 A B C D E

CRT Connector
CLOSE TO CONN
R766 1 2 PM@ 0_0402_5% CRT_R_1 L8 1 2 FCM1608CF-121T03_2P RED
(16) VGA_CRT_R
R767 1 2 GM@ 0_0402_5%
(10) GMCH_CRT_R +5VS
<BOM Structure> +CRT_VCC
1 R768 1 2 PM@ 0_0402_5% CRT_G_1 L9 1 2 FCM1608CF-121T03_2P GREEN 1
(16) VGA_CRT_G D24
R769 1 2 GM@ 0_0402_5%
(10) GMCH_CRT_G
<BOM Structure> 2 1
R770 1 2 PM@ 0_0402_5% CRT_B_1 L10 1 2 FCM1608CF-121T03_2P BLUE

1.1A_6V_SMD1812P110TF
(16) VGA_CRT_B
R771 1 2 GM@ 0_0402_5%
(10) GMCH_CRT_B RB491D_SC59-3

2
1 1 1 <BOM Structure> 1 1 1
@ @ @ F1
R772 R773 R774 C856 C857 C858 C859 C860 C861 W=40mils
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J JCRT1
2 2 2 2 2 2
6

1
11
RED 1
<BOM Structure> <BOM Structure> <BOM Structure> 7
CRT_DDC_DAT 12
+5VS +5VS +5VS GREEN 2
8
3 3 3 JVGA_HS 13
BLUE 3
1 BLUE 1 GREEN 1 RED 9
JVGA_VS 14 G 16
2 2 2 4 G 17
+CRT_VCC @ @ @ 10
D25 D26 D27 CRT_DDC_CLK 15
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 5
+5VS +5VS ALLTO_C10534-91507-L
1 ME@
3 3
C862
2 1 JVGA_HS 1 JVGA_VS 0.1U_0402_16V4Z 2
2
1

1
2 2
C863 R775 @ @
0.1U_0402_16V4Z 1K_0402_5% D28 D29
2 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
CLOSE TO CONN <BOM Structure>
5

2
OE#
P

R776 1 2 PM@ 0_0402_5% CRT_HSYNC 2 4 CRT_HSYNC_1 L11 1 2 FCM1608CF-121T03_2P JVGA_HS

(16) VGA_HSYNC A Y
G

R777 1 2 GM@ 0_0402_5% U32 <BOM Structure>

(10) GMCH_CRT_HSYNC
SN74AHCT1G125DCKR_SC70-5 L12 1 2 FCM1608CF-121T03_2P JVGA_VS
3

<BOM Structure>
1
@
C864
1
@ C865
PIN ASSIGMENT
+CRT_VCC 10P_0402_50V8J 10P_0402_50V8J
2 2

1
D-SUB FUNCTION
C866
0.1U_0402_16V4Z
9 +CRT_VCC
2
CLOSE TO CONN <BOM Structure>
1 RED
5

1
OE#
P

R778 1 2 PM@ 0_0402_5% CRT_VSYNC 2 4 CRT_VSYNC_1

(16) VGA_VSYNC A Y
6 GND
G

R779 1 2 GM@ 0_0402_5% U33

(10) GMCH_CRT_VSYNC
SN74AHCT1G125DCKR_SC70-5
2 GREEN
3

3 3
<BOM Structure>

2.2K
7, 5 GND
+3VS
3 BLUE
CLOSE TO CONN
+3VS +CRT_VCC
2.2K
8 GND
1

R86 R87 14 VSYNC

1

2.2K_0402_5% 2.2K_0402_5%
R783 R784 10 GND
2

(16) VGA_DDCDATA 1 R502 2 PM@ 0_0402_5% 2.2K_0402_5% 2.2K_0402_5%

13 HSYNC
2

R785 1 2 GM@ 0_0402_5% 4 3 CRT_DDC_DAT

(10) GMCH_CRT_DATA
<BOM Structure>
Q6B
11 SENSE
2

2N7002DW -T/R7_SOT363-6 <BOM Structure>

1 R786 2 GM@ 0_0402_5% 1 6 CRT_DDC_CLK
(10) GMCH_CRT_CLK
R787 1 2 PM@ 0_0402_5%
1
@
1
@
12 SM_DAT
(16) VGA_DDCCLK Q6A C867 C868
2N7002DW -T/R7_SOT363-6
2
100P_0402_50V8J
2
68P_0402_50V8J 15 SM_CLK
4 4

4 PIN4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 25 of 51
A B C D E
 5 4 3 2 1

D +3VS D

1 2 PCI_DEVSEL#
R788 8.2K_0402_5%
1 2 PCI_STOP#
R789 8.2K_0402_5%
1 2 PCI_TRDY# U34B
R790 8.2K_0402_5% PCI_AD0 D11 F1 PCI_REQ0#
PCI_FRAME# PCI_AD1 AD0 REQ0# PCI_GNT0#
1 2 C8 AD1 GNT0# G4
R791 8.2K_0402_5% PCI_AD2 PCI_REQ1#
1 2 PCI_PLOCK# PCI_AD3
D9
E12
AD2 PCI REQ1#/GPIO50
B6
A7 PCI_GNT1#
R792 8.2K_0402_5% PCI_AD4 AD3 GNT1#/GPIO51 PCI_REQ2#
E9 F13
PCI_IRDY# PCI_AD5 AD4 REQ2#/GPIO52 PCI_GNT2#
1 2 C9 AD5 GNT2#/GPIO53 F12
R793 8.2K_0402_5% PCI_AD6 E10 E6 PCI_REQ3#
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 B7 F6
R794 8.2K_0402_5% PCI_AD8 AD7 GNT3#/GPIO55
C7
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 C5 AD9 C/BE0# D8
R795 8.2K_0402_5% PCI_AD10 G11 B4 PCI_CBE#1
PCI_AD11 AD10 C/BE1# PCI_CBE#2
F8 AD11 C/BE2# D6
PCI_AD12 F11 A5 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 (31)
PCI_AD13 E7
+3VS PCI_AD14 AD13 PCI_IRDY#
A3 D3
PCI_AD15 AD14 IRDY# PCI_PAR
D2 AD15 PAR E3
1 2 PCI_PIRQA# PCI_AD16 F10 R1 PCI_RST#
R796 8.2K_0402_5% PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
D5 C6
PCI_PIRQB# PCI_AD18 AD17 DEVSEL# PCI_PERR#
1 2 D10 AD18 PERR# E4
R797 8.2K_0402_5% PCI_AD19 B3 C2 PCI_PLOCK#
PCI_PIRQC# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 F7 J4
R798 8.2K_0402_5% PCI_AD21 AD20 SERR# PCI_STOP#
C3 AD21 STOP# A4
1 2 PCI_PIRQD# PCI_AD22 F3 F5 PCI_TRDY#
R799 8.2K_0402_5% PCI_AD23 AD22 TRDY# PCI_FRAME#
F4 D7
PCI_PIRQE# PCI_AD24 AD23 FRAME#
1 2 C1
C R800 8.2K_0402_5% PCI_AD25 AD24 PLT_RST# C
G7 AD25 PLTRST# C14
1 2 PCI_PIRQF# PCI_AD26 H7 D4 CLK_PCI_ICH
PCI_AD27 AD26 PCICLK PCI_PME# CLK_PCI_ICH (22)
R801 8.2K_0402_5% D1 R2
AD27 PME# PCI_PME# (36)
1 2 PCI_PIRQG# PCI_AD28 G5
R802 8.2K_0402_5% PCI_AD29 AD28
H6 AD29
1 2 PCI_PIRQH# PCI_AD30 G1 1 2
R803 8.2K_0402_5% PCI_AD31 AD30 R804 @ 10K_0402_5%
+3VALW
H3 AD31
1 2 PCI_REQ0#
R805 8.2K_0402_5%
PCI_REQ1#
1
R806
2
8.2K_0402_5% PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_REQ2# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
1 2 E1 K6
R807 8.2K_0402_5% PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
J6 PIRQC# PIRQG#/GPIO4 F2
1 2 PCI_REQ3# PCI_PIRQD# C4 G2 PCI_PIRQH#
R808 8.2K_0402_5% PIRQD# PIRQH#/GPIO5
ICH9-M ES_FCBGA676

Place closely pin D4

PCI_GNT0# SB_SPI_CS#1 CLK_PCI_ICH
(28) SB_SPI_CS#1
Pull high?

2
1

1
@ @ R811
R809 R810 0_0402_5%
1 2 PCI_GNT3# 1K_0402_5% 1K_0402_5%

1
R812 @ 1K_0402_5%
2

2
1
C869
18P_0402_50V8J
B 2 B

Boot BIOS Strap PCI_RST#

PCI_RST# (36,38)

1
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
A16 Swap Override Strap R813
100K_0402_5%
Low= A16 swap override Enable 0 1 SPI
PCI_GNT#3

2
High= Default*
1 0 PCI
PLT_RST#
1 1 LPC* PLT_RST# (8,16,30,31)

1
R814
100K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 26 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS

R815
GATEA20 2 1
+RTCVCC 10K_0402_5%

R816 330K_0402_1% 1 2 ICH_RTCX1 R817

1 2 LAN100_SLP C870 15P_0402_50V8J KB_RST# 2 1
15P

1
R818 1M_0402_5% Y5 10K_0402_5%
1 2 SM_INTRUDER# 2 NC IN 1
32.768KHZ_12.5P_1TJS125BJ2A251 R819 +VCCP
R820 330K_0402_1% 3 4 10M_0402_5%
D NC OUT D
1 2 ICH_INTVRMEN LPC_AD[0..3] (36,38)
R821 @

2
U34A H_DPRSTP# 2 1
C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
1 2 C24 K4
C871 15P_0402_50V8J RTCX2 FWH1/LAD1 LPC_AD2 R824 @
L6
ICH_RTCRST# FWH2/LAD2 LPC_AD3 H_DPSLP#
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2 2 1
+RTCVCC R822 20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME# 56_0402_5%
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# (36,38)

RTC

LPC
CLRP1
@ ICH_INTVRMEN B22 J3 LPC_DRQ0#
+RTCBATT LAN100_SLP INTVRMEN LDRQ0# LPC_DRQ0# (38)
R823 2 1 A22 J1 +VCCP
LAN100_SLP LDRQ1#/GPIO23
1 2
E25 N7 GATEA20
2MM GLAN_CLK A20GATE GATEA20 (36)

1
2 100_0603_1% AJ27 H_A20M#
A20M# H_A20M# (5)
C872 1 2 C13
LAN_RSTSYNC
C873 1U_0603_10V4Z AJ25 H_DPRSTP_R# R825 2 1 0_0402_5% H_DPRSTP#
H_DPRSTP# (6,49)
R826
0.1U_0402_16V4Z DPRSTP# H_DPSLP# 56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# (6)
1
close to RAM door G13

2
LAN_RXD1 H_FERR#_S R827 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5% H_FERR# (5)

LAN / GLAN
D13 AD22 H_PWRGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD (6)
D12
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# (5)
+1.5VS B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# (5) +VCCP
AG25 H_INTR

CPU
GLAN_COMP INTR KB_RST# H_INTR (5)
1 2 B28
GLAN_COMPI RCIN#
L3 KB_RST# (36)
R362 need to place within 2" of ICH9M
R828 24.9_0402_1% B27
GLAN_COMPO

1
1 2 HDA_BITCLK_R AF23 H_NMI R360 must be place within 2" of R362 w/o stub.
(8,16,34) HDA_BITCLK_CODEC NMI H_NMI (5)
R829 0_0402_5% AF6 AF24 H_SMI#
HDA_SYNC_R HDA_BIT_CLK SMI# H_SMI# (5)
1 2 AH4 R830
(8,16,34) HDA_SYNC_CODEC HDA_SYNC H_STPCLK#
R831 33_0402_5% AH27 56_0402_5%
C HDA_RST_R# STPCLK# H_STPCLK# (5) C
(8,16,34) HDA_RST_CODEC# 1 2 AE7

2
R832 33_0402_5% HDA_RST# THRMTRIP_ICH# R833 1 H_THERMTRIP#
AG26 2 54.9_0402_1% H_THERMTRIP# (5,8)
THRMTRIP#
(8) HDA_SDIN0 AF4
HDA_SDIN0
(16) HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27
(34) HDA_SDIN2 AH3 HDA_SDIN2
AE5

IHDA
HDA_SDIN3
SATA4RXN AH11
1 2 HDA_SDOUT_R AG5 AJ11
(8,16,34) HDA_SDOUT_CODEC HDA_SDOUT SATA4RXP
R834 33_0402_5% AG12
SATA4TXN
AG7 AF12
HDA_DOCK_EN#/GPIO33 SATA4TXP
+3VS 1 2 AE8 HDA_DOCK_RST#/GPIO34
R835 10K_0402_5%
DRIVE_LED# 2 1 SATA_LED# AG8
(39) DRIVE_LED# RB751V_SOD323 D30 SATALED# R836 1
AH9 2 @ 1K_0402_5%
SATA_DTX_C_IRX_N0 SATA5RXN R837 1
(33) SATA_DTX_C_IRX_N0 AJ16 AJ9 2 @ 1K_0402_5%
SATA_DTX_C_IRX_P0 SATA0RXN SATA5RXP
HDD (33) SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0 C874 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N0
AH16
AF17
SATA0RXP SATA5TXN
AE10
AF10
(33) SATA_ITX_DRX_N0 SATA0TXN SATA5TXP
(33) SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 C875 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AG17
SATA0TXP CLK_PCIE_SATA#
AH18 CLK_PCIE_SATA# (22)
SATA_CLKN

SATA
SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
(33) SATA_DTX_C_IRX_N1 SATA1RXN SATA_CLKP CLK_PCIE_SATA (22)
SATA_DTX_C_IRX_P1 AJ13 AJ7
(33) SATA_DTX_C_IRX_P1 SATA1RXP SATARBIAS#
SATA_ITX_DRX_N1 C876 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 SATARBIAS R838 1 2 24.9_0402_1%
ODD (33) SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 C877 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1
AG14
SATA1TXN SATARBIAS
AH7
(33) SATA_ITX_DRX_P1 AF14
SATA1TXP 10mils width less than 500mils

ICH9-M ES_FCBGA676

SATA PORT LIST

B PORT DEVICE B

Need check
0 HDD
+3VS 1 ODD
XOR Chain Entrance Strap 4 E-SATA
2

ICH_TP3 HDA_SDOUT Description 5

R839
1K_0402_5% 0 0 RSVD
@
0 1 Enter XOR Chain
1

HDA_SDOUT_R
1 0 Normal Operation
1 1 Set PCIE port config bit 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 27 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS

R840 1 2 10K_0402_5% SERIRQ

+3VALW
R841 1 2 8.2K_0402_5% PCI_CLKRUN#
+3VS
R842 1 2 @ 10K_0402_5% GPIO38 +3VALW
Place closely pin B2 Place closely pin AC1

2
R843 1 2 @ 8.2K_0402_5% EC_THERM#
R844 R845 CLK_48M_ICH CLK_14M_ICH

1
2.2K_0402_5% 2.2K_0402_5% R846
U34C 8.2K_0402_5%

1
R848 1 2 10K_0402_5% OCP# R849 R847 G16 AH23
(22,30) ICH_SMBCLK

1
10K_0402_5% 10K_0402_5% SMBCLK SATA0GP/GPIO21 R857
D (22,30) ICH_SMBDATA
LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19
AF19
AE21 R850 10_0402_5%
D

SATA
GPIO
2

2
ME__EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 22_0402_5% @
C17 AD20
R851 1 SMLINK0 SATA5GP/GPIO37
2 @ 8.2K_0402_5% PM_BMBUSY# ME__EC_DATA1 B18 <BOM Structure>

2
SMLINK1 CLK_14M_ICH
H1 CLK_14M_ICH (22)
R858 1 +3VS CLK14 +3VALW
2 @ 10K_0402_5% GPIO39 ICH_RI# F19 clocks AF3 CLK_48M_ICH
CLK_48M_ICH (22) 1 1
RI# CLK48 C878
R852 1 2 10K_0402_5% GPIO48 R4 P1 ICH_SUSCLK T95 C879 10P_0402_50V8J
SUS_STAT#/LPCPD# SUSCLK

1
XDP_DBRESET# G19 10P_0402_50V8J @
(5) XDP_DBRESET# SYS_RESET#

1
C16 SLP_S3# @ 2 2
SLP_S3# SLP_S3# (36)
@ @ PM_BMBUSY# M6 E16 SLP_S4# R854
+3VALW R859 (8) PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# (36)
R853 G17 SLP_S5# 10K_0402_5%

SYS / GPIO
SLP_S5# SLP_S5# (36)
10K_0402_5% 10K_0402_5%
(36) EC_LID_OUT# 1 2 LID_OUT# A17

2
R856 1 SMBALERT#/GPIO11
2 10K_0402_5% LINKALERT# R855 0_0402_5% C10 S4_STATE#

2
H_STP_PCI# S4_STATE#/GPIO26 R860 1 M_PWROK
(22) H_STP_PCI# A14 2 @ 100_0402_5%
R861 1 STP_PCI#
2 @ 10K_0402_5% CL_RST#
(22) H_STP_CPU#
R862 1 2 0_0402_5% R_STP_CPU# E19 G20 ICH_POK
ICH_POK (8,36)
M_PWROK
STP_CPU# PWROK
1 2 R863
R864 1 2 10K_0402_5% XDP_DBRESET# PCI_CLKRUN# L4 M2 R865 1 2 499_0402_1% DPRSLPVR @ 10K_0402_5% 1

Power MGT
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR (8,49)
C880
R866 1 2 10K_0402_5% ICH_RI# ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT# @
(30,31) ICH_PCIE_WAKE# WAKE# BATLOW#
SERIRQ M5 1000P_0402_50V7K
(36,38) SERIRQ SERIRQ 2
R867 1 2 1K_0402_5% ICH_PCIE_WAKE# EC_THERM# AJ23 R3 PBTN_OUT#
(36) EC_THERM# THRM# PWRBTN# PBTN_OUT# (36)
R868 1 2 8.2K_0402_5% ICH_LOW_BAT# R869 1 2 0_0402_5% VRMPWRGD D21 D20
(8,49) VGATE VRMPWRGD LAN_RST#
R870 1 2 10K_0402_5% LID_OUT# T96 SST_CTL A20 D22 EC_RSMRST#R EC_RSMRST#R R871 1 2 10K_0402_5%
TP11 RSMRST#
R872 1 2 10K_0402_5% WOL_EN OCP# AG19 R5 CK_PWRGD_R R873 1 2 0_0402_5% CK_PWRGD
OCP# GPIO1 CK_PWRGD CK_PWRGD (22)
(30,36) CPUSB# AH21
GPIO7 GPIO6 M_PWROK
AG21 R6 M_PWROK (8)
EC_SMI# GPIO7 CLPWROK R874 1
(36) EC_SMI# A21 2 0_0402_5% VGATE (8,49)
R875 1 2 3.24K_0402_1% +3VS
+3VS EC_SCI# GPIO8 T97
(36) EC_SCI# C12 B16 1
GPIO12 SLP_M#

1
GPIO13 C21
R876 1 GPIO13
2 10K_0402_5% GPIO7 GPIO17 AE18 F24 CL_CLK0 (8)
C881 R877
GPIO18 GPIO17 CL_CLK0 0.1U_0402_16V4Z 453_0402_1%
K1 B19

GPIO
CL_CLK1

Controller Link
R878 1 GPIO18 CL_CLK1 2
2 10K_0402_5% GPIO13 GPIO20 AF8
GPIO22 GPIO20
AJ22 F22 CL_DATA0 (8)

2
R879 1 GPIO17 GPIO27 SCLOCK/GPIO22 CL_DATA0
2 @ 10K_0402_5% A9 C19 CL_DATA1
T98 GPIO27 CL_DATA1
C D19 C
R880 1 GPIO18 SATA_CLKREQ# GPIO28 CL_VREF0_ICH
2 @ 10K_0402_5% (22) SATA_CLKREQ# L1 C25
GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_ICH R881 1
AE19 A19 2 3.24K_0402_1% +3VALW
R882 1 GPIO20 GPIO39 SLOAD/GPIO38 CL_VREF1
2 10K_0402_5% AG22 1
SDATAOUT0/GPIO39

1
GPIO48 AF21 F21 CL_RST#
SDATAOUT1/GPIO48 CL_RST0# CL_RST# (8)
R883 1 2 10K_0402_5% GPIO22 R884 1 2 @ 1K_0402_5% GPIO49 AH24 D18 C882 R885
GPIO57 GPIO49 CL_RST1# @ 0.1U_0402_16V4Z 453_0402_1%
A8
GPIO57/CLGPIO5 D31 RB751V_SOD323 2
A16 SB_INT_FLASH_SEL (39)
SB_SPKR MEM_LED/GPIO24
(34) SB_SPKR M7 C18 2 1 ACIN ACIN (36,43,45)

2
+3VS MCH_ICH_SYNC# SPKR GPIO10/SUS_PWR_ACK GPIO14
AJ24 C11

MISC
(8) MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_RSVD B21 C20 +3VALW 2 1 2 1
R888 1 SB_SPKR TP3 WOL_EN/GPIO9
2 @ 10K_0402_5% T99 AH20 R886 R887 @ 0_0402_5%
T100 TP8 WOL_EN @ 10K_0402_5%
AJ20
T101 TP9
AJ21
GPIO57 TP10
R889 1 2 @ 100K_0402_5% change from 100k to 10k ohm 5/8
ICH9-M ES_FCBGA676
R890 1 2 @ 100K_0402_5% DPRSLPVR RSMRST circuit
R891 1 2 @ 1K_0402_5% ICH_RSVD @ R892 @ R893
0_0402_5% 0_0402_5%
low-->default 1 2 1 2 POK (46)
High -->No boot AC decoupling cap range of 75nF to 220nF
U34D EC_RSMRST#R

C
(36) EC_RSMRST# 3 1
+3VALW N29 V27 DMI_RXN0 Q8

E
PERN1 DMI0RXN DMI_RXN0 (8)
RP1 N28 V26 DMI_RXP0 DMI_RXP0 (8) BAV99DW-7_SOT363 MMBT3906_SOT23-3
USB_OC#6 PERP1 DMI0RXP DMI_TXN0
5 4 P27 U29 1 2

B
DMI_TXN0 (8) +3VALW

1 2
USB_OC#1 PETN1 DMI0TXN DMI_TXP0 R894 4.7K_0402_5%
6 3 P26 U28

Direct Media Interface

PETP1 DMI0TXP DMI_TXP0 (8)

2
7 2 USB_OC#2
8 1 USB_OC#4 L29 Y27 DMI_RXN1 DMI_RXN1 (8) @ D32B
PERN2 DMI1RXN DMI_RXP1 R895
L28 Y26 DMI_RXP1 (8)
10K_1206_8P4R_5% PERP2 DMI1RXP DMI_TXN1 2.2K_0402_5% D32A
M27 W29 DMI_TXN1 (8)
PETN2 DMI1TXN DMI_TXP1 BAV99DW-7_SOT363
M26 W28 DMI_TXP1 (8)

1
RP2 PETP2 DMI1TXP R896

6
PCI - Express
5 4 USB_OC#5 PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 (8) 1 2
(30) PCIE_RXN3 PERN3 DMI2RXN
6 3 USB_OC#7 PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 (8)
(30) PCIE_RXP3 PERP3 DMI2RXP
7 2 USB_OC#9 WLAN (30) PCIE_TXN3 C884 0.1U_0402_10V7K PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 (8) 2.2K_0402_5%
USB_OC#0 C885 0.1U_0402_10V7K PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2
8 1 (30) PCIE_TXP3 K26 AA28 DMI_TXP2 (8)
B PETP3 DMI2TXP B

10K_1206_8P4R_5% PCIE_RXN4 G29 AD27 DMI_RXN3

RP3 NEW CARD

(30)
(30)
PCIE_RXN4
PCIE_RXP4
C887 0.1U_0402_10V7K
PCIE_RXP4
PCIE_C_TXN4
G28
H27
PERN4
PERP4
DMI3RXN
DMI3RXP
AD26
AC29
DMI_RXP3
DMI_TXN3
DMI_RXN3
DMI_RXP3
(8)
(8) PCIE PORT LIST USB PORT LIST
(30) PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 (8)
5 4 USB_OC#8 (30) PCIE_TXP4 C888 0.1U_0402_10V7K PCIE_C_TXP4 H26 AC28 DMI_TXP3 DMI_TXP3 (8)
USB_OC#3 PETP4 DMI3TXP
6
7
3
2 USB_OC#10 E29 T26 CLK_PCIE_ICH#
CLK_PCIE_ICH# (22)
PORT DEVICE PORT DEVICE
USB_OC#11 PERN5 DMI_CLKN CLK_PCIE_ICH
8 1 E28 T25 CLK_PCIE_ICH (22)
PERP5 DMI_CLKP
10K_1206_8P4R_5%
F27
F26
PETN5
AF29
Within 500 mils 1 0 LEFT SIDE1
PETP5 DMI_ZCOMP DMI_IRCOMP R897 1 2 24.9_0402_1%
PCIE_IRX_PTX_N6 C29
DMI_IRCOMP
AF28 +1.5VS 2 1 LEFT SIDE2
(31) PCIE_IRX_PTX_N6 PERN6/GLAN_RXN
PCIE_IRX_PTX_P6 USB20_N0
LAN
(31) PCIE_IRX_PTX_P6
C891 0.1U_0402_10V7K PCIE_ITX_PRX_N6
C28
D27
PERP6/GLAN_RXP USBP0N
AC5
AC4 USB20_P0
USB20_N0 (40) 3 WLAN 2 CMOS
(31) PCIE_ITX_C_PRX_N6
C892 0.1U_0402_10V7K PCIE_ITX_PRX_P6 PETN6/GLAN_TXN USBP0P USB20_N1
USB20_P0 (40) LEFT USB1
(31) PCIE_ITX_C_PRX_P6 D26
PETP6/GLAN_TXP USBP1N
AD3
AD2 USB20_P1
USB20_N1 (40) 4 NEW CARD 3 3G
USBP1P USB20_N2
USB20_P1 (40) LEFT USB2
+3VS
D23
D24
SPI_CLK USBP2N
AC1
AC2 USB20_P2
USB20_N2 (40) 5 4 RIGHT SIDE
SB_SPI_CS#1 SPI_CS0# USBP2P USB20_N3
USB20_P2 (40) CMOS
(26) SB_SPI_CS#1 F23
SPI_CS1#GPIO58/CLGPIO6 USBP3N
AA5
AA4 USB20_P3
USB20_N3 6 LAN 5
USBP3P USB20_P3 3G Card
2

USB20_N4
@
SPI not used, Left NC D25
E23
SPI_MOSI SPI USBP4N
AB2
AB3 USB20_P4
USB20_N4 (40) 6 BT
R898 SPI_MISO USBP4P USB20_N5
USB20_P4 (40) RIGHT USB
330_0402_5% USB_OC#0 N4
USBP5N
AA1
AA2 USB20_P5
USB20_N5 7 CARD READER
(40) USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5
USB_OC#1 USB20_N6
(40) USB_OC#1 N5 W5 USB20_N6 (40) 8 WIRELESS
1

R899 1 VRMPWRGD USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6

2 @ 0_0402_5% N6 USB W4
USB_OC#3 OC2#/GPIO41 USBP6P USB20_N7
USB20_P6 (40) BT
P6
OC3#/GPIO42 USBP7N
Y3 USB20_N7 (37) 9
1

D USB_OC#4 USB20_P7
M1 Y2
@
(40) USB_OC#4
USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8
USB20_P7 (37) Card Reader
(49) CLK_ENABLE# 2
G Q9 USB_OC#6
N2
M4
OC5#/GPIO29 USBP8N
W1
W2 USB20_P8
USB20_N8 (30) 10 NEW CARD
RHU002N06_SOT323 USB_OC#7 OC6#/GPIO30 USBP8P USB20_N9
USB20_P8 (30) WLAN
S M3 V2 USB20_N9 11
3

USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9

N3 V3
USB_OC#9 N1
OC8#/GPIO44 USBP9P
U5 USB20_N10
USB20_P9 TV Tuner
OC9#/GPIO45 USBP10N USB20_N10 (30)
USB_OC#10 P5 U4 USB20_P10
USB_OC#11 P3
OC10#/GPIO46 USBP10P
U1 USB20_N11
USB20_P10 (30) New Card
OC11#/GPIO47 USBP11N USB20_N11
U2 USB20_P11
USBP11P USB20_P11
R900 1 2 22.6_0402_1% USBRBIAS AG2
USBRBIAS
A AG1 A
USBRBIAS#
Within 500 mils ICH9-M ES_FCBGA676

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 28 of 51
5 4 3 2 1
 5 4 3 2 1

+VCCP 04/16 add two 0.1U

20 mils U34F U34E
+RTCVCC A23 VCCRTC VCC1_05[01] A15 AA26 VSS[001] VSS[107] H5
VCC1_05[02] B15 AA27 VSS[002] VSS[108] J23

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 ICH_V5REF_RUN A6 C15 AA3 J26
C894 C898 V5REF VCC1_05[03] VSS[003] VSS[109]
VCC1_05[04] D15 AA6 VSS[004] VSS[110] J27
0.1U_0402_16V4Z 0.1U_0402_16V4Z E15 1 1 1 1 AB1 AC22
VCC1_05[05] VSS[005] VSS[111]

C1168

C1169
ICH_V5REF_SUS AE1 F15 C895 C899 0.1U_0402_16V4Z AA23 K28
2 2 V5REF_SUS VCC1_05[06] VSS[006] VSS[112]
VCC1_05[07] L11 AB28 VSS[007] VSS[113] K29
AA24 L12 0.1U_0402_16V4Z AB29 L13
VCC1_5_B[01] VCC1_05[08] 2 2 2 2 VSS[008] VSS[114]
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB4 VSS[009] VSS[115] L15
AB24 L16 AB5 L2
VCC1_5_B[03] VCC1_05[10] VSS[010] VSS[116]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AC17 VSS[011] VSS[117] L26
+5VS +3VS AC24 L18 AC26 L27
VCC1_5_B[05] VCC1_05[12] VSS[012] VSS[118]
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC27 VSS[013] VSS[119] L5
D R902 D
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC3 VSS[014] VSS[120] L7

2
AD25 P11 0.01U_0402_16V7K 1 2 AD1 M12

CORE
VCC1_5_B[08] VCC1_05[15] +1.5VS VSS[015] VSS[121]
R901 D33 AE25 P18 CHB1608U301_0603 AD10 M13
100_0402_5% VCC1_5_B[09] VCC1_05[16] VSS[016] VSS[122]
CH751H-40PT_SOD323-2 AE26 T11 1 1 AD12 M14
VCC1_5_B[10] VCC1_05[17] C896 C897 10U_0805_6.3V6M VSS[017] VSS[123]
AE27 T18 AD13 M15
VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[124]
AE28 U11 AD14 M16
1

VCC1_5_B[12] VCC1_05[19] VSS[019] VSS[125]

AE29 U18 AD17 M17
ICH_V5REF_RUN VCC1_5_B[13] VCC1_05[20] 2 2 VSS[020] VSS[126]
F25 VCC1_5_B[14] VCC1_05[21] V11 AD18 VSS[021] VSS[127] M23
1 20 mils G25 VCC1_5_B[15] VCC1_05[22] V12 AD21 VSS[022] VSS[128] M28
C893 H24 V14 AD28 M29
VCC1_5_B[16] VCC1_05[23] +VCCP VSS[023] VSS[129]
H25 VCC1_5_B[17] VCC1_05[24] V16 AD29 VSS[024] VSS[130] N11
1U_0603_10V4Z J24 V17 AD4 N12
2 VCC1_5_B[18] VCC1_05[25] VSS[025] VSS[131]

VCCA3GP
J25 VCC1_5_B[19] VCC1_05[26] V18 AD5 VSS[026] VSS[132] N13
K24 1 AD6 N14
VCC1_5_B[20] C900 10U_0805_10V4Z VSS[027] VSS[133]
K25 AD7 N15
VCC1_5_B[21] VSS[028] VSS[134]
L23 AD9 N16
VCC1_5_B[22] VSS[029] VSS[135]
L24 VCC1_5_B[23] VCCDMIPLL R29 AE12 VSS[030] VSS[136] N17
+5VALW +3VALW L25 2 AE13 N18
VCC1_5_B[24] VSS[031] VSS[137]
M24 VCC1_5_B[25] VCC_DMI[1] W23 AE14 VSS[032] VSS[138] N26
M25 Y23 +VCCP AE16 N27
VCC1_5_B[26] VCC_DMI[2] VSS[033] VSS[139]
2

N23 AE17 P12

R903 D34 VCC1_5_B[27] VSS[034] VSS[140]
N24 AB23 AE2 P13
100_0402_5% VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[141]
CH751H-40PT_SOD323-2 N25 VCC1_5_B[29] V_CPU_IO[2] AC23 AE20 VSS[036] VSS[142] P14

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P24 VCC1_5_B[30] AE24 VSS[037] VSS[143] P15
P25 AG29 +3VS 1 1 1 AE3 P16
1

VCC1_5_B[31] VCC3_3[01] VSS[038] VSS[144]

C902

C903

C904
ICH_V5REF_SUS R24 AJ6 +3VS 1 (DMI) AE4 P17
VCC1_5_B[32] VCC3_3[02] +3VS VSS[039] VSS[145]
20 mils R25
VCC1_5_B[33] VCC3_3[07]
AC10 1 (SATA) AE6
VSS[040] VSS[146]
P2
1 R26 C901 AE9 P23
C905 VCC1_5_B[34] 0.1U_0402_16V4Z C906 0.1U_0402_16V4Z 2 2 2 VSS[041] VSS[147]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AF13 VSS[042] VSS[148] P28
0.1U_0402_16V4Z 2

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 1 AF16 VSS[043] VSS[149] P29
1U_0603_10V4Z 2
T27 AG24 AF18 P4
2 VCC1_5_B[37] VCC3_3[05] C907 VSS[044] VSS[150]
T28 AC20 AF22 P7
C VCC1_5_B[38] VCC3_3[06] VSS[045] VSS[151] C
T29 VCC1_5_B[39] AH26 VSS[046] VSS[152] R11
U24 2 +3VS AF26 R12
R904 VCC1_5_B[40] VSS[047] VSS[153]
40 mils U25
VCC1_5_B[41] VCC3_3[08]
B9 AF27
VSS[048] VSS[154]
R13
+1.5VS 1 2 10U_0805_10V4Z V24 F9 AF5 R14
VCC1_5_B[42] VCC3_3[09] +3VS +1.5VS VSS[049] VSS[155]
1 V25 VCC1_5_B[43] VCC3_3[10] G3 1 1 1 AF7 VSS[050] VSS[156] R15
0_0805_5% 1 1 1 U23 G6 AF9 R16
VCC1_5_B[44] VCC3_3[11] VSS[051] VSS[157]

PCI
+ C910 C911 C912 W24 J2 C909 C913 C914 AG13 R17
VCC1_5_B[45] VCC3_3[12] VSS[052] VSS[158]

2
C908 W25 J7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AG16 R18
220U_D2_4VM VCC1_5_B[46] VCC3_3[13] 2 2 2 R906 VSS[053] VSS[159]
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[054] VSS[160] R28
2 2 2 2 Y24 R905 AG20 T12
VCC1_5_B[48] 0_0402_5% VSS[055] VSS[161]
Y25 PMIGM_NOHDMI@ AG23 T13
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[49] GM_HDMI@ VSS[056] VSS[162]
AJ4 AG3 T14

1
VCCHDA VSS[057] VSS[163]
R907 AG6 VSS[058] VSS[164] T15
AJ3 1 0_0402_5% AG9 T16
VCCSUSHDA 0.1U_0402_16V4Z VSS[059] VSS[165]
+1.5VS 1 2 AJ19 AH12 T17
VCCSATAPLL VSS[060] VSS[166]
1U_0603_10V4Z

1 C915 AH14 T23

VSS[061] VSS[167]
10U_0805_10V4Z

CHB1608U301_0603 AC8 T102 0.1U_0402_16V4Z AH17 B26

VCCSUS1_05[1] T103 C916 2 VSS[062] VSS[168]
1 1 +1.5VS AC16 F17 AH19 U12
VCC1_5_A[01] VCCSUS1_05[2] VSS[063] VSS[169]
C918

C919

1 AD15 AH2 U13

C917 VCC1_5_A[02] 2 VSS[064] VSS[170]
AD16 VCC1_5_A[03] AH22 VSS[065] VSS[171] U14
AE15 AD8 VCCSUS1_5_ICH_1 AH25 U15
2 2 VCC1_5_A[04] VCCSUS1_5[1] VSS[066] VSS[172]
ARX

1U_0603_10V4Z AF15 AH28 U16

2 VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[067] VSS[173]
AG15 F18 2 1 1 2 +3VALW AH5 U17
VCC1_5_A[06] VCCSUS1_5[2] R908 R909 VSS[068] VSS[174]
AH15 AH8 AD23
VCC1_5_A[07] 0_0402_5% 0_0402_5% VSS[069] VSS[175]
AJ15 AJ12 U26
VCC1_5_A[08] GM_HDMI@ PMIGM_NOHDMI@ VSS[070] VSS[176]
A18 AJ14 U27
VCCSUS3_3[01] VSS[071] VSS[177]
+1.5VS AC11 D16 AJ17 U3
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] VSS[072] VSS[178]

1 AD11 D17 AJ8 V1
C921 VCC1_5_A[10] VCCSUS3_3[03] VSS[073] VSS[179]
AE11 E22 1 B11 V13
VCC1_5_A[11] VCCSUS3_3[04] C920 VSS[074] VSS[180]
AF11 B14 V15
VCC1_5_A[12] VSS[075] VSS[181]
ATX

1U_0603_10V4Z AG10 B17 V23

2 VCC1_5_A[13] +3VALW 4.7U_0603_6.3V6M VSS[076] VSS[182]
AG11 B2 V28
B VCC1_5_A[14] 2 VSS[077] VSS[183] B
AH10 VCC1_5_A[15] B20 VSS[078] VSS[184] V29
AJ10 AF1 0.1U_0402_16V4Z B23 V4
VCC1_5_A[16] VCCSUS3_3[05] VSS[079] VSS[185]
1 1 B5 V5
VSS[080] VSS[186]
AC9 VCC1_5_A[17] B8 VSS[081] VSS[187] W26
+1.5VS C922 C923
1 C26 W27
C924 0.1U_0402_16V4Z VSS[082] VSS[188]
AC18 C27 W3
VCC1_5_A[18] 2 2 VSS[083] VSS[189]
AC19 E11 Y1
1U_0603_10V4Z VCC1_5_A[19] VSS[084] VSS[190]
T1 E14 Y28
2 VCCSUS3_3[06] VSS[085] VSS[191]
AC21 T2 E18 Y29
VCC1_5_A[20] VCCSUS3_3[07] VSS[086] VSS[192]
VCCSUS3_3[08] T3 E2 VSS[087] VSS[193] Y4
G10 VCC1_5_A[21] VCCSUS3_3[09] T4 E21 VSS[088] VSS[194] Y5
G9 T5 E24 AG28
VCC1_5_A[22] VCCSUS3_3[10] VSS[089] VSS[195]
VCCSUS3_3[11] T6 E5 VSS[090] VSS[196] AH6
AC12 U6 +3VALW E8 AF2
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[091] VSS[197]

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 F16 VSS[092] VSS[198] B25
AC14 V6 F28
VCC1_5_A[25] VCCSUS3_3[14] VSS[093]
V7 1 F29
VCCSUS3_3[15] C799 VSS[094]
+1.5VS AJ5 W6 G12
VCCUSBPLL VCCSUS3_3[16] 4.7U_0603_6.3V6K VSS[095]
+1.5VS W7 G14 A1
VCCSUS3_3[17] VSS[096] VSS_NCTF[01]
USB CORE

1 1 AA7 Y6 G18 A2
C800 C801 VCC1_5_A[26] VCCSUS3_3[18] 2 VSS[097] VSS_NCTF[02]
AB6 Y7 G21 A28
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[27] VCCSUS3_3[19] VSS[098] VSS_NCTF[03]
AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G24 VSS[099] VSS_NCTF[04] A29
AC6 G26 AH1
2 2 VCC1_5_A[29] VSS[100] VSS_NCTF[05]
AC7 VCC1_5_A[30] G27 VSS[101] VSS_NCTF[06] AH29
G8 AJ1
T104 VCC_LAN1_05_INT_ICH_1 VSS[102] VSS_NCTF[07]
A10 H2 AJ2
+3VS VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VSS[103] VSS_NCTF[08]
T105 A11 VCCLAN1_05[2] VCCCL1_05 G22 VCCCL1_05_ICH T106 H23 VSS[104] VSS_NCTF[09] AJ28
close to AC7 VCCCL1_5
G23 H28
VSS[105] VSS_NCTF[10]
AJ29
A12 1 H29 B1
VCCLAN3_3[1] C803 VSS[106] VSS_NCTF[11]
1 B12 B29
C802 VCCLAN3_3[2] @ 1U_0603_10V4Z VSS_NCTF[12]
A24 +3VS
0.1U_0402_16V4Z CHB1608U301_0603 2.2U_0603_6.3V4Z VCCCL3_3[1]
VCCCL3_3[2] B24
2
GLAN POWER

A ICH9-M ES_FCBGA676 A
1 2 A27
2 R910 VCCGLANPLL
+1.5VS 1 1
D28 VCCGLAN1_5[1]
C804 C805 D29
VCCGLAN1_5[2]
(10UF*1, 2.2UF*1) 2 2
E26 VCCGLAN1_5[3]
E27
10U_0805_10V4Z VCCGLAN1_5[4]
R911 4.7U_0805_10V4Z A26
+1.5VS 1 2
CHB1608U301_0603
+3VS
VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
1 Issued Date 2009/04/23 Deciphered Date 2010/05 Title

C806
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
Size Document Number Rev
2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 29 of 51
5 4 3 2 1
 A B C D E

Mini-Express Card(Slot 2-WIRELESS) 5.2mm high 1218 change +3VS +1.5VS

+3VS
JP18
ICH_PCIE_WAKE# 1 2 +1.5VS
(28,31) ICH_PCIE_WAKE# WAKE# 3.3V 1 1
(40) BT_ACTIVE BT_ACTIVE R364 1 2 @ 0_0402_5%
3 4 2Watt C678 WLAN@
WLAN_ACTIVE R363 1 NC GND
(40) WLAN_ACTIVE 2 @ 0_0402_5%
5 6 WLAN@ C680
WLAN_CLKREQ1# NC 1.5V 0.1U_0402_16V4Z 0.1U_0402_16V4Z
(22) WLAN_CLKREQ1# 7 CLKREQ# NC 8
9 10 2 2
GND NC
(22) CLK_PCIE_WLAN1# 11 REFCLK- NC 12
1 1
(22) CLK_PCIE_WLAN1 13 REFCLK+ NC 14
15 GND NC 16
17 NC GND 18
19 20 R369 1 2 0_0402_5%
NC NC WL_OFF# (36)
21 22 WLAN@
GND PERST# PLT_RST# (8,16,26,31)
23 24 R371 1 2 @ 0_0402_5% +3VALW
(28) PCIE_RXN3 PERn0 +3.3Vaux
25 26 R373 1 2 @ 0_0402_5% +3VS
(28) PCIE_RXP3 PERp0 GND
27 GND +1.5V 28
29 30 R375 1 2 @ 0_0402_5% ICH_SMBCLK (22,28)
GND SMB_CLK R377 1
(28) PCIE_TXN3 31 32 2 @ 0_0402_5% ICH_SMBDATA (22,28)
PETn0 SMB_DATA
(28) PCIE_TXP3 33 PETp0 GND 34
35 36 USB20_N8 (28)
GND USB_D-
37 NC USB_D+ 38 USB20_P8 (28)
+3VS 39 40 WLAN@
NC GND R378
41 42 1 2300_0402_5%
NC LED_WWAN# WLAN_LED#
43 44 1 2 WLAN_LED# (39)
NC LED_WLAN# R379 300_0402_5%
P80 port Debug @ 100_0402_5%
45 NC LED_WPAN# 46
WLAN@
47 48
EC_TX_P80_DATA R380 1 EC_TX_P80_DATA_R2 49 NC +1.5V
(36,38) EC_TX_P80_DATA 2 NC GND 50
EC_RX_P80_CLK 1 2 EC_RX_P80_CLK_R2 51 52 2005/09/27 modified.
(36,38) EC_RX_P80_CLK NC +3.3V
R383
@ 100_0402_5% 53 54 Base on OPTION GTM351E Datasheet Rev0.1
GND GND
Vcc 3.3V +/- 8%
1

R1094 TAITW_PFPET0-AFGLBG1ZZ4N0 Peak Icc 2750mA

100K_0402_5% ME@ with max supply droop 50mA
@
Average Icc 1000mA
2

JEXP1
2 2
1 GND
USB20_N10_R 2
+3VS (28) USB20_N10 USB20_P10_R USB_D-
3
Express Card Power Switch (28) USB20_P10
CPUSB# 4
5
USB_D+
CPUSB#
U38 RSV
2

R394 +1.5VS +1.5VS_CARD1 6

RSV
12 1.5Vin 1.5Vout 11 (22,28) ICH_SMBCLK 7 SMB_CLK
+1.5VS
0_1206_5%

14 13 +1.5VS_CARD1 8
1.5Vin 1.5Vout (22,28) ICH_SMBDATA SMB_DATA
9
1 NEWCARD@ +3VS_CARD1 Imax = 0.75A +1.5VS_CARD1
10
+1.5V
1

+1.5V
2 3.3Vin 3.3Vout 3 1 1 (28,31) ICH_PCIE_WAKE# 11 WAKE#
C688 4 5 NEWCARD@ +3VALW_CARD1 12
0.1U_0402_16V4Z +3VALW 3.3Vin 3.3Vout +3VALW_CARD1 C689 C690 PERST# +3.3VAUX
13 PERST#
2 NEWCARD@ 17 15 10U_0805_10V4Z 0.1U_0402_16V4Z 14
AUX_IN AUX_OUT 40mil 2 2 NEWCARD@ +3VS_CARD1
15
+3.3V
PLT_RST# +3.3V
(8,16,26,31) PLT_RST# 6 19 (22) EXP_CLKREQ# 16
SYSRST# OC# CPUSB# CLKREQ#
17
+3VS
(36,42,47) SYSON SYSON 20 8 PERST# 60mil 18
CPPE#
SHDN# PERST# +3VS_CARD1 (22) CLK_PCIE_EXP# REFCLK-
(22) CLK_PCIE_EXP 19
SUSP# REFCLK+
1 16 20
1 (34,36,42,47,48) SUSP# STBY# NC 40mil Imax = 1.35A 21
GND
(28) PCIE_RXN4 PERn0
C691 +3VALW R395 1 2 @ 100K_0402_5% 10 7 1 1 22
CPPE# GND (28) PCIE_RXP4 PERp0
0.1U_0402_16V4Z NEWCARD@ 23
2 NEWCARD@ CPUSB# C692 C693 GND
(28,36) CPUSB# 9 (28) PCIE_TXN4 24
CPUSB# 10U_0805_10V4Z 0.1U_0402_16V4Z PETn0
21 (28) PCIE_TXP4 25
PAD 2 2 NEWCARD@ PETp0
18 26
RCLKEN GND
+3VALW 27
P2231NL_QFN20 GND
28
NEWCARD@ +3VALW_CARD1 GND
1
C694 Imax = 0.275A SANTA_130801-5_RT
3 0.1U_0402_16V4Z ME@ 3
2 NEWCARD@ 1 1
@
C695 C696
10U_0805_10V4Z 0.1U_0402_16V4Z (NEW)
2 2 NEWCARD@

4 4

Security Classification
2009/04/23
Compal Secret Data
2010/05
Compal Electronics, Inc.
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/3G/TV /BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 30 of 51
A B C D E
 5 4 3 2 1

Layout Notice : Filter place as close L13 @ Layout Notice : Place as close
chip as possible. FBM-L11-321611-260-LMT_1206 chip as possible. Layout Notice : 1.2V filter. Place as close
1 2 chip as possible.
+2.5V_LAN +3V_LAN
L14 +3VALW +1.2V_LAN
2 1 1 3 Q12

S
+XTALVDD +5VALW
MBK1608601YZF_2P 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AO3414_SOT23-3

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C697 2 2 2 1

G
2
1

C698

4.7U_0805_10V4Z
0.1U_0402_16V4Z 2 2 2 2 2 2 2
1

C699

C700
R401 C701

C702

C703

C704

C705

C706

C707

C708
21.5 33K_0402_5% 1U_0603_10V4Z
L15 1 1 1 2
D
2 1 1 1 1 1 1 1 1 D
+LAN_AVDD

2
MBK1608601YZF_2P 2 2 1
C709 C710 C711 2

1
0.047U_0402_16V4Z 0.01U_0402_16V7K D C712
1
0.047U_0402_16V4Z 1 2 EN_WOL 2
(36) EN_WOL
Q13 G 0.1U_0402_16V4Z
2N7002_SOT23 S 1

3
L16
2 1 +LAN_BIASVDD
MBK1608601YZF_2P 1 U40
C713
41 LAN_TX0-
TRD0_N LAN_TX0- (32)
0.1U_0402_16V4Z 28 40 LAN_TX0+
2 (22) CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_RX1- LAN_TX0+ (32)
42 LAN_RX1- (32)
TRD1_N LAN_RX1+
(22) CLK_PCIE_LAN 29 43 LAN_RX1+ (32)
PCIE_REFCLK_P TRD1_P
TRD2_N 48 T109
(22) CLKREQ_LAN# 11 47 T110
CLKREQ TRD2_P
TRD3_N 49 T107
50 T108
+1.2V_LAN TRD3_P
1 2 3 +3V_LAN
+3VS LOW PWR
2 1 +AVDDL (CLKREQ#) and (ENERGY_DET) are R403 @ 0_0402_5%
L17 MBK1608601YZF_2P 1 2 1 2 53 2 R405 1 2 0_0402_5% C715 1 2 0.1U_0402_16V4Z
only supported in BCM5787M +3VS
R404 1K_0402_5% VMAIN_PRSNT LINKLED
1 R406 1 2 0_0402_5%
LINKLED# (32)
C714 C716 SPD100LED
+3V_LAN 1 2 54 VAUX_PRSNT SPD1000LED 67 R407 1 2 @ 0_0402_5%
1U_0603_10V4Z 0.1U_0402_16V4Z R402 1K_0402_5% 66 ACTIVITY# (32)
TRAFFICLED

3
2 1
MMJT9435T1G_SOT223
R408 1 2 59 65 LAN_CLK CTL12 1
(26) PCI_CBE#3 ENERGY_DET SCLK(EECLK)
2 1 +GPHY_PLLVDD @ 0_0402_5% 63
L18 MBK1608601YZF_2P 2 SI LAN_DATA +1.2V_LAN
2 +GPHY_PLLVDD 35 64
C GPHY_PLLVDD SO(EEDATA) Q14 C
62

2
4
C717 C718 CS
(28) PCIE_ITX_C_PRX_N6 32
4.7U_0805_10V4Z 0.1U_0402_16V4Z PCIE_RXD_N
1

2
1 1 C719
(28) PCIE_ITX_C_PRX_P6 31 PCIE_RXD_P
14 CTL12 R1098 R1099
0.1U_0402_16V7K PCIE_MRX_C_LTX_N6 REGCTL12 CTL25 10K_0402_5% 10K_0402_5% 10U_0805_10V4Z
(28) PCIE_IRX_PTX_N6 25 18
C720 PCIE_TXD_N REGCTL25 @ @ 2
2 1 +PCIE_PLLVDD RDAC 37 1 2
L19 MBK1608601YZF_2P 2 2 0.1U_0402_16V7K PCIE_MRX_C_LTX_P6 26 R409 1K_0402_5%
(28) PCIE_IRX_PTX_P6

1
C721 PCIE_TXD_P
C722 C723
4.7U_0805_10V4Z 0.1U_0402_16V4Z 23 +XTALVDD
1 1 XTALVDD
(8,16,26,30) PLT_RST# 10 6 +3V_LAN
PERST VDDIO
VDDIO 15
(28,30) ICH_PCIE_WAKE# @ 1 2 12 19
R410 0_0402_5% WAKE VDDIO
2 1 +PCIE_VDD (36) LAN_WAKE# 56
L20 MBK1608601YZF_2P 1 VDDIO
2 61
VDDIO +3V_LAN
C724 C725 +3V_LAN 1 2 58 17
SMB_CLK VDDP +2.5V_LAN
1U_0603_10V4Z 0.1U_0402_16V4Z R411 @ 47K_0402_5% 68
2 1 VDDP
+3V_LAN 1 2 57 SMB_DATA
R412 @ 47K_0402_5% 5 +1.2V_LAN
VDDC

4
13 Q15
VDDC MBT35200MT1G_TSOP6
20
VDDC
1 2 4 34
R413 0_0402_5% GPIO_0(SERIAL_DO) VDDC CTL25
55 3
LAN_WP VDDC
1 2 7 60
R414 @ 4.7K_0402_5% GPIO_1(SERIAL_DI) VDDC
1 2 GPIO2 8 36 +LAN_BIASVDD

1
2
5
6
R415 @ 4.7K_0402_5% GPIO_2 BIASVDD
Layout Notice : Place as close PCIE_PLLVDD
30 +PCIE_PLLVDD
chip as possible. +3V_LAN 1 2 9 27 +PCIE_VDD
R416 @ 0_0402_5% UART_MODE PCIE_VDD
33
PCIE_VDD
B +2.5V_LAN 38 B
AVDD +LAN_AVDD
XTALI 21 45
XTALI AVDD
R417 52
200_0402_1% XTALO AVDD
22 XTALO
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 1 XTALO 39
AVDDL +AVDDL +2.5V_LAN
10U_0805_10V4Z

2 2 2 44
AVDDL
C726

C728
C727

XTALI 16 46
Y6 REG_GND AVDDL
51 Notice : 4.7u 6.3V capactor Thickness 1.25mm

GND
AVDDL
27P_0402_50V8J

27P_0402_50V8J

1 2 24
1 1 1 PCIE_GND
2 2 Layout Notice : Filter place as close

69
C729

C730

25MHZ_20P chip as possible.

1 1
+3V_LAN

1 2

1
C731
0.1U_0402_16V4Z
R418 R419
4.7K_0402_5% 4.7K_0402_5%

2
U41
8 1
LAN_WP VCC A0
7 WP A1 2
LAN_CLK 6 3
LAN_DATA SCL NC
5 4
SDA GND
AT24C02_SO8
A LAN_CLK A
1 2
R420 4.7K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BCM5906
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 31 of 51
5 4 3 2 1
 5 4 3 2 1

+2.5V_LAN
RJ45 CONN
EMI request

R421
C732 1 2 0.1U_0402_16V4Z 330_0402_5% JRJ45
(31) ACTIVITY# 2 1 12
Amber LED-

1
R422 +3V_LAN 11 16
0_0402_5% U42 Amber LED+ SHLD4
D D
2 8 PR4- SHLD3 15
LAN_RX1+ 1 16 MDO1+ 220P_0402_50V7K
(31) LAN_RX1+

2
LAN_RX1- RD+ RX+ MDO1- C734
(31) LAN_RX1- 2 RD- RX- 15 7 PR4+
C733 1 2 0.1U_0402_16V4Z TCT 3 14 MCT0 R423 2 1 75_0402_5%
CT CT RJ45_PR 1 MDO1-
4 13 6
NC NC PR2-
5 NC NC 12
C735 1 2 0.1U_0402_16V4Z TCT 6 11 MCT1 R424 2 1 75_0402_5% 5
LAN_TX0+ CT CT MDO0+ PR3-
(31) LAN_TX0+ 7 TD+ TX+ 10
@ LAN_TX0- 8 9 MDO0- 4
(31) LAN_TX0- TD- TX- PR3+
MDO1+ 3
350uH_NS0013LF PR2+
MDO0- 2 PR1-
14
MDO0+ SHLD2
R425 1
330_0402_5% PR1+
(31) LINKLED# 2 1 10 13
Green LED- SHLD1

+3V_LAN 9 Green LED+

Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF 1
FOX_JM36113-P2221-7F
C736 ME@
220P_0402_50V7K
2

LAN_RX1- 2 1 C737
R426 49.9_0402_1% 1 2 0.1U_0402_16V4Z
LAN_RX1+ 2 1
R427 49.9_0402_1% RJ45_PR 1 2
C738
1000P_1206_2KV7K

2
C R428 C

0_0402_5%
LAN_TX0- 2 1 C739
R429 49.9_0402_1% 1 2 0.1U_0402_16V4Z

1
LAN_TX0+ 2 1
R430 49.9_0402_1%

near LAN controller

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONTROLLER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 32 of 51
5 4 3 2 1
 A B C D E F G H

+5VS +3VS

1 1 1 1 1 1
@
1 C740 C741 C742 C743 C744 C745 1
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

SATA HDD Conn. SATA ODD Conn.

JP22
JP21
1 GND 1 GND GND 14
SATA_ITX_DRX_P0 2 SATA_ITX_DRX_P1 2 15
(27) SATA_ITX_DRX_P0 A+ (27) SATA_ITX_DRX_P1 A+ GND
SATA_ITX_DRX_N0 3 SATA_ITX_DRX_N1 3
(27) SATA_ITX_DRX_N0 A- (27) SATA_ITX_DRX_N1 A-
4 4
2 SATA_DTX_C_IRX_N0 C796 1 SATA_DTX_IRX_N0 GND SATA_DTX_C_IRX_N1 SATA_DTX_IRX_N1 GND 2
2 0.01U_0402_16V7K 5 B-
C746 1 2 0.01U_0402_16V7K 5 B-
(27) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C797 1 SATA_DTX_IRX_P0 (27) SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1
2 0.01U_0402_16V7K 6 C798 1 2 0.01U_0402_16V7K 6
(27) SATA_DTX_C_IRX_P0 B+ (27) SATA_DTX_C_IRX_P1 B+
7 7
GND GND

8 8
VCC3.3 DP
+3VS 9 VCC3.3 +5VS 9 +5V
10 10
VCC3.3 +5V
11 GND 11 MD
12 12
GND GND
13 GND 13 GND
14
VCC5 OCTEK_SLS-13SD1G_NR
+5VS 15 VCC5
16 ME@
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12
22 VCC12
23
G1
24
G2
OCTEK_SAT-22SB1G_RV
ME@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 33 of 51
A B C D E F G H
 A B C D E

0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p
AUDIO CODEC CODEC POWER (3.33V)
For Layout: 250mW
In order for the modem wake on ring feature to function, Place decoupling caps near the power pins of R1030 +3VS
+5VALW +VDDA_CODEC
the CODEC must be powered by a rail that is not SmartAMC device. 2 1 W=40Mil U64
removed when the system is in standby. MBV2012301YZF_0805 @
1 2 1 2 1 5
+3VDD_CODEC +3VAMP_CODEC C1064 4.7U_0805_10V4Z C1065 0.1U_0402_16V4Z VIN OUT
1 1
R1031 R1032 2.2kohm for MICL + MICR 2 @ C1066 @ C1067
GND
+3VS 1 2 2 1 +VDDA_CODEC 4.7kohm for MICL or MICR

680P_0402_50V7K

680P_0402_50V7K
1 1

1U_0603_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
MBV2012301YZF_0805 MBV2012301YZF_0805 (30,36,42,47,48) SUSP# 3 4 0.1U_0402_16V4Z 4.7U_0805_10V4Z
SHDN# BP 2 2

680P_0402_50V7K

1U_0603_10V4Z
R1033 1 1 1 1 1 1 1 1 1
+3VALW 1 2 @ APE8805A-33Y5P_SOT23-5 @
MBV2012301YZF_0805 @ C1076
@ +3VAMP_CODEC 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

C1068

C1069

C1070

C1071

@ C1072

C1073

C1074

C1075

1K_0402_5%

<BOM Structure>
MIC_C_BIAS

R1034
10U_0805_10V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
R1036 1 1
+3VDD_CODEC

C1079

C1080
1 1 C1159 0.1U_0402_16V4Z
C1077

C1078
2 1

1
2

0.01U_0402_16V7K C1160 2 2
2 2

R19

R1038
R1036 1 2

44

26
40
36
9
4
3
<BOM Structure>

R1041

10U_0805_10V4Z
4.7K_0603_5% 0_0603_5% U65

2
PMIGM_NOHDMI@ R1037 0_0402_5% 1

VDD_IO
DVDD_1-8
DVDD_3-3
DVDD_44

AVDD_26
AVDD_40
AVEE
@

C1081
+1.5VS 1 GM_HDMI@
2
1

<BOM Structure>
34 HP_OUTL (35)
PORTA_L
2

2.2K_0402_5%

2.2K_0402_5%
R1042 1 2 33_0402_5%11 35
(8,16,27) HDA_RST_CODEC# HP_OUTR (35)

1
RESET# PORTA_R

4.7K_0402_5%
R1043

1
3.9K_0603_1% R1044 1 2 33_0402_5% 6 19
(8,16,27) HDA_BITCLK_CODEC BIT_CLK MICBIASB
@ R1045 1 2 33_0402_5%10 14
(8,16,27) HDA_SYNC_CODEC SYNC PORTB_L
R1046 1 2 33_0402_5% 8 15
(27) HDA_SDIN2
1

R1047 1 33_0402_5% 5 SDATA_IN PORTB_R

(8,16,27) HDA_SDOUT_CODEC 2 MIC_C_BIAS
SDATA_OUT C1082 2.2U_0603_6.3V6K
MICBIASC 18
@ 16 MIC_EXTL 1 2 R1048 2 1100_0402_5%

2
CX20548 DIBP_HS
DIBN_HS
R1049
R1051
1
1
@
2 0_0402_5% DIBP_C
2 0_0402_5% DIBN_C
43
42
DIB_P
DIB_N
PORTC_L
PORTC_R
17 MIC_EXTR 1
C2
2
2.2U_0603_6.3V6K R17
2 1
100_0402_5%
EXT_MIC_L (35)
EXT_MIC_R (35) external MIC
2

AMOM DAA R3
PORTD_L
27
2

PC_BEEP 12 28
100K_0402_5% PC_BEEP PORTD_R
11/20 update
48 20 MIC_INL 1 2 INT_MICL Internal MIC / Array MIC
S/PDIF MIC_L MIC_INR C1084 2.2U_0603_6.3V6K
PC_BEEP dB control 21
1

MIC_R
11/20 update
MONO 29 Internal WOOFER
1 2 45 30 LINE_OUTL (35)
R1052 1 GPIO2 STEREO_L
2 10K_0402_5% 46 GPIO1 STEREO_R 31 LINE_OUTR (35) Internal SPKR.
R1053 10K_0402_5% 47
(36) EAPD EAPD/GPIO0
+3VAMP_CODEC
13 SENSE 1 2
HDA_BITCLK_CODEC SENSEA For Vista R1054 5.1K_0402_1%
1 24 VC_REFA
DMIC_CLOCK VREF
2
DMIC_1/2
1 2 PLUG_IN (35) Port A
1

10U_0805_10V4Z
0.1U_0402_16V4Z
R1056 39 VREF_HI R1055 5.1K_0402_1%
R1056 FLY_P VREF_LO
FLY_N 37 1 2 1 1

C1087

C1088
33_0402_5% C1086 1U_0603_10V4Z 1 2 MIC_JD (35) Port C
GM@ 22 R1057 20K_0402_5%
DVSS_41

AVSS_25
AVSS_38

VREF_LO
DVSS_7

23
2

VREF_HI 2 2
1 RESERVED_32
32 port A : 5.11K ohm

1U_0603_10V4Z

1U_0603_10V4Z
47_0402_1% RESERVED_33
33 port B : 10.0K ohm
C1089 PM@ 1 1
GM@ CX20561-12Z_LQFP48_7X7 port C : 20.0K ohm
10P_0402_50V8J
7
41

25
38

2 port D : 39.2K ohm

C1089
2 2

C1090

C1091
3 0216_Change value. 3

33P_0402_50V8K
PM@ +3VS
DIGITAL ANALOG
1

R1058
C1092 10K_0402_1%
1 2
2

0.1U_0402_16V4Z 2 1C1093
1

C1094 1U_0603_10V4Z
1 2
0.1U_0402_16V4Z R1059
10K_0402_1%
C1095 C1096 1U_0603_10V4Z
2

1 2 1 2 PC_BEEP1 2 1 PC_BEEP
2

0.1U_0402_16V4Z R1060 20K_0402_5% MIC1

R25 1 2 1 INT_MICL
C1097 0_0402_5% 2 GNDA 0_0603_5% R1077
1

1 2 C1098 R1061 @ C 1
2

0.1U_0402_16V4Z (36) BEEP# 2 1 1 2 2 Q46 WM-64PCY_2P

1

1 B 2SC2411KT146_SOT23-3 R1062 45@ C1158

R1063 C1101 560_0402_5% E 20K_0402_5% 47P_0402_50V8J
3

1 2 1U_0603_10V4Z 2
0_0402_5% @ 0.1U_0402_16V4Z GNDA
1

2
R1064
1 2 @
0_0402_5%
4 C1102 4
R1065 R1066
1 2 (28) SB_SPKR 2 1 1 2
0_0402_5%
1

560_0402_5%
1U_0603_10V4Z R1067 D44 @
GND GNDA 10K_0402_5%
RB751V_SOD323

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

Place these C and R around AGND and DGND, CX20561-AMOM Codec
then choose the one which is close to Codec THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
to populate DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWA5/6 LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 34 of 51
A B C D E
 5 4 3 2 1

Speaker Connector

+3VALW
+5VS +5VAMP

W=40mil

2
2 1 R33
0_0603_5% R32 10K_0402_5%
1 1 @
U45

1
D C568 C569 D
0.1U_0402_16V4Z 4.7U_0805_10V4Z 16 12 GAIN0 GAIN1
2 2 VDD NC
6 PVDD
15 0 0 6dB
PVDD AMP_OFF# R34
SHUTDOWN 19 1 2 EC_MUTE# EC_MUTE# (36) 0 1 10dB
0_0402_5%
GAIN0 2 GAIN0
1 0 15.6dB
8 SPK_L1-
GAIN1 3
LOUT- 1 1 21.6dB
GAIN1 SPK_R1-
ROUT- 14

4 SPK_L2+ 20mil +5VAMP +5VAMP

0.033U_0402_16V7K C570 LOUT+
LINE_OUTL 1 2 LIN 5 18 SPK_R2+
(34) LINE_OUTL LIN- ROUT+

2
LINE_OUTR 1 2 RIN 17
(34) LINE_OUTR RIN-
1 @ R35 R36
0.033U_0402_16V7K C571 GND 100K_0402_1% 100K_0402_1%
9 LIN+ GND 11

1
R37 R38 1 13
GND
7 20

2 1

2 1
RIN+ GND

10K_0402_5%

10K_0402_5%
C572 21 GAIN0 GAIN1
@ @ GND
0.1U_0402_16V4Z
2 R39 R40
10 1
2

2
BYPASS 100K_0402_1% 100K_0402_1%
1
C573 @
C574 4.7U_0805_10V4Z

1
APA2031RI-TRL_TSSOP20 2
0.1U_0402_16V4Z
2

C
20MIL JP23 D8
C

SPK_R1- 2 1 R_SPK_R1- 1 R_SPK_R1- 2

SPK_R2+ 0_0603_5%2 1
1 R41 R_SPK_R2+ 2 2 1
SPK_L1- 0_0603_5%2 1 R42 R_SPK_L1- 3 R_SPK_R2+ 3
SPK_L2+ 0_0603_5%2 3
1 R48 R_SPK_L2+ 4 4
0_0603_5% R49 5 @ PJDLC05_SOT23-3
G5
6 G6 D9
Near JP14 ACES_85205-04001 R_SPK_L1- 2
ME@ 1
R_SPK_L2+ 3

@ PJDLC05_SOT23-3

Audio Jack
220P_0402_50V7K 220P_0402_50V7K SM010018110
EXT_MIC_L 1 2 EXT_MIC_L-2
(34) EXT_MIC_L
2

R50 S SUPPRE_ KC FBMA-L10-160808-800LMT 0603

C576 C575 Headphone
1

1 1
1

@ R52 @ R51 C577 @ C578

1K_0402_5% 1K_0402_5% 47P_0402_50V8J 10P_0402_50V8J
GNDA 2 2
Audio Jack
2

GNDA
GNDA GNDA
B GNDA JHP1 SM010018110 MIC IN B

1 EXT_MIC_R 1 2 EXT_MIC_R-2
(34) EXT_MIC_R
HP_OUTL 1SM010018110
2 PL-OUT R1096 56_0402_1% 2 R53 S SUPPRE_ KC FBMA-L10-160808-800LMT 0603
(34) HP_OUTL
R55 S SUPPRE_ KC FBMA-L10-160808-800LMT 0603 6
HP_OUTR 1SM010018110
2 PR-OUT R1097 56_0402_1% 3 1 1
(34) HP_OUTR
R54 S SUPPRE_ KC FBMA-L10-160808-800LMT 0603
(34) PLUG_IN PLUG_IN 4 C579 @ C580 JMIC1
47P_0402_50V8J 10P_0402_50V8J 1
2 2
5 2
6
FOX_JA6333L-B3S0-7F GNDA GNDA 3
ME@
(34) MIC_JD MIC_JD 4

1 GNDA 5

10P_0402_50V8J C581 FOX_JA6333L-B3S0-7F

@ ME@
2
GNDA

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title
AMP,Audio speaker CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 35 of 51
5 4 3 2 1
 +3VALW
+EC_AVCC
1 1 1 1 1 1

0.1U_0402_16V4Z
C516

0.1U_0402_16V4Z
C517

0.1U_0402_16V4Z
C518

0.1U_0402_16V4Z
C519

1000P_0402_50V7K
C520

1000P_0402_50V7K
C523
L21 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603
2 1
C521 2 2 2 2 2 2
0.1U_0402_16V4Z C522

111
125
1000P_0402_50V7K U46

22
33
96

67
9
1 2 1 ECAGND 2
L22 FBM-11-160808-601-T_0603

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 2
R56 0_0402_5%
D38 INVT_PWM
1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 21 INVT_PWM (24)
(27) GATEA20 KB_RST#_EC BEEP#
(27) KB_RST# 2 1 2 23 BEEP# (34)
RB751V_SOD323 KBRST#/GPIO01 BEEP#/PWM2/GPIO10
(28,38) SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 NOVO# (41)
@ 4 27 ACOFF
(27,38) LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (45)
(27,38) LPC_AD3 5 LAD3
LPC_AD2 7 PWM Output
(27,38) LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
(27,38) LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP BATT_TEMPA (44)
LAD0 LPC & MISC
(27,38) LPC_AD0 10 64 BATT_OVP (45)
BATT_OVP/AD1/GPIO39
2 1 2 1 65 ADP_I (45)
ADP_I/AD2/GPIO3A CPUSB#
@ C525 22P_0402_50V8J @ 10_0402_5%
(22) CLK_PCI_LPC 12
PCICLK AD Input AD3/GPIO3B
66 CPUSB# (28,30)
R58 13 75
(26,38) PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 TSATN#_EC
1 2 37 76 R59 1 2 @ 0_0603_5%
+3VALW ECRST# SELIO2#/AD5/GPIO43 TSATN# (8) +5VS
R57 47K_0402_5% EC_SCI# 20
(28) EC_SCI# SCI#/GPIO0E
2 38
CLKRUN#/GPIO1D DAC_BRIG TP_CLK R61
68 DAC_BRIG (24) 1 2 4.7K_0402_5%
C524 DAC_BRIG/DA0/GPIO3C EN_FAN1
EN_DFAN1/DA1/GPIO3D 70 EN_FAN1 (5)
0.1U_0402_16V4Z DA Output 71 IREF TP_DATA R62 1 2 4.7K_0402_5%
1 KSI0 IREF/DA2/GPIO3E IREF (45)
55 72 +3VALW
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ (45) BATT_OVP
56 KSI1/GPIO31 1 2
KSI2 57 EC_MUTE# R65 1 2 @ 10K_0402_5% C526 100P_0402_50V8J
KSI3 KSI2/GPIO32 BATT_TEMP
58 83 EC_MUTE# (35) 1 2
+3VALW KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_ON USB_ON R66
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_ON (40) 1 @ 2 10K_0402_5% C527 100P_0402_50V8J
KSI5 60 85 ACIN 1 2
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 C528 100P_0402_50V8J
KSO[0..15] KSI7 62 87 TP_CLK
(38) KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (38)
KSO0 39 88 TP_DATA
KSI[0..7] KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (38)
40 KSO1/GPIO21
(38) KSI[0..7] KSO2 41
KSO2/GPIO22
1

KSO3 42 97 R67 1 2 @ 4.7K_0402_5%

KSO4 KSO3/GPIO23 SDICS#/GPXOA00
R931 R932 43
KSO4/GPIO24 SDICLK/GPXOA01
98 EN_WOL (31) KB926 SPI STRAP PIN
KSO5
KSO5/GPIO25 Int. K/B
47K_0402_5% 47K_0402_5% 44 99 +3VS
SDIDO/GPXOA02 BATT_SEL_EC (45)
<BOM Structure>
<BOM Structure> KSO6 45 109
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 CMOS_OFF# (40)
46 SPI Device Interface
2

KSO7/GPIO27

1
KSO8 47
KSO1 KSO9 KSO8/GPIO28 FRD#SPI_SO
48 119 FRD#SPI_SO (39)
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI R68
49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI (39)
KSO2 KSO11 50 SPI Flash ROM 126 SPI_CLK 10K_0402_5%
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SPI_CLK (39)
51 128 FSEL#SPICS# (39)

2
KSO13 KSO12/GPIO2C SPICS# I2C_INT
52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73 +3VALW
KSO16 KSO15/GPIO2F CIR_RX/GPIO40 I2C_INT
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 I2C_INT (41)
KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG (45)

1
90 CHARGE_LED0#
BATT_CHGI_LED#/GPIO52 CAPS_LED# CHARGE_LED0# (39)
+3VALW 91
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
(44) EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 CHARGE_LED1# (39)
R21
EC_SMB_DA1 78 93 10K_0402_5%
(44) EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
2

EC_SMB_CK2 79 SM Bus 95 SYSON

(5,16) EC_SMB_CK2 SYSON (30,42,47)

2
R69 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 EC_RSMRST#
(5,16) EC_SMB_DA2 80 121 VR_ON (49)
10K_0402_5% SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
127 ACIN (28,43,45)
AC_IN/GPIO59 @
1

6 100 EC_RSMRST#
(28) SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# (28)
(28) SLP_S5# 14 101 EC_LID_OUT# (28)
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON
(28) EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON (41)
1 2 LID_SW# 16 103 D39 RB751V_SOD323
(31) LAN_WAKE# (41) LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06
R70 0_0402_5% ESB_CK_R 17 104 ICH_POK_EC 1 2 ICH_POK
ESB_DA_R SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# ICH_POK (8,28)
18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# (24)
1 2 EC_PME# 19 GPIO 106 1 2 1 2
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# (30) +3VS
R71 @ 0_0402_5% 25 107 R72 0_0402_5% R73 4.7K_0402_5%
(41) KILL_SW# FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 DDR3_SM_PWROK @
(5) FAN_SPEED1 28 108
FAN_SPEED1/FANFB1/GPIO14 GPXO11
S

3 1 3G_OFF# 29 FANFB2/GPIO15
(26) PCI_PME# EC_TX_P80_DATA
(30,38) EC_TX_P80_DATA 30
@ Q17 EC_RX_P80_CLK EC_TX/GPIO16
(30,38) EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# (28)
32 112
G

2N7002_SOT23 (41) ON/OFF# ENBKL (24)

2

+3VALW ON_OFF/GPIO18 ENBKL/GPXID2

(39) PWR_LED_SC# 34 114 EAPD (34)
NUM_LED# PWR_LED#/GPIO19 GPXID3 EC_THERM#
36
NUMLED#/GPIO1A GPI GPXID4
115 EC_THERM# (28)
116 SUSP#
GPXID5 PBTN_OUT# SUSP# (30,34,42,47,48)
117 PBTN_OUT# (28)
GPXID6
118 BT_OFF# (40)
XCLKI GPXID7
122 XCLK1
+3VALW XCLKO 123 124 ESB_CK_R 1 2 ESB_CK ESB_CK (41)
XCLK0 V18R R1090 0_0402_5%
1 1
AGND

1 2 FRD#SPI_SO ENE@
GND
GND
GND
GND
GND

R74 @ 100K_0402_1% C529 C927 CAPS_LED# 1 2

+3VALW 1U_0603_10V4Z 1U_0603_10V4Z R1091 0_0402_5%
1 2 FSEL#SPICS# KB926QFA1_LQFP128 2 2 @ NOSB@
11
24
35
94
113

69

R75 @ 100K_0402_1% 2 LID_SW#

1
R76 @ 100K_0402_1% D2 version
ECAGND

KSO17 ESB_DA_R ESB_DA ESB_DA (41)

1
R77
2
@ 10K_0402_5% SA00001J570 1 2
R1092 0_0402_5%
ENE@
NUM_LED# 1 2
R1093 0_0402_5%
+5VALW +3VS SUSP# NOSB@
SPI_CLK 1
1 2 EC_SMB_CK1 1 2 ESB_CK_R @
1

R78 4.7K_0402_5% R218 2.2K_0402_5% C530

ENE@ 1000P_0402_50V7K
1 2 EC_SMB_DA1 1 2 ESB_DA_R R221 2
R219 4.7K_0402_5% R220 2.2K_0402_5% 0_0402_5%
ENE@
2

1
+3VS
C531
10P_0402_50V8J
2 1 2
1

C532 15P_0402_50V8J
XCLKO
R222 R223
X1
1

2.7K_0402_5% 2.7K_0402_5%
3 4 @ For SED Team
2

EC_SMB_CK2 NC OUT R224

EC_SMB_DA2 2 1 20M_0603_5%
NC IN
1 1
2

@ @ XCLKI
C533
100P_0402_50V8J
C534 32.768KHZ_12.5PF_1TJS125BJ4A421P
100P_0402_50V8J<BOM Structure>
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
2 1 Issued Date 2009/04/23 Deciphered Date 2010/05 Title
C535 15P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 36 of 51
 5 4 3 2 1

D D

+VCC_3IN1
Card reader(XD/SD/MMC/MS/MS-Pro HD SD)
CARD@
C506
+3VALW 2 1
0.1U_0402_16V4Z
Trace width:20mil
Trace width:20mil 11/04 new added +VCC_3IN1 7 in 1 Card Reader
0.1U_0402_16V4Z

1
C507
C926 R929
CARD@ C508 0.1U_0402_16V4Z @ @
2
1 2 2 1
Trace width:20mil 1 2
+3VALW
CARD@ 10U_0805_6.3V6M 100K_0402_1%
T2 U47 JP34
Trace width:20mil T3
0.1U_0402_16V4Z

1 3 XD-VCC SD-VCC 21
1 AV_PLL MS-VCC 28
C509 3 SD_DATA5_XD_DATA0_MS_DATA6 32
CARD@ NC SD_CLK_XD_DATA1_MS_CLK XD-D0 SD_CLK
2
7 NC 10 XD-D1 7 IN 1 CONN SD_CLK 20
9 SD_DATA7_XD_DATA2_MS_DATA2 9 14 SD_DATA0_XD_DATA6_MS_DATA0
CARD_3V3 C510 XD-D2 SD-DAT0
11 XD_DATA3_MS_DATA1 8 12 XD_DATA4_SD_DATA1
D3V3 XD_DATA4_SD_DATA1 XD-D3 SD-DAT1 SD_DATA2_XD_RE#
33 D3V3 VREG 10 1 2 7 XD-D4 SD-DAT2 30
+3VALW 22 XD_DATA5_MS_BS 6 29 SD_DATA3_XD_WE#
MS_D4 SD_DATA0_XD_DATA6_MS_DATA0 XD-D5 SD-DAT3 SD_DATA4_XD_WP#_MS_DATA7
Trace width:20mil 8
NC 30 1U_0603_10V4Z SD_DATA6_XD_DATA7_MS_DATA3
5
4
XD-D6 SD-DAT4 27
23 SD_DATA5_XD_DATA0_MS_DATA6
RST# 3V3_IN CARD@ XD-D7 SD-DAT5 SD_DATA6_XD_DATA7_MS_DATA3
44 RST# SD-DAT6 18
0.1U_0402_16V4Z

1 1 MODE SEL 45 SD_DATA3_XD_WE# 34 16 SD_DATA7_XD_DATA2_MS_DATA2

C512 MODE_SEL XD_CLE SD_DATA4_XD_WP#_MS_DATA7 XD-WE SD-DAT7 SD_CMD
C
47 XTLO XD_CLE_SP19 43 33 XD-WP SD-CMD 25 C
C511 CARD@ CLK_48M_CR 48 42 XD_CE# XD_ALE 35 1 SD_CD#
(22) CLK_48M_CR XTLI XD_CE#_SP18 XD-ALE SD-CD-SW
10U_0805_6.3V6M 41 XD_ALE XD_CD# 40
2 2 USB20_N7 XD_ALE_SP17 SD_DATA2_XD_RE# XD_RDY XD-CD SD_WP
CARD@ (28) USB20_N7 4 DM SD_DAT2/XD_RE#_SP16 40 39 XD-R/B SD-WP-SW 2
USB20_P7 5 39 SD_DATA3_XD_WE# SD_DATA2_XD_RE# 38
(28) USB20_P7 DP SD_DAT3/XD_WE#_SP15 XD-RE
XD_RDY XD_CE#
14 GPIO0 XD_RDY_SP14 38
37 SD_DATA4_XD_WP#_MS_DATA7
close to connector (JP34) XD_CLE
37
36
XD-CE
26 MS_CLK
SD_DAT4/XD_WP#/MS_D7_SP13 SD_DATA5_XD_DATA0_MS_DATA6 CARD@ XD-CLE MS-SCLK SD_DATA0_XD_DATA6_MS_DATA0
SD_DAT5/XD_D0/MS_D6_SP12 35 MS-DATA0 17
34 SD_CLK_XD_DATA1_MS_CLK R227 1 2 MS_CLK 11 15 XD_DATA3_MS_DATA1
SD_CLK/XD_D1/MS_CLK_SP11 SD_DATA6_XD_DATA7_MS_DATA3 22_0402_5% 7IN1 GND MS-DATA1 SD_DATA7_XD_DATA2_MS_DATA2
SD_DAT6/XD_D7/MS_D3_SP10 31 31 7IN1 GND MS-DATA2 19
29 MS_INS# R228 1 2 SD_CLK 24 SD_DATA6_XD_DATA7_MS_DATA3
MS_INS#_SP9 SD_DATA7_XD_DATA2_MS_DATA2 22_0402_5% MS-DATA3 MS_INS#
SD_DAT7/XD_D2/MS_D2_SP8 28 MS-INS 22
27 SD_DATA0_XD_DATA6_MS_DATA0 CARD@ 13 XD_DATA5_MS_BS
SD_DAT0/XD_D6/MS_D0_SP7 MS-BS
1

CARD@ 1 26 XD_DATA3_MS_DATA1 41
R252 SD_DAT1/XD_D3/MS_D1_SP6 XD_DATA5_MS_BS 7IN1 GND
XD_D5_SP5 25 2 42 7IN1 GND
0_0402_5% C600 23 XD_DATA4_SD_DATA1 @ 2
47P_0402_50V8J XD_D4/SD_DAT1_SP4 SD_CD# C606 @ TAITW_R015-B10-LM_NR
SD_CD#_SP3 21
2 @ SD_WP 10P_0402_50V8J C607 ME@
20
2

SD_WP_SP2 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
19 XD_CD# 10P_0402_50V8J 1 1
XD_CD#_SP1 1
EEDI 18
C514 C515
2 13 R96 1 2 +3VALW CARD@ CARD@
RREF XTAL_CTR 0_0402_5% 2 2
12
MS_D5 24 20mil
DGND CARD@
close to U47 32 DGND EEDO 15
2

EECS 16
R229 6 17
6.19K_0402_1% AGND EESK SD_CMD
46 AGND SD_CMD 36
CLK_48M_CR CARD@
1
1

RTS5159-GR_LQFP48_7X7
R928 CARD@
22.1_0402_1%
CARD@ +3VALW
B 2 B
2

C601
10P_0402_50V8J R226
1 CARD@ CARD@
100K_0402_5%
2

RST#
1

1 R930
C513 510K_0402_1%
CARD@ @
RTS5159 application notes V1.0 2008/09/30 by Ryan Chen 1U_0603_10V4Z~D
2

R252 C600 USB Auto De-link(*1) MS Formatter(*2) Description

0 NC Yes Recommended

NC 47pF Yes Yes

Compatible with
NC NC RTS5158E

NC 680pF Yes LED ON (*3)

10K 180pF LED ON (*3)

10K 680pF Yes

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB_CR board
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 37 of 51
5 4 3 2 1
 5 4 3 2 1

Source:SP01000IE00
2nd source:SP01000IF00
30 pin
INT_KBD Conn. JP26 EC DEBUG PORT
KSI[0..7] KSI1 1
KSI[0..7] (36) 1
KSI7 2
KSO[0..15] KSI6 2
D KSO[0..15] (36) 3 3 D
KSO9 4
KSI4 4 JP25
5 5
KSI5 6 +3VALW 1
KSO2 C478 1 6 1
2 @ 100P_0402_50V8J KSO1 C479 1 2 @ 100P_0402_50V8J KSO0 7 7 (30,36) EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSI2 8 EC_RX_P80_CLK 3
8 (30,36) EC_RX_P80_CLK 3
KSO15 C480 1 2 @ 100P_0402_50V8J KSO7 C477 1 2 @ 100P_0402_50V8J KSI3 9 4
KSO5 9 4
10 10
KSO6 C481 1 2 @ 100P_0402_50V8J KSI2 C482 1 2 @ 100P_0402_50V8J KSO1 11 ACES_85205-0400
KSI0 11
12 12 ME@
KSO8 C483 1 2 @ 100P_0402_50V8J KSO5 C484 1 2 @ 100P_0402_50V8J KSO2 13
KSO4 13
14 14
KSO13 C485 1 2 @ 100P_0402_50V8J KSI3 C486 1 2 @ 100P_0402_50V8J KSO7 15
KSO8 15
16 16
KSO12 C487 1 2 @ 100P_0402_50V8J KSO14 C488 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO11 C489 1 2 @ 100P_0402_50V8J KSI7 C490 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO10 C491 1 2 @ 100P_0402_50V8J KSI6 C492 1 2 @ 100P_0402_50V8J KSO14 21
KSO11 21
22 22
KSO3 C493 1 2 @ 100P_0402_50V8J KSI5 C494 1 2 @ 100P_0402_50V8J KSO10 23
KSO15 23
24 24
KSO4 C495 1 2 @ 100P_0402_50V8J KSI4 C496 1 2 @ 100P_0402_50V8J

KSI0 C497 1 2 @ 100P_0402_50V8J KSO9 C498 1 2 @ 100P_0402_50V8J 26

GND2
GND1 25
KSO0 C499 1 2 @ 100P_0402_50V8J KSI1 C500 1 2 @ 100P_0402_50V8J

E-T_6905-E24N-01R +5VS JP27

C
CONN PIN define need double check ME@ 1 C
TP_CLK 1
(36) TP_CLK 2 2
TP_DATA 3
(36) TP_DATA 3
SW /L 4
SW /R 4
5 5
6 6
7 GND

6
5
8 GND
2 4
SW /L ACES_85201-06051
1 3 ME@

FOR LPC SIO DEBUG PORT SW 1 +5VS TP_DATA C501 1 2 @ 100P_0402_50V8J

EVQPLHA15_4P
JP28 TP_CLK C502 1 2 @ 100P_0402_50V8J
1 +5VS C503
1

6
5
2 2
3 +3VS 2 4 0.1U_0402_16V4Z
3 SW /R
4 4
5 5 1 3
6 6 CLK_14M_SIO (22)
7 LPC_AD0
7 LPC_AD0 (27,36) SW 2
8 LPC_AD1 TP_CLK TP_DATA
8 LPC_AD1 (27,36) EVQPLHA15_4P
9 LPC_AD2
9 LPC_AD2 (27,36)
10 LPC_AD3
10 LPC_AD3 (27,36)

2
11 LPC_FRAME#
11 LPC_FRAME# (27,36)
12 LPC_DRQ0# D40
12 LPC_DRQ0# (27)
13 PCI_RST# PJDLC05_SOT23-3
B 13 PCI_RST# (26,36) B
14 2 1 @
14 CLK_PCI_DB R232 10K_0402_5%
15 15 CLK_PCI_DB (22)
16 SERIRQ @
16 SERIRQ (28,36)
17 17
18 18
19

1
19
20 20

ACES_85201-2005
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 38 of 51
5 4 3 2 1
 FOR EC 16M SPI ROM

+3VALW
20mils
1

2
C504
0.1U_0402_16V4Z R233
2
10K_0402_5%

U48

1
INT_SPI_CS# 1 8
FRD#SPI_SO R234 1 SPI_SO CS# VCC
(36) FRD#SPI_SO 2 15_0402_5% 2 SO HOLD# 7
3 6 SPI_CLK_R R235 1 2 15_0402_5% SPI_CLK SPI_CLK_R
WP# SCLK SPI_SI FWR#SPI_SI SPI_CLK (36)
4 5 R236 1 2 15_0402_5%
GND SI FWR#SPI_SI (36)

1
MX25L1605AM2C-12G_SO8 <BOM Structure>
R237
33_0402_5%

2
+3VALW
1
<BOM Structure>
C505
22P_0402_50V8J
INPUT 2
OUTPUT
Y
OR Gate
A B R238

5
U49
1 INT_FLASH_EN# 100K_0402_5% 1 2

P
INT_SPI_CS# R239 1 INB
L L L 2 15_0402_5% 4 O
2 FSEL#SPICS#
INA FSEL#SPICS# (36)

G
H L H MC74VHC1G32DFT2G_SC70-5

3
L H H
H H H 1
@
2
R240 22_0402_5%

+3VALW
JP29
FSEL#SPICS# 1 2
SPI_SO 1 2 INT_FLASH_EN#
3 4
3 4 SPI_CLK_R
(28) SB_INT_FLASH_SEL 5 6
5 6 SPI_SI FD1 FD2 FD3 FD4
7 8
7 8
1 1 1 1
ME@ E&T_2941-G08N-00E~D

H1 H2 H3 H4
HOLEA HOLEA HOLEA HOLEA

+5VALW +5VS
LED Green

1
H5 H6 H7 H8 H9 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
LED2 1 2 BT_LED# (40)
R6 BT@ 0_0402_5%
1 2 2 1
R241 300_0402_5% H11 H12 H13 H14 H15 H16 H17 H18
1 2 WLAN_LED# (30) HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
19-213A-T1D-CP2Q2HY-3T_WHITE
R7 WLAN@
0_0402_5%

1
LED3 H20 H21 H22
HOLEA HOLEA HOLEA
1 2 2 1 DRIVE_LED# (27)
R242 432_0402_1%

1
19-213A-T1D-CP2Q2HY-3T_WHITE
LED4

1 2 2 1 PWR_LED_SC# (36)
R243 432_0402_1%
LED5
19-213A-T1D-CP2Q2HY-3T_WHITE
Blue CHARGE_LED0#
1 2 2 1 CHARGE_LED0# (36)
R244 432_0402_1%

19-213A-T1D-CP2Q2HY-3T_WHITE 7.3mA
+3VALW R245 LED6 Amber CHARGE_LED1#
1 2 2 1 CHARGE_LED1# (36)
499_0402_1%
S LED 19-217/S2C-FM2P1VY/3T 0603 ORANGE
6mA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 39 of 51
 A B C D E

+5VALW
+USB_VCCA
U50
1 GND OUT 8
C440 0.1U_0402_16V4Z 2 7
IN OUT
2 1 3 IN OUT 6
USB_ON 4 5
(36) USB_ON EN
G545A1P1U_SO8
OC# USB_OC#0 (28)
LIFT USB CONN. 1 LIFT USB CONN. 2
USB_OC#1 (28)
<BOM Structure>
+USB_VCCA +USB_VCCA
1
1 C444 W=60mils W=60mils 1
@ 1000P_0402_50V7K 1 +USB_VCCA
1 1
2 + C443
150U_B2_6.3VM_R35M
C441 C442
470P_0402_50V7K 470P_0402_50V7K
2 2 2
JUSB1 JUSB2
1 VCC 1 VCC
USB20_N0 2 USB20_N1 2
(28) USB20_N0 D- (28) USB20_N1 D-
D6 D7 USB20_P0 3 USB20_P1 3
(28) USB20_P0 D+ (28) USB20_P1 D+
USB20_P0 2 USB20_P1 2 4 4
GND GND
1 1
USB20_N0 3 USB20_N1 3 5 5
GND1 GND1
6 GND2 6 GND2
PJDLC05_SOT23-3 PJDLC05_SOT23-3 7 7
@ @ Source:DC233001X00 8
GND3 Source:DC233001X00 8
GND3
GND4 GND4
2nd source:DC233002C00 SUYIN_020173MR004G579ZR
2nd source:DC233002C00 SUYIN_020173MR004G579ZR
ME@ ME@

CMOS Camera Conn

(39) BT_LED#
Q18 BT MODULE CONN

1
DTC124EKAT146_SC59-3

OUT
2 JP30 2
+5VS 1
BTON_LED 1
IN 2 2 2
S

3 1 WLAN_ACTIVE 3
D
(30) WLAN_ACTIVE

GND
BT_ACTIVE 3
1 (30) BT_ACTIVE 4 4
1

1
CMOS@ BT@ (28) USB20_P6 USB20_P6 5
Q19 C445 USB20_N6 5
6
G

(28) USB20_N6
2

3
R246 SI2301BDS-T1-E3_SOT23-3 R247 0.1U_0402_16V4Z 6
7 7
10K_0402_5% 0_0603_5% 2 CMOS@ 8
CMOS@ CMOS@ +5VS 8
9
2

2
CMOS1 +3VS +3VS_BT GND1
10 GND2
30mils
1

S
BT@ 3 1 MOLEX_53780-0870

D
1 ME@
OUT

JP31 R248 Q20

1 10K_0402_1% BT@ C446

G
2
CMOS@ USB20_N2 1 0.1U_0402_16V4Z
(36) CMOS_OFF# 2 (28) USB20_N2 2

2
IN USB20_P2 2 SI2301BDS-T1-E3_SOT23-3 2 BT@
(28) USB20_P2 3
GND

3
4 4

1
Q21 1 5
DTC124EKAT146_SC59-3 CMOS@ 5
6
change pin define

OUT
3

C447 GND1
7 GND2
10U_0805_10V4Z BT@
2 ACES_88266-05001
(36) BT_OFF# 2 IN
for new symbol (JP22)
ME@ Q22

GND
DTC124EKAT146_SC59-3 on C test
3 3

3
LIFT USB CONN. 1
+USB_VCCC
+5VALW
W=60mils
1 +USB_VCCC
1 1218 change
+ C449
150U_B2_6.3VM_R35M
C448 +USB_VCCC
470P_0402_50V7K U53
2 2 1 8
JUSB3 C450 0.1U_0402_16V4Z GND OUT
2 IN OUT 7
1 1 2 1 3 IN OUT 6
USB20_N4 2 (36) USB_ON 4 5
(28) USB20_N4 2 EN OC# USB_OC#4 (28)
USB20_P4 3
(28) USB20_P4 3
4 G545A1P1U_SO8
4
5 GND <BOM Structure>
1

6 GND 1
7 R20 C451
GND 100K_0402_5% @ 1000P_0402_50V7K
8
Source:DC233001X00 GND
@
ALLTO_C10784-104A3-L 2
2nd source:DC233002C00
2

ME@
4 4

D5
USB20_P4 2
1
Security Classification Compal Secret Data Compal Electronics, Inc.
USB20_N4 3 2009/04/23 2010/05 Title
Issued Date Deciphered Date
PJDLC05_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 40 of 51
A B C D E
 +5VS

+3VS
Switch Board Conn.

2
R13

2
+3VALW 0_0603_5%
D10
R249 JP33
ON/OFFBTN# 2 0_0603_5% 10

1
ENE@ GND
1 9 GND

2
NOVO_BTN# 3 8

1
R250 ON/OFFBTN# 8
7 7
PJSOT24C_SOT23-3
No switch board: NOVO_BTN# 6 6
100K_0402_5% 5 5
D41
@ CAPS_LED# =>ESB_CK (36) ESB_CK 1 ENE@ 2 ESB_CK_C 4

1
R256 1 ENE@ 4
(36) ESB_DA 2 FBMA-11-100505-601T ESB_DA_C 3 3
(36) NOVO#
NOVO# 2 NUM_LED# =>ESB_DA (36) I2C_INT
R258 1 ENE@ 2 FBMA-11-100505-601T I2C_INT_C 2 2
1 NOVO_BTN# R259 0_0402_5% 1
51_ON# 1
(43) 51_ON# 3
R256 R258 2 2 ACES_87151-0807G
DAN202UT106_SC70-3 C455 C456
done ME@

18P_0402_50V8J 18P_0402_50V8J
@ 1 1 ENE@
NOSB@ NOSB@
ON/OFF switchSW 3 0_0402_5% 0_0402_5%
1 3
Power Button 2 4
SMT1-05_4P
@
02/26 remove SMbus for CY
6
5

+3VALW

TOP
2
Side
1

2
J5 @ JOPEN ON/OFFBTN#

J6
2 1
@ JOPEN R260
Kill Switch NOVO_BTN#
100K_0402_5%
Bottom Side D42
I2C_INT_C

0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0402_16V4Z
1

3 ON/OFF# 1 1 2
ON/OFF# (36)
ON/OFFBTN# 1

C452

C453

C454
2 51_ON#
51_ON# (43)
W LAN@ SW 4
+3VALW DAN202UT106_SC70-3 @ 2 @ 2 @ 1
+3VALW 2 1 3 3

1
2 R18 100K_0402_5%
@ 2
(36) KILL_SW # 2
1

C457 D43 KILL_SW#

1000P_0402_50V7K @ RLZTE1120A LL34
@ R261 1
1

2
4.7K_0402_5% 1
D
1
2

EC_ON 2 1BS003-1211L_3P
(36) EC_ON
G Q23 W LAN@
S 2N7002_SOT23
3
2

R251
10K_0402_5%
1

Lid Switch

+3VALW 1 2 +VCC_LID R284 1 2 100K_0402_5%

R283 0_0402_5%
2

A3212ELHLT-T_SOT23W -3
VDD

1
OUTPUT 3 LID_SW # (36)
C475
0.1U_0402_16V4Z 2
GND

2
C476
U58 10P_0402_50V8J
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title
Audio Jack & SW connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 41 of 51
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS

+5VALW +5VS +3VALW +3VS
U54 U55 +5VS
8 D 1 8 D 1
S S
1 7 D S 2 1 1 1 7 D S 2 1 1

1
6 D S 3 6 D S 3 1 1 1 1
C458 5 C459 C460 C461 C462 C463
10U_0805_10V4Z D G 4 10U_0805_10V4Z 1U_0603_10V4Z R263
5
10U_0805_10V4Z D G 4 10U_0805_10V4Z 1U_0603_10V4Z R264 C3 C4 C5 C6
1 2 2 2 2 2 2 1
SI4800BDY-T1-E3_SO8 470_0603_5% SI4800BDY-T1-E3_SO8 470_0603_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 @ 2 @ 2 @ 2 @

1 2

1 2
B+ B+
D D
2 SUSP 2 SUSP

1
G G
S Q25 S Q26

3
R266 2N7002_SOT23 R267 2N7002_SOT23
20K_0402_5% 47K_0402_5%

2
5VS_GATE
2

2
1 1
1

1
D R269 D R270
SUSP 2 Q28 0_0402_5% C467 SUSP 2 Q29 0_0402_5% C468
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K
S @ 2 S @ 2
3

1
+1.5V to +1.5VS
+1.5V +1.5VS
U57
8 D
S 1
2 1 7 2 1 1 2
D S

1
6 D
C470 S 3 C471 C472 +1.5V +VCCP +0.75VS
5 D 4
10U_0805_10V4Z G 10U_0805_10V4Z 1U_0603_10V4Z R272
2 2
SI4800BDY-T1-E3_SO8 2 470_0603_5%

1
2
R274 R275 R276
1
B+ D 470_0603_5% 470_0603_5% 470_0603_5%
2 SUSP

1 2

1 2

1 2
G
Q31 D D D
S
3

2N7002_SOT23 2 SYSON# 2 SUSP 2 SUSP

R277 G G G
150K_0402_5% S Q33 S Q34 S Q35

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
1.5VS_GATE
2

Q36 1 1
1

D R278 @
SUSP 2 0_0402_5% C473 C474
G 0.1U_0603_25V7K
2N7002_SOT23S @ 2 2
3

0.1U_0603_25V7K

3 3

RTCVREF +5VALW
+5VALW
1

@
0.01U_0402_16V7K

R279 R280
10K_0402_5% 100K_0402_5% R281
100K_0402_5%
2

SUSP 1
(47,48) SUSP
2

SYSON#
SYSON#
C1166

Q37 Q38
1

DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
2
0.01U_0402_16V7K

OUT

OUT

1 2 SYSON 2
(30,34,36,47,48) SUSP# IN (30,36,47) SYSON IN
GND

GND
C1167

2
3

4 @ 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWA5/6 LA-5081P
Date: Tuesday, April 28, 2009 Sheet 42 of 51
A B C D E
 A B C D

PJ101
Vin Detector
1
DC030006J00 1 1 2 2 VIN 1

@
JUMP_43X118
PL101
High 17.944 17.706 17.470
APDIN
PF101
APDIN1
SMB3025500YA_2P Low 16.242 16.027 15.808
4 4 1 2 1 2

3 @ 7A_24VDC_429007.W RML
3 PR102
1M_0402_1%

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2

@ 0.018U_0603_50V7J

@ 0.018U_0603_50V7J
2 VINDE-2 1 2

1
1 VIN
1 VS
JDCIN VIN

2
PC112

PC101

PC102

PC113

PC103

PC104
@ 4602-Q04C-09R 4P P2.5

0.01U_0402_25V7K

10K_0805_5%
1
1

PC105

PR104
PR103 PR105
84.5K_0402_1% 10K_0402_1%

2
1 2

2
PR106 ACIN (29,37,46)

8
90.9K_0402_1%
VINDE-1 1 2 3

P
+ PACIN

1000P_0603_50V7K
O 1 PACIN
VINDE-3 2 -

G
1

22K_0402_1%

10K_0402_1%
PU102A

0.1U_0402_16V7K

RLZ4.3B_LL34
1

1
LM393DG_SO8

4
PC106

PR107

PC107

PR108
PD102
2

2
2
2
PR109 2

2
10K_0402_1%
2 1 RTCVREF 3.3V

VIN

2
PD103
LL4148_LL34-2

PD101

1
LL4148_LL34-2 51ON-1
BATT+ 2 1

1
PR110 PR111
PQ101 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR101

2
200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
3 3

0.22U_0603_25V7K
1

1
PC108
PR112 PC109
100K_0402_1% 0.1U_0603_25V7K

2
PR113

2
22K_0402_1%
1 2 51ON-3
(42) 51_ON#

RTC Battery
- +

1
JRTC RTCVREF
PR114
2 1 200_0603_5%
+RTCBATT +CHGRTC PU101
PR115 PR116 G920AT24U_SOT89-3
3.3V

2
PD104 560_0603_5% 560_0603_5%
@ MAXEL_ML1220T10 1 2 1 2RTCVREF-1
1 2 3 OUT IN 2CHGRTCIN

RB751V-40TE17_SOD323-2

1
GND PC111
PC110 1U_0805_25V4Z
10U_0805_6.3V6M 1

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 44 of 53
A B C D
 A B C D

1 1

PJ201 PH1 under CPU botten side :

1 1 2 2 CPU thermal protection at 92 degree C
@
VMB2 JUMP_43X118 VMB Recovery at 56 degree C
PL201
JBATT PF201 SMB3025500YA_2P
1 1 2 1 2 VL
1 BATT+ VL
2 2
3 EC_SMCA @ 12A_65V_451012MRL
2 3 EC_SMDA 2

4 4

2
5 TS
5

1
6 PR202
6

1
7 PC201 PC202 PH201 47K_0402_1%
7
1

8 1000P_0402_50V7K 0.01U_0402_25V7K PR203

MAINPW ON (47)
2

2
GND 100K_0603_1%_TH11-4H104FT 47K_0402_1%
9

1
GND PR204 PR206 TM-2 1 2
@ TYCO_1775789-1 100_0402_5% 100_0402_5%

2
PR205
2

8
13.7K_0402_1%

1
TM-1 D
1 2 5

P
+ TM-3 PQ201
O 7 2
TM_REF1 6 G 2N7002KW _SOT323-3
EC_SMB_CK1 (31,37) -

G
PU102B S

3
LM393DG_SO8
EC_SMB_DA1 (31,37)

4
1000P_0402_50V7K
15.4K_0402_1%
1 2 +3VALW P

1
PR209

0.22U_0603_25V7K
1

1
PR207
6.49K_0402_1% 2 1 VL

PC203

PC204
PR208

1
100K_0402_1%

2
PR210
1
PR211
2 BATT_TEMPA (37) A/D 100K_0402_1%
10K_0402_1%

2
3
BATT_SEL_HW (37,46) 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 45 of 53
A B C D
 A B C D

24751_PVCC
PQ301 PQ302 B+
FDS6675BZ_SO8 FDS6675BZ_SO8
8 1 1 8 PR302
VIN 7 2 2 7 0.015_1206_1%
6 3 3 6 PJ301
5 5B+_IN 1 4 2 2 1 1 CHG_B+

1
2

2
@ JUMP_43X118 PR303

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
2 3

4
PR301 PC302 100K_0402_1%

2
3.3_1210_5% 0.01U_0402_25V7K

CHGEN#
0.01U_0402_25V7K

SIS412DN-T1-GE3_POWERPAK8-5

1
PC303

PC304

PC305
PC310

0.01U_0402_25V7K

2
2

1
PC307

100K_0402_1%

@ 0.1U_0603_25V7K
2 1

1
2

3
2
1
1 1

PC301

PC306
0.1U_0402_16V7K PU301 0.1U_0603_25V7K

BK-1
PQ304

0.1U_0603_25V7K
1 2 1 28 1 2

1
PR305 CHGEN PVCC FDS6675BZ_SO8

1
/BATDRV

PR304

PC309
3.3_1210_5% PR307 4

PQ303
PC308
0_0402_5%
27 24751_BTST-1
1 2 4
1 1

2
BTST

2
BK-2
PC311 PR306
2.2U_0805_25V6K 340K_0402_1% 24751_ACN 2 26 24751_HIDRV
24751_ACP 3 ACN HIDRV
2

3
2
1

5
6
7
8
ACP PR308

1
24751_ACDRV# 4 25 24751_PH PL202 0.02_1206_1%
ACDET 5 ACDRV PH 10U_LF919AS-100M-P3_4.5A_20%
ACDET BATT+
124751_BTST 224751_SW -1

10U_1206_25V6M
2 1 2 1 1 4
PD301

10U_1206_25V6M
SI7716DN-T1-E3_PAK1212-8
5
PC312

10U_1206_25V6M
REGN
LL4148_LL34-2 0.1U_0603_25V7K 2 3
2

1
PR311

1
PC331

PC314
PR310 84.5K_0402_1%
54.9K_0402_1%

PC313
PR309 24751_VREF 1 2 ACSET 6 PR312

2
ACSET

PQ305
340K_0402_1% 24 4.7_1206_5%

2
REGN

127K_0402_1%
4
1

2
1

1
PC316

24751_SNB
1

PR313
1U_0603_10V6K
PC315

2
@ 0.01U_0402_25V7K

3
2
1
1 224751_ACOP
7 ACOP

1
PC317 23 24751_LODRV
0.47U_0603_16V7K LODRV 24751_VREF 24751_VREF
CP setting PC318

2
2

PR314 22 680P_0402_50V7K
PGND

2
54.9K_0402_1% 24751_OVPSET 8 PC319
OVPSET
2
CP Point Setting PR338 PR315 0.1U_0402_16V7K 2

100K_0402_1% 100K_0402_1% 1 2
CP point=Iadapter*85% 9 21 ACOFF ACOFF (37)
1

AGND LEARN
90W adapter

1
Vacset=3.3*(127K/(84.5K+127K))=1.885V
CP Point=(Vacset/Vvdac)*(0.1/PR302)=4A PQ312 PQ310 PC320 PC321

1
24751_VREF CELLS D
2N7002KW _SOT323-3 D 2N7002KW _SOT323-3 0.1U_0603_25V7K @0.1U_0603_25V7K
20 BATT_SEL_HW (37,45)

2
CELLS
65W adapter 2 2BAT_SEL2 1
Vacset=3.3*(115K/(165K+115K))=1.355V 10 PR334 G G PR332
VREF

@ 0_0402_5%
CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.74A PQ306 @ 0_0402_5% S S @ 0_0402_5% BATT_SEL_EC

3
3

2
SI2301BDS-T1-E3_SOT23-3

1U_0603_6.3V6M
2 1

2
1
PC322

PR337
PR333
Input OVP : 22.3V PR316 19 24751_SRP 0_0402_5%
100K_0402_1%
+EC_AVCC SRP
ACIN detect : 17.26V 1 2 2 2 1 224751_VDAC
11 VDAC 18 24751_SRN

1
PR336 SRN
Fsw : 300KHz 0_0402_5% 17
BAT

1
VADJ 12 VADJ PC323
1

24751_VREF ACSET 0.1U_0603_25V7K

2
TP 29
24751_VREF 24751_OCP-3 24751_ACGOOD#
1 2 13 ACGOOD ICHG setting
1

PC324 RTCVREF 24751_VREF

PR318 PR319
200K_0402_1% 0.1U_0603_25V7K SRSET
SRSET 16 2 1 IREF (37)
1

/BATDRV

100K_0402_1%

100K_0402_1%
14 BATDRV 54.9K_0402_1%
1

1
D
2

PR317

PR335
PR320 24751_OCP-2 2 PQ307 PR322
100K_0402_1% G 2N7002KW _SOT323-3 15 IADAPT
1 2 180K_0402_1% PC325
IADAPT @0.01U_0402_25V7K
S
2

2
1

D BQ24751ARHDR_QFN28_5X5 PR321

2
3 3
ACOFF 1 2 24751_OCP-1 2 PQ308 10_0603_5% @ ACIN (29,37,44)
G 2N7002KW _SOT323-3 REGN
1

1
PC326 D
S
3

0.1U_0402_16V7K PC327 24751_ACGOOD# 2 PQ311

PR323 100P_0402_50V8J G @ 2N7002KW _SOT323-3

2
1

340K_0402_1% ADP_I (37) IREF Current S

3
PR324
2

@ 0_0402_5%
VMB2 PR326 2.842V 3.3A
210K_0402_1%
2

VADJ
499K_0402_1% 340K_0402_1%

(37) CHGVADJ 1 2
1

VS
PR327

CHGVADJ Pre Cell

1000P_0402_50V7K
1

499K_0402_1%
1
PR328
0.01U_0402_25V7K

24751_VREF
PC328

3.3V 4.35V
OVP-1 2

2
1

PC329

2
1

2
0V 4V
PR329

PR325
2

100K_0402_1%
"CHGVADJ" connect to EC DA pin
2

1
8

PR330
10K_0402_1% 3 OVP-2 CHGEN#
P

+
(37) BATT_OVP 2 1 1 0

1
D
- 2
G

PQ309
105K_0402_1%

A/D (37) FSTCHG 2

1

PU302A 2N7002KW _SOT323-3

LI-3S :13.5V----BATT-OVP=1.5V G
0.01U_0402_25V7K
4

1
PR331

LM358DR_SO8 S

3
PC330

4
BATT-OVP=0.1112*BATT+ 4
2
2

OVP-3 5
P

+
7 0
6
- Security Classification Compal Secret Data Compal Electronics, Inc.
G

PU302B 2008/05/21 2009/05/21 Title

Issued Date Deciphered Date
4

LM358DR_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OVP-4 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 46 of 53
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ401 PR401
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

2200P_0402_50V7K
2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5
D D

1
PC401

PC402

PC403

PC406
5

PC404

PC405
1U_0603_10V6K
VL

2
2
2

PC408
PC407

PQ401

PQ402
0.1U_0603_25V7K 4

4.7U_0603_6.3V6M
<BOM Structure>
3/5V_VCC
1

1
3/5V_VIN
4

PC409
+5VALWP

3
2
1
PL402

1
2
3
PL401 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PC410 2 1
1 2 1U_0603_10V6K

VIN

VCC

LDO
+3VALWP 33 19 1 2
TP PVCC

1
SI7716DN-T1-E3_PAK1212-8
1

5
UG3 26 15 HG5

SI7716DN-T1-E3_PAK1212-8
PR402 UGATE2 UGATE1 PR404
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

BOOT2 BOOT1
2

PR403 PR405

15V_SNB
1

2
2

2
+

PQ404
PR406

PC421 0_0603_5% 0_0603_5%

@ 61.9K_0402_1%
4

13V_SNB
2
+

PQ403
4 PC411

2
0.1U_0603_25V7K PC413

1
2 220U_6.3V_M

PR407
SW 3 25 16 SW 5
1

220U_6.3V_M 2 PC414 PHASE2 PHASE1 PC412

3
2
1
680P_0402_50V7K 0.1U_0603_25V7K PC415

1
2
3

2
2 LG3 23 18 LG5 680P_0402_50V7K

1
LGATE2 LGATE1
10K_0402_1%
2

PGND 22

2
C C
PR408

FB3 30 OUT2

PR409
0_0402_5%
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC416
0.22U_0603_25V7K 9
BYP
8 LDOREFIN
PD401
RB751V-40TE17_SOD323-2 29 5V_SKIP 2 1
SKIP PR410
VL
1 2
@ 0_0402_5%
1 2
20 28 PR411
PD402 PR412 NC POK2 0_0402_5%
VS RLZ5.1B_LL34 100K_0402_1%
POK (29)
1 2 EN_LDO-1 1 2 EN_LDO 4 13
EN_LDO POK1
2
200K_0402_5%

2
PR413

PC417 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 ILIM1 PR414
301K_0402_1%
1

3/5V_EN2 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2 PR415
PU401 301K_0402_1%

21
B PD403 VL ISL6237IRZ-T_QFN32_5X5 B
RB751V-40TE17_SOD323-2
806K_0603_1%

13/5V_NC
2

1 2 PR416

13/5V_TON
PR417

0_0402_5%
1

PR419 1U_0603_6.3V6M
PC418

@ 47K_0402_5%
2VREF_ISL6237

PR418
1

2 1 1 2
2

0_0402_5% PR420
0.047U_0402_16V7K

MAINPW ON (45) 0_0402_5% PJ402

@ 0.047U_0402_16V7K
1

+3VALWP 2 1 +3VALW
2

2 1
PC419

PC420

@ JUMP_43X118
2

2VREF_ISL6237

PJ403
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/06/22 2008/06/22
Issued Date Deciphered Date Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 47 of 53
5 4 3 2 1
 5 4 3 2 1

PJ501
1.5V_IN 2 1 B+
PR501 2 1

@ 1000P_0402_50V7K
240K_0402_5% @ JUMP_43X79

@ 10U_1206_25V6M

4.7U_1206_25V6K

4.7U_1206_25V6K
1.5V_TON 1 2 PL503

SIS412DN-T1-GE3_POWERPAK8-5
1

1
@ HCB4532KF-800T90_1812
PD501 1 2

PC532

PC531

PC502

PC501
@ 1SS355_SOD323-2

2
1 2 +5VALW

PQ501
PR502 PR503
PC503
D
0_0402_5% 2.2_0603_5% 4 D
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2
1,37,43,49) SYSON
1 0.1U_0603_25V7K
PL501

15

14

3
2
1
1
PC504 1.5UH_PCMC063T-1R5MN_9A_20%
0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.5VP
2

1
UG_1.5V

4.7_1206_5%
2 TON DRVH 13

SI7716DN-T1-E3_PAK1212-8

PR506
PR504 3 12 SW _1.5V
422_0603_1% VOUT LL

1000P_0402_50V7K
10U_0805_6.3V6M
220U_D2_4VY_R15M
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW

11.5V_SNB2
V5FILT TRIP

1
+

PC505

PC506

PC507
PR505

PQ502
1.5V_FB 5 10 17.8K_0402_1% 4
VFB V5DRV

2
1

LG_1.5V 2
6 PGOOD DRVL 9

PGND
PC508 PC509

680P_0402_50V7K
GND

PC510
1U_0603_10V6K @ 47P_0402_50V8J
2

3
2
1
1
1 2

2
PC511

8
PU501 4.7U_0805_10V6K

2
TPS51117RGYR_QFN14_3.5x3.5 PJ504
PR507 2 1
21K_0402_1% +VCCPP 2 1 +VCCP

@
1 2 JUMP_43X118
1

PR508 +1.5VP 1 2 1.5V_PGOOD

21K_0402_1%
1

PR521 PJ505
100K_0402_1% PC528 2 1
+1.5VP +1.5V
2

C @0.1U_0402_16V7K 2 1 C
2

@
PJ502 JUMP_43X118
VCCP_IN 2 1 B+
PR509 2 1

@ 1000P_0402_50V7K
240K_0402_5% @ JUMP_43X79

@ 10U_1206_25V6M

4.7U_1206_25V6K

4.7U_1206_25V6K
VCCP_TON 1 2

1
PL504 PJ506

5
6
7
8
PD502 1 2 2 1
+0.75VSP 2 1 +0.75VS

PC534

PC533

PC512

PC513
1SS355_SOD323-2 @ HCB4532KF-800T90_1812

SI4686DY-T1-E3_SO8
2

2
1 2 +5VS @ JUMP_43X79

PQ503
PR510 PR511 4
PC514
75K_0402_1% 2.2_0603_5%
1 2 VCCP_EN BST_VCCP1 2BST_VCCP-1
1 2
43,49) SUSP#
0.1U_0603_25V7K

3
2
1
1

PL502
15

14
1

PC515 1.5UH_PCMC063T-1R5MN_9A_20%
0.1U_0402_16V7K 1 2
EN_PSV

TP

VBST

+VCCPP
2

1
UG_VCCP

4.7_1206_5%
2 TON DRVH 13

PR512
PR513 3 12 SW _VCCP
VOUT LL

5
6
7
8
422_0603_1%

1000P_0402_50V7K
10U_0805_6.3V6M
220U_D2_4VY_R15M
1
1 2 VCCP_V5FILT 4 11 VCCP_TRIP
1 2 +5VS

SI4634DY-T1-E3_SO8
+5VS

1VCCP_SNB2
V5FILT TRIP

1
+

PC516

PC517

PC518
PR514
VCCP_FB 5 10 12K_0402_1%
VFB V5DRV

2
1

LG_VCCP 2
6 PGOOD DRVL 9 4
PGND

PQ504
PC519
GND

1U_0603_10V6K PC520

680P_0402_50V7K
B B
2

PC522
@ 47P_0402_50V8J
1 2 PC521
7

3
2
1

2
PU502 4.7U_0805_10V6K
2

TPS51117RGYR_QFN14_3.5x3.5
PR515
13.3K_0402_1%
1 2
2

PR516
30.1K_0402_1%
1

+1.5V
1

PJ503
1

JUMP_43X79
2

PU503
2

0.75V_IN 1 6 +3VALW
VIN VCNTL
2 GND NC 5
1

PC523
4.7U_0603_6.3V6M PR517 3 7 PC524
1K_0402_1% VREF NC 1U_0603_6.3V6M
2

4 VOUT NC 8
A A
2

TP 9
0.75V_REF
APL5331KAC-TRL_SO8
1

PR518 +0.75VSP
1

0_0402_5% D PR520
2N7002KW_SOT323-3

1 2 2 1K_0402_1%
(20,31,43,49) SUSP G PC525 PC526 Security Classification Compal Secret Data Compal Electronics, Inc.
1

10U_0805_6.3V6M
PQ505

S 0.1U_0402_16V7K 2007/11/12 2008/11/12 Title

Issued Date Deciphered Date
3

PC527
1.5V / 0.9V / VCCP
@

0.1U_0402_16V7K
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 48 of 53

5 4 3 2 1
 5 4 3 2 1

PJ601
1.8V_IN 2 1 B+
PR601 2 1
240K_0402_5% @ JUMP_43X79

4.7U_1206_25V6K

4.7U_1206_25V6K
SIS412DN-T1-GE3_POWERPAK8-5
1.8V_TON 1 2

1
5
PD602

PC602

PC601
@ 1SS355_SOD323-2

2
1 2 +5VALW

PQ601
PR631 PR603 4
PC603
40.2K_0402_1% 0_0603_5%
1 2 1.8V_EN BST_1.8V 1 2BST_1.8V-1
1 2
D SUSP# D

0.1U_0603_25V7K
(31,37,43,48)

3
2
1
1
PL601

15

14
1
PC604 2.2UH_PCMC063T-2R2MN_8A_20%
0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.8VSP
2

1
UG_1.8V

4.7_1206_5%
2 TON DRVH 13

PR604
PR605 3 12 SW _1.8V
VOUT LL

5
422_0603_1%

1000P_0402_50V7K
10U_0805_6.3V6M
220U_D2_4VY_R15M
SI7716DN-T1-E3_PAK1212-8
1
+5VS 1 2 1.8V_V5FILT 4 11 1.8V_TRIP
1 2 +5VS

1 1.8V_SNB 2
V5FILT TRIP

1
+

PC605

PC606

PC635
PR606 PJ602
1.8V_FB 5 10 16.5K_0402_1% 2 1
VFB V5DRV +VGA_COREP 2 1 +VGA_CORE

2
1

PQ602
6 9 LG_1.8V 4 @ JUMP_43X118
PGOOD DRVL

PGND
PC607

GND
1U_0603_10V6K PC609
2

1
@ 47P_0402_50V8J PJ603

680P_0402_50V7K
PC608
1 2 PC610 2 1

3
2
1
PU601 4.7U_0805_10V6K 2 1

2
TPS51117RGYR_QFN14_3.5x3.5 @ JUMP_43X118

PR607
PJ604
30.1K_0402_1%
1 2 +1.1VSP 2 2 1 1 +1.1VS
1

@ JUMP_43X79

PR608
21K_0402_1% PJ606
PR609
205K_0402_1% PJ605 2 1
+1.8VSP +1.8VS
2

C VGA_TON VGA_IN 2 1 C
1 2 2 2 1 1 B+
@ JUMP_43X79

10U_1206_25V6M

10U_1206_25V6M
PR610 PD601 @ JUMP_43X79

5
6
7
8
@ 0_0402_5% 1SS355_SOD323-2

1
PC611

PC612
1 2 VGA_EN 1 2 +5VS
SUSP#
1

(31,37,43,48)

2
PC637 PC613 PR611
PC614
@ 0.1U_0402_16V7K @ 0.1U_0402_16V7K 0_0603_5% 4
2

PR626 BST_VGA 1 2BST_VGA-1

1 2
1

0_0402_5% D
1 2 2 0.1U_0603_25V7K PQ603
SUSP
G PQ610 SI4686DY-T1-E3_SO8 PL602
15

14

(20,31,43,48)

3
2
1
1

PC636 S 2N7002KW _SOT323-3 1UH_PCMB103E-1R0MS_20A_20%

3

@ 0.1U_0402_16V7K 1 2
EN_PSV

TP

VBST

+VGA_COREP
2 1
PR633 2 13 UG_VGA
TON DRVH

1
0_0402_5%

4.7_1206_5%
PR613 +VGA_COREP 2 1VGA_VOUT 3 12 SW _VGA
VOUT LL

5
6
7
8

5
6
7
8

PR612
422_0603_1%

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
1

330U_D2_2.5VY_R15M
1
1 2 VGA_V5FILT 4 11 VGA_TRIP
1 2 +5VS

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
+5VS V5FILT TRIP

1
+

PC615

PC616

PC633

PC634
PR614

1VGA_SNB
2
+3VS VGA_FB

10_0402_5%
5 10 9.1K_0402_1%
VFB V5DRV
1 2

2
2

PR615
6 9 LG_VGA 4 4

2
PGOOD DRVL
PGND

PQ604

PQ605
PC617 PR522
GND

1U_0603_10V6K 100K_0402_1%

680P_0402_50V7K
1

PC618
1

@ 0_0402_5%

PC620
1

3
2
1

3
2
1

2
PR634

VGA_PW ROK PU602 4.7U_0805_10V6K

2

TPS51117RGYR_QFN14_3.5x3.5
B 2 1 PC619 B
@ 47P_0402_50V8J
2

PC529 PR620 1 2 PR617

@ 0.1U_0402_16V7K 91K_0402_1% 0_0402_5%
1 2 1 2 VGA_FB1 2 1
1GVID1-2

+VGASENSE
PR616
13.3K_0402_1% +1.8VSP +3VS
PR616=>9.09K
2N7002KW_SOT323-3

1 2
D PR619 PR622=>2.21K
2
PQ606

2 1GVID1-1
2 39.2K_0402_1%
GPU_VID1 PR629,PR630,PC625,PQ606,PR620=>un-pop
1

1
PR630 G
1

10K_0402_1% S PR618 PJ607 PJ608

PR621,PR624,PC632,PQ607,PR618=>un-pop
1

1
(17)
3
1

@
PR629 113K_0402_1% JUMP_43X79 JUMP_43X79
10K_0402_1%
1GVID0-2 1

2
2

PC625 PU603 PU604

2

2
0.022U_0402_16V7K 1.1V_IN 1 6 +5VS LDO_1.8V_IN 1 6 +5VS
VIN VCNTL VIN VCNTL
D
2 GND NC 5 2 GND NC 5
1

1
2 1GVID0-1 2 PC621 PC623
GPU_VID0
1

1
PR624 G 4.7U_0603_6.3V6M 3 7 PC622 @ 4.7U_0603_6.3V6M 3 7 PC624
PR621 10K_0402_1% VREF NC 1U_0603_6.3V6M VREF NC @1U_0603_6.3V6M
S PQ607 PR622 PR623
(17)
3

2
1

10K_0402_1% 2N7002KW _SOT323-3 1.91K_0402_1% 4 8 @ 1K_0402_1% 4 8

VOUT NC VOUT NC
PC632 9 9
2

2
0.022U_0402_16V7K TP TP
1.1V_REF APL5331KAC-TRL_SO8 LDO_1.8V_REF @ APL5331KAC-TRL_SO8

@ 1.24K_0402_1%
@ 2N7002KW_SOT323-3
1

1
PR625 +1.1VSP PR632 +1.8VSP
1

1
D D

PR628
30.1K_0402_1% PR627 @ 31.6K_0402_1%
(20,31,43,48) SUSP 1 21.1V_EN 2 3.16K_0402_1% PC626
(20,31,43,48) SUSP 1 2 2 PC627
1

1
G 0.1U_0402_16V7K G @ 0.1U_0402_16V7K
2N7002KW_SOT323-3

A A
2

2
1

PQ609
S PC628 S PC629
3

2
@10U_0805_6.3V6M
PQ608

PC630 10U_0805_6.3V6M PC631

For N10M-GE1 For N10M-GS
2

2
0.1U_0402_16V7K @ 0.1U_0402_16V7K
2

2
GPIO15 GPIO20 GPIO15 GPIO20
GPU_VID1 GPU_VID0 VGA_CORE GPU_VID1 GPU_VID0 VGA_CORE Security Classification Compal Secret Data Compal Electronics, Inc.
0 0 0.95V 0 0 0.85V Issued Date 2007/11/12 Deciphered Date 2008/11/12 Title

1.0V 0.9V VGA_CORE/1.8V/1.1VS

0 1 0 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.2V 1.0V 0.1
1 1 1 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 49 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS

@ 10K_0402_5%
1.91K_0402_1%
1

1
PR830

PR831
(8,29) VGATE

2
(29) CLK_ENABLE# 1 2
PR832

DPRSLPVR
D
@ 0_0402_5% D
+3VS +5VS

(37)
VR_ON

(8,29)
1

1
@ 0_0402_5%

0_0402_5%
+CPU_B+ PL801

PR834

PR865
HCB4532KF-800T90_1812
1 2 B+

0_0402_5%

0_0402_5%

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

1000P_0402_50V7K
2

2
1

1
PC808

PC804

PC809

PC838

220U_25V_M
1

2
+

124K_0402_1%

PC805
2

2
2

1CPU_VREF
1

5
2

1
PR837
0_0402_5%

0_0402_5%

PR838
1
2
PR833
2 1 4

CPU_DPRSLPVR
PC824 PQ801

CPU_CLK_EN#
CPU_TRIPSEL
CPU_OSRSEL

CPU_TONSEL
1U_0603_10V6K SI7686DP-T1-E3_SO8

CPU_VR_ON
CPU_V5FILT

CPU_ISLEW
PL802

2
PR835

PR836
0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
1 4 +CPU_CORE

5
6
7
8

5
6
7
8

1
CPU_CSP1-1
2 3
+5VS PR819

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8

1
C 4.7_1206_5% C

17.8K_0402_1%
41

40

39

38

37

36

35

34

33

32

31

PR801
1CPU1_SNB
2
CPU_VREF
1 2
GND

V5FILT

ISLEW

OSRSEL

TONSEL

TRIPSEL

PWRMON

VR_ON

CLK_EN#

DPRSLPVR

PGOOD

2
PR839 PD801 4 4 PR840

PQ802

PQ803
5.76K_0402_1% 1SS355_SOD323-2 69.8K_0402_1%

2
1 2CPU_DROOP 1 30 UGATE_CPU1 1 2
PC825 68P_0402_50V8J DROOP DRVH1 PC815

1
CPU_CSP1 2 1 1 2CPU_VREF 2 29 BOOT_CPU1
1 PR841 2BOOT_CPU1-1
1 2 680P_0402_50V7K

3
2
1

3
2
1
VREF VBST
PR861 470_0402_1% PC826 0.22U_0603_10V7K 0_0603_5% PC827 1 2CPU_SN-1
1 2 PH801

2
2

3 28 PHASE_CPU1 0.22U_0603_10V7K PR842 100K_0603_1%_TH11-4H104FT

GND LL1

CPU_CSN1
CPU_CSP1
PC836 +CPU_B+ 28.7K_0402_1%
100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 1 2
1

CPU_CSN1 2 PC828 33P_0402_50V8K CSP1 DRVL1 PC829

1000P_0402_50V7K
1 +5VS

5
PR862 470_0402_1% 2 CPU_CSN1-1 0.033U_0402_16V7K

10U_1206_25V6M

10U_1206_25V6M
1 5 CSN1 V5IN 26 1 2

1
CPU_CSN2 2 1 PC830 33P_0402_50V8K PC831 10U_0805_6.3V6M

PC817

PC818

PC839
PR863 470_0402_1% 1 2 CPU_CSN2-1 6 CSN2
PU801
PGND 25
2

PC832 33P_0402_50V8K TPS51620RHAR_QFN40_6X6

2
PC837 1 2 CPU_CSP2-2 7 CSP2 DRVL2 24 LGATE_CPU2
100P_0402_50V8J PC833 33P_0402_50V8K 4
1

CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2

PR864 470_0402_1% GNDSNS LL2 PQ804
CPU_VSNS 9 22 BOOT_CPU2
1 PR846 2BOOT_CPU2-1
1 2 SI7686DP-T1-E3_SO8 PL803
VSNS VBST2 0_0603_5% PC834 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
CPU_THERM UGATE_CPU2 0.22U_0603_10V7K
DPRSTP#

10 THERM DRVH2 21 1 4
1

VR_TT#

1
0_0402_5%

0_0402_5%

1 2 CPU_CSP2-1
2 3
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

+5VS

5
6
7
8

5
6
7
8
PD802

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
1

1
PR844

PR845

1SS355_SOD323-2 PR829

17.8K_0402_1%
PR848
4.7_1206_5%
2

11

12

13

14

15

16

17

18

19

20

1CPU2_SNB
PR849

2
20K_0402_5% PR850
1CPU_DPRSTP#

B 4 4 69.8K_0402_1% B
2

2
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

PQ805

PQ806
1 2
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

PC823 PH803
680P_0402_50V7K 1 2CPU_SN-2
1 2 100K_0603_1%_TH11-4H104FT

3
2
1

3
2
1
PR851

2
1

CPU_CSN2
CPU_CSP2
PR843 PR847 28.7K_0402_1%
100_0402_5% 100_0402_5% 1 2
2

PC835
0.033U_0402_16V7K
PR852

PR853

PR854

PR855

PR856

PR857

PR858

PR859

PR860
@ 68P_0402_50V8K

<BOM Structure>
2

1
(6) VSSSENSE

+CPU_CORE
(6)VCCSENSE

2
PC840

(6) H_PSI#
H_DPRSTP#

(6) CPU_VID6

(6) CPU_VID5

(6) CPU_VID4

(6) CPU_VID3

(6) CPU_VID2

(6) CPU_VID1

(6) CPU_VID0
(6,8,28)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/05/21 Deciphered Date 2009/05/21 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 50 of 53
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

modify battery select circuit add PQ312 and PR338 2009.01.14

D
1 D

2 change +1.1VS voltage to +1.05V change P622 to 2.21K only for N10M-GS(40nm) 2009.01.14

C C

10

11

B 12 B

13

14

15

16

17

18

19
A A
20

21
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWAX_LA-5081P
Date: Tuesday, April 28, 2009 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------------------------------
1 12/10 39 Remove D11, and add R6, R7
12/10 36 change PWR_LED_SC# from U46.38 to U46.34

D
2 1/15 39 modify H18 hold size, and change the H5 、H6 and H18 hold type. D
42 add 4 CAPs C3, C4, C5 and C6 for EMI.
35 change C572 and C574 footprint from 0603 to 0402.
34 add R25 for BEEP# test

3 3/16 06 add R1089, C1162 and H_DPRSTP#_R

add C1163, C1164,and C1165 for EMC request.
08 change H_DPRSTP# to H_DPRSTP#_R
19 P19 add Bom structure 40nm@ GPU and 55nm@ GPU
R999 change to 24.9K
23 add R1095 pull high
35 swap HP_OUTL and HP_OUTR
36 add R1090, R1091, R1092, R1093
C CAPS_LED#, NUJM_LED#, ESB_CK_R, and ESB_DA_R C

41 add R256, R258 Bom configuration

Remove CY SMBus
42 add C1166, C1167 for EMC request.

4 4/20 27 R829 changed to 0ohm.

08 R80 changed to 33ohm
34 R1044 changed to 33ohm
R1056 changed to 33ohm
C1089 changed to 10P

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/23 Deciphered Date 2010/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KIWAX_LA-5081P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, April 28, 2009 Sheet 51 of 51
5 4 3 2 1
www.s-manuals.com