Dual Dynamic Hybrid FlipFlop

Low-Power and Low-Area Dual Dynamic Node Hybrid

FlipFlop Featuring Efficient Embedded Logic for Low Power
CMOS VLSI Circuits Using 120nm Technology

PROJECT SUPERVISOR: Engr. M. Aamir Akram

SUBMITTED BY: Syed Abdullah

Roll No: 14ES35

SESSION 2014-2018
Dual Dynamic Hybrid FlipFlop

1
Dual Dynamic Hybrid FlipFlop

Acknowledgment
I would like to express my deepest appreciation to all those who provided me
possibility to complete this report.A special gratitude to our SemesterSupervisor,
Engr. M. Aamir Akram. Whose contribution in stimulating suggestions and
encouragement, helped us to coordinate and complete my project especially in
writing this report.
'

1
Dual Dynamic Hybrid FlipFlop

Abstract
In this paper, there is a dual dynamic flip-flop (DDFF) and a novel embedded logic module
(DDFF-ELM) based on DDFF. These proposed designs remove the large capacitance existing in
the precharge node by following a split dynamic node structure to independently drive the output
pull-up and pull-down transistors. It presents speed efficient method to incorporate complex
logic functions into the flip-flop with small delay penalty and reduces the power dissipation by
reducing the precharge capacitance. The DDFF offers power and area reduction. The main aim
of the DDFF-ELM is to reduce pipeline overhead which arises due to the pipeline setup time,
propagation delay and clock skew. It presents an area, power, and speed efficient method to
incorporate complex logic functions into the flip-flop. The execution comparisons are made in
180nm and 250nm CMOS technology. A high speed ring counter with clock gating technology
using digital CMOS gate logic components by the DDFF structure is also designed which is well
suited for modern high performance circuits. The performance improvements indicate that the
proposed designs are well suited for modern high-performance designs where power dissipation
and latching overhead are of major concern. And also here, DDFF and DDFF-ELM are
compared with other flip-flop designs by implementing a 4-b Johnson Counter. Here the
performance improvements indicate that proposed designs are well suited for modern high
performance designs.

Keywords: Flip-Flops, High-Speed, Low-Power, Embedded Logic, Leakage Power,

DDFF

1
Dual Dynamic Hybrid FlipFlop

TABLE OF CONTENTS

Sr.No Page
1 Introduction 01
2 Purpose 02
3 Designs 03
4 Simulation on DSCH software and Timing Diagram 04
5 Simulation of A 4 bit array multiplier on DSCH software 05
6 Block diagram of 4 bit Array Multiplier 06
7 Simulation of A 4 bit array multiplier on DSCH software 07
8 Timing Diagram 08
9 Conclusion 09
10 Refferences 10

1
Dual Dynamic Hybrid FlipFlop

Introduction
Over the past decade, power consumption of VLSI chips has constantly been increasing. The
trends in VLSI technology scaling in the last few years show that the number of on chip
transistors is increasing every year. Operation frequency of VLSI systems is also increasing.
Although capacitances and supply voltages are scaled down, meanwhile power consumption of
the VLSI chips is increasing continuously. On the other hand, cooling systems cannot improve
as fast as the power consumption increases. Therefore in the very close, future chips are
expected to have limitations of cooling system and solving this problem will be expensive and
inefficient. This necessitates the design of low power circuits.

The low power chip and system are using for both industrial and educational purposes. The
industry for low power electronic products are increasing rapidly in market. At the same time,
newly emerging CMOS processing technologies present more requirements to the power
dissipation of digital system due to increased device count, speed and complexity. Power
dissipation of VLSI chips has been continuously increasing. For high performance low power
CMOS chip-design the choice of method has a significant effect, on the design time and cost.
Large no of gates are present in the VLSI CMOS system and gates are having different
parameters due to process variation.

Among all the types of flip-flops and latches, mostly D Flip-flop latches are used. They are
often called as level sensitive because their output follows their inputs as long as they are
enabled. They are transparent during this entire time when the enable signal is asserted. There
are situations when it is more useful to have the output change only at the rising or falling edge
of the enable signal, which is usually the controlling clock signal.

In this paper, we propose a new dual dynamic node hybrid flip-flop (DDFF) and a novel
embedded logic module (DDFF-ELM). Both of them eliminate the drawbacks of XCFF. The
new designs are free from unwanted transitions resulting when the data input is stable at zero.
DDFF-ELM presents a speed, area, and power efficient method to reduce the pipeline over-
head.

1
Dual Dynamic Hybrid FlipFlop

Purpose

1
Dual Dynamic Hybrid FlipFlop

Analysis of different types of Flip-Flop Architectures

The flip-flop designs are basically grouped as static and dynamic design styles. The master-slave
designs include, transmission gate based master-slave flip-flop and the Power PC 603 master-
slave latch. Here Power PC means Performance Optimization With Enhanced RISC Performance
Computing. They dissipate comparatively low power and they are also having low clock-to-
output (CLK-Q) delay. In synchronous systems, the latching elements have the delay overhead
which is expressed by the data-to-output (D-Q) delay rather than CLK-Q delay. Here, D-Q delay
is the combination of CLK-Q delay and the setup-time of the flip-flop. But the static designs lack
the low D-Q delay due to their large positive setup-time, and also most of them are susceptible to
flow through resulting from CLK overlap. In synchronous system we are using flip flops. High
speed has been achieved using pipelined techniques . In progressive, deep-pipelined
architectures, pushing the speed excepting demands a lower pipeline overhead. This overhead is
latency analogous with the pipeline elements, similar as flip-flops and latches. Substantially,
work has been dedicated to improve the performance of the flip-flops in the past few decades.
The factors which are recommendable in latches and flip-flops are (1) High speed, (2) Low
power consumption, (3) Robustness and noise stability, (4) Small area and less number of
transistors, (5) Supply voltage scalability, (6) Less internal activity in ideal condition.

Figure.1. Power PC 603 Flip-Flop

Hybrid latch flip-flop (HLFF) and semi dynamic flip-flop (SDFF) are observing the classic
highperformance of flipflops [1]. Flip-flops can be designed by two type (1) Static logic, (2)
Dynamic logic style. Dynamic logic occupies less area and high speed, on otherhand static
logic cannot have charge sharing problem. Now we consider a hybrid flip flop which is
working like dynamic and static logic. Hybrid design has an internal dynamic node and static
output node, in flip flop design. On other hand semi dynamic flip-flop (SDFF) works
efficiently and have different capabilities. It helps to reduce the latency in flip flop design.
Power, delay and area are main concerns.

1
Dual Dynamic Hybrid FlipFlop

Figure.2. Hybrid Latch Flip-Flop (HLFF).

HLFF is not the fastest but has a lower power consumption when compared to SDFF because of
the longer stack of nMOS transistors at the output node makes it slower than SDFF and causes
large hold-time requirement. Due to this large hold time requirement, makes the integration of
HLFF to complex circuits difficult process. And also HLFF is inefficient in embedding the logic.
SDFF is the fastest classic hybrid structure, but it has high power consumption because of the
large CLK load as well as the large precharge capacitance. Its speed is high when compared to
that of the HLFF.

Figure.3. Semi-Dynamic Flip-Flop (SDFF).

1
Dual Dynamic Hybrid FlipFlop

CDMFFs have the best power-delay product in their groups, respectively. In the aspect of
power dissipation, the single-ended and differential CDMFFs consume the least power at
data activity less than 50%, and are 31% and 26% less power than the conditional capture
flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve
small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the
modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best
internal race immunity among pulse-triggered flip-flops. A post-layout case study is
demonstrated with comparison to a transmission-gate flip-flop. The results indicate the
single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25%
data activity, in spite of the 34% increase in size.

Figure.4. Conditional Data Mapping Flip-Flop (CDMFF).

CDMFF uses an output feedback structure to conditionally feed the data to the flip-flop
which reduces overall power dissipation by eliminating unwanted transitions when a
redundant event is predicted. Considerable speed performance is there, since there are no
added transistors at the output node, similar to that of the HLFF.

1
Dual Dynamic Hybrid FlipFlop

Proposed DDFF Architecture

In the DDFF architecture, NodeX1 is pseudo-dynamic, with a weak inverter acting as a keeper,
whereas, compared to the XCFF, in the new architecture node X2 is purely dynamic. An
unconditional shutoff\ mechanism is provided at the frontend instead of the conditional one in
XCFF. The operation of the flip-flop can be done into two phases: 1) the evaluation phase, when
CLK is high, and 2) the pre charge phase, when CLK is low.
Dual Dynamic Hybrid Flip Flop (DDFF) has extra inv4 occupies an additional area to flip flop
and then it requires more power. In the output QB is inverted by inv3, to get the output Q. again
the output Q is inverted and it is not required. Large area and high power consumption is
drawback here. When inv-4 is connected to QB, it causes an error.

Figure.6. Dual Dynamic Node Hybrid Flip-Flop (DDFF).

In the evaluation phase the latching occurs at 1-1 overlap of CLK and CLKB. If D is high, node
X1 is discharged through NM0-2. The switching state of the cross coupled inverter pair INV1-2
causing node X1B to go high and output QB to discharge through NM4. The nodeX1 is retained
by the inverter pair INV1-2 at low level. There is no need of latching for the evaluation phase.
Node X2 is high throughout the evaluation period by the pMOS transistorPM1.The circuit enters
the pre charge phase and node X1 is pulled high through PM0, switching the state of INV1-2
when the CLK is low. Node X2 is not driven by any transistor, it stores the charge dynamically.
The outputs at node QB and maintain their voltage levels through INV3-4. Node X1 remains
high and nodeX2 is pulled low throughNM3 as the CLK goes high, if Dis zero prior to the
overlap period. The node QB is charged high through PM2 and NM4 when these transistors are
off. As the CLK falls low, node X1 remains high andX2 stores the charge dynamically At the
end of the evaluation phase. The architecture exhibits negative setup time since the short
transparency period defined by the 1–1 overlap CLK of and CLKB allows the data to be sampled
even after the rising edge of the CLK before CLKB falls low. When the CLK makes a low to
high transition NodeX1 undergoes charge sharing while D is low. This result in a momentary fall
in voltage at nodeX1, but the inverter pair INV1-2 is skewed properly such that it has a switching
threshold well below the worst case voltage drop at nodeX1 due to charge sharing. The timing

1
Dual Dynamic Hybrid FlipFlop

diagram shows that node X2 has the charge level during the pre charge phase when it is not
driven by any transistor. Note that the temporary pull down at node X2 when sampling a “one” is
due to the delay between X1 andX1B.
Proposed ELM
Dual dynamic node hybrid flip-flop with logic embedding capability (DDFF-ELM) transistor
driven by the data input is replaced by the PDN and the clocking scheme in the frontend is
changed. The reason for this in clocking is the charge sharing, which becomes uncontrollable as
the number of MOS transistors in the stack increases. XCFF also incapable of embedding
complex logic functions for this same reason. In order to get a clear picture of the charge sharing
in XCFF, it was simulated with different embedded functions and the amount of worst case
charge sharing was calculated.

Figure.8. Proposed DDFF-ELM

In the proposed model, the transistor driven by the data input is replaced by the PDN and the
clocking scheme in the frontend is changed.
Here by using the above flip-flops a Johnson up-down counter can be designed and the results
are compared accordingly.

Figure.9. Johnson Counter Using SDFF

1
Dual Dynamic Hybrid FlipFlop

Figure.10. Johnson Counter Using XCFF

Figure.11. Johnson Counter Using DDFF

Counter is a device that stores the number of times a particular event or process has occurred
often in relation to a clock signal. Counters are used in almost all the digital circuits for counting
operations. There are many types of counters used in digital circuits. Johnson counter also called
as twisted ring counter is the modified form of a ring counter. Figure 3 shows the architecture of
4-bit synchronous up-down Johnson counter. In Johnson counter output of the last stage is
complemented and connected to the input of the first stage.
In the 4-bit up-down Johnson counter designed Dual dynamic pulsed hybrid flip-flop is used. By
embedding a multiplexer into the flip-flop architecture as shown in the figure 2 counting
operation can be performed in either up counting mode or down counting mode. Last stage
output is complemented and connected to the input of the first stage for an up counter and first
stage output is complemented and connected to last stage input.
Clock gating technique is used to reduce the dynamic power dissipation by stopping the clock
signal to the segments of the circuit that are inactive at that instant of time. Clock transitions
contribute to the major part of power consumption in a digital circuit. By eliminating the
unwanted distribution of the clock signal to the segments that are not active power dissipation
can be reduced in the digital circuits. For clock gating to the Johnson counter in this design XOR
and NAND gates are used.

1
Dual Dynamic Hybrid FlipFlop

Results

Figure.12. Simulation Result for DDFF

Figure.13. Simulation Result for DDFF-ELM

The simulation were performed in 90nm technology. The supply voltage is given as 1.2v for the
simulation. The flip flop operated at 2 GHz clock frequency. It has negative set up time and
positive hold time with respect to CLK and CLKB.
From the above results we can notice the performance improvements in DDFF and DDFF-ELM.
This flip-flop can be added as a component in standard cell library and can be used for
implementation of low power counters and shift registers. It is also possible to incorporate reset
functionality to proposed flip-flop for further improvements.

1
Dual Dynamic Hybrid FlipFlop

Conclusion
The results are compared with the existing techniques. The proposed DDFF using
sleep transistor approach with NMOS eliminates the leakage power. The overlap
period of clock that is required to select proper width has been provided in order to
make design simpler. The experiment result shows an improvement in leakage
power and delay. The better case of internal data activity has been found out. The
input vectors reduces leakage power. The efficiency of DDFF using sleep transistor
approach with NMOS has been highlighted using a 4-bit Johnson up and down
counter. The speed of the proposed DDFF is same as the existing. It was proven
that the proposed architectures are well suited for modern high performance
designs where area, delay overhead and power dissipations are of major concern.

1
Dual Dynamic Hybrid FlipFlop

References
[1] Kalarikkal absel, Lijo Manuel, and R. K. Kavitha, “Low-Power Dual Dynamic Node Pulsed
Hybrid Flip-Flop Featuring Efficient Embedded Logic” in IEEE VLSI Transactions (Volume:21
Issue:9) pp. 1693-1704.

[2] Ahmed Sayed and Hussain Al-Assad, 2011, „Low-Power Flip-Flops: Survey, Comparative
Evaluation and a New Design, IACSIT International Journal of Engineering and Technology,
Vol.3, No.3.

[3] Ismail.S.M. and Islam.F.T.,2012,‟Low Power design of Johnson Counter using clock gating‟
International Conference on Computer and Information Technology (ICCIT),pp 510-517.

[4] G. Gerosa, S. Gary, C. Dietz, P.Dac, K. Hoover, J. Alvarez, H.Sanchez, P. Ippolito, N. Tai, S.
Litch, J. Eno, J. Golab, N. Vanderschaaf, and J. Kahle, “A 2.2 W, 80 MHz superscalar RISC
microprocessor,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1440-1452, Dec. 1994.

[5] C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, “Conditional data
mapping flip-flops for low-power and highperformance systems,” IEEE Trans. Very Large Scale
Integr.(VLSI) Syst., vol. 14, no. 12, pp. 1379-1383, Dec, 2006.

[6] P. Zhao, T . K. Darwish, and M. A. Bayoumi, “High- Performace and low-power conditional
discharge flip-flop,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Syst., vol. 12, no .5, pp.
477-484, May 2004.

[7] S. H. Rasouli, A. Khadermzadesh, A. Afzali-Kusha, and M. Nourani, “Low-Power Single-

and double-edge-triggered flip-flop for highspeed applications,” Proc. Inst. Elect. Eng. Circuits
Devices Syst., vol. 152, no. 2, no. 2, pp. 118-122, Apr. 2005.

[8] A. Ma and K. Asanovic, “A double-pulsed set- conditional-reset flipflop,” Laboratory for

Computer Science, Massachusetts Inst. Technology, Cambridge, Tech. Rep. MIT-LCS-TS-844,
May 2002.

[9] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra low-power clocking scheme
using energy recovery and clock gating,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
vol. 17, no. 1, pp. 33-44, Jan.2009.