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Abstract—This paper presents a new class of three phase seven voltage levels m grows the number of active switches
level inverter based on a multilevel DC link (MLDCL) and a increases according to 2×(m-1) for the cascaded H-bridge
bridge inverter to reduce the number of switches. There are 3 multilevel inverters. Multilevel inversion is a power
types of multilevel inverters named as diode clamped multilevel conversion strategy in which the output voltage is obtained in
inverter, flying capacitor multilevel inverter and cascaded
steps thus bringing the output closer to a sine wave and
multilevel inverter. Compared to diode clamped & flying
capacitor type multilevel inverters cascaded H-bridge multilevel reduces the total harmonic distortion (THD).
inverter requires least no. of components to achieve same no of
voltage levels and optimized circuit layout is possible because This paper presents a 3–Ф seven level cascaded H-bridge
each level have same structure and there is no extra clamping multilevel inverter based on an MLDCL and a bridge inverter.
diodes or capacitors. However as the number of voltage levels m Compared with the existing cascaded multilevel inverters, the
grows the number of active switches increases according to 2×(m- proposed MLDCL inverter topologies can have enhanced
1) for the cascaded H-bridge multilevel inverters. Compared with performance by implementing the pulse width modulation
the existing type of cascaded H-bridge multilevel inverter, the (PWM) techniques. This paper also presents the most relevant
proposed MLDCL inverters can significantly reduce the switch
control and modulation methods by a new reference/carrier
count as well as the number of gate drivers as the number of
voltage levels increases. For a given number of voltage levels, the based PWM scheme for MLDCL inverter and comparing the
required number of active switches is 2 (m-1) for the existing performance of the proposed scheme with that of the existing
multilevel inverters, but it is m+3 for the MLDCL inverters. The cascaded H-bridge multilevel inverter. The proposed MLDCL
output of proposed MLDCL is synthesized as the staircase wave, inverter can significantly reduce the switch count as well as
whose characteristics are nearer to a desired sinusoidal output. the number of gate drivers as the number of voltage levels
The proposed MLDCL inverter topologies can have enhanced increases. For a given number of voltage levels m, the
performance by implementing the pulse width modulation cascaded MLDCL inverter requires m+3 active switches,
(PWM) techniques. This paper also presents the most relevant roughly half the number of switches.
control and modulation methods by a new reference/carrier
based PWM scheme for MLDCL inverter and comparing the II. CASCADED H-BRIDGE INVERTER
performance of the proposed scheme with that of the existing
cascaded H-bridge multilevel inverter. Finally, the simulation The cascade H-bridge inverter is a cascade of H-bridges, or
results are included to verify the effectiveness of the both H-bridges in a series configuration. A single H-bridge inverter
topologies in multilevel inverter configuration and validate the is shown in fig (1) and three phase cascaded H-bridge inverter
proposed theory. A hardware set up was developed for a single- for seven-level inverter is shown in fig (2). Fig (1) and fig (2)
phase 7-level D.C.Link inverter topology using constant pulses. shows the basic power circuit of single H-bridge inverter and
the cascade of H-bridge inverter for seven-level inverter
Keywords-Cascaded H - bridge, multilevel dc link inverter,
respectively. An N level Cascaded H bridge inverter consists
Pulse width modulation, Total Harmonic Distortion.
of series connected (N-1)/2 number of cells in each phase.
Each cell consists of single phase H bridge inverter with
I. INTRODUCTION separate dc source. There are four active devices in each cell
The voltage source inverters produce an output voltage or and can produce three levels 0, Vdc/2 and –Vdc/2. Higher
current with levels either 0 or ±Vdc. They are known as the voltage levels can be obtained by connecting these cell in
two-level inverter. To produce a quality output voltage or a cascade and the phase voltage van is the sum of voltages of
current wave form with less amount of ripple content, they individual cells, van = v1 + v2 + v3 + :::: + vN.
require high switching frequency. In high- power and high
voltage applications these two level inverters, however, have
some limitations in operating at high frequency mainly due to
switching losses and constraints of device ratings. These
limitations can be overcome using multilevel inverters.
There are 3 types of multilevel inverters named as diode
clamped multilevel inverter, flying capacitor multilevel
inverter and cascaded multilevel inverter. These three types of
multilevel inverters requires more no. of components such as
switches, clamping diodes and capacitors. As the number of
978-1-4673-6030-2/13/$31.00 ©2013 IEEE
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2013 International Conference on Power, Energy and Control (ICPEC)
Fig.1 Configuration of single-phase H-bridge inverter switches, roughly half of the no. of switches, clamping diodes,
Table 1. Load voltage with corresponding conducting switches and voltage-splitting capacitors in the diode clamped
configuration or clamping capacitors in the flying capacitor
Active Switches Output Voltage(Vab) configuration. Simulation results are included to verify the
S1,S2 +Vdc operating principle of the proposed MLDCL inverters.
S3,S4 -Vdc
S1,S4 or S2,S3 0
Output
voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
Fig. 3 output wave form of single phase 7 level cascaded inverter 0Vdc 1 0 1 0 1 0 1 0 1 0
Output 2Vdc 1 0 0 1 0 0 1 1 1 0
0Vdc 1 0 1 0 1 0 1 0 1 0 1 0 -Vdc 0 1 1 0 1 1 0 0 1 1
Vdc 1 0 0 1 0 0 1 1 0 0 1 1 -2Vdc 0 1 1 0 0 1 1 0 1 1
2Vdc 1 0 0 1 0 0 1 1 1 0 0 1 -3Vdc 0 1 1 0 0 1 1 0 0 1
-2Vdc 0 1 1 0 0 1 1 0 1 1 0 0
-3Vdc 0 1 1 0 0 1 1 0 0 1 1 0
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V. SIMULATION RESULTS
The Simulation was conducted to verify the operation of the
Cascaded H-Bridge MLI and proposed MLDCL inverter using
SPWM and Modified SVPWM Techniques.
A. Seven Level Cascaded H-bridge MLI for 1–Ф :
Fig.8 line voltage of 1–Ф seven level Cascaded H-Bridge MLI using SPWM
Fig.12 FFT analysis of line voltage of 1–Ф seven level MLDCL inverter using
SPWM
Fig.9 FFT analysis of line voltage of 1–Ф seven level cascaded H-Bridge MLI
using SPWM
Fig.13 line voltage of 1–Ф seven level MLDCL Inverter using Modified
SVPWM
Fig.8 line voltage of 1–Ф seven level Cascaded H-Bridge MLI using Modified
SVPWM
Fig.14 FFT analysis of line voltage of 1–Ф seven level MLDCL inverter using
Modified SVPWM
Fig.10 FFT analysis of line voltage of 1–Ф seven level cascaded H-Bridge
MLI using Modified SVPWM
Fig.15 line voltage of 3–Ф seven level Cascaded H-Bridge MLI using SPWM
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2013 International Conference on Power, Energy and Control (ICPEC)
Fig.16 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using Fig.21 line voltage of 3–Ф seven level MLDCL Inverter using SPWM
SPWM
Fig.17 line voltage of 3–Ф seven level Cascaded H-Bridge MLI using
Modified SVPWM
Fig.22 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using
Modified SVPWM
The simulation results of the seven level cascaded H-
bridge inverter and proposed MLDCL Inverter using SPWM
and Modified SVPWM for 1–Ф and 3–Ф and its corresponding
E. COMPARISON OF RESULTS:
Fig.20 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using Table. 4 comparison of THD for various PWM Methods for 1–Ф
Modified SVPWM
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Modified
space
262.1 8.79 274.2 6.84
vector Fig. 24 Proposed 1–Ф 7-level DC Link inverter hardware diagram
PWM
A summary of THD and fundamental output voltage for
various multilevel inverter topologies with their control
strategies are presented. i.e., 1–Ф 7-Level cascaded inverter
and 1–Ф 7-level MLDCL inverters were simulated using
SPWM and modified SVPWM with triangular carriers. And it
is concluded that 1–Ф 7-level MLDCL inverter using modified
SVPWM has given good fundamental output voltage (274.1
V) with less THD (20.64%).
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