Appendices

Z-100 Series Computers

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CONSISTS OF

MANUAL
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FLYSHEET
597-2922-D2

TAB SET
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Copyright ~ 1983 by Zenith Data Systems Corporation, all rights reserved.

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 TABLE OF CONTENTS
Appendices

Appendix A S - 100 Bus A.1

Appendix B 8 08 5 Architecture .. B.1

Appendix C 8 0 8 5 Instruction Set C.1

Appendix D i A PX88 Book and Other Data Sheets .. D.1

IV
Description
In Appendix A, yo u a r e f u rnished with the I EEE T ask
696.1/D2, S-100 Bus Standards.

In Appendices B and C, you are furnished the architecture

and instruction sets for the Intel 8085 microprocessor.

The 8085 microprocessor is an 8-bit general purpose micro-

processor that is capable of accessing up to 64K bytes of
memory and has status lines for controlling large systems.

Contained in the 8085 microprocessor are the functions of

clock generation, system bus control, and interrupt priority
selection, in addition to execution of the instruction set.

The 8085 microprocessor implements a group of instructions

that move data between registers, between a register and
memory, and between a register and an I/O port. It also has
arithmetic and logic instructions, and machine control instruc-
tion. The CPU recognizes these instructions only when they
are coded in binary form.

The architecture and instruction set for the 8088 microproces-

sor are located in the iAPX 88 Book, which is included as
part of this Appendix.

The 8088 microprocessor is an 8-bit microprocessor. It com-

bines a 16-bit microprocessor internal architecture with an
easy to use 8-bit bus interface. Most of the bus lines are identi-
cal in function to the 8085A.

The 8088 is totally software compatable with the 16-bit 8086

CPU. All the power of the 8086 16-bit instruction set is avail-
able in the 8-bit 8088.
With the 16-bit internal architecture, the 8088 provides 16-bit
wide registers, data paths, a 16-bit ALU, and a set of powerful
16-bit instructions identical to the ones found in the 8086
microprocessor. It also provides a 20-bit memory address
range and a 16-bit input/output port address range for I/O
cycles. This gives the 8088 a full megabyte of memory addres-
sability and 64K bytes of I/O addressability.

The instruction set for the 8088 includes a full complement

of arithmetic operations including addition, subtraction, multi-
plication, and division, on 8-bit or 16-bit quantities. If also has
a complete set of string manipulation operations for perfor-
mance and flexibility in application where large amounts of
data are involved.

Appendix D provides you with the data sheets and program-

ming instruction for the major IC's.
 page A.1

APPENDIX A
S100 Bus Specifications

The following pages provide you 1EEE

Task 696.1/D2, S-100 Bus Standards.
 page B.1

APPENDIX B
8085 Architecture

The following pages are reprinted with

the permission of Intel Corporation.
page B.2

8085A ARCHITECTURE

2.1 W H AT THE 8085A IS functions to perform READ and WRITE opera-

The 8085A is an 8-bit general-purpose micro- tions and also to select memory or I/O ports.
p rocessor that i s v ery co st-effective in s m a ll The 8085A can address up to 256 different I/O
systems because of its extraordinarily low hard- locations. These addresses have the same
ware overhead requirements. At the same time numerical values (00 through FFH) as the first
it is capable of accessing up to 64K bytes of 256 memory addresses; they are distinguished
memory and ha s s t a tus l i nes fo r c o n trolling by means of the 10/M output from the CPU. You
large systems. m ay also c h o os e t o a d d r es s I / O p o rt s a s
memory locations (i.e., memory-map the I /O,
2.2 W H AT'S IN THE 8085A Section 3.2).
In the 8085A microprocessor are contained the
functions of clock generation, system bus con-
trol, and interrupt priority selection, in addition 2.2.1 R e gisters
to execution of the instruction set. (See Figure The 8085A, like the 8080, is provided with inter-
2-1.) The 8085A transfers data on an 8-bit, bi- nal 8-bit r e gisters an d 1 6 -bit r e g isters. The
d irectional 3-state bus (ADQ.7) which is t i m e- 8085A has eight addressable 8-bit registers. Six
multiplexed so a s t o a l s o t r a nsmit th e e ight of them can be used either as 8-bit registers or
lower-order address bits. A n a d d itional eight a s 16-bit r e g ister p a i rs . R e gister p a ir s a r e
lines (As.iq) expand the MCS-85 system memory treated a s t h o ug h t h e y w e r e s i n g le, 1 6-bit
addressing capability to 16 bits, thereby allow- registers; the high-order byte of a pair is located
ing 64K bytes of memory to be accessed direct- in the first register and the l ow-order byte is
ly by the CPU. The 8085A CPU (central process- located in the second, In addition to the register
ing unit) generates control signals that can be pairs, th e 8 0 85A c o n t ains t w o m o r e 1 6 -bit
used to select appropriate external devices and registers.

INTA RST 6 5 TRAP

I NTR RST 5 5 RSTT 5

ACCUMULATOR TEMP REG INSTRUCTION

(A RED) (8) (8) REGISTER IM

FLAG (5)
FLIP. FLOPS
8 (8) C (6)
REG REG
I N 5 TRU CTI ON
ARITHMETIC IBI E (61
DECODER 6EG
LOGiC AND REG
UNIT MACHINE H (TI 6)
(ALU) CYCLT REG REG REGISTER
(6) ENCODING ('t61 ARRAY
STACK POINTER

PROGRAM COUNTER ( )
POWERJ 5V
SUPPLY i G ND INCREMENTERIOECREMENTER
ADDRESS LATCH I(8)

ADDRESS BUFFER ) OATAIADDRESS BUFFER

Xl CLK RESET
XI GEN CONTRO L STATUS OM A

CLK OUT RD WR ALE So S>10/M HLDA t RES ET

QUT
READY HOLD RESET IN AA 5 ACT
ADDRESS BUS ADDRESSJOATA BUS

FIGURE 2-1 8085A CPU FUNCTIONAL BLOCK DIAGRAM


FUNCTIONAL DESCRIPTION
The 8085A's CPU registers are distinguished as
follows:
• The accumulator (ACC or A Register) is
the focus of al l o f t h e a c c umulator in-
s tructions ( T able 4 - 1), w h ic h i n c l u d e
arithmetic, logic, load and store, and I/O
instructions. It is an 8-bit register only.
(However, see Flags, in this list.)
• The program counter (PC) always points
t o the memory location of th e n ext i n -
struction to be executed. It always con-
tains a 16-bit address.
• General-purpose registers BC, DE, and
HL may be used as six 8-bit registers or
as three 16-bit registers, interchangeably,
depending on the instruction being per-
formed. HL functions as a data pointer to
r eference memory a d dresses t ha t a r e
either the sources or the destinations in
a n umber o f i n s t r u ctions. A s m a l l e r
number of instructions can use BC or DE
for indirect addressing.
• The stack pointer (SP) is a special data
pointer that always points to the stack
top (next available stack address). It is
an indivisible 16-bit register.
• The fl ag r egister contains f i ve o n e-bit
flags, each of wh ich records processor
status information and may also control
p rocessor o p e r a t i on . ( Se e f o l l o w i n g
paragraph.)
2.2.2 F l a gs
T he five f lags i n t h e 8 0 85A CPU are s h ow n
below:
D7 D6 D5 D4 Dg Dz D~ Dp
S Z AC P CY
The carry flag (CY) is set and reset by arithmetic
operations. Its status can be directly tested by
a program. For example, the addition of t w o
one-byte numbers can produce an answer that
does not fit into one byte:
HEXIDECIMAL BINARY
AEH 1 0 1 0 1 1 1 0
+ 74H 0 1 1 1 0 1 0 0
122H 1 0 0 1 0 0 0 1 0
j'
Carry bit sets carry flag to 1
Page 8.3
A n a d d i t io n o p e r a t io n t h a t r e s u l t s i n a n
o verflow out o f t h e h i g h-order bit o f t h e a c -
c umulator s et s t h e c a r r y f l a g . A n a d d i t i on
operation that does not result i n a n o verflow
clears the carry flag. (See 8080/8085 Assembly
L anguage P rogramming M a n ua l f o r f u r t h e r
details.) The carry flag also acts as a "borrow"
flag for subtract operations.
The auxiliary carry flag (AC) indicates overflow
out of bit 3 of the accumulator in the same way
that the carry flag indicates overflow out of bit
7. This flag is commonly used in BCD (binary
coded decimal) arithmetic.
The sign flag is set to the condition of the most
significant bit of the accumulator following the
execution of a r i thmetic o r l o gi c i n structions.
These instructions use bit 7 of data to represent
t he sign of t h e n u m ber contained in th e a c -
c umulator. This p e rmits th e m a n i pulation o f
numbers in the range from — 128 to + 127.
The zero flag is set if t he r esult generated by
c ertain instructions is z e ro. The zero f lag i s
cleared if the result is not zero. A result that has
a carry but has a zero answer byte in the ac-
cumulator will set both the carry flag and the
zero flag. For example,
HEXADECIM AL BINARY
A7H 1 0 1 0 0 1 1 1
+ 59H + 0 1 0 1 1 0 0 1
100H 1 0 0 0 0 0 0 0 0
Carry bit
Eight zero bits set zero flag to 1
I ncrementing o r d e c r e menting c e r t ai n C P U
registers with a zero result will also set the zero
flag.
The parity flag ( P) is s e t t o 1 i f t h e p a r i t y
(number of 1-bits) of the accumulator is even. If
odd, it is cleared.
2.2.3 S t a ck
The stack pointer maintains the address of the
l ast byte e n t ered i nt o t h e s t a ck . Th e s t a c k
pointer can be initialized to use any portion of
read-write memory as a stack. The stack pointer
is decremented each time data is pushed onto
the stack and is incremented each time data is
p opped of f t h e s t a c k ( i .e., th e s t ac k g r o w s
downward in terms of memory address, and the
stack "t op " i s t h e l o w est n u merical address
represented in the stack currently in use). Note
that the stack pointer is always incremented or
d ecremented b y t w o b y t e s s i n c e a l l s t a c k
operations apply to register pairs.
Page 8.4
FUNCTIONAL DESCRIPTION
2.2.4 A r ithmetic. Logic Unit (ALU)
The ALU contains the accumulator and the flag
register (described in Sections 2.2.1 and 2.2.2)
and some t emporary registers that ar e i n ac-
cessible to the programmer.
Arithmetic, logic, and rotate operations are per-
formed by the ALU. The results of these opera-
tions can be deposited in the accumulator, or
they can be transferred to the internal data bus
for use elsewhere.
2.2.5 I n struction Register and Decoder
During an instruction fetch, the first byte of an
instruction (containing th e o p c ode) i s t r a n s-
ferred from the internal bus to the 8-bit instruc-
tion register. (See Figure 2-1.) The contents of
the instruction register are, in turn, available to
t he instruction d e c oder. Th e o u t pu t o f t h e
decoder, gated by timing signals, controls the
registers, ALU, and data and address buffers.
The outputs of the instruction decoder and in-
ternal clock generator generate the state and
machine cycle timing signals.
2.2.6 I n ternal Clock Generator
The 8085A CPU incorporates a complete clock
generator on its chip, so it requires only the ad-
dition of a quartz crystal to establish timing for
its operation. (It will accept an external clock in-
put at its X, input instead, however.) A suitable
crystal for the standard 8085A must be parallel-
resonant at a fundamental of 6.25 MHz or less,
twice the desired internal clock frequency. The
8 085A-2 will operate with c rystal of u p t o 1 0
MHz. The functions of the 8085A internal clock
generator are shown in F i gure 2-2. A Schmitt
trigger is used interchangeably as oscillator or
SCHMITT
AMP
XI
'EXTERNAL CAPACITORS REOUIREO ONLY FOR CRYSTAL FREOUENCIES
FIGURE 2-2 8085A CLOCK LOGIC
as input conditioner, depending upon whether a
crystal or an external source is used. The clock
circuitry generates two nonoverlapping internal
clock signals, pi and p2 (see Figure 2-2). pi and
g2 control the internal timing of the 8085A and
are not directly available on the outside of the
chip. The external pin CL K i s a b u f f ered, in-
verted version of 0,. CLK is half the frequency of
t he crystal input signa! and may be used fo r
clocking other devices in the system.
RST T 5
RST 05
RST 5.5
8085A
E5 E 0 UTIN0
SOFTWARE
RST INSTRUCTIONS
IN RESPONSE TO INTR
8085A
SYSTEM
MEMORY
FIGURE 2-3 8085A HARDWARE AND SOFT-
WARE RST BRANCH LOCATIONS
2.2.7 I n t errupts
The five hardware interrupt inputs provided in
the 8085A are of three types. INTR is identical
with the 8080A INT line in f u nction; i.e., it is
maskable (can be enabled or disabled by El or
Dl software instructions), and causes the CPU
to fetch in an RST instruction, externally placed
on the data bus, which vectors a branch to any
one of eight fixed memory locations (Restart ad-
d resses). (See Figure 2-3.) INTR can a lso b e
controlled by the 8259 programmable interrupt
controller, which generates CALL instructions
instead of RSTs, and can thus vector operation
of the CP U t o a p r e p rogrammed subroutine
TMHT located anywhere i n y o u r s y s t em's m e m ory
map. The RST 5.5, RST 6.5, and RST 7.5 hard-
ware interrupts are different in function in that
they are maskable through the use of the SIM
 Page B.5

FUNCTIONAL DESCRIPTION

instruction, which enables or disables these in-
terrupts by c l earing or s e t t ing c o rresponding
mask flags based on data in the accumulator.
(See Figure 2-4.) You may read the status of the
interrupt mask previously set by p e forming a
RIM instruction. Its execution loads into the ac-
c umulator t h e f o l l o w i n g i n f o r m a t i on . ( S ee
Figure 2-5.)
• C urrent i n t errupt m a sk s t a t us f o r t h e
RST 5.5, 6.5, and 7.5 hardware status.
• Current interrupt enable flag status (ex-
cept that i m mediately following TRAP,
the IE flag status preceding that inter-
rupt is loaded).
• RST 5.5, 6.5, and 7.5 interrupts pending.
RST 5.5, 6.5, and 7.5 are also subject to being
enabled or disabled by the El and Dl i n struc-
tions, respectively. INTR, RST 5.5, and RST 6.5
are level-sensitive, meaning that these inputs
may be acknowledged by the processor when
they are held at a high level. RST 7.5 is edge-
sensitive, meaning that an internal flip-flop in
the 8085A registers the occurrence of an inter-
rupt the instant a r ising edge appears on the
RST 7.5 input line. This input need not be held
h igh; the f l i p-flop w il l r e m ain se t u n t i l i t i s
cleared by one of three possible actions:
• The 8 085A r e sponds to t h e i n t e r rupt,
and sends an internal reset signal to the
RST 7.5 flip-flop. (See Figure 2-6A.)

SIM — SET INTERRUPT MASK RST 7.5

(OPCODE = 30)
8085A
CONTENTS OF ACCUMULATOR BEFORE EXECUTING SIM:

RST 7.5 RESET

F.F. (INTERNAL)

RESETINTERRUPT T.S INTERRUPT

FLIP FLOP
REQUEST
(INTERNAL)

FIGURE 2.6A RST 7.5FLIP FLOP

FIGURE 2-4 INTERRUPT MASKS SET USING
SIM INSTRUCTION

SCH MITT
TRIGGER

TRAP
D CLK INTERRUPT
RIM — READ INTERRUPT MASK REQUEST
(OPCODE = 20) UNTERNALI

D
CONTENTS OF ACCUMULATOR AFTER EXECUTING RIM: F(F

II.5 155 155 IE MI S M5 5 M5 5

INTERNAL
TRAP
ACKNOWLEDGE

FIGURE 2-68 TRAP INTERRUPT INPUTS

INTERRUPT ENASLE FLAG

FIGURE 2-6 RST 7.5 AND TRAP INTERRUPT

FIGURE 2.5 RIM — READ INTERRUPT MASK INPUTS
page B.6

FUNCTIONAL DESCRIPTION

• The 8085A, before resporiding to the RST terrupt mask) and SIM (set interrupt mask) in-
7.5 interrupt, receives a RE~ET IN signal struction listings. Interrupt functions and their
f rom an external source; this a lso a c - priorities are shown in the table that follows.
tivates the internal reset.

• The 8085A executes a S IM i n struction,

with accumulator bit 4 previously set to Address (1)
Name Priority 8 r anched to
1. (See Figure 2-4.) when inter.
The third type of hardware interrupt is TRAP. rupt occurs
This input is not subject to any mask or inter- TRAP 24H Rising edge
rupt enable/disable instruction. The receipt of a AND high
positive-going edge on the TRAP input triggers level until
the processor's hardware interrupt sequence, sampled
b ut t h e p u l s e m u s t be he l d h i g h u nt i l RST 75 2 3CH Rising edge
acknowledged internally (see Figure 2-68). (latched)
T he sampling of al l i n t errupts occurs on t h e RST 6.5 3 34H High level
until sam.
descending edge of CLK, one cycle beforethe pled
end of the instruction in which the interrupt in-
RST 5.5 4 2CH High level
put is activated. To be recognized, a valid inter- until sam-
rupt must occur at least 160 ns before sampling pled
time in the 8085A, or 150 ns in the 8085A-2. This INTR (2) High level
means that to guarantee being recognized, RST until sam-
5.5 and 6.5and TRAP need to be held on for at pled
l east 17 c l oc k s t a te s p l u s 1 6 0 n s ( 1 5 0 f o r
8085A-2), assuming that the interrupt might ar- NOTES:
rive just barely too late to be acknowledged dur- (1) In the case of TRAP and RST 5.5-7.5, the
ing a particular instruction, and that the follow- contents of t h e P rogram Counter are
ing instruction might be an 18-state CALL. This pushed onto the stack before the branch
timing assumes no WAIT or HOLD cycles are occurs.
used, (2) Depends on the instruction that is pro-
vided to the 8085A by the 8259 or other
The way interrupt masks are set and read is circuitry when the interrupt is acknowl-
described in Chapter 4 under the RIM (read in- edged.

EFFECT OF IUM INSTRUCTION

2.2.8 S e rial Input and Output

The SID and SOD pins help to m i nimize chip
count in small systems by providing for easy in-
terface to a serial port using software for timing /
and for coding and decoding of the data. Each LAIOA
time a RIM instruction is executed, the status of
the SID pin is read into bit 7 of the accumulator. EFFECT OF SIM INSTRUCTION
RIM is t hus a d u a l-purpose instruction. (See SO D

Chapter 4.) In similar fashion, SIM is used to

latch bit 7 of the accumulator out to the SOD
output via an internal flip-flop, providing that bit
6 of the accumulator is set to 1. (See Figure 2-7.)
Section 2.3.8 describes SID and SOD timing.

SID can also b e u sed a s a g e n e ral purpose

TEST input and SOD can serve asa one-bit con- FIGURE 2.7 EFFECT OF RIM AND SIM
trol output. INSTRUCTIONS ON SERIAL DATA LINES
 Page B.7

FUNCTIONAL DESCRIPTION

2 .3 HO W TH E MCS-85 SYSTEM WO R K S components with improved timing margins and

T he 8085A CPU g e nerates s i g nals t h a t t e l l
peripheral devices what type of information is
on the multiplexed Address/Data bus and from
that point on the operation is almost identical
to the MCS-80™ CPU Group. A multiplexed bus
structure was chosen because it freed device
pins so that more functions could be integrated
on the 8085A and other components of the fami-
ly. The multiplexed bus i s d e s igned to a l l ow
complete compatibility t o e x i s ting peripheral
access requirements. (See Figure 2-8.)
To enhance the system integration of MCS-85,
several s pecial c o m p onents w i t h c o m b i ned
memory and I/O were designed. These new
devices directly i n terface t o t h e m u l t i plexed
bus of the 8085A. The pin locations of the 8085A
a nd th e s p e c ial p e r ipheral c o m ponents a r e
a ssigned to m i n i mize PC b oard area and t o
a llow f o r e f f i c i en t l a y o ut . T h e d e t a i l s o n
peripheral components are contained in subse-
q uent p a r a g raphs o f th i s c h a p t e r a n d i n
Chapters 5 and 6.

ADDRESS BUS
8080A
ADDRESS BUS
8085A

8224 INTR M 0 L TP
I L EX ED
INTA ADDRESS/DATA BUS
8228
DATA RD
BUS RESET IN WR
RESET IN ~
MEM RD RESET DUT ID/9
MEM WR
IDRD
ITO WR

FIGURE 2-8A MCS-80TM CPU GROUP FIGURE 2.8B MCS-85™ CPU/8085A (Mcs-80 COMPATIBLE
FUNCTIONS)

DATA/ADDRESS BUS

ADDRESS

D~ DP

TIME MULTIPLEX DATA BUS

FIGURE 2-8C MULTIPLEXED BUS TIMING

FIGURE 2.8 BASIC CPU FUNCTIONS

Page B.S
FUNCTIONAL DESCRIPTION
2.3.1 M u ltiplexed Bus Cycle Timing
The execution of any 8085A program consists
of a sequence of READ and WRITE operations,
of which each transfers a byte of data between
the 8085A and a particular memory or I/O ad-
dress. These READ and WRITE operations are
the only communication between the processor
and the other components, and are all that is
necessary to e x ecute any i n struction or p r o-
gram.
Each READ or WRITE operation of the 8085A is
referred to as a machine cycle. The execution of
each instruction by the 8085A consists of a se-
quence of from one to five machine cycles, and
each machine cycle consists of a minimum of
from three to six clock cycles (also referred to
as T states). Consider the case of the Store Ac-
c umulator Direct (STA) instruction, shown i n
Figure 2-9. The STA instruction causes the con-
t ents of th e a c c umulator to b e s t o red at t h e
direct address specified in the second and third
b ytes o f t h e in s t r u c t ion. D u r in g t h e fi r s t
machine cycle (M,), the CPU puts the contents
of the program counter (PC) on the address bus
and performs a MEMORY READ cycle to read
from memory the opcode of the next instruction
(STA). The Mi machine cycle is also referred to
as the OPCODE FETCH cycle, since it fetches
the operation code of th e next i nstruction. In
the fourth clock cycle (T4) of Mi, the CPU inter-
prets the data read in and recognizes it as the
opcode of the STA instruction. At this point the
MACHINE
MI
CYCLE
T STATE TI TT TA
TS
TYPE OF
MACHINE CYCLE
THF. ADDRESS (CONTENTS OF THE
PROG RA M C O U N T E R ) POINTS TO THE TO THE SECOND BYTE OF
FIRST BYTE (OPCODEI OF THE
INST R UCT ION
DATA BUS
FIGURE 2-9 CPU TIMING FOR STORE ACCUM U LA TOR DIRECT (STA) INSTRUCTION
CPU knows that it must do three more machine
cycles (two MEMORY READs and one MEMORY
WRITE) to complete the instruction.
T he 8085A t h e n i n c r e m e nt s t h e p r o g r a m
counter so that it points to the next byte of the
instruction an d p e r forms a M E M ORY R EAD
machine cycle (Mz) at address (PC+ i ) . The ac-
cessed memory places the addressed data on
the data bus for the CPU. The 8085A temporarily
stores this data (which is the low-order byte of
the direct address) internally in the CPU. The
8085A again increments the program counter to
location (PC+2) and reads from memory (Mq)
t he next b y t e o f d a t a , w h i c h i s t h e h i g h -
order byte of the direct address.
At this point, the 8085A has accessed all three
bytes of the STA instruction, which it must now
execute. The execution consists of placing the
data accessed in M>and Mq on the address bus,
then placing the contents of the accumulator
o n th e d a t a b u s , a n d t h e n p e r f o r m in g a
MEMORY WRITE machine cycle (M4). When M4
is finished, the CPU will fetch (Mi) the first byte
of the next instruction and continue from there.
State Transition Sequence
As the preceding example shows, the execution
o f a n i n s t r u c t io n c o n s i st s o f a se r i e s o f
machine cycles whose nature and sequence is
determined by the opcode accessed in the M,
INSTRUCTION CYCLE - - -
MP- MA
TT TI TT TS TI TT TS
MEMORY READ MEMORY READ MEMORY WRITE
T HE l DDRESSIPC I ) P O I N T S THE ADDRESS IPC • 2l POINTS THE ADDRESS IS THE DI REF:T
TO THE THIRD BYTE OF THE ADDR ESS ACCESSED IN MP
THE INSTRUCTION I N S T R U C T0I N AND MS
I OW ORDER BYTE OF T H F H IGH OR D E R B Y T E O F T H E CONTENTS OF TH E
DIRECT ADDRESS DIRECT A D D R ESS A CCUMULA T O R
 Page B.9

FUNCTIONAL DESCRIPTION

RESET
STATUS CONTROL
MACHINE CYCLE IQ/M 5 1 SO R D WM I N T A
0 0 I I RESET
OPCODE FETCH (QF)
MEMORY READ ILIRI 0 I 0 0 I I
MES)DRY WRITE (MIY) 0 0 1 I I 0 I RESET
I/O READ //QR) I I 0 0 I I
I/O WRITE ((OW) I 0 I I 0 I HALT
INTR ACKNQIYLEDG E ( IN A) I ( I I 0 I
Bus IDLE (BI) DA D 0 I 0
I '/4 R S T I I HALT
i, R E A DY
HALT /5 0 0 TS TS
(READY / BIMC)

0 = Logic "0 " 1 = Loi)ic " 1 " T S = High )mprdance X = Unspecified

READY / BIMC
TWai T

HOLD
P )-VALIDINT
HOLD •

THAL 1

FIGURE 2-10 8085A MACHINE CYCLE CHART VALIDINT

YES
H OLD I

SET RESET
SET HLDA FF HALT FF
HLDA FF

machine cycle. While no one instruction cycle MI CC 6 YES SET

will consist of more than five machine cycles, Ts T4 HOLD I INTA FF
RESET
every machine cycle will be one of th e seven INTE FF
CC 4
types listed in Figure 2-10. These seven types of
m achine cycles ca n b e d i f f erentiated by t h e
state of the three status lines (IOIM, St a n d S,)
and the t h ree c o ntrol s i g nals (RD, WR, and HLDA FF YES
INTA). SET

THQLD ) HOLD
Most machine cycles consist of three T states,
HOLD
(cycles of the CLK output) with the exception of LAST
OPCODE FETCH, which n o rmally ha s e i t her MACHINE CYCLE
OF INSTRUCTION RESET
four or six T states. The actual number of states HLDA FF
required to perform any instruction depends on YES
the instruction being executed, the particular
machine cycle within the instruction cycle, and
the number of WAIT and HOLD states inserted NO
VALIDINT . I H ALT I
YES

into each machine cycle through the use of the

READY and HOLD i n puts o f t h e 8 0 85A. The
s tate t r a nsition d i a g ram i n F i g u r e 2 - 1 1 i l - YES NO

lustrates how the 8085A proceeds in the course SET

of a machine cycle. The state of various status INTA FF
RESET
a nd control s i g nals, a s w e l l a s t h e s y s t e m INT'E FF

buses, is shown in Figure 2-12 for each of the

ten possible T states that the processor can be
in. NOTE: SYM BOL DEFINITION

0T„ CPU STATE T„. ALL CPU STATE TRANSITIONS OCCUR

ON THE FALLING EDGE OF CLK
Figure 2-11 also shows when the READY, HOLD, X — A DECISION (X) THAT DETERMINES WHICH OF SEVERAL
ALTERNATIVE PATHS TO FOLLOW.
a nd interrupt s ignals ar e s a m pled, and h o w
X — PERFORM THE ACTION X
they modify the basic instruction sequence (T,-
FLOWLINE THAT INDICATES THE SEQUENCE OF EVENTS.
T6 and Twerp). As we shall see, the timings for X : FLOWLINE THAT INDICATES THE SEQuENCE QF Ei,ENTS
each of the seven types of machine cycles are IF CONDITION X IS TRUE

almost identical. CC NUMBER OF CLOCK CYCLES IN THE CURRENT IVIACHINE

CYCLE.
BIMC "BUS IDLE MACHINE CYCLE" - MACHINE CYCLE WHICH
DOESN'T USE THE SYSTEM BUS.
VALIDINT . "VALID INTERRUPT" — AN INTERRUPT IS PENDING
OPCODE FETCH (OF): THAT IS BOTH ENABLFD AND UNMA S KED (MASK
ING ONLY APPLIES FOR RST 5.5, 6.5, AND 7 5
T he OPCODE FETCH (OF) machine cycle i s INPUTS).
H LDA FF I NT E R N A L . IQLD ACKNOY/LEDGE FLIP FLOP NQI E
unique in t ha t i t h a s m o r e t h a n t h ree c lock THAT THE 6065A SYSTEM BUSES ARE 0 STATED ONE
cycles. This is because the CPU must interpret CLOCK CYCLE AFTER THE HLDA FLIP FLOP IS SET

the opcode accessed in T1, T2, and Ts before it

can decide what to do next. FIGURE 2-11 8085A CPU STATE TRANSITION
Page B.10

FUNCTIONAL DESCRIPTION

Status & Buses Control The 8085A also sends out a 16-bit address at the
Machine T beginning of every machine cycle to identify the
State S 1 ,SO IO/M Aa-Ate ADo-AD/ R D/WR INTA AL E particular memory location or I/O port that the
X X machine cycle applies to. In the case of an OF
X X 0
cycle, the contents of the program counter is
T2 X X
placed on the address bus. The high order byte
X X X X X 0
TWA IT
X (PCH) is placed on the AB-Ats lines, where it will
T3 X X X X X 0 stay until at least T4. The low order byte (PCL) is
Ta I 0 X TS I 1 0 placed on the AD0-AD7 lines, whose three-state
1 0 X TS 1 I 0 d rivers are enabled i f n o t f o u n d a l ready o n .
I O' X TS 1 I 0
Unlike the upper address lines, however, the in-
formation on th e l o wer address lines will re-
TRESET X TS TS TS TS I 0
main there for only one clock cycle, after which
THALT 0 TS TS TS TS 1 ' 0 the drivers will go to their high impedance state,
THOLO X TS TS TS TS I indicated by a dashed line in Figure 2-13. This is
necessary because the AD0-AD> lines are time
0 = Logic "0 " 1 = Logic "I " T S = High Impedance X = Unspecified m ulitplexed b etween t h e a d d r ess a n d d a t a
ALE not generated during 2nd and 3rd machine cycles of DAD buses. During T1 of every machine cycle, AD0-
Instruction. ADz output the l o wer 8-bits of a d d ress af ter
which AD0-AD/ will e ither output th e d e sired
ID/M =- 1 during T4-TS states of RST and INA cycles.
data for a WRITE operation or the drivers will
float (as is the case for the OF cycle), allowing
FIGURE 2-12 8085A MACHINE STATE CHART the external device to drive the lines for a READ
operation.

Since the address information on AD0-AD, is of

Figure 2-13 shows the timing relationships for
an OF machine cycle. The particular instruction
illustrated is DCX, whose timing for OF differs
f rom other i n structions i n t h a t i t h a s s i x T
states, while s om e i n s t ructions require on ly
four T states for OF. In this discussion, as well
as the following discussions, only the relative
timing of the signals will be discussed; for the
actual timings, refer to the data sheets of the in-
dividual parts in Chapters 5 and 6.
The first thing that the 8085A does at the begin-
ning of every machine cycle is to send out three
status signals (IO/M, S1, SO) that define what
type of machine cycle is about to t ake place.
The IO/M signal identifies the machine cycle as
being either a memory reference or input/output
operation. Th e S 1 s t a t u s s i g n a l i d e n t i f i es
whether the cycle is a READ or WRITE opera-
tion. The SO and S1 status signals can be used
together (see F igure 2-10) to i d e ntify R EAD,
WRITE, or OPCODE FETCH machine cycles as
well as the HALT state. Referring to Figure 2-13,
the 8085A will send out IO/M = 0,S1 = 1 , S O = 1
at the beginning of the machine cycle to iden-
tify it as a READ from a memory location to ob-
tain an opccde; in other words, it identifies the
machine cycle as an OPCODE FETCH cycle.
a transitory nature, it must be latched either in-
ternally in special multiplexed-bus components
like the 8155 or externally in parts like the 8212
8-bit latch. (See Chapter 3.) The 8085A provides
a special t i m i n g s i g n al , A D D RESS L ATCH
ENABLE (ALE), to facilitate the latching of A0-A7,'
ALE is present during Tt of every machine cycle.
After the status signals and address have been
sent out an d t h e A D0-AD7 drivers have been
disabled, the 8085A provides a low level on RD
to enable the addressed memory device. The
device will then start driving the AD0-AD, lines;
this is indicated by the dashed line turning into
a solid line in Figure 2-13. After a period of time
(which is the access time of the memory) valid
data will be present on AD0-AD7. The 8085A dur-
ing T3 will load the memory data on AD0-AD> in-
to its instruction register and then raise R5 to
the high level, disabling the addressed memory
device. At this point, the 8085A will have fin-
ished accessing the opcode of the instruction.
Since this is the first machine cycle (M,) of the
instruction, the CPU will automatically step to
T4, as shown in Figure 2-11.
During T,, the CPU will decode the opcode in
the instruction register and decide whether to
e nter Ts on the next c l ock o r t o s t ar t a n e w
machine cycle and enter T,. In the case of the
D CX instruction shown i n F i g ure 2-13, it w i l l
enter Ts and then Ts before going to T,.

FUNCTIONAL DESCRIPTION
MI (DFI
SIGNAL
ID/M,
I D/M P , S I= I, SO = I
SI, SO
AB-A15
ADOAD/ Dp-DT (DCX(
RD
FIGURE 2-13 OPCODE FETCH MACHINE CYCLE {OF DCX INSTRUCTION)
During T5 and T6, of DCX, the CPU will decre-
ment the designated register. Since the AB-A(5
lines are driven by the address latch circuits,
which are part of the incrementer/decrementer
logic, the AB-A,5 lines may change during T5 and
T6. Because the value of AB-A,5 can vary during
T4-T6, it is most important that all memory and
I /O devices on t h e s y s te m bu s q u a l ify t h e ir
selection with RD. If t hey don't use RD, they
may be spuriously selected. Moreover, with a
linear selection technique {Chapter 3), two or
more devices could be simultaneously enabled,
w hich c o ul d b e p o t e n t i ally d a m a g ing. T h e
generation of spurious addresses can also oc-
cur momentarily a t a d d ress bu s t r a nsitional
p eriods in T<. Therefore, the selection of a l l
memor~and I/O devices must be qualified with
RD or WR. Many new memory devices like the
8155 and 8355 have the RD input that internally
is used to enable the data bus outputs, remov-
ing the need for externally qualifying the chip
enable input with RD.
Figure 2-14 is identical to Figure 2-13 with one
exception, which is the use of the READY line.
As we can see in Figure 2-11, when the CPU is in
T2, it examines the state of the READY line. If
the READY line is high, the CPU will proceed to
T3 and finish executing the instruction. If the
READY line is low, however, the CPU will enter
Tw+(> and stay there indefinitely until READY
goes high. When the READY line does go high,
the CPU will exit Twq(q and enter T3, in order to
c omplete t h e m a c h in e c y c le . A s s h o w n i n
Page B.11
MI
T4
UNSPECIFIED
F igure 2-14, the external effect o f u s in g t h e
READY line is to preserve the exact state of the
processor signals at the end of T2 for an integral
number of clock periods, before finishing the
machine cycle. This "stretching" of the system
timing has the further effect of increasing the
a llowable a c c es s t i m e f o r m e m o r y o r I / O
devices. By inserting Tw/ L(q states, the 8085A
can accom m o d ate even the slowest of
memories. Another common use of the READY
l ine i s t o s i n g e-step t h e p r o c essor w i t h a
manual switch.
2.3.2 Read Cycle Timing
MEMORY READ {MR).
Figure 2-15 shows the timing of two successive
MEMORY READ {MR) machine cycles, the first
without a Tw~(~ state and the second with one
Tw<(+ state. The timing during T,-T3 is absolute-
ly identical to the OPCODE FETCH machine cy-
cle, with the exception that the status sent out
during T> is IO/M = 0, S1 = 1, SO = 0, identify-
ing the cycles as a READ from a memory loca-
tion. This differs from Figure 2-13 only in that SO
= 1 for an OF cycle, identifying that cycle as an
OPCODE FETCH operation. Otherwise, the two
cycles are identical during T, ST>.
A second difference occurs at the end of T3. As
shown in Figure 2-11, the CPU always goes to T 4
from T3 during M,, which is always an OF cycle.
During all other machine cycles, the CPU will
always go from T3 to T~ of the next machine
cycle.
page B.12

FUNCTIONAL DESCRIPTION

MI (OF)

SIGNAL TWA
IT T4 TS

CLK

10/M,
I O/M 0 , S I 1 ,50 I
SI, Sp

AB.A15 PCN UNSPECIFIEO

OUT IN

ADp ADT PCL Dp DT IDCXI

ALE

RD

READY

FIGURE 2-14 OPCODE FETCH MACHINE CYCLE WITH ONE WAIT STATE

MR OR IOR MR OR IOR
SIGNAL
TS TWA
IT

CLK

IO/M,
IO/M 0 ( M RI OR I IIORI, 5I 1 50 0 IO/M 0 I MRI OR I I IORI, Sl I , Sp 0
SI, Sp

8 A IS
OUT IN OUT IN

ADp-AOT Ap-A 1 Dp DT p. AT Dp.DT

ALE

RD

READY

FIGURE 2-15 MEMORY READ (OR I/O READ) MACHINE CYCLES

(WITH AND WITHOUT WAIT STATES)

FUNCTIONAL DESCRIPTION
The memory address used in the OF cycle is
always the co ntents of t h e p r ogram counter,
which points to th e c u rrent instruction, while
the address used in the MR cycle can have
several possible origins. Also, the data read in
during an MR cycle is placed in the appropriate
register, not the instruction register.
I/O READ (IOR):
Figure 2-15 also shows the timing of two suc-
cessive I/O READ (IOR) machine cycles, the first
without a Tw/ur state. As is readily apparent, the
timing of an IOR cycle is identical to the timing
of an MR cycle, with the exception of IO/M = 0
for MR and IO/M = 1 f o r IOR; recall that IO/M
status signal identifies the address of the cur-
r ent m a c h in e c y c l e a s s e l e c t in g e i t h e r a
memory location or a n I/ O po rt. The address
used in the IOR cycle comes from the second
byte (Port No.) of an I NPUT instruction. Note
that the I/O port address is duplicated onto both
AD0-AD7 and AB-A,5. The IOR cycle can occur
only as the third machine cycle of an INPUT in-
struction.
N ote that th e R EADY signal can b e u sed t o
generate Tw~(q states for I/O devices as well as
memory devices. By gating the READY signal
with the proper status lines, one could generate
Tw<q states for memory devices only or for I/O
devices only. By gating in the address lines, one
can further qualify Tw/((q state generation by the
particular devices being accessed.
SIGNAL
IO/M,
IO/M 0 (MWI OR I (IOW) Sl =. 0, SO = I
SI, SP
ASA IS
ADp.AD/ Ap.AT Dp D/
WR
FIGURE 2-16 MEMORY WRITE (OR I/O WRITE) MACHINE CYCLES
(WITH AND WITHOUT WAIT STATES)
Page B.13
2.3.3 W R ITE Cycle Timing
MEMORY WRITE (MW):
Figure 2-16 shows the timing for two successive
MEMORY WRITE (MW) machine cycles, the first
without a Tw<(+ state, and the second with one
T»(z state. The 8085A sends out the status dur-
ing Ti in a s i milar fashion to the OF, MR and
IOR cycles, except that IO/M = 0, S1 = 0 , and
SO = 1, identifying the current machine cycle as
being a WRITE operation to a memory location.
The address is sent out during T, in an identical
manner to MR. However, at the end of T„ there
is a difference. While the AD0-AD> drivers were
disabled during T2-T3 of MR in expectation of
the addressed memory device driving the AD0-
AD7 lines, the drivers are not disabled for MW.
This is because the CPU must provide the data
to be written into the addressed memory loca-
tion. The data is placed on AD0-AD> at the start
of T2. The WR signal is also lowered at this time
to enable the writing of the addressed memory
device. During T2, the READY line is checked to
see if a Twq(-r state is required. If READY is low,
Tw>(q states are i n serted u n ti l R EADY goes
high. During T3, the WR line is raised, disabling
the addressed memory device and thereby ter-
minating the WRITE operation. The contents of
the address and data lines are not changed un-
til the next T,, which directly follows.
Note t h a t t he d a t a o n A D0 - A D 7 i s n o t
guaranteed to be stable before the falling edge
TI /A IT
IO/M 0 I MWI ORI (IOWI, SI . 0, Sp
Ap A/ Dp -01
Page B.14
FUNCTIONAL DESCRIPTION
of WR. The ADo-AD7 lines are guaranteed to be
stable both before and after the rising edge of
WR.
I/O WRITE (IOW):
A s Figure 2-16 shows, the t i m ing fo r a n I / O
WRITE (IOW) machine cycle is the same as an
MW machine cycle except that IO/M = 0 during
the MW cycle and IO/M = during the IOW cycle.
As with the IOR cycle discussed previously, the
address used in an IOW cycle is th e I/O port
number which is d u plicated on both the high
and low bytes of the address bus. In the case of
IOW, the port number comes from the second
byte of an OUTPUT instruction as the instruc-
tion is executed.
2.3.4 I n terrupt Acknowledge (INA) Timing
Figures 2-17 and 2-18 (a continuation of 2-17)
depict the course of a c t ion the CPU takes in
response to a high level on the INTR line if the
INTE FF (interrupt enable flip-flop) has been set
M2 (MR)
ID/M, SI, Sp (0.1,01
AS A)6 (PC. I I H
ADD.ADT Dp DT Dp DT (CALL)
RD
WR
FIGURE 2-17 INTERRUPT ACKNO W L E D G E MA C H INE CYCLES
(WITH CALL INSTRUCTION IN RESPONSE TO INTR)
by the El instruction. The status of the TRAP
and RST pins as well as INTR is sampled during
the second clock cycle before M ( • T(. If INTR
was the only valid interrupt and if INTE FF is
set, then the CPU will reset INTE FF and then
enter a n I N T ERRUPT ACKNOWLEDGE (INA)
machine cycle. The INA cycle is identical to an
OF cycle with two exceptions. INTA is sent out
i nstead of R D . A l so , I O/ M = 1 d u r i n g I N A ,
whereas IO/M = 0 f o r O F . A lthough the con-
tents of the program counter are sent out on the
address lines, the address lines can be ignored.
When INTA is sent out, the external interrupt
logic must provide the opcode of an instruction
to execute. The opcode is placed on the data
bus and read in by the processor. If the opcode
is the first byte of a m u l t iple-byte instruction,
additional INTA pulses will be provided by the
8 085A t o c l o c k i n t h e re m a i n i n g b y t e s .
RESTART and CALL instructions are the most
MI (INA) MT (INAI
TS Tl Tp
Dp.D) (82)

FUNCTIONAL DESCRIPTION
logical choices, since they both force the pro-
cessor to p us h th e c o n tents o f t h e p r ogram
counter onto the stack before jumping to a new
location. In Figure 2-17 it i s a s s umed that a
CALL opcode is sent to the CPU during Mi. The
CALL opcode could have been placed there by a
device like th e 8 259 p rogrammable interrupt
controller.
After receiving the opcode, the processor then
decodes it and determines, in this case, that the
CALL instruction requires two more bytes. The
CPU therefore performs a second INA cycle (M2)
to access the second byte of t h e i n struction
from the 8259. The timing of this cycle is iden-
tical to M i , e x c ept t ha t i t h a s o n l y t h ree T
states. M2 is followed by another INA cycle (M3)
to access the third byte of the CALL instruction
from the 8259.
M3 IINA I
T2 13 TI
INTA
IO/M,SI , 50
AB A)5
DDT
AOO AOT Dp.DT (B3) (Bp 1)C
RD
FIGURE 2-18 INTERRUPT ACKNO W L E D G E MA C H INE CYCLES
(WITH CALL INSTRUCTION IN RESPONSE TO INTR)
Page B.15
Now that the CPU has accessed the entire in-
struction used to acknowledge the interrupt, it
will execute that instruction. Note that any in-
struction could be used (except El or Dl, the in-
structions which enable or disable interrupts),
but the RESTART and CALL instructions are the
most logical choices. Also notice that the CPU
i nhibited t h e i n c r e menting o f t h e p r o g r a m
counter (PC) during the t h ree INA c y cles, so
that the correct PC value can be pushed onto
the stack during M4 and M5.
During M4 and M5, the CPU performs MEMORY
WRITE machine cycles to write the upper and
then lower bytes of the PC onto the top of the
stack. The CPU then places the two bytes ac-
cessed in M2 and Mz into the lower and upper
bytes of the PC. This has the effect of jumping
the execution of th e p r ogram to th e l o cation
specified by the CALL instruction.
MA IMWI t M5 (MW) MI (OFI
T2
(0,0,)I (0,0,1) IO,I,H
PCH(B 3)
DpD) (PCHI (Bp 2)C Dp'DT (PCL) B2
Page B.16
FUNCTIONAL DESCRIPTION
2.3.5 Bus Idle (Bl) and HALT State
M ost m a c h i n e c y c l e s o f t he 80 8 5 A a r e
associated with either a READ or WRITE opera-
tion. There are two exceptions to this rule. The
first exception takes place during M2 and Mz of
the DAD instruction. The 8085A requires six in-
ternal T states to execute a DA D instruciton,
but it is not desirable to have Mi be ten (four
normal pius six extra) states long. Therefore,
the CPU generates two extra machine cycles
that do not access either the memory or the I/O.
These cycles are referred to as BUS IDLE (Bl)
machine cycles. In the case of DAD, they are
identical to MR cycles except that RD remains
h igh an d A L E i s n o t g e n e rated. N ot e t h a t
READY is ignored during M2 and M3 of DAD.
MI IO P)
T4 TP
I0IM
SI, SO
A (T AI S
AOO AOT
WR
FIGURE 2-19 RST 7.5 BUS IDLE MACHINE CYCLE
The other time when the BUS IDLE machine cy-
cle occurs is during the internal opcode genera-
tion for the RST or TRAP interrupts. Figure 2-19
illustrates the Bl cycle generated in response to
RST 7.5. Since t h i s i n t e rrupt i s r i s i ng-edge-
triggered, it sets an internal latch; that latch is
sampled at the falling edge of the next to the
last T-state of the previous instruction. At this
point the CPU must generate its own internal
RESTART instruction which will (in subsequent
machine cycles) cause the processor to push
the program counter on the stack and to vector
to location 3CH. To do this, it executes an OF
machine cycle without issuing RD, generating
t he RESTART opcode i n stead. After M , , t h e
C PU co n t i n ues e x e c u t io n n o r m a ll y i n a l l
respects except that th e s t ate of t h e R EADY
line is ignored during the Bl cycle.
MI (Bl) MZ IMWI
TT
ISP 1)L PCH

FUNCTIONAL DESCRIPTION
Figure 2-20 illustrates the Bl cycle generated in
response to RST 7.5 when a HALT instruction
has just been executed and the CPU is in the
TH«q state, with it s v a rious signals f loating.
There are only two ways the processor can com-
pletely exit the THq)r state, as shown in Figure
2-11. The first way is for RESET to occur, which
always forces the 8085A to TREsE-r. The second
way to exit T„~zz permanently is for a valid in-
terrupt to occur, which will cause the CPU to
disable further interrupts by resetting INTE FF,
and to then proceed to M< • T, of t he next in-
struction. When the HOLD input is a c t ivated,
the CPU will exit THq) z for the duration of THo) p
and then return to THqzq.
M I (OCI MT(HALT)
THALT THALT
IOIM
AB. A15
AOO AO)
FIGURE 2-20 HALT STATE AND BUS IDLE MACHINE CYCLE
RST 7.5 TERMINATES THg) g STATE
page B.17
In Figure 2-20 the RST 7.5 line is pulsed during
THqqq. Since RST 7.5 is a rising-edge-triggered
interrupt, it will set an i nternal latch which is
sampled during CLK = "1" of every THqq-r state
( as well as d u r ing C L K = " 1" two T s t a t e s
before any M, • T>.) The fact that the latched in-
t errupt was high (assuming that INTE FF = 1
and the RST 7.5 mask =0) will force the CPU to
exit the TH~qq state at the end of the next CLK
period, and to enter M, • T~.
T his completes our analysis of t h e t i m ing of
each of the seven types of machine cycles.
MI (BI) MB (MW)
TS Tp TS
(SP IIH
(SP 1)L
Page B.18
FUNCTIONAL DESCRIPTION
2.3.6 H O LD and HALT States
The 8085A uses the THpLp state to momentarily
cease executing machine cycles, allowing ex-
ternal devices to gain co ntrol of th e bus and
peform DMA cycles. The processor internally
latches the state of the HOLD line and the un-
masked interrupts during CLK = "1" of every
THALT state. If the internal latched HOLD signal
is high during CLK = "1" of any THAiT state, the
C PU will e xi t T HTT,LT a nd enter THpip o n t h e
following CLK = "1". As shown in Figure 2-21
this will occur even if a valid interrupt occurs
simultaneously with the HOLD signal.
The state of the HOLD and the unmasked inter-
rupt lines is latched internally during CLK = 1
o f each THpLp state as w el l a s d u r ing T „ « T
states. If the i nternal latched HOLD signal is
low during CLK = 1, the CPU will exit THQLp and
enter THALT on the following CLK = 1 .
SIGNALS TT Toooo ETYT
INTERRUPT
SIGNIFIES THAT TY TI MAY TAKE PLACE INSIDE THE ODBSAEVEN WHILE THE PROCESSOR IS IN A HOLD STATE
FIGURE 2-21 HOLD VS INTERRUPT — NON HALT
The 8085A accepts the first unmasked, enabled
interrupt s a m p l ed; t h e r eafter, a l l i n t e r r u pt
s ampling is i n h ibited. The i n terrupt t hus a c -
c epted will i n evitably be e x ecuted w hen t h e
CPU exits the HOLD state, even at the expense
o f h o l d i n g o f f h i g h e r - p r i o r it y i n t e r r u p t s
(including TRAP). (See Figure 2-22.)
When the CPU is not in THpiT or THpLp, it inter-
nally latches the HOLD line only during CLK =
1 of the last state before T3 (T2 or Twqrr) and dur-
ing CLK = 1 of the last state before T5 (T4 of a
six T-state M,). If t h e i n t ernal latched HOLD
signal is high during the next CLK = 1, the CPU
will enter THpLp after the following clock. When
the CPU is not in THALT or THpLp, it will internally
latch the state of the unmasked interupts only
during CLK of the next to the last state before
each M, • Ti.
TOOLS
OYT THOLO TTOT THOLO THOLO
INTERRUPTS SAMPLED
HERE REGARDLESS
OF HOLD
START OF INTERRUPT
CYCLE DELAYED
BY HOLD
 Page B.19

FUNCTIONAL DESCRIPTION

THALr THALT THALI THOLc TnoLB

LOW PRIORITY
INTERRUPT CYCLE
HOLD

EXITS HALT
IMMEDIATELY AFTER
HOLD REMOVED

INTERRUPT ACCEPTED HERE CAUSES SAMPLING TO BE INHIBITED-

I • HI BITING HIGHER INTERRUPTS IEVEN TRAPI
LOW PRIORITY
INTERRUPT)S)

HIGH PRIORITY
INTERRUPT(S)

FIGURE 2-22 8085A HOLD VS INTERRUPTS — HALT MODE

2.3.7 P o wer On and RESET IN CPU will enter M, • T< for the next T state. Note
The 8085A employs a special internal circuit to that the various signals and buses are floated in
increase its speed. This circuit, which is called T REsET as well a s T ~aj T and T~o) o. For t h i s
a substrate bias generator, creates a negative r eason, i t i s de s i r a bl e t o p r o v i d e p u l l - u p
v oltage which i s u sed t o n e g atively bias t h e resistors fo r th e m a i n c o n t r ol s i g n als ( p ar-
substrate. The circuit employs an oscillator and ticularly WR).
a charge pump which require a certain amount Specifically, the RREET I I s i g nal causes the
of time a f te r P O WER O N t o s t a b i lize. (See following actions:
Figure 2-23.)
RESETS SETS
Taking this circuit into account, the 8085A is
not guaranteed to work until 10 ms a f ter Vcc P ROGRAM CO U N T E R RST 5.5 MASK
reaches 4.75V. For this reason, it is suggested INSTRUCTION REGISTER RST 6.5 MASK
that RESET IN be kept low during this period. INTE FF RST 7.5 MASK
Note that the 10 ms period does not include the RST 7.5 FF
time it takes for the power supply to reach its TRAP FF
4.75V level — w h ic h ma y b e m i l l iseconds in SOD FF
some systems. A simple RC network (Figure 3-6) MACHINE STATE FF's
can satisfy this requirement. MACHINE CYCLE FF's
INTERNALLY LATCHED
The RESET IN line is latched every CLK = 1 . FF's for HOLD, INTR,
This latched signal is recognized by the CPU and READY
during CLK = 1 of the next T state. (See Figure
2-24.) If it is low, the CPU will issue RESET OUT R~EET IN does not explicitly change the con.
and enter Tz<) T for the next T state. RESET IN tents of the BGSSA registers (A, B, C O, E, H, L)
should be kept low for a minimum of three clock and the condition flags, but due to RESET IN oc.
periods to ensure proper synchronization of the curring at a random time during instruction ex-
CPU. When the ARSE~I s i g n a l goes high, the ecution, the results are indeterminate.
Page B.20

FUNCTIONAL DESCRIPTION

M, (OF)

TAEE(I

V 0

VAA (INTERNAL)

FIGURE 2-23 POWER-ON TIMING

M) (OF) 81) (OF I Following RESET, the 8085A will start executing
22 TAEEEI TAE)E TAE)EE TEE)I T,
instructions a t l o c a t ion 0 w i t h t h e i n t e rrupt
system disabled, as shown in Figure 2-24.

Figure 2-24also shows READ and WRITE opera-

RESE'T IN
tions being terminated by a RESET signal. Note
that a RESET may prematurely terminate any
READ or WRITE operation in process when the
RESET OUT
RESET occurs.

IO/M
AAIE

READ MODE DA TA 2.3.8 SID and SOD Signals:

AD01
Figure 2-25 shows the timing relationship of the
RD, SID and SOD signals to the RIM and SIM instruc-
tions. The 8085A has the ability to read the SID
line into the accumulator bit 7 using RIM instruc-
tions. The state of the SID line is latched inter-
nally during T3 • CLK = 0 of the RIM instruction.
Following this, the state of th e i nterrupt pins
WR
and masks are also transferred directly to the
accumulator.
RD

The 8085A can set the SOD flip-flop from bit 7 of

+NOTE THAT FROM T) TO H ERE ) H E 8088'I BUS IS IN THE INPUT MODE AND
IT IS FLOAT) NG T H E DEVICE DRIVING THE BUS WILL CONTINUE TO DRIVE
THE BUS UNT IL RD GOES HIGH
FIGURE 2-24 RESET IN TIMING
the accumulator using the SIM instruction. (See
Figure 2-26.) The data is transferred from the ac-
cumulator b! t 7 to SOD during M, • Tq • CLK = 0
of the instruction following SIM, assuming that
accumulator bit 6 is a 1. Accumulator bit 6 is a
"serial output enable" bit.
 Page B.21

FUNCTIONAL DESCRIPTION

MI IOF) MI (OF) MI IOF)

ACCUMULATOR
(8)T 7)

8 15

OUT

ADO-AOT

RD

FIGURE 2.25 RELATIONSHIP OF SID AND SOD SIGNALS TO RIM AND SIM INSTRUCTIONS

EFFECT OF RIM INSTRUCTION EFFECT OF SIM INSTRUCTION

S)D SOD

8085A 8085A
F.F.

ACCUMULATOR ACCUMULATOR

FIGURE 2.26 EFFECT OF RIM AND SIM INSTRUCTIONS

2.4 C O M PARISON OF MCS.80 AND MCS-85

SYSTEM BUSES
This section compares the MCS-80 bus with the
MCS-85 bus. Figure 2-28 details the signals and
general timing o f t h e t w o b u s es; th e t i m i ng
diagrams are drawn to the same scale (8080A
clock cycle = 480 ns and 8085A clock cycle =
320 ns) to facilitate comparison.
page B.22

FUNCTIONAL DESCRIPTION

MCS-80™ System Bus MCS-85™ System Bus

The MCS-80 bus isterminated on one end by the
CPU-GROUP (consisting o f t h e 8 0 80A, 8224,
8228) and o n t h e o t h e r e n d b y t h e v a r ious
memory and I/O circuits. The following figure
shows the major signals of the MCS-80 bus.
The MCS-85 bus isterminated on one end by the
8085A and theother end by various memory and
I/O devices. The MCS-85 bus may be optionally
de-multiplexed with an 8212 eight bit latch to
provide an M C S-80 type b us . Th e f o l l owing
figure shows the major signals of the MCS-85
bus.

ALE
INTA 18 4 18 I 0 P2 I 0 N A L I
8712 Ae A
HOLD 8080A HOLD
4'8
HLDA 8224 HLDA
8228 7 Ae Ale

READY READY 8 ADe ADI

RESET R ISE T O I RD TVR
VEII R V E 1 1H IO'M ALE
2 TTLI
4 I 0 R I O'4

FIGURE 2-27 COMPARISON OF SYSTEM BUSES

MCS-80™ System Bus MCS-85™ System Bus

SIG NAL(S) FUNCTION
Ap-Ais The 16 lines of the address
bus identify a memory or I/O
location for a data transfer
operation.
Dp-D7 The 8 lines of the data bus
a re used f o r t h e p a r a l l e l
t ransfer o f d a t a b e t w e e n
two devices.
MEMR, MEMW, T hese f i v e c o n t r o l l i n e s
IOR, IOW, INTA (MEMORY READ, MEMORY
WRITE, I/O READ, I/O WRITE,
and INTERRUPT ACKNOWL-
EDGE) identify the type and
timing o f a d a t a t r a n s f er
operation.
READY, RESET, These signals are used for
HOLD, HLDA the synchronization of slow
t)2 (TTL), INT
E speed mem ories, system
reset, DMA, sytem t i m i ng,
and CPU interrupt.
FIGURE 2-28 COMPARISON OF SYSTEM BUSES
SIG NAL(S) FUNCTION
As-Ais T hese are t h e h i g h o r d e r
eight bit s o f t h e a d d r ess,
and are used t o i d e ntify a
memory or I/O location for a
data transfer cycle.
ADp-AD7 T hese eight l i ne s s e rve a
d ual f u n ct ion. D u r ing t h e
beginning of a data transfer
operation, these lines carry
t he low order eight bits o f
the address bus. During the
r emainder o f t he c y c l e ,
these lines are used for the
parallel transfer of data be-
tween two devices.
RD, WR, INTA T hese signals i d entify t h e
t ype and t i m ing o f a d a t a
transfer cycle.
IO/M The IIOIMEMOIMV line iden-
tifies a data transfer as be-
ing in the I/O address space
or th e m e m or y a d d r e ss
space.
ALE ADDRESS LATCH ENABLE
enables the latching of t he
Ap-A7 signals.
READY, RESET These signals are used for
OUT, HOLD, the synchronization of slow
HLDA, CLK, INTR speed mem ories, system
reset, DMA, system t i m ing
and CPU interrupt.
 page 8.23

FUNCTIONAL DESCRIPTION

MCS-80™ System Bus forREAD CYCLE MCS.85™ System Bus forREAD CYCLE
The basic timing of the MCS-80 BUS for a READ The basic timing of the MCS-85 BUS for a READ
CYCLE is as follows: CYCLE is as follows:

A A is, 10/M

Oi Q7
(OPTIONALLY
Ao Ais Ai LATCHED
SIGNALS)

Qs 04 08 OUT 04 IN 07 OUT

DBo DBT - - AD, D,- —

I
Qi
A, , ~
4
~
Os
DO,
C
07 (
ALE 07
MEMR, IOR o INTA Os

RD o INTA Qs 08

The MCS-80 first presents the address Qia n d
shortly thereafter th e c o n t rol s i g nal Q2. The
data bus, which wa s i n t h e h i g h i m pedance
state, is driven by the selected device Q3. The
selected device eventually presents the valid
data to the processor Q4. The processor raises
the control signal Qs, which causes the select-
ed device to put the data bus in the high impe-
dance stateQs. The p rocessor then c hanges
the address' for t he start o f t h e n ex t d a t a
transfer.
At the beginning of the READ cycle, the 8085A
sends out al l 1 6 b i t s o f a d d r essQ~. This is
f ollowed b y A L EQ 2which c a uses t h e l o w e r
eight bits of address to be latched in either the
8155/56, 8355, 8755A, or in an external 8212. RD
is then dropped Q3by the 8085A. The data bus is
then tri-stated by the 8085A in preparation for
t he selected d evice d r iving t h e b u s Q4; t h e
selected device will continue to drive the bus
with valid data Qs, until RD is raised Qsby the
8085A. At the end of the READ CYCLE Q7, the
address and data lines are changed in prepara-
tion for the next cycle.

MCS-80™ System Bus for WRITE CYCLE MCS.85™ System Bus for WRITE CYCLE
T he basic t i m ing o f t h e M C S-80 BUS fo r a T he basic t i m ing o f t h e M C S-85 BUS fo r a
WRITE CYCLE is as follows: WRITE CYCLE is as follows:

AS-
A IS, IO/M

I O8T I O NA L L Y
Ao A,s A AI LA T C H E D
SIGNA LSt
07 Qs QS
OBo 087- A DS.ADT — — Ao.A T Do OT

Qi Oz
MEMW o IOW Q7 $/8238) 0 Os

The MCS-80 first presents the address Qi, t he n
e nables t h e d a t a b u s d r i v e rQ2, and la te r
p resents the d a t a Q s. Shortly t hereafter, th e
MCS-80 drops the control signal Q4 for an inter-
val of time and then raises the signal Qs. The
M CS-80 t h e n c h a n g e s t h e a d d r e s sQs in
preparation for the next data transfer. The ad -
vance write signal of the 8238 is also shown Q7.
FIGURE 2-28 (Continued) COMPARISON OF SYSTEM BUSES
The ti m i n g of the WRITE CYCLE is identical to
t he MC S -85 READ CYCLE with the exception of
t he ADo - ADq lines. A t t h e - b e g i nning o f t h e
cyc le QT , the low order eight bits of address are
o n A Do - AD7. After ALE drops, the eight bits of
d at a Qu are put on AD0 AD7. They are removedQs
a t th e e n d of the WRITE CYCLE, in anticipation
o f th e n ext data transfer.
Page B.24
FUNCTIONAL DESCRIPTION
The following observations of t h e t w o b u ses
can be made:
1. The access t i mes f ro m a d dress leaving
the processor to returning data are almost
i dentical, e ve n t h o u g h t h e 8 0 8 5 A i s
operating 50% faster than the 8080.
2. With the addition of an 8212 latch to the
8 085A, th e b a s i c t i m i ng s o f t h e tw o
systems are very similar.
3. The 8085A ha s m o r e t i m e f o r a d d ress
setup to RR5 than the 8080.
4. The MCS-80 has a wider RD signal,but a
narrower WR signal than the 8085A.
5. The MCS-80 provides stable data setup to
t he leading an d t r a i ling e d ges o f W R ,
while the 8085 provides stable data setup
to only the trailing edge of WR.
6. The MCS-80 control signals have different
widths and occur at different points in the
machine cycle, while the 8085A control
signals have identical timing.
7. While not shown on the chart, the MCS-80
data and address hold times are adversely
affected by t h e p r o cessor preparing to
enter the HOLD state. The 8085A has iden-
tical timing regardless of entering HOLD.
8. Also not shown on the c hart is the fact
that all output signals of the 8085A have
— 400qa of source current and 2.0 ma of
sink current. The 8085A also ha s i n p ut
voltage levels of V~z — 0.8V and V~H — 2.0V.
CONCLUSION:
The preceding discussion has c l early shown
that the MCS-85 bus satisfies the two restric-
tions of COMPATIBILITY and SPEED. It is com-
patible because it requires only an 8212 latch to
generate an MCS-8~0t e h u a. tf the tour control
s ignals M E MR , M E MW , I l ) R a n d I l ) W a r e
desired, they can be generated from RD, WR,
and IO/9 w it h a d e coder or a few g ates. The
MCS-85 bus is also fast. While running at 3MHz,
the 8085A generates better timing signals than
the MCS-80 does at 2 M Hz. Furthermore, the
m ultiplexed bu s s t r u c ture d o esn't s l o w t h e
8085A down, because it i s u s ing th e i nternal
states to overlap the fetch and execution por-
tions of different machine cycles. Finally, the
MCS-85 can be slowed down or sped up con-
siderably, w h i l e s t i l l p r o v i d in g r e a s o nable
timing.
TO USE. The RD, KR, and ~IN A control signals
all have identical timing, which isn't affected by
the CPU preparing to enter the HOLD state. Fur-
thermore, theaddress and data bus have good
setup and hold t i mes r e lative to t h e c o n t rol
signals. The voltage and current levels for the
interface signals will all drive buses of up to 40
MOS devices, or 1 schottky TTL device.
The MCS-85 system bus is also EFFICIENT. Effi-
ciency is the reason that th e l o wer eight ad-
dress lines are multiplexed with the data bus.
Every chip that needs to use both A0-A7 and D0-
D> saves 7 pins (the eighth pin is used for ALE)
on the interface to the processor. That means
that 7 more pins per part are available to either
add features to th e p art o r t o u s e a s m a l ler
p ackage i n s o m e c a s es . I n t h e t h r e e c h i p
s ystem shown i n F i g ure 3-6, the us e o f t h e
MCS-85 bus saves 3 x 7 = 2 1 p i ns, which are
used for extra I/O and interrupt lines. A further
advantage of th e M CS-85 bus is a p parent in
Figure 3-7, which shows a printed circuit layout
of the circuit in Figure 3-6. The reduced number
of pins and the f act t hat c o m patible pinouts
were used, provides for an extremely compact,
simple, and efficient printed circuit. Notice that
great care was t a ken when the pinouts were
assigned to ensure that the signals would flow
easily from chip to chip to chip.
 page C.1

APPENDIX C
8085 Instruction Set

The following pages are reprinted with

the permission of Intel Corporation.
page C.2

8085A INSTRUCTION SET

5.1 WHAT THE INSTRUCTION SET IS DDD,SSS The bi t p a t t er n d e s i gnating

A computer, no matter how sophisticated, can one of th e r egisters A,B,C,D,
do only what it is instructed to do. A program is E ,H,L ( D D D = dest i n a t i o n ,
SSS = source):
a sequence of i n structions, each of w h ich is
r ecognized by the computer and causes it t o D DD or REGIS T E R
perform an operation. Once a program is placed SSS NAME
i n memory space t ha t i s a c c e ssible to y o u r 111
CPU, you may run that same sequence of in- A
8
000
structions as o f ten as yo u w is h t o s o lve the 001
same problem or to do the same function. The 010 D
C
E
set of instructions to which the 8085A CPU will 011
respond is permanently fixed in the design of 100
the chip. 101 H
L
E ach computer instruction allows you t o i n i - r'p One of the register pairs:
tiate the performance of a s pecific operation.
The 8085A implements a group of instructions 8 represents the B,C pair with
that move data between registers, between a 8 as t h e h i g h-order register
register and memory, and between a register a nd C a s t h e lo w - o r d e r
and an I/O port. It also has arithmetic and logic register;
instructions, c o n d it ional a n d un c o n d itional D represents the D,E pair with
b ranch instructions, and m a c hine control i n - D as th e h i g h-order register
structions. The CPU recognizes these instruc- a nd E a s t h e lo w-o r d e r
tions only when they are coded in binary form. register;
H represents the H,L pair with
H as t h e h i g h-order register
5.2 SYMBOLS AND ABBREVIATIONS: a nd L a s t h e l o w -o r d e r
register;
The following symbols and a bbreviations are
u sed i n t h e s u b s equent d e s cription o f t h e SP represents the 16-bit stack
8085A instructions: pointer register.
RP The bi t p a t t er n d e s ignating
SYMBOLS MEANING
o ne o f t he reg i s t e r p a i r s
accumulator Register A B,D,H,SP:
addr 16-bit address quantity REGISTER
RP
data 8-bit quantity PAIR
00 8-C
data 16 16-bit data quantity
01 D-E
byte 2 The second byte of the instruc- 10 H-L
tion 11 SP
byte 3 The third byte of th e i nstruc- rh The first (high-order) register
tion of a designated register pair.
port 8-bit address of an I/O device
T he s e c o n d ( low-o r d e r )
r,r1,r2 One of t h e r e g i sters A , B,C, r egiste r o f a d e s i g n a t e d
D,E,H,L register pair.

THE INSTRUCTION SET
PC 16-bi t pr og r a m c o un t e r
r egister (PCH a n d P C L a r e
used to refer to the high-order
and low-order 8 b i t s r e s pec-
tively).
SP 16-bit st ac k p o i n ter r e gister
(SPH and SPL are used to refer
to the high-order and low-order
8 bits respectively).
'm Bit m of the register r (bits are
number 7 through 0 from left
to right).
LABEL 16-bit address of subroutine.
The condition flags:
Zero
S
Z
p physical memory. That location is described by one of
Sign
Parity
CY Carry
AC Auxiliary Carry
() The contents of t h e m e m ory
location or registers enclosed
in the parentheses.
"Is transferred to"
Logical AND
Exclusive OR
Inclusive OR
Addition
Two's complement subtraction
Multiplication
"Is exchanged with"
The one's complement (e.g., (A))
n The restart number 0 through 7
NNN The binary representation 000
through 111 for restart number
0 through 7 respectively.
The instruction set encyclopedia is a detailed
description of the 8085A instruction set. Each
instruction is described in the following man-
ner:
1. The MCS-85 macro assembler format, con-
s isting o f t h e i n s t r u ction m n e m onic a n d
operand fields, is printed in BOLDFACEon
the first line.
2. The name of th e i n struction is e nclosed in
parentheses following the mnemonic.
3. The next lines contain a symbolic description
of what the instruction does.
4. This is followed by a narrative description of
the operation of the instruction.
page C.3
5 . The boxes describe the b i nary codes t h a t
comprise the machine instruction.
6. The last four lines contain information about
the execution of the instruction. The number
of machine cycles and states required to ex-
ecute the instruction are listed first. If the in-
struction has two possible execution times,
a s in a c o n d i t ional j u mp , b ot h t i me s a r e
listed, separated by a s l ash. Next, data ad-
dressing modes are listed if applicable. The
last line lists any of the five flags that are af-
fected by the execution of the instruction.
5 .3 INSTRUCTION AND DATA FORMA T S
Memory used in the MCS-85 system is organ-
ized in 8-bit bytes. Each byte has a unique location in
a sequence of16bit binary addresses. The 8085A can
address up to 64K (K = 1024, or 210; hence, 64K
represents the decimal number 65,536) bytes of
memory, which may consist of both random-access,
read-write memory (RAM) and read-only memory
(ROM), which is also random-access.
Data in the 8085A is stored in the form of 8-bit
binary integers:
DATA WORD
D 7 Ds D 5 D 4 D 3 D 2 D ] DQ
MSB LSB
When a register or data word contains a binary
number, it is necessary to establish the order in which
the bits of the number are written. In the Intel 8085A,
BIT 0 is referred to as the Least Significant Bit (LSB),
and BIT 7 (of an 8-bit number) is referred to as the
Most Significant Bit (MSB).
An 8085A program instruction may be one, two or
three bytes in length. Multiple-byte instructions must
be stored in successive memory locations; the address
of the first byte is always used as the address of the in-
struction. The exact instruction format will depend
on the particular operation to be executed.
Single Byte Instructions
D7 DQ Op Code
Two-Byte Inst ructjons
Byte
DQ Op Code
One
Byte Data or
Two Address
Page C.4
THE INSTRUCTION SET
Three-Byte Instructions
Byte
One Dp O p Code
Byte
Two D> D ata
or
Byte Address
Dp
Three
5.4 A D DRESSING MODES:
Often the data that is to be operated on is stored in
memory. When multi-byte numeric data is used, the
data, like instructions, is stored in successive memory
locations, with the least significant byte first, follow-
ed by increasingly significant bytes. The 8085A has
four different modes for addressing data stored in
memory or in registers:
• Direct — Bytes 2 and 3 of the instruction
contain the exact memory ad-
dress of the data item (the low-
order bits of the address are in
b yte 2, th e h i g h-order bits i n
byte 3).
• Register — The instruction specifies the
register or register pair in which
the data is located.
• Register I n d i r ect — Th e i n s t r uction
specifies a register pair which
contains the m e mory address
where the data is l o cated (the
high-order bits o f t h e a d dress
a re in the f i rst r egister of t h e
p air the l o w-order bits i n t h e
second).
• Immediate — T he i n s truction contains
the data itself. This is either an
8-bit quantity or a 16-bit quanti-
ty (least significant byte f i rst,
most significant byte second).
Unless directed by a n i n t errupt or b ranch in-
s titution, th e e x e c ution o f i n s t r uctions p r o -
c eeds t h r o u g h c o n s e c u t i v el y i n c r e a s i n g
m emory locations. A b r a nc h i n s truction c a n
specify the address of the next instruction to be
executed in one of two ways:
• Direct — The branch instruction contains
the address of the next instruc-
tion to be executed. (Except for
the ' RST' instruction, b yt e 2
contains the low-order address
and byte 3 t h e h i g h-order ad-
dress.)
• Register indirect — The branch instruc-
tion i n d icates a r e g i s t er-pair
which contains the address of
t he next i n struction t o b e e x -
ecuted. (The high-order bits of
t he address a r e i n t h e f i r s t
r egister o f t h e p a i r , t h e l o w -
order bits in the second.)
The RST instruction is a special one-byte call in-
s truction ( usually u se d d u r in g i n t e rrupt s e -
quences). RST includes a t h ree-bit field; pro-
gram control is t r ansferred to th e i n struction
whose address is eight times the contents of
this three-bit field.
5.5 C O NDITION FLAGS.
There are five condition flags associated with
the execution o f i n s t r uctions o n t h e 8 0 85A.
They are Zero, Sign, Parity, Carry, and Auxiliary
Carry. Each is represented by a 1-bit register (or
flip-flop) in the CPU. A flag is set by forcing the
bit to 1; it is reset by forcing the bit to 0.
Unless indicated otherwise, when an i n struc-
tion affects a flag, it affects it in the following
manner:
Zero: If t he re s u l t o f a n i n s t r uction
has the value 0, this flag is set;
otherwise it is reset.
Sign: If the m o s t significant bit of the
result of the operation has the
value 1, this flag is set; other-
wise it is reset.
Parity If the modulo 2 sum of the bits
of the result of the operation is
0, (i.e., if th e r e sult ha s e v en
parity), this f lag i s s e t ; o t her-
wise it is reset (i.e., if the result
has odd parity).
Carry: If t he i n s t r u ction resulted in a
carry (from addition), or a bor-
row (from subtraction or a com-
parison) out o f t h e h i g h-order
bit, this flag is set; otherwise it
is reset.
Auxiliary Carry: If the instruction caused a
carry out of bit 3 and into bit 4
of the resulting value, the aux-
iliary carry is set; otherwise it is
reset. This flag i s a f f ected by
single-precision additions, sub-
tractions, i n c r ements, d e c r e-
ments, comparisons, and logi-
cal operations, but is principal-
ly used with additions and i n-
c rements p r e c eding a DA A
(Decimal Adjust A c c u mulator)
instruction.
 Page C.5

THE INSTRUCTION SET

5.6 INSTRUCTION SET ENCYCLOPEDIA MOV r, M (Move from memory)

In the e n s uing d o zen p a g es, t h e c o m p l ete (r) — ((H) (L))
8085A instruction set is described, grouped in The content of the memory location, whose
order under five different functional headings, address is in registers H and L, is moved to
as follows: register r.

1. Data Transfer Group — Moves data be- 0 1 D D D 1 1 0

t ween r e g isters o r b e t w ee n m e m o ry
locations and registers. Includes moves, Cycles: 2
l oads, s t o r es , a n d ex c h a nges. ( S ee States: 7
below.) Addressing: reg . i n d i rect
2. Arithmetic Group — Adds, subtracts, in- Flags: no ne
c rements , o r de c rem ents d a t a i n
registers or memory. (See page 5-13.) MOV M, r (Move to memory)
3. Logic Group — ANDs, ORs, XORs, com- ((H)) (L)) — (r)
T he content of register r is moved to t h e
pares, rotates, or complements data in memory l o c ation w h o s e a d d r ess i s i n
r egisters o r b e t w ee n m e m or y a n d a
registers H and L.
register. (See page 5-16.)
4. Branch Group — Initiates conditional or
unconditional jumps, calls, returns, and 0 1 1 1 0 S S S
restarts. (See page 5-20.)
5. Stack, I/O, and Machine Control Group Cycles: 2
— Includes instructions for maintaining States: 7
t he s t a ck , r e a ding f r o m i n p u t p o r t s , Addressing: reg. indirect
w riting t o o u t p u t p o r t s , s e t t in g a n d Flags: none
reading interrupt masks, and setting and
clearing flags. (See page 5-22.) MVI r, data (Mo ve I m m e diate)
(r) — (byte 2)
The content of byte 2 of the instruction is
The formats d e s c ribed i n t h e e n c y c lopedia moved to register r.
reflect th e a s sembly language processed by
Intel-supplied assembler, used with the intellec® 0 0 D D D 1 1 0
development systems.
data

5.6.1 Data Transfer Group Cycles: 2

This group of instructions transfers data to and States: 7
from registers and memory. Condition flags are Addressing: immediate
not affected by any instruction in this group. Flags: none

MVI M, data (Move to memory immediate)

MOV r1, r2 (Move Register) ((H) (L)) — (byte 2)
(r1) — (r2) The content of byte 2 of the instruction is
T he content o f r e g i ster r 2 i s m o ve d t o moved to the memory location whose ad-
register r1. dress is in registers H and L.

0 1 D D D S S S 0 0 1 1 0 1 1 0

Cycles: 1 data
States: 4 (8085), 5 (8080)
Addressing: register Cycles: 3
Flags: none
States: 10
Addressing: immed./reg. indirect
Flags: none
Page C.6

THE INSTRUCTION SET

LXI rp, data 16 (Load register pair immediate)
(rh) — (byte 3),
(rl) — (byte 2)
Byte 3 of the instruction is moved into the
high-order register (rh) of the register pair
rp. Byte 2 of the instruction is moved into
the low-order register (rl) of the register pair
rp.
LHLD addr (Load H and L direct)
(L)-((byte 3)(byte 2))
(H)-((byte 3)(byte 2)+1)
The content of the memory location, whose
address is specified in byte 2 and byte 3 of
the instruction, is moved to register L. The
content of the memory location at the suc-
ceeding address is moved to register H.

0 0 R P 0 0 0 1 0 0 1 0 1 0 1 0

low-order data low-order addr

high-order data high-order addr

Cycles: 3 Cycles: 5
States: 10 States: 16
Addressing: immediate A ddressing: d i re c t
Flags: none Flags: no ne

LDA addr (Load Accumulator direct) SHLD addr (Store H and L direct)
(A) — ((byte 3)(byte 2)) ((byte 3)(byte 2))-(L)
The content of the memory location, whose ((byte 3)(byte 2)+1)-(H)
address is specified in byte 2 and byte 3 of The content of register L is moved to the
the instruction, is moved to register A. memory l o c a t i o n w ho s e ad d r e s s is
specified in byte 2 and byte 3. The content
0 0 1 1 1 0 1 0 of register H is moved to the succeeding
memory location.
low-order addr 0 0 1 0 0 0 1 0

high-order addr
low-order addr
Cycles: 4
States: 'l3 high-order addr
Addressing: direct
Flags: none Cycles: 5
States: 16
STA addr (Store Accumulator direct) A ddressing: d i re c t
((byte 3)(byte 2)) — (A) Flags: non e
The content of the accumulator is moved to
t he memory l o c ation w h os e a d d ress i s
specified in byte 2 and byte 3 of the instruc- LDAX rp (Load accumulator indirect)
tion. (A) — ((rp))
The content of the memory location, whose
0 0 1 1 0 0 1 0 address is in the register pair rp, is moved
to register A . N o t e : o n l y r e g ister p a i rs
r p = 8 ( r e g isters B a nd C) o r rp = D
low-order addr (registers D and E) may be specified.

high-order addr 0 0 R P 1 0 1 0

Cycles: 4 Cycles: 2
States: 13 States: 7
A ddressing: d i rec t Addressing: reg. indirect
Flags: n on e Flags: none
 Page C.7

THE INSTRUCTION SET

STAX rp (Store accumulator indirect) ADD M (Add memory)

((rp)) — (A)
The content of register A is moved to the
memory location whose address is in the
register pair rp. Note: only register pairs
rp = 8 ( r e g isters B an d C) o r rp = D
(registers D and E) may be specified.
(A) — (A) + ((H)(L))
The content of the memory location whose
a ddress i s c o n t a ined i n t h e H and L
registers is added to the content of the ac-
cumulator. The result is placed in the ac-
cumulator.

0 0 R P 0 0 1 0
1 0 0 0 0 1 1 0
Cycles: 2
States: 7
Addressing: reg . i n d i rect
Flags: no ne Cycles: 2
States: 7
XCHG (Exchange H and L with D and E) Addressing: reg . i n d i rect
(H) — (D) Flags: Z,S, P ,CY,AC
(L) — (E)
The contents of registers H and L are ex-
changed with the contents of registers D ADI data (Add immediate)
and E. (A) — (A) + (byte 2)
The content of the second byte of the in-
struction is added to the content of the ac-
1 1 1 0 1 0 1 1 cumulator. The result is placed in the ac-
e umul at or.
Cycles: 1
States: 4
Addressing: register 1 1 0 0 0 1 1 0
Flags: none

5.6.2 A rithmetic Group

This group of instructions performs arithmetic
operations on data in registers and memory.
Cycles: 2
Unless indicated otherwise, all instructions in States: 7
this group affect the Zero, Sign, Parity, Carry, A ddressing: i mmed i a t e
and Auxiliary Carry flags according to the stan- Flags: Z,S, P ,CY,AC
dard rules.
All subtraction operations are p erformed via
two's complement arithmetic and set the carry ADC r (Add Register with carry)
flag to one to indicate a borrow and clear it to (A) — (A) + (r) + (CY)
indicate no borrow. The content of register r and the content of
the carry bit are added to the content of the
ADD r (Add Register) accumulator. The result is placed in the ac-
(A) — (A) + (r) cumulator.
T he content of r egister r is a dded to t h e
content of the accumulator. The result is
placed in the accumulator.
1 0 0 0 1 S S S
1 0 0 0 0 S S S

Cycles: 1 Cycles: 1
States: 4 States: 4
A ddressing: reg i s t e r A ddressing: reg i s t e r
Flags: Z,S , P ,CY,AC Flags: Z,S, P ,CY,AC
Page C.S

THE INSTRUCTION SET

ADC M (Add memory with carry) SUB M (Subtract memory)

(A) — (A) + ((H) (L)) + (CY)
The content of the memory location whose
a ddress is c o ntained i n t h e H a n d L
registers and the content of the CY flag are
added to the accumulator. The result is
placed in the accumulator.
(A) — (A) — ((H)(L))
The content of the memory location whose
a ddress is c o ntained i n t h e H a n d L
registers is subtracted from the content of
the accumulator. The result is placed in the
accumulator.

1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0

Cycles: 2 Cycles: 2
States: 7 States: 7
Addressing: reg. indirect Addressing: re g . i ndirect
Flags: Z,S,P,CY,AC Flags: Z,S, P ,CY,AC

ACI data (Add immediate with carry) SUI data (Subtract immediate)
(A) — (A) + (byte 2) + (CY) (A) — (A) — (byte 2)
The content of the second byte of the in- The content of the second byte of the in-
struction and the content of the CY flag are struction is subtracted from the content of
added to the contents of the accumulator. the accumulator. The result is placed in the
The result is placed in the accumulator. accumulator.

1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0

data data

Cycles: 2 Cycles: 2
States: 7 States: 7
Addressing: imm e d i ate Addressing: imme d i ate
Flags: Z,S , P ,CY,AC Flags: Z,S , P ,CY,AC

SUB r (Subtract Register) SBB r (Subtract Register with borrow)

(A) — (A) — (r)
The content of register r is subtracted from
the content of the accumulator. The result
is placed in the accumulator.
(A) — (A) — (r) — (CY)
The content of register r and the content of
the CY flag are both subtracted from the
accumulator. The result is placed in the ac-
cumulatorr.

1 0 0 1 0 S S S 1 0 0 1 1 S S S

Cycles: 1 Cycles: 1
States: 4 States: 4
A ddressing: re g i s t er A ddressing: regi s t er
Flags: Z,S , P ,CY,AC Flags: Z,S , P ,CY,AC
 Page C.9

THE INSTRUCTION SET

SBB M (Subtract memory with borrow) INR M (Increment memory)

(A) — (A) — ((H) (L)) — (CY)
The content of the memory location whose
a ddress i s c o n t a ined i n t h e H a nd L
registers and the content of the CY flag are
both subtracted from the accumulator. The
result is placed in the accumulator.
((H) (L) — ((H) (L)) + 1
The content of the memory location whose
a ddress i s c o n t a i ned i n t h e H an d L
registers is incremented by one. Note: All
condition flags except CY are affected.

0 0 1 1 0 1 0 0
1 0 0 1 1 1 1 0

Cycles: 3
Cycles: 2 States: 10
States: 7 Addressing: reg. indirect
Addressing: reg. indirect Flags: Z,S,P,AC
Flags: Z,S,P,CY,AC

SBI data (Subtract immediate with

borrow) DCR r (Decrement Register)
(A) — (A) — (byte 2) — (CY) (r) — (r) — 1
The contents of the second byte of the in- The content of register r is decremented by
struction and the contents of the CY flag one. Note: All co ndition f lags except CY
are both subtracted from the accumulator. are affected.
The result is placed in the accumulator.

0 0 D D D 1 0 1
1 1 0 1 1 1 1 0

data Cycles: 1
States: 4 (80 8 5), 5 (8080)
A ddressing: reg i s t e r
Cycles: 2 Flags: Z,S, P , AC
States: 7
Addressing: immediate
Flags: Z,S,P,CY,AC

DCR M (Decrement memory)

INR r (Increment Register) ((H) (L)) — ((H) (L)) — 1
(r) — (r) + 1 The content of the memory location whose
The content of register r is incremented by address i s c o n t a i ned i n t h e H an d L
one. Note: All condition flags ex c ept CY registers is decremented by one. Note: All
are affected. condition flags except CY are affected.

0 0 D D D 1 0 0 0 0 1 1 0 1 0 1

Cycles: 1 Cycles: 3
States: 4 (80 8 5), 5 (8080) States: 10
A ddressing: reg i s t e r Addressing: re g. i n d i rect
Flags: Z,S, P , AC Flags: Z,S, P , AC
Page C.10

THE INSTRUCTION SET

INX rp (Increment register pair) DAA (Decimal Adjust Accumulator)

(rh) (rl) — (rh) (rl) + 1 The eight-bit number in the accumulator is
T he content of t h e r e gister pair rp i s i n - adjusted to form two four-bit Binary-Coded-
cremented by one. Note: No condition flags Decimal digits by the following process:
are affected. 1. If the value of the lease significant 4 bits
of the accumulator is greater than 9 or if
the AC flag is set, 6 is added to the ac-
0 0 R P 0 0 1 1 cumulator.
2. If the value of the most significant 4 bits
of the accumulator is now greater than 9,
or if the CY flag is set, 6 is added to the
Cycles: 1 most s i g n i ficant 4 b i t s o f the ac -
States: 6 (80 8 5), 5 (8080) e umul at or.
A ddressing: reg i s t e r
Flags: no ne NOTE: All flags are affected.

0 0 1 0 0 1 1 1
DCX rp (Decrement register pair)
(rh) (rl) — (rh) (rl) — 1
T he content o f t h e r e g i s ter p a i r r p i s Cycles: 1
decremented by one. Note: No c ondition States: 4
flags are affected. Flags: Z,S, P ,CY,AC

0 0 R P 1 0 1 1 5.8.3 Logical Group

This group o f i n s t r uctions p e rforms l o g ical
(Boolean) operations on data in registers and
Cycles: 1 memory and on condition flags.
States: 6 (80 8 5), 5 (8080) Unless indicated otherwise, all instructions in
A ddressing: reg i s t e r this group affect the Zero, Sign, Parity, Auxiliary
Flags: no ne Carry, and Carry flags according to th e s t an-
dard rules.

DAD rp (Add register pair to H and L) ANA r (AND Register)

(H) (L) — (H) (L) + (rh) (rl)
The content of the register pair rp is added
to the content of the register pair H and L.
The result is placed in the register pair H
and L. Note: Only the CY flag is affected. It
is set if there is a carry out of the double
precision add; otherwise it is reset.
(A) — (A) 4 (r)
The content of register r is logically ANDed
with the content of the accumulator. The
result is placed in the accumulator. The CY
flag is cleared and AC is set (8085). The CY
flag is cleared and AC is set to the OR'ing
of bits 3 of the operands (8080).

0 0 R P 1 0 0 1 1 0 1 0 0 S S S

Cycles: 3 Cycles: 1
States: 10 States: 4
Addressing: register A ddressing: reg i s t e r
Flags: CY Flags: Z,S, P ,CY,AC
 page C.11

THE INSTRUCTION SET

ANA M (AND memory) XRA M (Exclusive OR Memory)

(A) — (A) ~ ((H) (L))
T he co ntents o f t h e me m o r y l o c a t i on
whose address is contained in the H and L
registers is logically ANDed with the con-
t ent o f t h e a c c u m ulator. Th e r e s ult i s
placed in the accumulator. The CY flag is
cleared and AC is set (8085). The CY flag is
cleared and AC is set to the OR'ing of bits 3
of the operands (8080).
1 0
1 0 1 0 0 1 1 0
(A) — (A) ~ ((H) (L))
The content of the memory location whose
a ddress i s c o n t a ined i n t h e H a nd L
r egisters is e x clusive-OR'd with th e c o n-
t ent o f t h e a c c u m ulator. Th e r e s ul t i s
placed in the accumulator. The CY and AC
flags are cleared.
1 0 1 1 1 0

Cycles: 2
Cycles: 2 States: 7
States: 7 Addressing: r eg . i n d irect
Addressing: reg . i n d i rect Flags: Z,S, P ,CY,AC
Flags: Z,S , P ,CY,AC

ANI data (AND immediate) XRI data (Exclusive OR immediate)

(A) — (A) A (byte 2) (A) — (A) w (byte 2)
The content of the second byte of the in- The content of the second byte of the in-
struction is logically ANDed with the con- s truction is e x clusive-OR'd with the c o n -
t ents o f t h e a c c u m ulator. The r e sult i s t ent o f t h e a c c u m ulator. Th e r e s ult i s
placed in the accumulator. The CY flag is placed in the accumulator. The CY and AC
cleared and AC is set (8085). The CY flag is flags are cleared.
cleared and AC is set to the OR'ing of bits 3
of the operands (8080).
1 1 1 0 1 1 1 0
1 1 1 0 0 1 1 0
data
data
Cycles: 2
Cycles: 2 States: 7
States: 7 Addressing: immediate
A ddressing: immed i a t e Flags: Z,S,P,CY,AC
Flags: Z,S, P ,CY,AC

XRA r (Exclusive OR Register) ORA r (OR Register)

(A) — (A) ~ (r)
The content of register r is exclusive-OR'd
with the content of the accumulator. The
result is placed in fhe accumulator. The CY
and AC flags are cleared.
(A) — (A) V (r)
The content of register r is inclusive-OR'd
with the content of the accumulator. The
result is placed in the accumulator. The CY
and AC flags are cleared.

1 0 1 0 1 S S S 1 0 1 1 0 S S S

Cycles: 1 Cycles: 1
States: 4 States: 4
Addressing: register A ddressing: reg i s t e r
Flags: Z,S,P,CY,AC Flags: Z,S, P ,CY,AC
page G.12

THE INSTRUCTION SET

ORA M (OR memory) CMP M (Compare memory)

(A) — (A) V ((H)(L)) (A) — ((H)(L))
The content of the memory location whose The content of the memory location whose
a ddress i s c o n t a i ned i n t h e H a nd L address i s c o n t a i ned i n t h e H a nd L
registers is inclusive-OR'd with the content registers i s s ub t r a c te d f r o m t he ac-
of the accumulator. The result is placed in cumulator. The accumulator remains un-
the accumulator. The CY and AC flags are changed. The condition flags are set as a
cleared. result of the subtraction. The Z flag is set
to 1 if (A) = ((H) (L)). The CY flag is set to 1 if
(A) < {{ H) {L)).
1 0 1 1 0 1 1 0
1 0 1 1 1 1 1 0

Cycles: 2
States: 7 Cycles: 2
Addressing: reg . i n d i rect States: 7
Flags: Z,S, P ,CY,AC Addressing: reg . i n d i rect
Flags: Z,S, P ,CY,AC
ORI data (OR immediate)
(A) — (A) V (byte 2) CPI data (Compare immediate)
The content of the second byte of the in- (A) — (byte 2)
struction is inclusive-OR'd with the content The content of the second byte of the in-
of the accumulator. The result is placed in struction i s su b t r a c te d f r o m t he ac -
the accumulator. The CY and AC flags are cumulator. The condition flags are set by
cleared.. the result of the subtraction. The Z flag is
set to 1 if (A) = (byte 2). The CY flag is set to
1 if (A) < (byte 2).
1 1 1 1 0 1 1 0

1 1 1 1 1 1 1 0
data
data

Cycles: 2
States: 7 Cycles: 2
A ddressing: immed i a t e States: 7
Flags: Z,S, P ,CY,AC A ddressing: i mmed i a t e
CMPr (Compare Register)
Flags: Z,S,P,CY,AC
(A) — (r)
The content of register r is subtracted from RLC (Rotate left)
the accumulator. The accumulator remains (An+ 1) ( A n) ~(Ao) — (A7)
unchanged. The condition flags are set as (CY) — (A7)
a result of the subtraction. The Z flag is set The content of the accumulator is rotated
to1 if (A) = (r). The CY flag is set to1if (A) left one position. The low order bit and the
< (r). CY flag are both set to the value shifted out
of the high order bit position. Only the CY
flag is affected.
1 0 1 1 1 S S S
0 0 0 0 0 1 1 1

Cycles: 1
States: 4 Cycles: 1
A ddressing: r egi s t e r States: 4
Flags: Z,S, P ,CY,AC Flags: CY
 page C.13

THE INSTRUCTION SET

RRC (Rotate right) CMA (Complement accumulator)

( Ap) ( A ~ + ])I (A7) ( A p ) (A) — (A)
(CY) — (Ap) The contents of the accumulator are com-
The content of the accumulator is rotated p lemented (zero bits become 1, one b i ts
right one position. The high order bit and become 0). No flags are affected.
the CY flag are both set to the value shifted
out of the low order bit position. Only the
CY flag is affected.
0 0 1 0 1 1 1 1

0 0 0 0 1 1 1 1
Cycles: 1
States: 4
Flags: no ne
Cycles: 1
States: 4
Flags: CY
CMC (Complement carry)
(CY) — (CY)
The CY flag i s c o m p lemented. No o ther
RAL (Rotate left through carry) flags are affected.
(A„+ ))-(A„); (CY)-(A7)
(Ap) —
(CY)
The content of the accumulator is rotated
left one position through the CY flag. The 0 0 1 1 1 1 1 1
low order bit is set equal to the CY flag and
the CY flag is set to the value shifted out of
the high order bit. Only the CY flag is af-
fected. Cycles: 1
States: 4
Flags: CY

0 0 0 1 0 1 1 1

STC (Set carry)

(CY) — 1
Cycles: 1
States: 4 The CY flag is set to 1. No other flags are
affected.
Flags: CY

0 0 1 1 0 1 1 1
RAR (Rotate right through carry)
( Ap) ( A ~ + )))(CY) ( A p )
(A7) — (CY)
The content of the accumulator is rotated Cycles: 1
right one position through the CY flag. The States: 4
high order bit is set to the CY flag and the Flags: CY
CY flag is set to the value shifted out of the
low order bit. Only the CY flag is affected.

0 0 0 1 1 1 1 1

Cycles: 1
States: 4
Flags: CY
Page C.14

THE INSTRUCTION SET

5.6.4 B r anch Group Jcondition addr (Conditional jump)

This group of instructions alter normal sequen- If (CCC),
tial program flow. (PC) — (byte 3) (byte 2)
If the specified condition is true, control is
Condition flags are not affected by any instruc- t ransferred to t h e i n s t ruction w hose a d -
tion in this group. dress is specified in byte 3 and byte 2 of the
The two types of branch instructions are uncon- current instruciton; otherwise, control con-
d itiona l a n d co nd i t i o n a l . U n c o n d i t i o n a l tinuess sequen
tially.
transfers simply perform the specified opera-
tion on register PC (the program counter). Con-
ditional transfers examine the status of one of
t he four p rocessor f lags t o d e t ermine i f t h e 1 1 C C C 0 1 0
specified branch is to be executed. The condi-
tions that may be specified are as follows: low-order addr

high-order addr
CONDITION CCC
NZ — not zero (Z=O) 000
Z — zero (Z = 1) 001
NC — no carry (CY =0) 010 Cycles: 2 / 3 (8085), 3 (8080)
C - carry (CY = 1) 011 States: 7 / 10 (8085), 10 (8080)
PO — parity odd (P =0) 100 Addressing: i m m e d iate
PE — parity even (P = 1) 101 F lags: none
P — plus (S =0) 110
M - minus (S = 1) 111
CALL addr (Call)
((S P) — 1) — (PC H)
((S P) — 2) — (PC L)
(SP) — (S P) — 2
JMP addr (Jump) (PC) — (byte 3) (byte 2)
(PC) — (byte 3) (byte 2) T he high-order eight b it s o f t h e n ex t i n -
Control is t r a n sferred t o t h e i n s t ruction
struction a d d r es s a r e mo v e d to th e
whose address is specified in byte 3 and
byte 2 of the current instruction. m emory location w h ose a d dress i s o n e
less than the content of register SP. The
low-order eight bits of the next instruction
address are moved to the memory location
1 1 0 0 0 0 1 1 whose address is two less than the content
of register SP. The content of register SP is
decremented by 2. Control is transferred to
low-order addr the instruction whose address is specified
in byte 3 and byte 2 of the current instruc-
high-order addr tion.

Cycles: 3 1 1 0 0 1 1 0 1
States: 10
A ddressing: i mmed i a t e low-order addr
Flags: no ne

high-order addr

C ycles: 5
States: 1 8 (8085), 17 (8080)
, i m m ediate/
Addressing: reg, indirect
Address'
F lags: n o n e
 page C.15

THE INSTRUCTION SET

Ccondition addr (C ondition call) Rcondition (Conditional return)

If (CCC), If (CCC),
((SP) — 1) — (PCH) (PCL) — ((SP))
((S P) — 2) — (PC L) (PCH) — ((SP) + 1)
(SP) — (SP) — 2 (SP) — (SP) + 2
(PC) — (byte 3) (byte 2) If the specified condition is t r ue, the ac-
If the specified condition is t r ue, the ac- tions specified in the RET instruction (see
tions specified in the CALL instruction (see above) are performed; otherwise, control
above) are performed; otherwise, control continues sequentially.
continues sequentially.

1 1 C C C 0 0 0
1 1 C C C 1 0 0

low-order addr Cyc les: 1/3

States: 6 / 12 (8085), 5/11 (8080)
high-order addr Addressing: r e g . indirect
F lags: none

RST n (Restart)
Cycles: 2 / 5 (8085), 3/5 (8080) ((SP) — 1) — (PCH)
States: 9 / 18 (8085), 11/17 (8080) ((S P) — 2) — (PC L)
immediate/ (S P) — (S* P) — 2
Addressing: (PC) — 8 (NNN)
reg. indirect
F lags: none T he high-order eight b it s o f t h e n ex t i n -
struction a d d r es s a r e mo v e d t o t he
m emory location w h ose a d dress i s o n e
less than the content of register SP. The
low-order eight bits of the next instruction
RET (Return) address are moved to the memory location
(PCL) — ((SP)); whose address is two less than the content
(PCH) — ((SP) + 1); of register SP. The content of register SP is
(SP) — (SP) + 2; decremented by two. Control is transferred
The content of the memory location whose to the instruction whose address is eight
address is specified in register SP is moved times the content of NNN.
to the low-order eight bits of register PC.
The content of the memory location whose
address is one more than the content of 1 1 N N N 1 1 1
register SP is moved to the high-order eight
bits of register PC. The content of register
SP is incremented by 2.
C ycles: 3
States: 1 2 (8085), 11 (8080)
Addressing: r e g . indirect
1 1 0 0 1 0 0 1 F lags: n o n e

151413 12 1 1 10 9 8 7 6 5 4 3 2 1 0
Cycles: 3
States: 10 0 0 0 0 0 0 0 0 0 0 N N N 0 0 0
Addressing: reg. indirect
Flags: none Program Counter After Restart
Page C.16

THE INSTRUCTION SET

PCHL (Jump H and L indirect - The content of register A is moved to the

move H and L to PC)
(PCH) — (H)
(PCL) — (L)
The content of register H is moved to the
high-order eight b it s o f r e g ister PC. The
content of register L is moved to the low-
order eight bits of register PC.
m emory location w h ose a d dress i s o n e
less than register SP. The contents of the
condition flags are assembled into a pro-
cessor status word and the word is moved
to the memory location whose address is
two less than the content of register SP.
The content of register SP is decremented
by two.

1 1 1 0 1 0 0 1
1 1 1 1 0 1 0 1
C ycles: 1
States: 6 ( 8085), 5 (8080) C ycles: 3
Addressing: r e g i s ter States: 1 2 (8085), 11 (8080)
F lags: n o n e Addressing: r e g . indirect
Flags: none
5.6.5 S t a ck, I/O, and Machine Control Group
This group of instructions performs I/O, manipu-
lates th e S t a ck , a n d a l t er s i n t e rnal c o n t rol FLAG WORD
flags.
Unless otherwise specified, condition flags are D7 D6 D5 D4 D3 D2 D] DP
not affected by any instructions in this group.
S Z X AC X P X CY
PUSH rp (Push)
((S P) — 1) — (rh)
((SP) — 2) — (ri) X: undefined
((SP) — (SP) — 2
The content of t h e h i gh-order register of
register pair rp i s m o ved t o t h e m e mory POP rp (Pop)
location whose address is on e l ess t h an (r I) — ((S P))
the content of register SP. The content of (rh) — ((SP) + 1)
the low-order register of register pair rp is (SP) — (SP) + 2
moved to the memory location whose ad-
d ress i s t w o l e s s t h a n t h e c o n t ent o f The content of the memory location, whose
register SP. The content of register SP is a ddress i s s p e c i fied b y t h e c o n t en t o f
decremented by 2. Note: Register pair rp = register SP, i s m o v e d t o t h e l o w - order
SP may not be specified. register of register pair rp. The content of
the memory location, whose address is one
more than the c o ntent o f r e g ister SP, is
1 1 R P 0 1 0 1 moved to the high-order register of register
r p. The c o n t en t o f re g i s te r S P i s i n-
cremented by 2. Note: Register pair rp =
C ycles: 3 SP may not be specified.
States: 1 2 (8085), 11 (8080)
Addressing: r e g . indirect
F lags: n o n e

PUSH PSW (Push processor status word) 1 1 R P 0 0 0 1

((SP) — 1) — (A)
({SP) — 2)p — (CY), {{SP) — 2)i — X
(( ) — )2 — ( )>(( ) — ) 3 — X Cycles: 3
((SP) — 2)4 — (AC), ((SP) — 2)5 — X States: 10
((SP) — 2)6 — (Z), ((SP) — 2)7 — (S) Addressing: reg.indirect
(S P) — (S P) — 2 X: Undefined. Flags: none
 page C.17

THE INSTRUCTION SET

POP PSW (Pop processor status word) SPHL (Move HL to SP)

(CY) — ((S P))o (SP) — (H) (L)
(P) — ((SP))2 The contents of registers H and L (16 bits)
are moved to register SP.
(AC) — ((SP))4
(Z) — ((S P))6
(S) — ((S P))7
(A) — ((SP) + 1) 1 1 1 1 1 0 0 1
(SP) — (SP) + 2
The content of the memory location whose
a ddress i s s p e c ified b y t h e c o n t ent o f C ycles: 1
register SP is used to restore the condition States: 6 (8085), 5 (8080)
flags. The content of the memory iocation Addressing: r e g i s ter
whose address is one more than the con- F lags: none
tent of register SP is moved to register A,
The content of register SP is incremented
by 2. IN port (Input)
(A) — (data)
T he dat a p l a ce d o n t h e ei g h t b i t b i -
directional data bus by the specified port is
1 1 1 1 0 0 0 1 moved to register A.

Cycles: 3 1 1 0 1 1 0 1 1
States: 10
Addressing: reg . i n d i rect port
Flags: Z,S , P ,CY,AC

Cycles: 3
XTHL (Exchange stack top with H States: 10
and L) A ddressing: d i rec t
(L) — ((SP)) Flags: no ne
(H) — ((SP) + 1)
The content of the L register is exchanged
with the content of t h e m e mory location OUT port (Output)
whose address is specified by the content (data) — (A)
of register SP. The content of the H register The content of register A is placed on the
i s exchanged w i t h t h e c o n t en t o f t h e e ight b i t b i- d i r ectiona l d a t a b us f o r
m emory location w h ose a d dress i s o n e transmission to the specified port.
more than the content of register SP.

1 1 0 1 0 0 1 1

1 1 1 0 0 0 1 1 port

C ycles: 5 Cycles: 3
States: 1 6 (8085), 18 (8080) States: 10
Addressing: r e g . indirect A ddressing: d i rec t
Flags: none Flags: no ne
Page C.18

THE INSTRUCTION SET

El (Enable interrupts)
The interrupt system is enabled following 0 0 0 0 0 0 0 0
the execution of the next instruction. Inter-
r upts are not r ecognized during the E l
instruction. Cycles: 1
States: 4
Flags: no ne
1 1 1 1 1 0 1 1
RIM (Read Interrupt Masks) (8085 only)
The RIM instruction loads data into the ac-
Cycles: 1 c umulator relating t o i n t e rrupts and t h e
States: 4 serial input. This data contains the follow-
Flags: no ne ing information:
• Current interrupt mask status for the
NOTE: Placin~an El instruction on the bus in RST 5.5, 6.5, and 7.5 hardware inter-
response to INTA during an INA cycle is pro- rupts (1 = mask disabled)
hibited. (8085) • Current interrupt enable flag status (1
i nterrupts e n a bled) e x cept i m -
mediately following a TRAP interrupt.
DI (Disable interrupts) (See below.)
The interrupt system is d i sabled immedi- • Hardware i n t e rrupts p e n d in g ( i .e.,
ately following the execution of the Dl in- signal received but not yet serviced),
struction. Interrupts are not r ecognized
on the RST 5.5, 6.5, and 7.5 lines.
during the Dl instruction. • Serial input data.
immediately fo llowing a T R A P i n t errupt,
1 1 1 1 0 0 1 1 the RIM instruction must be executed as a
part of the service routine if you need to
retrieve current interrupt status later. Bit 3
Cycles: 1 of the accumulator is (in this special case
States: 4 only) loaded with the interrupt enable (IE)
Flags: no ne flag status that existed prior to the TRAP
interrupt. Following an RST 5.5, 6.5, 7.5, or
INTR interrupt, the interrupt flag f l ip-flop
N OTE: PlaclnrLa DI instruction on the bus i n reflects the current interrupt enable status.
response to INTA during an INA cycle is pro- Bit 6 o f t h e a c c umulator (I7.5) is loaded
hibited. (8085) with the s t atus o f t h e R S T 7.5 f l i p-flop,
which is always set (edge-triggered) by an
input on the RST 7.5 input line, even when
HLT (Halt) that interrupt has been previously masked.
The processor is s t o p ped. The registers
and flags are unaffected. (8080) A second (See SIM Instruction.)
ALE is generated during the execution of
HLT to strobe out the Halt cycle status in-
formation. (8085) O pcode. 0 0 I 0 0 0 0 0

Accumulator
0 1 1 1 0 1 1 0 Content
After RIM: SI D 1 7. 5 1 6. 5 1 5 . 5 I E M7 . 5 M 6 5 M5 5

Cycles: 1 + ( 8 085), 1 (8080)

Interrupt Masks
States: 5 (8085), 7 (8080) Interrupt Enable Flag
F lags: n o n e
Interrupts Pending
Serial Input Data

NOP (No op) Cycles: 1

No operation is p erformed. The registers States: 4
and flags are unaffected. Flags: no ne
 page C.19

THE INSTRUCTION SET

SIM (Set Interrupt Masks) (8085 only)

The execution of the SIM instruction uses
the contents o f t h e a c c u m ulator (which
must be previously loaded) to perform the
following functions:
• P rogram the i nterrupt mask for t h e
RST 5.5, 6.5, and 7.5 hardware inter-
rupts.
• Reset the edge-triggered RST 7.5 in-
put latch.
• Load the SOD output latch.
To program the interrupt masks, first set ac-
cumulator bit 3 to 1 and set to 1 any bits 0,
1, and 2, which disable interrupts RST 5.5,
6.5, and 7.5, respectively. Then do a SIM in-
struction. If accumulator bit 3 is 0 when the
SIM instruction is executed, the interrupt
m ask r e g ister w i l l n o t ch a n ge . I f a c -
cumulator bit 4 is 1 when the SIM instruc-
tion is executed, the RST 7.5 latch is then
reset. RST 7.5 is distinguished by the fact
that its latch is always set by a rising edge
on the RST 7.5 input pin, even if the jump to
service routine i s i n h i bited b y m a s k ing.
This latch remains high until cleared by a
R ESET IN, by a SI M I n struction with ac -
cumulator bit 4 high, or by an internal pro-
cessor acknowledge to an RST 7.5 interrupt
subsequent to the removal of the mask (by
a SIM instruction). The RESET IN signal
always sets all three RST mask bits.
If accumulator bit 6 is at the 1 level when
the SIM instruction is executed, the state
of accumulator bit 7 is loaded into the SOD
latch and thus becomes available for inter-
face to an external device. The SOD latch is
unaffected by the SIM instruction if bit 6 is
0. SOD is always reset by th e RESET IN
signal.

O pcode: 0 0 1 1 0 0 0 0

Accumutato 7 6 5 3 2 0
Content
SOD SOE X R7. 5 M S E M 7.5 M6 5 M5.5
SIM;
RST 5 5 Mask
RST 6.5 Mask
RST 7.5 Mask
Mask Set Enable
Reset RST 7.5 Flip-Flop
Undefined
SOD Enable
Serial Output Data
Cycles: 1
States: 4
Flags: no ne
Page C.20

8085A

8080A/8085A INSTRUCTION SET INDEX

Table 5-1
7 States T States
Instruction Code Bytes Machfne Cycles Instructfon Code Bytes Machine Cydes
8085A 8080A 8085A BOBOA
ACI DATA CE data FR L XI RP,DATA16 DORP 0001 data16 10 10 FRR
A DC BE G 1000ISSS F MOV REG,REG 0100 OSSS 5 F
A OC M BE FR MOV M,REG 0111 OSSS 7 FW
7
4
ADD REG 1000 OSSS F MOV REG,M OIQD D110 FR
A OO M 86 FR MVI REG,DATA OQQD 0110dala FR
AD I DAT A C6 data FR MV I M,DATA 36 data 10 10 F R IV
ANA REG 1010 OSSS sf OP 00
ANA M FR ORA REG 1011 QSSS
ANI DAT A E6 data FR DRA 86 7 FR
CALL L A B EL CO addr 18 17 SR RWW' 0RI DATA F6 data 7 FR
CC LABE L DC addr 9/18 I I/I 7 5 R•/SR RWW OUT PORT D3 data 10 10 FRO
Gill L ABEL FC addr 9/18 11/17 SR •/S R RWW' PCHL E9 6 9'
CMA 2F 4 F POP RP I I RP 0001 10 10 FRR
CMC 3F PUSH RP I I RP 0101 12 SWW'
C MP REG 1011ISSS RAL 17 4 F
C MP M BE 7 FR RAR IF 4 F
C Nt; LAB E L D4 addr 9/18 11/17 S Re/S R RWIN RC DB 6/12 5/11 9/9 R R
C NZ LAB E L C4 addr 9/18 11/17 S Re/S R RW IY RET C9 10 10 FRR
CP LABE L F4 addr 9/18 11/17 SR • /SR RWW' RIM 18085A on'yf 20 4 F
C PE LABE L EC addr 9/18 I li17 s R• s R R syv/' RLC 07 4 F
CPI DATA FE data FR RM FB 6/12 5/ I I 9/5 R R
C PO LAB E L E4 addr 9/18 11/17 S R • /S R R WW RNC 00 6/I 2 5/11 5/9 R R
CZ LABE L CC addr 9/18 11/17 S R•/S R R 'IVW RNZ CO 6/I 2 5/11 6/9 R R
OAA 27 RP FO 6/12 5/11 6/9 R R
DAO RP OORP 1001 10 10 FBB RPE EB 6/12 5/11 5/9 R R'
O CR RE G BOSS S101 F RPO EO 6/12 5/11 9/6 R R'
O CR M 35 10 10 FRV/ RRC OF 4 4 F
DCX RP OORP 1011 6 5 9' RST I IXX X111 12 11 SWW'
Ol F3 RZ CB 6/I 2 5/ I I 6/6 R R
El FB SBB REG 1001 ISSS 4 F
HLT 76 FB SBB 9E FR
IN PORT QB cata 10 10 FRI S BI DATA DE data FR
INR REG 00SS SI00 SHLQ *OOR 22 addr 16 16 FRRWIW
INR 34 10 10 FRW SIM (8085A only ) 30 F
INX RP OORP 0011 6 5 5' SPHL F9 6 S'
JC LABE L OA addr I/10 10 FR/FR RI STA AODR 32 addr 13 13 FRRW
JM LABE L FA addr 7/10 10 F R/F R Rt STAX RP OOOX 0010 7 FW
J MP LABE L C3 addr 10 10 FR R STC 37 F
J NC LAB E L 02 addr 7/10 10 FR/FR RI SUB REG 1001 OSSS F
J NZ LAB E L C2 ad dr 7/10 10 FR/FR RI SUB M 96 FR
JP LABEL F2 addr I/10 10 FR/FRRI SU I DATA D6 data FR
J PE LABE L EA addr 7/10 10 F R/F R Rt XCHG EB F
J PO LAB E L E2 addr 7/10 10 FR/FR RI XRA REG 1010 ISSS 4 F
JZ LABEL CA addi I /10 10 F R/F R Rt XRA AE 7 47 FR
LQA ADDR 3A arldr 13 13 FRRR XRI DATA EE data I FR
L DAX RP OOOX 1010 FR XTHL E3 16 18 FR RWW
L HLO ADDR ZA addr 16 16 FR RRR
I lac I yr.le types
F Four clock pvnod nslr later
S x clock per od instr telcli
5R
klem ory read
I/O read
).I a m rf r y v r I r
0 I/O ivr rr
Bus die
X
6
Var ahle or optional Iiinary rl qif
OQO 8 narv d q ts de t tv» q " dist s ' nn req .i 9 - 000 C Off f 0 q l t l I / e no r - 110
SSS 8 arv I I t o, i », , l a ss " r I sl e E 0 1 1 H 1 3 0L - 1 0 1 A .
5 6-00 H L 1 0
RP Remslvr Pair
OE 01, SP 11
'F vr rrurk per nd nstruct on fetch with 8080A
I fh I i qer nach nv cyrle sequr»ce apulies regardless it iond I nn nvaluat on w th 8080A
• An t . i R E AD cycle IR) anil orc r tnr th s cond t i w th 8080A
 page C.21

8085A

8 085A CPU INSTRUCTIONS IN OPERATION CODE SEQUENC E

Table 5.2

OP OP OP OP OP OP
CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC

00 NOP 28 DCX H 56 MOV D,M 81 ADD AC XRA D7 R ST 2

H
L
01 LXI B,D16 2C IN R L 57 MOV D,A 82 ADD C
E
D AD XRA DB RC
02 STAX 8 2D DCR L 58 MOV E,B 83 ADD AE XRA Iyl D9
2E MVI L,DB 59 MQV E,C 84 ADD AF XRA DA JC A dr
03 INX 8 L
H A
8
2F CMA 5A MOV E,D 85 ADD 80 QRA DB IN DB
04 INR 8
30 5IM 58 MOV E,E 86 ADD 81 ORA DC CC A dr
05 DCR 8
06 MVI B,DB 31 LXI SP,D16 5C MOV E,H 87 ADD 8
A
M 82 ORA DD
07 RLC 32 STA Adr 5D MQV E,L 88 ADC 83 QRA C
L
H
E
D DE SBI DB
33 INX SP 5E iy1OV E,M 89 ADC 84 QRA DF RST 3
08
09 DAD 34 INR M 5F MOV E,A SA A DC 85 ORA EO RPO
60 MOV H,B 88 ADC L
H
E
D
C 86 QRA El PQP H
OA LDAX 8 35 DCR M
08 DCX 36 MVI M,DS 61 MOV H,C SC ADC 87 ORA 8
A
M E2 J PO A di
OC INR 37 STC 62 MOV H,D SD A DC 88 CMP E3 XTHL
OD DCR 38 63 MOV H,E BE A DC 89 CMP E4 C PO A dr
C
C,DB
C 64 MOV H,H SF ADC 8
A
M BA CMP EG P USH H
OE MVI 39 DAD SP
OF RRC 3A LDA Adr 65 MQV lt,L 90 SUB 88 CMP H
E
D
C
L E6 A NI DB
38 DCX SP 66 MOV H,M 91 SUB BC CMP E7 R ST 4
10
11 LXI D,D16 3C IN R 67 MOV H,A 92 SUB BD CMP ES RPE
12 STAX D 3D DCR 68 iMOV L,B 93 SUB C
L
H
E
D BE CMP E9 PCHL
A ,DB A
M
13 IN X D 3E MV I 69 MOV L,C 94 SUB SF CMP EA JPE A dr
14 I NR D 3F CMC GA xrlOV L,D 95 SUB CO RNZ EB XCHG
'I
15 DCR D 40 MQV B,B 68 MQV L,E 96 S LIB C1 PQP B EC CPE A dr
16 MVI D,DS 41 MQV B,C 6C MOV L,H 97 SUB C2 JNZ Adr ED
A
8
17 RAL 42 MOV B,D 6D MOV L,L 98 SBB C3 JMP Adr EE X RI DB
18 43 MOV B,E 6E iVIOV I,M 99 SBB C4 CNZ Adr EF R ST 5
19 DAD 44 MOV B,H GF tv1OV I,A 9A SBB Cr5 PUSH 8 FO RP
1A LDAX 45 MOV B,L 70 MOV M,B 98 SBB C
L
H
E
D CG AD I DS Fl POP PSW
18 DCX D
E,DS
E 46 MOV B,M 71 MOV M,C 9C SBI3 C7 RST 0 F2 JP Art r
IC INR 47 MOV B,A 72 MOV M,D 9D SBS CS RZ F3 Dl
ID DCR 48 MOV C,B 73 MQV M,E 9E SBB iyl C9 RET Adr F4 CP Ail (
1E MVI 49 MOV C,C 74 MOV M,H 9F SBB A CA JZ F5 P USH PSW
IF RAR 4A iM Q V C,D 75 MOV M,L AO ANA 8 CB F6 OR I DS
20 RIM 48 MOV C,E 76 HLT Al ANA CC CZ Adr F7 RST 6
D
C
21 LX I r-r, D 1 6 4C MQV 77 VQV lit A A2 CD CALL Adr FS RM
22 SHLD Adr 4D MQV C,L 78 MQV A,S CE AC I D8 F9 SPHL
23 INX H 4E MQV C,M 79 MOV A,C A4 ANA L
H
E C I- RST I FA JM A dr
24 IN R H 4F MOV C,A 7A MQV A,D A5 ANA DO RNC FB El
25 DCR H 50 MOV D,B 78 iMOV A,E A6 ANA M Dl POP D FC CM A rlr
26 MVI H,DS 51 MQV D,C 7C MOV A,H A7 ANA D2 JNC Adr FD
8
A
27 DAA 52 MOV D,D 7D MOV A,L AS XRA DJ QUT DS FE C PI D8
28 53 MOV D,E 7E MQV A,M A9 XRA D4 CNC Adr FF RST 7
29 DAD H 54 MOV D,H 7F MQV A,A AA XRA E
D
C D5 PUSH
2A LHLD Adr 55 MOV D,L 80 ADD 8 AB XRA DG SUI DS
D

DS - constant, or logical/arit h m e tic expression that evaluates D16- constant, Or lc gical/a r i t h m e t i c e x p r ess ion that evaluates
to an 8-bit d ata quantity t o a 16 - b i t d a t a q u a n t i t y
A dr - 16-bit ad d r ess
page C.22

8085A

8085A INSTRUCTION SET SUMMARY BY FUNCTIONAL GROUPING

Table 5-3
Instruction Code (U Instrucuon Code (I)
Mnernomc O e scnplion D/ DH 05 04 03 02 Dl DU Page Mnemomc O e srnpnon 0/ 0 (, 05 04 0 3 02 01 00 Page

MOVE, LOAD, AND STORE

MOVrl r 2 hl u v e register tu registei 0 I 0 0 0 S S S 54 CZ Call nn rr rr) I I 0 0 I I 0 0 J14

MOV 51 r memory
M u v e rei ster to 0 I I I U S S S 54 CNZ Cail un nn )Pro I I 0 0 0 I 0 0 5 14
MUV r M Mo v e npmory lo register 0 I 0 0 0 I I 0 54 CP Call on pnsilivr I I I I 0 I 0 0 5 14
MVI I Muve mmedmte register 0 0 0 D 0 I I 0 54 CM Cdd Ui r i f i )1«i I I I I I 0 0 5 11
lsl V I I(1 lsluve nnmedmle memory U 0 I I tl I I U '4 CPE Call un par ty pvrn I I I 0 I I 0 U 5 14
LXI 0 Load mmedmte rirpsli.r U U 0 0 0 0 0 CPO LJH un parity urld I I I 0 0 I 0 0 5 14
Pa«08 C RETURN
L XI U Lu,id i nmerhalr, rrgislrr 0 0 0 I tl 0 tl I 5 5 RLI Helurn I I 0 U I 0 0 I 5 14
Pair 08 E Ri'Iuf)1 u)1 cd)r e I I 0 I I 0 tl 0 5 14
I XI H L oad irnmrdmt r r g i i l e r 0 0 I 0 0 U 0 I 5 5 RNC Return un nu carry I I 0 I 0 0 0 0 J14
Vair tl & L
I'I'Intr) or) rein I I 0 0 I tl 0 0 5 14
STAX 8 Srnr A mdncct 0 0 0 0 fl tl I 0 5 fi
RNI 0 c IUr i or) 1) u ter u I I 0 0 0 0 0 0 5 14
STAX 0 Store A 111(I)reel 0 0 0 I 0 0 I 0 55
Rrturri un pos t ve I I I I 0 0 0 0 5 11
LOAX 8 Li)J)I A 11)if))cut U 0 tl 0 I U I U '514
Return un minus I I I I I 0 0 0
LUAX 0 L Oad A indii Ci l 0 0 0 I I 0 I 0 ')5
RVE Hrl r i i on pdr ty pve« I I I 0 I U 0 fl 5 14
STA Sture A dirct.t 0 0 I I 0 U I 0
RPO Return un pdr ty oild I I I 0 0 0 U U 5 14
LOA Load A direct 0 0 I I I 0 I 0 5 5
RESTART
SHLO Sture H & L ilirect 0 0 I 0 0 0 I 0 55
HST Rrslul I I A A A I I I
LHLO Led)i H 8 L (I)reel 0 0 I 0 I 0 I 0 55
IN P U T/0 U 3 PUT
XCHG Excl an)a 0 & E H 8 L I I I 0 I 0 I I ')6
IN put I I 0 I I 0 I I ') lti
Hpg ster)
STACK 0PS OUT Output I I tl I U U I

PUSH 0 Pu)h rrrpilr r Pair 8 8 I I 0 0 0 I U I 5 15 INCREMENT ANO DECREMENT

C «n stack INR r Incremerit req ster 0 0 0 0 0 0 0 58
PUSH U Pi)it) It! I)slur PJ f 0 8 I I tl I U I U I 5 15 DCR r Decrement reg slur 0 0 0 0 0 I U I 58
6 on)tack INII hl Increinr nt me m nry 0 0 I I 0 I 0 tl ')H
PUSH H Vu)tr register PJ r H 8 I I I 0 0 I 0 I ')15 OCR M Derremenl mmnnry 0 0 I I 0 I 0 I 5H
L un stark
INX 8 Inrremrnt 0 8 0 0 0 0 0 0 0 I I
PUSH VSIV Rust) A anrl Elaqs I I I I U I 0 I 5 15 ii ] strrs
oii stack INX D Inrrement 0 P E 0 0 0 I 0 0 I I 59
POP 8 Vnp rt ) ster Pan 0 8, I I 0 0 fl U fl I 5 15 req slcfs
C uU stark INX H Inmernent H 8 L 0 0 I 0 0 U I I 59
POP D Pop req ster Pa r 0 & I I 0 I tl fl U I 5 15 fi ) rstcf's
E )tt stark
OCX 8 Occirn enl 0 8 C 0 0 U U I 0 I I J9
POV H Pup reM)te Pa r H 8 I I I U U 0 0 I 5 th
DCX 0 U Pc) P. )1 PI) I 0 8 0 U 0 I I 0
L uft ) t i r k
UCX H Dec)en enl H 8 L 0 U I 0 I 0 I I 59
POV PSIV Vnp A amf fl ags I I I I 0 0 0 I ', I ',
nH stark AOD
XTHL t.xcl Jnp tup uf I I I 0 0 0 I I 5 16 AOUr Ad I I )lr tnA I tl Il 0 0 S S S 5 )i
)ter k H & L A I)C I U fl U I \ S S .5) fi
SPHL H & I ) U SIJ(k fi lit))i'r I I I I tl fl I ') IG m )1 (J ) i )

L XI SP Ludd m nedmtc stark 0 0 I I 0 0 l(D Il hl I 0 C 0 0 I I 0 56

por ilpf AIR. 51 1 0 0 0 I 0 5 /
INX SP Ini.ri'r )Sr)I )IJck I ) or)i(pi 0 0 I I U 0 I I 59 w li J ry

DCX SP Or(re ne it stack 0 0 I I I 0 I AU I A Irl n rl .i I l i A I I 0 0 0 I I 0 JG

po ilef ACt 0 0 I I fl ' /
n d i,rrs
JUMP
tlAO 0 A d(H P, (. t • H V, I 0 U IJ 0 I 0 0 I 59
JMP I 0 0 0 U
OAO U A il I IJ r, E t H& L 0 0 f) I I U 0 I 5) 9
JC J p u ca i r y I I 0 I I I) I 0 5 13
DAO H A tl t( 8 L l i H 8 L U 0 I tl I U 0 I 5 !I
JNC Jump nn nn ra ry I I U I 0 0 I 0 5 13
OAO SV AII )l d k i n n)' f u 0 0 I 0 0 I '9
JZ Jii ifr Ori re)i) I I 0 0 I fl I 0 5) I J
tt/', L
JNZ Jr))rifi Ul) 11)l ref U I I 0 0 0 0 I 0 J13
JP SUBTRACT
Jump on pus I ve I I I I 0 U I 0 5 13
SUH h l, t f eist I 0 5 5 5 ' /
Jump n m nus I I I I I tl I 0 5 13
JPE Jr) rp 011 ildf )le i'VP)1 I I I 0 I 0 I 0 5 13
SHH tl U I I 5 S 5 '/
JPU rnp • n pdr ly udrl I I I 0 0 0 I 0 5 13
A • t t h )u )
I'Ctl( H 8 L tu pro)ram I I I 0 I 0 0 I 5 15 . 'Ult 51 0 II I tl 0 ' /
co )l e)
CALL SHti 51 0 U I I I I 0 '8
CALI Call u in«d I nrml I 0 0 I I tl I 5 13 A n,l l ti )n w
Call un r.drry I I 0 I I I 0 0 5 11 SUt I 0 ) 0 5/
C NE. C.it) )i) i)i) (dire I 0 I 0 I U 0 5 14 l ri ' A
 page C.23

8085A

8085A INSTRUCTION SET SUMMARY (Cont'd)

Table 5-3
Inoruction Code Il) tnstruction Code Ill
Mnemamc Descnptian 07 05 05 0 4 0 9 02 01 00 Page Mnemomc Descnption D7 05 05 04 0 9 D2 01 DU Page
cjl S.c rett 55 uRC 5 12
I •,n A w t» borrj» Rolak A ietl through 0 0 0 I 0 I I I 5 12
LOGICAL carry
ANA r A»d re g ister w tl A I 0 I 0 0 9 5 5 59 RAR Rotate A right tnruugn 0 0 0 I I I I I 5 12
XRA r Ex lat i v e OR reg ste 0 I 0 I S S S 5 10 carry
wtn A
0 I I I' S S
SPECIALS
ORA OR egtt ry i n A I 5 517
ClhP r Compare rea ster» I A 0 I I I 5 5 5 5 11 .'h A Cjm„ v m v .il A = 12

ANA hl And memory ivrtn A 0 I 0 0 I I 0 5 10 STC Set carry 0 I I 0 I I I 512

XRA M Exclus ve DR memr ry 0 I 0 I I 0 5HI CMt. Cornpiemenr cjriv 0 I I I I 512
willi A Dec mm adlust A 0 0 I 0 0 I I 5.9
DRAM OR m e m ory wilt A I 0 I I 0 I I U 5 11
CONTROL
CMP lh Co. n uar mernurv .v in A I 0 I I I I I 0 5 11
' Ei 0
ANI A 0 I 0 j ld
XRI Exciusrve 0R tmmeu ate I I 0 I I I 0 5 10 UI 0 sab e Inta rui.t I I I I 0 Il I I 5 17
w th A NOP feo uperation 0 0 0 0 0 U 0 517
ORI OR mmediate v. Iti A I I I I 0 I I 0 5 11 HLI Hall 0 0 I 0 517
CPI Co npare nmea ate I I I I I I I 0 5 11
v.thA NEW 8085A INSTRUCTIONS
ROTATE RIM ' rr ' itf ' 0 U I J r 0
RLC Rotate A lelt 0 0 0 0 0 I I I 5 11 SIM S et Interrur:t 'ij t r, 0 0 I I 0 0 0 0 5 18

NOTES I DDS or SSS 8 000, C uut, 0 010, Eull, H 100, L 101 Men ury 110, A 111
2 Iwo pose ble cycle I mes (Sr'121 ndi cate r strut t an cycles dependsil on cllndit on Rags
 page D.1

APPENDIX D
Data Sheets

The following pages are reprinted with

the permission of Motorola, Intel,
Monolithic Memories, Texas Instruments,
Western Digital Corporation, Advanced
Micro Devices, Fairchild, and Hitachi.
Page D.2

Data Sheet Index

MAIN BOARD
PART MODEL DESCRIPTION PAGE
NUMBER NUMBER NUMBER

443-970 6665 Dynamic RAM D.4

443-1010 8085A-2 Single Chip 8 BIT N-Channel D.21
Microprocessor
443-1012 8259A Programmable Interrupt Controller D.37
443-1014 68A21 Peripheral Interface Adapter D.56
443-1040 9602 Dual Retriggerable Resettable D.67
Monostable Multivibrator
443-1061 2661 Enhanced Programmable D.74
Communications Interface
443-1066 8253 Programmable Interval Timer D.94
444-126 PAL16L8 Memory Timing Control D.105
444-128 PAL12H6 Processor Swap D.105
444-129 PAL16L2 PROM Address Decode D.105
444-130 PAL14L4 Memory HIADS Decode D.105
444-9018 27S21 1024 Bit Generic Series D.116
Bipolar PROM
444-9019 27S19 Bipolar PROM D.122
444-9027 2764 UV Erasable PROM D.128
444-9031 8741A Universal Peripheral Interface D.134

VIDEO LOGIC BOARD

PART MODEL DESCRIPTION PAGE
NUMBER NUMBER NUMBER

443-1013 68A45 CRT Controller D.146

444-9011 TBP18522 PROM D.176
443-970 6665 64K Dynamic RAM D.4
443-1106 6633 32K Dynamic RAM D.219

FLOPPY DISK CONTROLLER BOARD (Z-207)

PART MODEL DESCRIPTION PAGE
NUMBER NUMBER NUMBER

443-997 1790 Floppy Disk Formatter D.184

443-998 1691 Floppy Support Logic D.207
443-1000 2143 Four Phase Clock Generator D.215
 page D.3

Main Board
page D.4

o e •

• •
MCM6665A
• •

MOS
IN CHANNLL, SILICON GATE)
64K BIT DYNAMIC RAII/I
The MCM6665A is a 65,536 bit,high speed, dynamic Random
Access Memory O r ganized as 65,536 one bit words and f,>bricated 65,536- B IT
using HMOS high pcrformarice N charm<>i silicon qate Icchrioloqy, this DYNAMIC RANDOM ACCESS
new breed of 5 v ol t o nly d yr»,mtc RA M c o rri(»nes high p<irformanc(i MEMORY
with low cost and i mprovedreliaoility
By multiplexinq ro w a n d c o l i im n address rnpiits, th e M C M 6665A
requ>res only eight address lines and pcrniits packag>n<3 ir> standard
16 pm dual in (me packaqes Complete a<klrcss decodiriq is <lone on
chip w>th address latches iricorporatrd D >ta out is t.ontrollcd by CAS
allowing for greater system fl exib
ility
All inputs and o u t p u ts, inclu<hng clocks, are fi illy TTL 0 >rr>patible P SUFFIX
The MCM6665A incorporates a one transistor cell design and dynami( pkns>t( pncknnr
>6 CASk 6Qa
storage technrques
• Or g a nized as 65,.>36 Words of I B it
• Si n gle + 5 V Operation (+ 10%)
• Fu l l Power Supply Ranqe Capabilities
• Ma x i m um A ccess Time
L SUFFIX
MCM6665A 12 — 120 ns CI BAM>(' pncx/tok
>6
MCM6665A 15 — 150 ns < nsk sfw>
MCM6665A 20 = 200 iis
• Lo w P o w er Dissipation
302 5 mW Maximum (Active) (MCM6665A 151
22 mW Maximum (Stan<)by)
PIN ASSIGNMENT
• Th r ee State Data Output
• In t e r nal Latches for Ail<(ress and Data Inpiit N/C I• 16 >/ss
• Ea r ly W r i te Common I /O ( ' a p ability 15 i~A
• 16K o
Cmpatibl
e 128 Cycle, 2 ms Refresh 14
• RA S o nly Refresh Mode
RAN 13 AB
• CA S C on trolled Output
AO 12
• Up w a r d P>n Compatible from thc 16K RAM (MCM4116, MCM4c517)
• Fast Page Mode Cycle Time
• Lo w S o f t E rror Rate (0 1 % p e r 1 000 Hoiirs ISee Soft Error Testing) Al 10 As
>/CC A7

BLOCK DIAGRAM PIN NAMES

~ vss AO A7 Address Iiiput
P lt ' t , it < i t '
D Data ln
( ter i Memory tMel>lcf'/ Data Our
AO
ttt
Qt
Array 0 Aflak Read/Write input
\t t
0 BAS
W
0
c> Row Address Strobe
AI C1 BAS
B ow Diirou c i Bow Otto>dcr CAS Coliimn Address Strobe
E
ucc Power ( + 5 V)
A7 0 CAS
tQ Ml.flint/ tMcf>iofy ll:
CC uss Ground
A3 C
Q Arr,>y A ff t / tl
W (Ill s W
CQ
0
A4 Menioiy Metr>cry Bt I Bl-SH*
C
0
Qt
Array Qt Arr,>y 0> D ,>t,l Il i D This device contains circuitry to protect the
tf'
0> t
t inputs against damage due to h igh static
Bow Dccc<fei c> Bow D i < tidt r E 0 tl>I>tli v oltages or electric fields; however, it is
C
00 F Ci Dain O advised that normal precautions be taken to
A7 M fi f f t u f v Men>cry avoid appkcation of any voltage higher than
0
P tt'I t , l f I Arr;>y Array m aximum rated v o ltages t o t h i s h i g h -
( il l
impedance c>rcuit.
+ Bc>fash Fill>t.>lo(1 Available Oli MCM(k(»IR

«>Motoric< n IN(' >sez DS f>H63

i>>ru>Q<
t «noi 8/6>
 page D.S

• • •

ABSOLUTE MAXIMUM RATINGS (See Note) FIGURE 1 — OUTPUT LOAD

Rating Symbol Value Unit 5V
Voltage on Any Pin Relative to VSS
(except VCCI Vin Vout — 210 +/ 970 0
Voltage on VCC Supply Relat ive to VSS Vcc — )to i /
Q
Operating Temperature Range TA Q to e 7 0 'C
O
Storage Temperature Range Tstg — 65 to c 150 C
Power Diss ipation PD 10 I QQ pF' 12 kg
Data Out Current 'o,it riA

iNQTE Permanent device damage mav occur if ABSC. U E f ( A X I M U(vc RATINGS are ex
ceeded Functionai operation snould be restricted to RECOMMENDED OPERATING
CONDITIONS Exposure to higher than recommended voltages for ext i.ndcrd penods Includes Jig Capacitance
of time could affect device reliability

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperati irc. r,crige unless otherwise noted.l

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit Notes
Supply Voltage M CiM66Fi!>A IA 15 , 2 0 Vcc 45 50 55
VSS
Logrc I Voltage, All Inputs VIH 24 Vcc+ I
Logic 0 Voltage, All Inputs VIL — 1 0' 08 V
'The device will withstand undershoots Io the — 2 volt level wrth a maximurri per)so width of 20 ns at the — I 5 volt level This is penodically
sampled rather than 100% tested
DC CHARACTERISTICS
Characteristic Symbol Min Max Units Notes
VCC Power Supply Current (Standby) 'CC2 40 mA
VCC Power Supply Current
6665A 12, tRC = 250 ns 60
6665A 15 tRC = 270 ns iCC1 55 mA
6665A-20, tRC = 330 ns 50
VCC Power Supply Current Dunng RAS only Refresh Cycles
6665A-12, tRC = 250 ns 50
6665A-15, tRC = 270 ns iCC3 45 mA
6665A-20, IRC = 330 ns 40
VCC Powe Supply Current Dunng Page Mode Cycle for tRAS = 10 /csee
6665A 12, tpC = IR p = 120 ns 45
6665A-15, tpC = tRp = 145 ns I CC4 40 mA
6665A-20, tpC = tRp = 200 ns 35
Input Leakage Current ~VSS < V, < VCCi ll(Li 10
OutPut Leakage Current (CAS at logic I, VSS s Vout 5 VCC) 'OiLi 10 tcA
Output Logic 1 Voltage @ Io„, - — 4 mA -

VOH 24
Output Logic 0 Voltage g I o„ t -— 4 mA VOL Q4

CAPACITANCE (I = I 0 M H ) L T A = 25'C. VCC=. 5 V Periodicaily Sampled Rather Than 100% Tes ted)
Parameter Symbol Typ Max Unit Notes
Input Capacitance (AQ.A7), D CII pF
Input Capacitance RAS, CAS, WRITE C(2 pF
Output Capacitance(QI, (CAS = V)H to disable output) CO pF
NOTES I A l l voltages referenced to VSS
2 VIH min and V)L max are reference levels for measunng tirnin i) of rripiit signals Transition times are measured between V(H and
VIL
3 A n i n itial pairse of 100 tcs is required after power up followi d h v , i i iv 6 RAS c ycles before proper device operation is guaranteed
4 C u rrent is a function of cycle rate and output loading, maximum current is measured at the fastest cycle rate with the output
open
5 RAS and CAS are both at a logic I
6 The tr ansition time specification applies for all inputs sigricls l ii a ddition to meeting the transition rate specification, all input
signals must transmit between VIH and V)L lor between VIL ancf VIH) in a monotonic manner
7 Capacitance measured with a Boon(on Meter or effective cap,icitarice calculated from the equation C =
AV
page 0.6

• • •

AC OPERATING CONDITIONS AN D C H A R A C TERISTICS ( i l n i <l. Wiite, and Read Modify Wr te Cyciesl

t Full Operating Voltage and Temperature Rangr Uniess Otii</rwise Nnti)d, See Notes 2, 3, 6, arid Figure I )
6665A-12 6665A-15 6665A-20
Parameter Symbol Min Max Min Max Min Max Units Notes
Ra )do-i Ron<i cr W' ue C) cle i .r 2)o0 27n 33C '1 s 8o
Read '/Vr ' ., ' e T n i r- IHV. (' 255 280
' cease T)n)e " n r i Riiw A d o res 120
n c ' ; i" '
. '
- Ader - Stin t) 7= ') s 12
O.i'oi.t Butt e / n n t , r ''' ' pr. „
I( ,l F I
Row Address Strobe Precnarge T ime 'HP 120 ns
Row Address Strobe Pulse Widtli tf(AS 120 ns
Column Address Strobe Pulse Width (CAS f)0 I CCCF) 100FX ns
How to Column Strobe Lead Time IH(. I) 25 F)0 75 ns 13
Row Addiess Setup Time 'ASH i)s

Row Address Hold Time' IH/'<I I 20 25 ns

Column Address Setup Time (RS(' ns
Column Address Hold Time I( Al-I 35 45 ns
Column Address Hold Tim< Rr far<)need to HA.) (7<H 120 17
Transition Time fRise and Faii) 50 ns
Read Command Setup Tiine IHi ' ns
Read Command Hold mini< ns 14
Read Commarid Hold T ime Refereiiced to RA S tl(HI I 14
Write Command Hold Time tvVt I I 35 45 ns
Write Command Hold Time Referenceit to RAS t W (. I ' 95 120 17
Write Command P i ilse W i d t ti 'W I' 45 ns
Write Command to Row Strobe Lead Timr 'HWI 55 ns
Wnte Command to Column Strobe Lead T nie li W I 45 55
Data in Setup Time ns 15
Data in Hold Time 2 i 35 45 ns 15
Data in Hold Time Referenced to RAS II ) IIH 95 120 ns 17
Column to How StrobePrecharge Time '( HI' 10 . 10 ns
RAS Hold Time 75 ns
Refresh Period 'Rl St( 20 20 20 ms
WRITE Command Setup Time itV( .j — 10 10 ns 16
CAS to WHIIE Delay 'C(V() 45 ns 16
RAS to WRITE Delay 120 155 ns 16
CAS Hold Time 170 150 ns
CAS Precharge Tim<. (Page )Vtode Cycle Onlyl ')0 ns
Page Mode CycleTime I!/0 ns

8 T h e specifications for tRC (min), and tRWC (min) are used oiily to )nd)cate cycle time at whicfi proper operation over the full
temperature range IQ'C «TA «70'C) is assured
9 AC measurements t T = 5 0 ns
10 Assumes that IHCD« t RCp (max)
A ssun es '.hat IRCpx t q C p m a x i
12 Measured with a current load eouivalent to 2 TTL ( — 2CQ PA 4 m A ) i o ads and 100 pF with the data output trip poir ts set at
VOH =2 0 V and VOL =Q 8 V
13 O p e ration w i t hin the IRCp <n)ax) li ii t er sures ! nat t qA C ( m ax) <an be n et tHCp l'n ax i i s specified as a re'erence oc)nt only, if

tRCp s greats than the spec ifi ed tRCD<max) I i rr t, thr n access I ri e s c o n t rol ed r xclusive y oy ', A C
14 Ei',her tRRH or tRCH must be satislied lor a read cycle
15 These parameters are referenced to CAS leading edge in random write) eye(its and to WRITE leading edge in delayed wrrte or read-
modify wnte cycles
16 tw c s , t c w p a n d tRw p are not restrictive operating parametr rs They are inriuded in the data sheet as electrical characteristics
only, if tWCS ~ tWCS (m in), the cycle is an early wnte cvcl< ,)nd the) dat,i out pin w ill remain open circuit (high impedancel
throughout the entire cycie, if ICWp > (CWp (min) and (RWD a tRWD Imiri), the cycle is read write cycle and the data out will
contain data read from the selected cell, if neither of the abov( , i I » ii( « i n d)t)uns is satisfied, the condition of the data out (at ac
cess ti
me> is indeterminate
I AR mm — IA R = IRCD + I C A H
I DHR mm — I D H R = IRCD + I D H
IWCR m'n — IWCR = IRCD + I W C H
18 tof f (maX) defineS the t ime at WhiCh the OutOut aChieVeS the Oni ii < irr iiit <:nii<litiOn and iS nat referenCed tO OutPut VOI(age leVelS
 page 0.7

READ CYCLE TIMING

tRAS

V I H-
HAS
el(
I( SH IHP

tH( D 'HSH I( HP

'(..AS
CAS
VIL

(HAH
'A.' H (AS<' I('AH

VIH-
Addresse Row Col(rrrt •
VIL Address Addri ss

IRHH

(HCo h
V I H-
V I L-
t< A<
'HA(.

VOH Valid
Q (Data Oiitr Higtr 2
VOL- Data

WRITE CYCLE TIMING

IRC
tRAS
IAR
V I L-

(RSI-i (RP
tCSH
'RCD ICAS I< HP

Vt,
IRAH
tASR IAS( ICAII

Addresses VIH Row Column

Adrlress Address
VIL

ICWI
'WCS IWCH
VIH - IWP
VIL

IRWL
IWCH
IDS 'DH
VIH Valid
D (Data Iril
VIL Data

tPHR

VOH-
Q (Data Oot) Itrgh Z
VOL-

~~ SSD L A Se m i conductor Producte tnc

page D.S

PAGE MODE READ CYCLE

IRAS

HAS 'AR

'CSH IRSH 'RF'

I PL
IRCD 'CAS '(.AS
' I H-
CAS
VII
IRAH ICAH ICAH ICAH
P
IASR 'ASCM 'ASC

Addresses
Row Col C<tl Cni
V I L- A Add Add A(jil

iCAC 'CAC

IRAC 'CFF (OFF 'Pi F

VPH-
p (Data put) I-Ii Z
VOL-
IH( S

'RCS 'RCH IH('H

VIH
V I L-

PAGE MODE WRITE CYCLE

'HAS
VIH
RAS IAH
VIL
ICSH IRSH IRP
IPC
IRCD ICAS ICRP

VIH ICAS
CAS
VIL
IRAH ICAH I( Al< ICAH

IASR IASC IASC IASC

V I H- Ro Coi Col Col
Addresses w
d
Ad Add Add Ad(j
VIL
WCH 'WC H t'vVCH

ICWL I( I.VI

+IH
V L-
iWP 'WP 'WP
'DS
'WCR IOH IRWL
'DS IDH 'DS IDH~
V I H- Valid V,ilid Valid
D (Data lnl
Dare D,it,i Data
VIL
'DHR
 R//R-DNLY REFRESH CYCLE
IData in and Write are Don't Care, CAS is HIGHI

IRC
IRP

tRAS
RAS
VIL
I II P
tRAH
IASR

Addresses, Row Addri ss

AO-A6 ViL

READ-WRITE/READ-MODIFY-WRITE CYCLE

'RWC
tRAS
VIH
VIL
IRSH IRU
ICSH
IRCD ICAS
V I I-I-
VIL
'ASR
IRAtl
IASC ICAH
V I I-I Row Column
Addresses
VIL Address Addiess

IRWD 'CWL
IRCS 'CWD iRWL

VIH
VIL
IWP IQFF
ICAC

V Va id
0 IData Out) Hi<th Z
VOL- Data
IRAC
IDS IDH

V,i id
D I Data In)
VIL D,ita
page 0.10

• • •

TYPICAL CHARACTERISTICS

FIGURE 2 — RAS ACCESS TIME versus SUPPLY VOLTAGE FIGURE 3 — CAS ACCESS TIME versusSUPPLY VOLTAGE
1.3
12 CD
( I 0- tRAC(BVCC - 5 V. (A - 25'C) (7.0-tCACIIVCC-5 V, TA-25'Cl
x
1.2
11
CD

U 1.1
X
10 TA-70'C
I-
I/O
I/O TA-70'C
xD o 1.0
rn 0 9 TA - 25'C
Q
u 0.9 TA-25'C
TA-O'C
0.8
TA-O'C
0.8
4 4.5 5 5.5 6 4,5 5 5.5
VCC. SUPPLYVOLTAGE(VOLTSI VCC, SUPPLYVOLTAGE(VOLTSI

FIGURE 4 — RAS ACCESS TIME versus FIGURE 5 — CAS ACCESS TIME versus
AMBIENT TEMPERATURE AMBIENT TEMPERATURE
1.2 1.2
ro (I.O-IRACOVCC-4.5 V, TA-25'CI CD
II.O-ICACIIVCC-4.5 V, TA-25'Cl
1.1 1.1

CD

I
1.0 1.0
K
I
E

0.9 u 0.9

gc., 0.8 ~ 0,8

07 07
0 20 40 60 80 20 40 60 80
TA,AMBIENT TEMPERATURE I'Cl TA, AMBIENTTEMPERATURE('CI

FIGURE 6 — RA%, W INPUT LEVEL versus SUPPLY VOLTAGE FIGURE 7 — CAS, W INPUT LEVEL versus SUPPLY VOLTAGE
2.5 2.5

2.0 -VIH Min 2.0

I/I I/I
VIH MIn
I-

cx 15 -VIL Max I-'D I5

)
I
VIL Max-
10 ~ 10

0.5 0.5
TA-25'C TA-25 *C

5 5 55 6 4 4.5 5 5.5
VCC, SUPPLYVOLTAGE(VOLTS) VCC. SUPPLYVOLTAGEIVOLTSI
 page 0.11

• • •

TYPICAL CHARACTERISTICS I continued)

FIGURE 9 — ICCI SUPPLY CURRENT

FIGURE 8 — ICCI SUPPLY CURRENT versus CYCLE RATE versus SUPPLY VOLTAGE
50 t 50
VCC-5.5 V TA-25'C
tRP- 120 ns IRC
TA-25'C 290 ns
E 40 E 40 tCAS -160 ns
I
cu
cc
30 Q 30

20 20
) )
I-
o
C 1000 ns
10 - 10

2 4 4.5 5 5.5 6
I itRC, CYCLERATE IMHzt VCC. SUPPLYVOLTAGEIVOLTSI

FIGURE 10 — ICCI SUPPLY CURRENT FIGURE 11 — ICC1 SUPPLY CURRENT

versus SUPPLY VOLTAGE versus AMBIENT TEMPERATURE (min tRP)
50 50 T ~ C
VCC-5.5 V, tRP-120 ns
IRC
TA-25'C 290 ns
40 tRP-120 ns E 40 'RC
I-
290 ns
cu
cc
CK
o 30 ~
o 30
500 ns
ll. 500 ns
o.

20 20
I-
1000 ns
•C C
000 ns
10 o 10
o

4 4.5 5 5.5 6 20 40 60 80
VCC, SUPPLYVOLTAGE(VOLTS) TA, AMBIENT TEMPERATURE('Cl

FIGURE 12 — ICC1 SUPPLY CURRENT

versus AMBIENT TEMPERATURE (min RASI FIGURE 13 — ICC2 SUPPLY CURRENT versus SUPPLY VOLTAGE
50

IRC E
E 40
I VCC-5.5 V 290 ns 3
tRAS-160 ns cc
30
500 ns 2
cn
20 co
)
I-
«C TA-25'C
1000 ns I
o 10
o

20 40 60 80 4 45 5 55
TA, AMBIENTTEMPERATURE ("CI VCC. SUPPLYVOLTAGE(VOLTS(
page D.12

TYPICAL CHARACTERISTICS (continued)

FIGURE 14 — ICC2 STANDBY CURRENT
versus AMBIENT TEMPERATURE FIGURE 15 — ICC3 SUPPLY CURRENT versus CYCLE RATE

50

x t
E
vcc-55v vcc-5.5 v TA-25'C
40 IRP-120 nx
3
CK

LJ

co
2
IXl

<n
10

0
20 40 60 60 2 3
TA. AMBIENT TEMPERATURE
('C) IltRC, CYCLERATE(MHt)

FIGURE 16 — ADDRESS INPUT LEVEL versus SUPPLY VOLTAGE FIGURE )7 DA T A I N PUT LEVEL versus SUPPLY VOLTAGE
25 25

CI>
20 l
VIII Min
ox
20 VIH Min

I
ca15 cx 1.5 VIL Msx
) )J
VIL Max
1.0 i ~ I.O
o o.

05 0.5
TA-25'C TA-

4 45 5 55 60 4 4.5 5 5.5 6
VCC. SUPPLYVOLTAGEIVOLTSI VCC, SUPPLY
VOLTAGEIVOLTS)

SOFT ERROR TESTING

The storage cell depletion regions as well as the sense
amplifier and its associated bit lines are susceptible to charge
collection of electrons from an alpha "hir " H o wever, the
susceptibility of these vulnerable regions varies Depleted
storage cells are vulnerable at all times, whereas the sense
amplifiers and associated bit lines are susceptible only dunng
the small portion of tlie memory cycle lust prior to sensing
Hence, an increase in the frequency of dynamic RAM access
will cause a corresponding increase in the soft error rate
To take this memory access dependency into account, the
total soft error rate profile includes a cycle time component
The soft error rate due to bit line hits at the system's memory
cycle rate is added to the soft error rate due to storage cell
hits which are not frequency dependent Figure 18 illustrates
the i mpact t h a t f r e q uency o f a c c ess h a s o n t he
MCM6664A/MCM6665A overall soft error rate
Under normal operating conditions, the die will be expos
ed to radiation levels of less than 0.01 alpha/cm2/hr. Ac-
celerated soft error resting data is generated from at least
three high-intensity sources having an Alpha Flux Density
range of 1 x 105 to 6x 105 lalpha/cm2hr) placed over un-
coated die. Figure 19 shows th'e soft error rate for a given
alpha I'ux density at a cycle rate of 100 kHz The accelerated
data of Figures 18 and 19 pro)ect tnat the soft error rate for
package level radiation will be less than 0 1%/1000 hours.
SYSTEM LIFE OPERATING TEST CONDITIONS
1) Cycle time. 1 microsecond for read, wnte and refresh
cycles
2) Refresh Rate 1 millisecond
31 Voltage. 5.0 V
4) Temperature: 30' C ~ 2' C (ambient temperature inside
enclosure)
5) Elevation; Approximately 620 feet above mean sea level
6) Data Patterns: Write the entire memory space sequential-
ly with all "1 "s and then perform continuous sequential
reads for 6 hours. Next, write the entire memory space
with all "0"s sequentially and then perform continuous
sequentia, 'reads for 6 hours, Next, go back to the all "1 "s
pattern and repeat the sequences all over again.

MO T O R O L A Semi c o n ductor Products Inc

 page 0.13

• • •

FIGURE 18 — ACCELERATED SOFT ERROR FIGURE 19 — SOFT ERROR RATE versus

versus CYCLE TIME ALPHA FLUX DENSITY
103 10/
106
I- 100 (rHr
cc I Q5 25cC
ypp-40 y Cl
ypp-4 5 y
D 102 25"C cr I p4 ri Source TH230
Uncoated pie o
Uncoated Qre
n Source. TH230 I p3
3 1 0 5 nrcm2 Hr
I
cx 10
(cell hitsl 102

(Q
(bil (ine hi(sl
I NOTE: The Alpha Flux Pensrty
co
that the die is sub(ected
to with a die coat is less
10-1 I0 (02 103 104 10-1 than 0.01 a/cm2 Hr
CTCLE TIME(ps(
10-2
lp 10-2 10- 1 I (Q 102 ( 03 104 105 (06
A(PHA FLUX OENSITY ( rrcm> Hrl

CURRENT WAVEFORMS
FIGURE 20 — RAS/CAS CYCLE FIGURE 21 — LONG RAS/CAS CYCLE
—5 5
V
RAS V RAS
Q
5
CAS V
V CAS
—Q Q O

— 8Q

60
mA
icc — 4Q
— 4Q icc
n /r
2Q 2Q

—Q
I
5Q ns/Div Time (nsi 5Q ns/Div Time (ns)

FIGURE 22 — RAS ONLY CYCLE FIGURE 23 — PAGE MODE CYCLE

—5 —5
V RAS V
RAS
—Q Q

CAS —5 CAS 5
V V
Q c>
Q
co
n
SQ
) I-
— 6Q 6Q )
mA mA
Icc 4Q icc 4Q

— 2Q — 20

5 Q ns/ D v Tir e i n s ' 5Q risi Div T n-e (r si

page 0.14

Ql

C
0
0
CI
D Cl
CO — OO
0 Ul CO
C, CO
0 0

o\ IO 0
Ol Ql
O ) CO

CO
0 0
O O.
0
D Ql
N 0
Ql
apoaaij otunIog
Q
tll tc 9IQZ IO 1
0
Ql O
ca
IT
(3

O
hc
O
O
dt Q Ql
D 0
CO 0 QQ 0
IQ 0 tQ IJ Ql
N N Ql N
Z Ol TO OI OI OQ CO
0
CO 5 CO CO 5 Ol
0 tc 0 Ol
IT IT

U
Z
O
I2 0

IT

W
0
0
0 w
'D
0 0
<COO

S
C
/. 0
I/I
0 0 D
CC 0 Q
D

CO
0h
0
V Ql IO UI
Ql
0 D Tl Ql
VI
0
D ~ E
on< 0 CQ
2
Ql
X
Ql
D
0 OQ D
0
Q I
IO
0 0 zW
IO IC
0 0
IT
O/ 0
0

• •
DEVICE INITIALIZATION
Since the 64K dynamic RAM is a single supply 5 V only
device, the need for power siipply sequencing is no longer
required as was the case in older generation dynamic RAMs
On power-up an initial pause of 100 microseconds is required
for the internal substrate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles of the row address strobe (clock) to
initialize the various dynamic nodes internal to the device
Dunng an extended inactive state of the dev>ce (greater than
2 ms with devicepowered up) the wake up sequence (8
active cycles) will be necessary to assure proper dev>ce
operation. See Figures 25, 26 for power on characteristics of
the RAM for two conditions (clocks act>ve, clocks inactive)
T he row a ddress strobe is t h e p r imary " c lock" t h a t
act>vates the device and maintains the data when the RAM is
in the standby mode T his is the main feature that distin-
quishes it as a dynamic RAM as opposed to a statii; RAM A
dynamic RAM is placed in a l<>w power standby mode when
the device receives a positive-going row address strobe. The
vanation in the power dissipation of a dynamic RAM from
the active to the standby state is an order of magnitude or
more for NMOS devices. This feature is used to its fullest ad-
vantage with high density mainframe memory systems,
where only a very small percentage of the devices are in the
active mode at any one time and the rest of the devices are in
the standby mode. Thus, large memory systems can be
assembled that dissipate very low power per bit compared to
a system where all devices are active continuously.
ADDRESSING THE RAM
The eight address pins on the dev>ce are time multiplexed
with two separate 8-bit address helds that are strobed at the
beginning of t h e m e mory cycle b y t w o c l ocks (active
negative) called the row address strobe and the column
CURRENT WAVEFORMS
FIGURE 25 — SUPPLY CURRENT versus SUPPLY
VOLTAGE DURING POWER UP, RAS, CAS= Vcc
Vcc
mA
icc —0
0 5»s/D>v Time >us)
page 0.15
address strobe. A total of sixteen address bits will decode
one of the 65,536 ceil locations in the device. The column
address strobe follows the row address strobe by a specified
minimum and maximum time called "tRCD," w h ich is the
row to column strobe delay This time interval is also referred
to as the multiplex w>ndow which gives flexibil>ty to a system
designer to set up his external addresses into the RAM
These conditions have to be met for normal read or write
cycles. Th>s >n>tial portion of the cycle accomplishesthe nor-
mal addressing of the device There are, however, two other
vanat>ons in addressing the 64K RAM: one is called the page
mode cycle (described later) where an 8-bit column address
field is presented on the input p>ns and latched by the ~A
clock, and the other is the RAS only refresh cycle (descnbed
later) where a 7-bit row address field is presented on the in-
put pins and latched by the RAS clock In the latter case, the
most s>gnif>cant bit on Row Address A7 (p>n 9) is not re-
quired for refresh. See bit address map for the topology of
the cells and the>r address selection
NORMAL READ CYCLE
A read cycle is referred to as normal read cycle to differen-
tiate if f rom a p age mode-read cycle, a read while-wnte
cycle, and read-modify write cycle which are covered in a
tater section
The memory read cycle beg>ns with the row addresses
val>d and the TIAS clock transitioning from VIH to the VIL
level. The ~ clo c k must also make a transition from VIFI to
the VIL level at the specified tRCD t>ming limits when the
c olumn addresses are latched. Both the ~RA a n d ~ A
clocks trigger a sequence of events which are controlled by
several delayed internal clocks. Also, these clocks are linked
in such a manner that the access time of the device is in-
dependent of t h e ad d ress multiplex window. T he o n l y
stipulation is that the ~AS clock must be active before cr at
FIGURE 26 — SUPPLY CURRENT versus SUPPLY
VOLTAGE DURING POWER UP, RAS, CAS = VSS
Vcc
10
mA
icc 5
I I
0,5As/Div Time l»s)
page D.16
• • •
the tqCp maximum specification Ior an access (data val idl
f rom the RAS clock edge to be guaranteed (tqAC) I f t h c
tqCp m a ximum c o ndition is no t m e t , t h e a c cess (tCAC)
from the CAS clock active transition will determine read ac
cess time The external CAS signal is ignored until an iriter
nal RAS siqnal is available, as noted in thc f i iri<.tional block
diagram, Fiqure 24 This gating feature on the CAS clock will
allow the external CAS siqnal to become active as soori as
the row address liold time (tRAHI specificatiori h,>s been mct
and defines thc tqCp rn>ntrnum speuficatiori T he. time dif
terence betw eeri t q C p m i n i r n ii m an d t q C p 111'1xlf1>lint t.'drt b<i
used to absorb skew delays in sw itct>inq the address bus
from row to c o l umn addrlfsscs arid in gcncrat>nq the CAS
c I ock
Once the clocks have t>i>come active, they niust stay active
for thc minimum I t q A S I p e riod fo r th e RA S c lo<.k arid thc
m inin>un> (tCAS) period fnr the. CAS tilock T h « R A S c l o c k
must stay irial.tiVe fnr the minimum itqp) tirni. T lie former >s
for thc comp(<'ttor> of the eye(i> in progress, ,ind the latter is
for the dev>u. internal circuitry to t><i precharrlcd f<>r th<i next
active cycle
Data out rs not let<.hit<i and >s v,>lid as >orig as the CAS
clock is act>ve, tl>e output will switch to the three statff mode
when thc CAS cloi:k goe" ir>active f h c C A S c l ock can r«.
ma>ri activt> for a m a x>mtirn of 1 0 r>s (t( RI>» r>t<> th<i r>«xt
cycle To perform , i r<ad cycle, the write (Wl input must b<i
held at the Vill li'.v«l from the tirn<> tt>t CAS clo t:k rr»,k>, >t,
active. tref>sit>or> ( IRCS) to I ti c t l nlc w h <in >1 tl >ns>t>or>s lrl'to
t l«i in;ictiv « ( t q C H ) r n o d i i
WRITE CYCLE
A write cy<.'le is sirntlar to a re >d cycle <rxc«pt tl>at lhc Write
(W) clock must go active (Vl( l«vel) at or before th<' CAS
c lock qoes active at a m i n i mu m t W C S t i rrii. I f t h c a b o v e
f >onrlrtior»s mfit, then the i yr;lt >ri lir<«lr«ss is ref«r r<>d to a:
early wrrtt> cycl« ln an e<trly wr>le <.yclc, tl>c wr>tc clock ar>d
thc data >n >s r«f<.r<.'neo<i to the .>i:t>vc trar>sitiori <>f tl>t CAS
«lock «dqc There are two i mportant p,t r,irricti rs w it h r e s p e c t
to th e w r i t e « y e ll > t h r c o t > in>n «trot>if t<l w r i t i I « .,><l tirr»i
i tCWL) arid t h i . rtiw s t r n l i E ti l w r i t <i l«il<t tir>ill (t q W L I 1 h cs i f
dc(inc t h « m i n i r ni>rri tirrii. tii,it R A S , i r i d C A S c l o<>ks n«c<t to
b c active aft<.r thc w r i t « u p f >ratiori h >s started (W c l o<.k ; i t
VIL level)
I t >s also puss>ble tn pi>rf<>rrr» I >te write cycle F o r t h i s
cycl<.' tlie write clock ts activ,>ted >ftcr tile CA S q oes low
whi«li is beyond t W C S m i n i m ii m t rm c T i l l>» th<. par af»et<fr»
tCW( an d t q W L m u s t b e satisifed before terminating this
cycle The difference between an early write cycle and a late
write cycle is that in a late write I'y<.'Ic the write (Wl <.lock r.;sri
occiir m uc h la ter ill t im«. wttli respect to th e a< tive trarisitiori
o f th e C A S c l o c k I h i s t > rt>c could b c Ei s l o ri g a s 1 0
microseconds — It qW L i tq p t 2 T( j
At the st >rt of a write cycle, the data out is in a three stat<.
< .ondition an d r e m a ins ir>active t h ro i i q h ou t t h e c y <.le T h t .
data out remains three state becaus«, th«. active transition
of thc write (W) clock prcver its tl>ri CAS clot.k (lorn er>abliriq
tl>«. dat > out butlers as noted in Funct>or>al Block praqrarri
The three-state condition (high impedance) of the Data Out
Ptn during a write cycle can be effectively <ft>l>zcd ir> a system
that has a common input/ o u t put bu s I h e only stipiilation is
tt>at the system usE. only early writ«. mode op«r,itioris for all
wr>te cycles to avoid biis contentior>
READ-MODIFY-WRITE AND READ-WHILE-WRITE CYLES
As the name implies, both a read and a wnte cycle is ac
complished at a selected b>t during a single access The read
modify write r:ycle is similar to the late wrrte cycle d>scussed
above
For the read modify write cycle a normal read cycle is in
itiated with the write (Wl clock at the V(H level iintil the read
data occurs at the dcv>cc access tinie (tqAC ) A t t h i s t ime
tlic write (W) clock is asserted The data in is setup and held
with resp<<.t tO the active edge of the write clock The cycle
described assiirnes a ~ero modify time between read and
write
A riother var>ation o f t h e r e a d m o d ify w r ite c y cle i s t h e
r ead while wr>t« c y c l e For t t> r s c y c le , t h c f ol l o w i n g
p arametiirS ltqWD , t C WD ) play an important role A r e a d
while write cycle starts as a normal r«a<f cycle with the write
(W) clilck b e ing a sserted at m i n irriurn t q W p o r r n i n irnum
tCWp tim r „ d e p ending upon the application T hrs results in
star tinq a write <>peratiori to th e selected cell even before
d ata out oc c iir s T l i e rr»riimum specification on t q W p a r i d
tCWp ass iircs tliat data nut do«s occur I n t his case, the
data rri >s s«t up with respect to write (W) clock active edge
PAGE-MODE CYCLES
l'aqc mod<>ulii>ratioti >liow. f aster successive data opera
ttofis at th c 2 56 r. oliirnn I<><.atioris P a ge a c c ess (tCAC) r s
typic;illy h,>lf the regular ~RA. clock access (tqA c) ori tl ie
Motorola 64K ifynarriic RAM p a g e mode operatron cons>sts
o f holdinq tfie RAS clock i i : tive while cyclrng the ~ A c (o c k
t o ai:cr.ss th«. i:oliir»ri l o c ,i tions d e t e r m ined b y t h e 8 b i t
column ar'<lrr» s fiel<t Ther«are two controlling factors that
limit the accE>ss to a(1256 co(un>n locations in on« ~RA clock
active operation I h c s c arc the refresh interval nf the devi<.e
( 2 ms/ ) 2 8 = 15 6 microseconds) arid the max>mum active
tirr>e speci(«.at«in fo r t l i e ~RA cl o c k ( 1 0 m i c roseconds>
Since 10 microseconds is thc smaller value, th<. maxirniim
sp<'cif«»>trnr> <if tl>i.' RAS I:lock or> t>rr«> rs th<'. Iirr»t>ng factor
of the n u n i birr of s a g>ter>Ital page access<.s possible f c n
rnicroseci>nds w i t ( p rt t v « l c ( > p p r o x i n i a tel y ( 1 0 mi cr o
scl ond 1I p>qc modt. eye lr t>n><il 5() su«cess>v<. page accesses
for every row address selected before the RAS clock is reset
I h<. page cycle is,>(ways initiated w>th a row address heing
p rovided and latched t>y the RAS clock, followed by t h e
colurnr> address arid CAS clock F rom the timing rllustrated,
thc initial cycle is a normal read or write cycle, that has been
previously described, followed by t he s horter CAS cycles
(tppi T h e CAS cycle time (tpC) consists of the CAS clock
actrve time (tCAS), and CAS clock precharge time (tCp) and
twu transitions In addition to read and write cycles, a read
modify write cyr le can also be performed in 4 page mode
operation Fo r a read mod>fy wr>te or read while write type
cycle, the conditions normal to that mode of operation will
apply in t h e p ag e m od e a ls o T h e p a g e r f iode c y cles il
lustrated show a s«ries of sequential reads separated by a
series of sequential writes T h is is lust one mode of opera
t>ori In pract><;e, any combrnation of read, wr>te and read
modify write cycles can be p e rformed to s u>t a part>cular
,>pplication
REFRESH CYCLES
I bc dynar>iic RAM design is based on capau tur c l iarqe
s torage fo i e a<.ti btt iri t h e a r r,>y T h i s r.barge w il l t i »i d t o
 page D.f 7

degrade with time and temperature Therefore, to retain the
correct information, the bits need to be refreshed at least
once every 2 m s T h i s i s a c complished by sequentially
cycling through the 128 row address locations every 2 ms, or
at least one row every lb.6 microseconds A riorma! read or
write operation to the RAM will serve to refresh all the bits
(256l associated with that particular row decoded
RAS Only Refresh — When the meniory component is in
standby the ~RA o nly refresh scheme is employed This
refresh method performs a RAS only cycle on all 128 row
addresses every 2 ms The row addresses are I/itched in w ith
the RAS clock, and the associatr.d internal row locations are
refreshed As the heading implres, the CAS ciock is not re-
quired and should be inactive or at a VIH ievel Io conserve
power

PIN ASSIGNMENT COMPARISON

MCM4116 MCM4517 M C M6632 A

VBB I• 16 Vss N/C I• 16 vss REFRESH I• le vss
15 CAS 15 CAS 2 15 CAS
14 14 14

RAS 13 A6 RAS 13 A6 RAS 13 Ae

AO 12 A3 AO 12 A3 AO 12 A3
A2 A4 A2 A4 A2 ll A4
Al 10 A5 AI 10 Al / 10

Voo VCC Vcc N/C Vcc 6 9 A7

M C M6633A M C M6664A M C M6665A

N/C I• 16 VSS REFRESH I• 16 Vc s N/C I• 16 Vss
15 CAS 15 CAS 15 CAS
14 14 14

RAS 13 A6 RAS 13 A6 RAS 13 Ae

AO 12 A3 AO 12 A3 AO 12
A2 A4 A2 A4 A2
Al 10 A5 Al 10 Al 10 Ae
Vcc A7 vcc A7 Vcc A7

PIN VARIATIONS

PIN NUMBER MCM4116 MCM4517 MCM6632A MCM6663A M C M6664A MCM6665A

VBB( — 5 V) N/C REFRESH N/C REFRESH N/C
Vppl+ 12 Vl Vcc '/cc Vcc Vcc Vcc
VCCI + 5 VI N/C A/ A7 A7 A7
page D.18

• • •

PACKAGE DIMENSIONS
MI L L IME TERS INCHES
OI M MIN MAX MIN MAX
20.07 20.57 0:790 0.810
711 762 28 0 300
L SUFFIX 2.67 4.19 0.105 0.165
CERAMIC PACKAGE 0.38 0 53 0.015 0.021
CASE 690-13 0.76 I 52 0.030 0.060
2. 54BSC 0.100 BSC
0. 76 1.78 0.030 0.070
0 20 030 0 008 0 012
318 5.08 0.125 0.200
7.62BSC 0.300BSC
10n 10"
0.38 I 52 0.015 0 060

NOTES
I A A • D 6 ARE DATUMS
2 T I S SEATING PLANE
3 POSITIONAL TOLERANCE I OR LEADS (D).

4. DIMENSION L TOCENTER OF LEADS

WHEN FORMED PARALLEL
5 DIMENSIONING ANO TULE RANGING
PER ANSI Y)4 5, 1973.

MILLIMETERS INCHES
f DIM MIN MAX
18,80 21 34
MIN MAX
0. 740 0,840
6.10 6.60 0.240 0.260
P SUFFIX 4.06 5.08 0. 160 0. 200
PLASTIC PACKAGE 0 38 053 0.015 0.021
~F ~ g OPTIONAL LEAD CASE 646 05 1.02 1.78 0.040 0.070
CONFIG. (1, 8, 9, & 16) 2.54 BSC 0.100BSC
A 0 .38 2 . 4 1 0.015 0.095
0.20 0 . 38 0.008 0,015
3.43 0.135
7.62 BSC 0.300BSC
0 10o 10c
NOTES 0 .51 1 . 0 2 0.020 0. 040
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION ATSEATING
~r--J PLANE AT MAXIMUM
PLANE MATERIAL CONDITION.
DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL
3. DIMENSION "8"DOES NOT
INCLUDE MOLD FLASH
4. "F" DIMENSION ISFOR FULL
LEADS "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
I, 8, 9, and 16).
5 ROUNDED CORNERS OPTIONAL
 page 0.19

MCM6666A BIT ADDRESS MAP

Row A ,ldiess A7 Ati A5 A4 A3 A2 A l A Q

Col i » A d o e sv A/ A6 O' A 4 A 3 A? Al A O Column Addresses

Raw Hex Oec A7 A6 A3 A4 A5 A2 Ao A I

FE 254 I 1 Q
FF 255 I I I I
FC ? 52 I I 0 0
FD 253 I Q 1
FA 250 1 0
FB ?51

F9 /49 0

CQ 192 0 0 0 0
193 0 0 0
BF 191 I 0 I 1
BE 190 I 17 1 1 I I 1 0

ll
82 130 0 0 0 0 0 1 0
Bi 1 29 0 0 0 0 () 0
BQ 128 o n 0 o ii o 0
17 /E 126 0
c /r i? O 0
E 7C 124 0
o

1? 66 0 1 0 0 G 0 0
43 6/ 0 1 0 0 0 U
4Q lvj 0 1 0 0 n n 0 0
41 6, 0 1 0 0 0 0
31 63 I' Q I 1 I 'I

li

ID 61 i il 1 1

I 0 Q 0 ( i il Q
03 0 0
0? 0 0 0

U 0 I/ U 0 U
i
4t .) 2t'oI ' o S
Z

O O O O O
O O

O O O O U ' O O

o c» o o

O O O O O O

Data Storl 0 = Din e ADx e A I Y

Column Row
Address Address Dsts
Al AO Stored

0 True
0I
inverted
0I1 Inverted
0I
True

Motorola reseives the right to make changes to any products herein to imprave relrab/lity funct/an oi design Motorala does not assume any liability ansing
oul af the applicatian ar use of any product or circuit described herein, neither does it convey any license under its palenl rights nar Ihe nghls ol others

3501 ED BLUESTEIN BLVD, AUSTIN TEXAS 78721 • A SUBSIDIARY OF MOTOROLA INC

Page D.20
 Page 0.21

intei'
8085A/8085A-2
S INGLE CHIP 8-BIT N-CHANNEL MICROPR O C E S S O R S

• Single +5V Power Supply • Fo ur Vectored Interrupt Inputs (One is

• 1 00% Software Compatible with 8080A non-Maskable) Plus an 8080A-
compatible interrupt
• 1.3 assInstruction Cycle (8085A);
0.8 ps (8085A-2) • Serial In/Serial Out Port
• On-Chip Clock Generator (with External
• Decimal, Binary and Doubie Precision
Crystal, LC or RC Network)
Arithmetic
• On-Chip System Controller; Advanced
Cycle Status Information Available for • Direct Addressing Capability to 64k
Large System Control Bytes of Memory

The InteIBT 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction set is 1008% software compatible
with the 8080A microprocessor, and it is designed to improve the present 8080A s performance by higher system speed
Its high level of system integration allows a minimum system of three IC's I8085A i CPU i, 8156 i RAM/IO i and 8355/8755A
i ROM/PROM/IOi I while maintaining total system expandability. The 8085A-2 is a faster version of the 8085A.
The 8085A incorporates all of the features that the 8224 iclock generatori and 8228 isystem controller(provided for the
BOBOA, thereby offering a high level of system integration.
The 8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The
on-chip address latches of 8155Y8156/8355/8755A memory products allow a direct interface with the 8085A

INTA RST6 5 TRAP

R SI 5 RSTT 5 S ID SD D

INTERRUPT CONTROL SERIAL I,O CONTROL

ACCUMULATOR TEMP REG INSTRUCTION

18) (81 REGISTER 8 1

8 L A II
FLIP I LOPE
B
REG REG
ARITHMETIC INSTRUCTION D (8' 5 8
LOGK' I(I CODE R REG REG
UN( I AN 0
H ( 81 L 81 RE G IS T5 R
MACHINE
IALUI ('YCLE REG REG ARRAY
8 I NCODING
STACK POINTER
61
PROGRAM COUN T ER
POWER 5Y IKK'REMENTER'DECREMENTER
SUPPL Y G ND
ADDRESS LATC »8

X( CLK ADDRESS BUFFER DATA(ADDRESS BUFFER (Bi

RFSET
XT GEN STATUS DMA

CLK OUT RD WR ALE Sp S, IO M HLDA RESET OUT

A 8-8 8 A DI A D p
READ'Y HOLD RESET IN
ADDRESS BUS ADDRESS/DATA BUS

Figure 1. 8085A CPU Functional Block Diagram

page D.22

8085A/8085A-2

XI I 40 vcc Symbol Function

X2 2 39 HOLD
RESET OUT 3 38 HLDA Si can be used as an advanced R/W
SOD 4 37 CLK IOUT) status. IO/M,So and Si become valid
S ID 5 36 RESET IN at the beginning of a machine cycle
TRAP 6 35 READY a nd remain stable t h roughout t h e
RST 7.5 7 34 IO/M cycle. The falling edge of ALE may be
RST 6.5 8 33 St used to latch the state of these lines.
RST 5.5 9 32 RD
INTR 10 8085A WR RD READ control: A low level on RD in-
INTA 11 30 ALE (Output, 3-state) dicates the selected memory or I/O
ADp 12 29 so device is to be read and that the Data
AD1 13 28 A15 Bus is available for the data transfer,
AD2 14 27 A14 3-stated during Hold and Halt modes
AD3 15 26 A13 and dunng RESET,
AD4 16 25 A12
WR WRITE control. A Iow level on WR in-
AD5 17 24 AI I
AD6 18 23 A10 (Output, 3-state) dicates the data on the Data Bus is to
AD7 19 22 A9 be written into the selected memory
vss 20 21 As or I/O location. Data is set up at the
trailing edge of WR. 3-stated dunng
Hold and Halt m odes and d u ring
Figure 2. 8085A Pinout Diagram RESET
READY If READY is high during a read or write
8 085A FUNCTIO NAL PIN D E FINIT IO N (Input) cycle, it indicates that the memory or
peripheral is ready to send or receive
The following describes the function of each pin: data. If READY is low, the cpu will
Symbol Function wait an i n tegral number of c l o ck
Address Bus: The most significant 8 cycles for READY to go high before
As AI5
bits of the memory address or the 8 completing the read or write cycle.
(Output, 3-state)
bits of the I/O address, 3-stated dur- HOLD HOLD indicates that another master
ing Hold and Halt modes and during (Input) is requesting the use of the address
RESET and data buses. The cpu, upon re-
c eiving the h ol d r e quest, will r e -
AD0 7 Multiplexed Address/Data Bus. Low-
(Input/Output, er 8 bits of the memory address Ior linquish the use of the bus as soon as
3-state) I/O address) appear on the bus dur- the completion of the current bus
ing the first clock cycle IT statei of a transfer. Internal processing can con-
machine cycle. It then becomes the tinue. The processor can regain the
data bus during the second and third bus only after the HOLD is removed.
clock cycles. When the HOLD is acknowledged, the
Address, Data, RD, WR, and IO/M
ALE Address Latch Enable: It occurs dur- lines are 3-stated.
(Output) ing the first clock state of a machine
cycle and enables the address to get HLDA HOLD ACKNOWLEDGE: Indicates
latched into the on-chip latch of pe- (Output) that the cpu has received the HOLD
ripherals. The falling edge of ALE is request and that it will relinquish the
set to guarantee setup and hold times bus in the next clock cycle. HLDA
for the address information. The fall- goes low after the Hold request is
ing edge ofALE can also be used to removed The cpu takes the bus one
strobe the status information. ALE is half clock cycle after HLDA goes low.
never 3-stated. INTR INTERRUPT REQUEST: is used as a
So, Si, and IO/M (Input) general purpose interrupt. It is sam-
Machine cycle status: pled only during the next to the last
(Output)
IO/M Si So Status clock cycle of an instruction and dur-
0 0 1 Memo r y write ing Hold and Halt states. If it is active,
0 1 0 Mem o r y read the Program Counter I PC I will be in-
1 0 1 I/O w r i t e hibited from i ncrementing and an
1 1 0 I/O r e a d INTA will be issued. During this cycle
0 1 1 Op co d e fetch a RESTART or CALL instruction can
1 1 1 Int e r r upt Acknowledge be inserted to jump to the interrupt
0 0 Halt service routine. The INTR is enabled
X X Hold and disabled by software. It is dis-
X X R e s et abled by Reset and immediately after
' = 3-state h igh impedance, an interrupt is accepted
X = unspecified
 page D.23

8085A/8085A-2

8085A FUNCTIO NAL PIN D E SCRIPTION (C ontinued)

~Sm bol Function Symbo

l Function

INTA INTERRUPT A C K N O W L E D G E : Is S chmitt-triggered i n p u t , al l o w i n g

(Output) used instead of and has the same c onnection t o a n R - C n e t w ork f o r
timing as R D d u r ing the Instructior power-on RESET delay The cpu is
cycle after an INTR is accepted. It can held in the reset condition as long as
be used to activate the 82591nterrupt r|ESET IN ppl d
chip or some other interrupt port.
RESET OUT Indicates cpu is being reset Can be
RST 5.5 RESTART INTERRUPTS: These three
RST 6.5 inputs have the same timing as INTR
(Output) used as a system reset. The signal is
synchronized to the processor clock
RST 7.5 except they cause an internal RE-
and lasts an integral number of clock
(Inputs) START to be automatically inserted
periods.
The prionty o f t h es e i n t errupts is
ordered as shown in Table 1 These Xi, Xz X i and Xz are connected to a crystal,
interrupts have a higher priority than
(Input) LC, or RC network todrivethe internal
clock generator X i can also be an
INTR. In addition, they may be indi-
vidually masked out using the SIM external clock input from a logic gate.
The input frequency is divided by 2 to
instruction.
give the processor's internal oper-
TRAP Trap interrupt is a noi,maskable RE- ating frequency.
(Input) START interrupt. It is recognized at
the same time as INTR or RST 5.5-7.5 CLK Clock Output for use as a s y stem
lt is unaffected by any mask or Inter- (Output) clock. The period of CLK is twice the
rupt Enable. It has the highest priority Xi, Xz input period
of any interrupt. ~See Table 1.i
S ID Serial input data line. The data on this
RESET IN Sets the Program Counter to zero and (Input) line is loaded into ac;cumulator bit 7
(Input) resets the interrupt Enable and HLDA whenever a RIIVl instruction is exe-
flip-flops. The data and address buses cuted
and the control lines are 3-stated dur-
SOD Serial output data line. The output
ing RESET and because of the asyn-
(Output) SOD is set or reset as specified by the
chronous nature of RESET. the pro- SIM instruction.
cessor's internal registers and tlags
may be altered by RESET with unpre- Vcc +5 volt supply
d ictable r e s ults. R E SET I N i s a Vss Ground Reference

TABLE 1. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY

Address Branched To (1)

Name Priority When Interrupt Occurs Type Trigger
TRAP 24H Rising edge AND high level until sampled
RST 75 3CH Rising edge ',latched
RST 6.5 34H High level until sampled.
RST 55 2CH High level until sampled
INTR See Note '2 . High level until sampled
NOTES:
il) The processor pushes the PC on the stack before branching to the indicated address.
i2i The address branched to depends on the instruction provided to the cpu when the interrupt is
acknowledged
Page 0.24
8085A/8085A-2
FUNC T IO N A L D E S C R IPTION
The 8085A is a complete 8-bit parallel central processor
It is designed with N-channel depletion loads and requires
a single +5 volt supply Its basic clock speed is 3 MHz
8085A or 5 MHz 8085A-2, thus improving on the present
8080A's performance with higher system speed Also it is
designed to fit into a minimum system of three IC's: The
cpu I 8085A, a RAM/IO 8156, and a ROM or EPROM/IO
chip 8355 or 8755A
The 8085A has twelve addressable 8-bit registers. Four of
them can function only as two 16-bit register pairs. Six
others can be used Interchangeably as 8-bit registers or
as16-bit register pairs The 8085A register set is as follows
Mnemonic Receister Contents
ACC or A A ccum u l a t or 8 bits
PC Program Counter 16-b i t address
BC,DE,HL Ge ne r a l -Purpose 8 bit s x 6 or
Registers, data 16 bits x 3
pointer HL
Stack Pointer 16-bit address
Flags or F Flag R e g ister 5 flags 8-bitspace
The 8085A uses a multiplexed Data Bus. The address is
split between the higher 8-bit Address Bus and the lower
8-bit Address/Data Bus D u ring the first T state .clock
cycle o f a m a chine cycle the low order address is sent
out on the Address/Data bus These lower 8 bits may be
latched externally by the Address Latch Enable signal
ALE D u r ing the rest of the machine cycle the data bus is
used for memory or I/O data.
The 8085A provides AD, WR, So, Su and IO/M signals for
bus control. An Interrupt Acknowledge signal (INTA) is
also provided, HOLD and all Interrupts are synchronized
with the processor's internal clock. The 8085A also pro-
vides Serial Input Data (SID) and Serial Output Data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three mask-
able, vector interrupt pins and one nonmaskable TRAP
interrupt.
I NTERRUPT AND S E RIAL I/ O
The 8085A has 5 interrupt inputs. INTR, RST 5.5, RST 6.5,
RST 7 5, and TRAP I NTR is identical in function to the
8080A INT Each of the three RESTART inputs, 5 5, 6.5,
and 7.5, has a programmable mask, TRAP is also a
RESTART interrupt but it is nonmaskable.
The three maskable interrupts cause the internal execu-
tion of RESTART I saving the program counter in the stack
and branching to the RESTART address if the interrupts
are enabled and if the interrupt mask is not set. The non-
m askable TRA P c a uses th e i n t e rnal e x ecution o f a
RESTART vector independent of the state of the inter-
rupt enable or masks See Table 1.
There are two different types of inputs in the restart in-
terrupts RST 5 5 and RST 6.5 are high level-sensIIIVe IIke
INTR I and INT on the 8080~ and are recognized with the
same timing as INTR. RST 7.5 is nsing edge-sensitive.
For RST 7.5, only a pulse is required to set an internal
flip-flop which generates the internal interrupt request
I See Section 5.2 7. The RST 7.5 request flip-flop remains
set until the request is serviced. Then it is reset auto-
matically. This flip-flop may also be reset by using the
SIM instruction or by issuing a RESET IN to the 8085A.
The RST 7.5 internal flip-flop will be set by a pulse on the
RST 7.5 pin even when the RST 7.5 interrupt is masked out.
The status of the three RST interrupt masks can only be
affected by the SIM instruction and RESET IN. I See SIM,
Chapter 5
The interrupts are arranged in a fixed priority that deter-
mines which interrupt is to be recognized if more than
one is pending as f o llows. TRAP — h i ghest priority,
R ST 7.5 RST 6 5. RST 5.5, INTR lo w e s t priority T h i s
priority scheme does not take into account the priority
of a routine that was started by a higher priority interrupt.
RST 5.5 can interrupt an RST 7.5 routine if the interrupts
are re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic events such
as power failure or bus error. The TRAP input is recog-
nized just as any o t her i nterrupt but has the highest
priority. It is not affected by any flag or mask. The TRAP
input is both edge and level sensilive. The TRAP input
must go high and remain high until it is acknowledged.
It will not be recognized again until it goes low, then high
again. This avoids any false triggering due to noise or
logic glitches. Figure 3 i l lustrates the TRAP interrupt
request circuitry within the 8085A Note that the servicing
of any interrupt T RAP, RST 7.5 RST 6.5, RST 5 5, INTR
disables all future interrupts e x c ept TRAPs u n t i l an El
instruction is executed.
I'NSIDE THE
8085A
EXTERNAL
TRAP
I NT E R ROPT
REQUEST TRAP
RESET IN SCHI I IT T
TRIGGER
RESET ~ TRA P
~I N TERR L I P T
'5V D CLK REQUEST
D
TP
C L I. A R
INTERNAL TRAP P f
TRAP
ACKNOWLEDGE
Figure 3. TRAP and RESET IN Circuit
The TRAP interrupt is special in that it disables interrupts,
but preserves the previous interrupt enable status. Per-
forming the first RIM instruction following a TRAP inter-
rupt allows you t o d e t ermine whether interrupts were
enabled or disabled prior to the TRAP. All subsequent
RIM instructions provide current interrupt enable status.
P erforming a R I M I n Struction f o l lowing I NT R o r R S T
5 5-7 5 w il l p r o v Id e c u r r en t I n t e r rupt E n a bl e s t a t us,
revealing that Interrupts are disabled See the descnp-
tion of the RI M i n struction in Chapter 5
The serial I/O system is also controlled by the RIM and
SIM instructions. SID is read by RIM, and SIM sets the
SOD data.
 Page 0.25

8085A/8085A-2

DRIVING THE X1 AND X2 INPUTS To minimize variations in frequency, it is recommended

You may drive the clock inputs of the 8085A or 8085A-2
with a crystal, an LC tuned circuit, an RC network, or an
external clock source. The driving frequency must be at
least 1 lvlHz, and must be twice the desired internal clock
frequency; hence, the 8085A is operated with a 6 MHz
crystal, for 3MHz clock „and the 8085A-2 can be operated
with a 10 MHz crystal (for 5 MHz clock). It a crystal is used,
it must have the following characteristics:
Parallel resonance at twice the clock frequency desired
CL load capacitance 5 30 pf
C, !shunt capacitancei < 7 pf
Rs !equivalent shunt resistance i < 75 Ohms
Drive level: 10 mW
Frequency tolerance: +.005% (suggested i
Note the use of the 20pF capacitor between Xz and
g round. T hi s c a p a citor i s re q u i red w i t h c r y s t al
frequencies below 4 MHz to assure oscillator startup at
the correct frequency, A parallel-resonant LC circuit
may be used as the frequency-determining network for
the 8085A, providing that it s f requency tolerance ol
approximately ~ 10% is acceptable. The components
are chosen from the formula:
that you choose a value for C«i that is at least twice that
of C,«, or 30 pF. The use of an LC circuit is not recom-
mended for frequencies higher than approximately 5 MHz.
An RC circuit may be used as the frequency-determining
network for the 8085A if maintaining a precise clock fre-
quency is of n o i m p o rtance V a riations in the on-chip
timing generation can cause a wide variation in frequency
when using the RC mode. Its advantage is its low com-
ponent cost. The driving frequency generated by the
circuit shown is approximately 3 MHz. It is not recom-
mended that frequerICieS greatly higher or lower than this
be attempted.
Figure 4 shows the recommended clock driver circuits.
Note in D and E that pullup resistors are required to assure
that the high level voltage of the input is at least 4 V.
For driving frequencies up to and including 6 MHz you
may supply the driving signal to Xt and leave Xz open-
circuited I Figue 4D I. If the driving frequency is from 6 MHz
to 10 MHz, stability of the clock generator will be i mproved
by driving both Xi and Xz with a push-pull source (+igure
4E!. To prevent self-oscillation of the 8085A, be sure that
Xz is not coupled back to Xi through the driving circuit.

2rrv L , Cexi 4 C i n i

X) 8085A
xraV
I
C IN T 470! 2
J I5pF TO
TK!2

200 F Xr

'20 pF CAPACITORS REOUIREO FOR

CRYSTAL FREQUENCY 4 Y IHx ONLY

A. Quartz Crystal Clock Driver

X2
8085A
Xi X2 LEFT FLOATING

D. 1-6 MHz Input Frequency External Clock Driver

NT
15PF
Circuit
Ltxr Ctxr

XP +5V
Low time > 40 ns
I
470!!
B. LC Tuned Circuit Clock Driver
Xi
8085A
X, +5V

470! '

X2

Xr

E. 1-10 MHz Input Frequency External Clock Driver

C. RC Circuit Clock Driver Circuit

Figure 4. Clock Driver Circuits

page D.26

8085A/8085A-2

GEN E R A T ING AN 8085A WAIT STATE The 8085A cp u c a n a ls o i n t erface with th e s t andard
memory that does nof have the multiplexed address/data
If your system requirements are such that slow memories bus It w il l req u ire a simple 8212 i8-bit latch i as shown in
or peripheral devices are being used, the circuit shown in Figure 8
Figure 5 may be used to insert one WAIT state in each
8085A machine cycle
The D flip-flops should be chosen so that
• CLK is rising edge-tnggered VTT VI L
P[
• CL E AR is low-level active
X, XI
Il1 RESET IN
TRAP NOLO
RSTT 8 RLOA

HSTE 5
8085A
HST'

INI H Si
wrA RESET '0
AOORI OOT
CLEAR 8085A OATH A L E R O V 8 iO I M ROV CL X
AEF CEK CLK OUTPUT CEK IO
8085A v vr r
"0" 'D' flEAOV IS I (8)
FIF F IF
PO R I
0
A
V'H
Po H I
Ro 81 58
l iL E
POHI
OI.TAI
HOOR
Figure 5. Generation of a Wait State for 8085A CPU IN
IO'EI Ilvli 8
OUT
As in the 8080, the READY line is used to extend the read RISE T

and write pulse lengths so that the 8085A can be used with
slow memory HOLD causes the cpu to relinquish the bus
when it is through with it by floating the Address and Data
Buses ALE
POP I
CL A

SYSTEM INTERFACE
8355/
The 8085A family includes memory components, which 8/55A
OATAI
are directly compatible to the 8085A cpu For example, a HOOR
system consisting of the three chips, 8085A, 8156, and
IOIM
PORI
8355 will have the following features
RFSF T

Vr
• 2K Bytes ROM
10 R
• 256 Bytes RAM
• 1 Timer/Counter VIS V,, Vi 8 PROI

• 4 8-bit I/O Ports 8,

• 1 6-bit I/O P o r t
V,,
• 4 Interrupt Levels
• Serial In/Serial Out Ports N OTE O Pi I O N A L C O N N E C T I O N

This minimum system, using the standard I/O technique F igure 6 . 8 0 8 5 A M i n i mum S y stem ( S t andard I / O
is as shown in Figure 6. Technique)
In addition to s t andard I/O, the memory mapped I/ O
o ffers an e f f i c ient I/ O a d d r e ssing t e c h n iqu e W i t h t h i s
technique, an area of memory address space is assigned
for I/O address, thereby, using the memory address for
I/O manipulation F i g ure 7 shows the system configura-
tion of Memory Mapped I/O using 8085A
 page D.27

8085A/8085A-2

8085A MINIMUM SYSTEM CON F IGU R A T ION

A8-15

ADD 7

ALE

8085A YCC
YCC
IO/)6
CLK
RESET DUI
READY
YCC

) TIMER AD AS- AD 10 I
RESET IN WR R D A L E CE IO M CE ALE P CLK RSTIRD Y
67 A IO 67

TIMER
OUT
8158 8355 [ROM + i/0]
[RAM + I/O + COUNTER/TIMER] OR
8755A [PROM+ i/0]

'NOTE OPTIONAL CONNECTION (6) (81 IS) (8) (SI

Figure 7. MCS-85'" Minimum System (Memory Mapped i/0)

l4~4
X) RESET IN
XT
TRAP RO LD
RST7 HLOA
RST6
RST5 8085A SID
INTR S,
INTA RESET
ADOR/ OUT
ADDR DATA ALE RO W T) IO/M A D YC L K

(8) IS)

10/M ICSI
WR
82)2 RD

DA TA

STAK'DARD
MEMORY

AODR NSI

(16)

CLK

RESET

IO M (CSI I/O PORTS

CONTROLS
WR
RD

DA7A
STANDARD
(70
ADOR

vcc
Ycc
Ycc

Figure 8. MCS-85™ System (Using Standard Memories)

page D.28

8085A/8085A-2

B ASIC SYSTEM T I M I N G TABLE 2. 8085A MACHINE CYCLE CHART

The 8085A has amultiplexed Data Bus. ALE is used as a M ACHINE CY C L E

STATUS CONTROL
io/M S 1 SQ RO WR INTA
strobe to sample the lower 8-bits of address on the Data
D PCDDE F F T C H (DF)
Bus Figure 9 shows an instruction fetch, memory read MELIDH Y RF AD I hl tt I 0
and I/O write cycle as would occur during processing of h (F h(DI) Y l / H I T E (h1)h' 0
the OUT instruction N o t e t hat during the I/Owrite and I D HFA D t )DH t 0
I 'D 0/RITE ( I D(Y I 0
read cycle that the I/O port address is copied on both the
ACK KDM/L L DGE
upper and lower half of the address DF I YTF) (INA) )
QUS fr)L) (Bl) DA D I 0
There are seven possible types of machine cycles. Which
ACK OF
of these seven takes place is defined by the status of the RST TRAP I I I I I
three status lines IIO/M, Si, SQ) and the three control HALT TS 0 0 TS TS
signals (RD, WR, and INTA). ISee Table 2,/ The status
lines can be used as advanced controls l for device selec-
TABLE 3. 8085A MACHINE STATE CHART
tion, for examplei, since they become active at the Ti
state, at the outset of each machine cycle. Control lines Status Er Buses Control
RD and WR become active later, at the time when the Machmc
transfer of data is to take place, so are used as command S tate S 1 , S QI 0/M Aa-Ate ADP-ADT RD,WR INTA ALE
lines. Tf X 1 1

A machine cycle normally consists of three T states, with T/ X X 0

the exception of OPCODE FETCH, which normally has ) )Yni r X X 0
either four or six T states Iunless WAIT or HOLD states Ts X X 0
are forced by the receipt of READY or HOLD inputs). Any 14 1 0' TS I 0
T state must be one of ten possible states, shown in Te I 0' TS 1 0
Table 3. Te 1 0' TS 1 0
TRESET X TS Ts TS TS I 0

THALT 0 TS TS TS TS 1 0
T»OLQ X TS TS TS Ts 1 0
0 L 4 0" TS H gh Impede ce
I Lo g "I' X U epee( ed

ALL t; » \ d d 02 d e d g d * h « c yc le l o f D A D I ct o
lt) .",; I l« g r c-Te of IKA mach, e c y cfo

raI hl l hl 1

CLK Ts Te Tl T/ Ts ' t

Ae-Afs PC (HIGH ORDER ADDRESS) (PC ' I) )O PORT

Ape.f
LQ 0 DE
CC)- -- WDOC3.
DATA FROI DATA FROM MEMORY
IO PORT

DAFA FO MEMORY
ADDRESS( MEMORY (I,O PORT ADDRESS) OR PERIPHERAL
I lg) RUCTIOfyl
ALE

RD

)O/hl

STATUS SiSo (FETCH) 10 (READ) 01 WRITE

Figure 9. 8085A Basic System Timing

 page 0.29

8085A/8085A-2

TABLE 4. ABSOLUTE MAXIMUM RATINGS'

Ambient Temperature Under Bias. ... . 0 C to 70'C 'COMMENT

T
.— 65 C to+150 C Stresses above those listed under Absolule Maximum Ratings" may cause
S torage Temperature . . .
. . . . . .

permanent damage lo the device This is a slress rating only and functional
Voltage on Any Pin operation of th e d e vice at t hese or an y o t her conditions above thoae
— 0,5V to +7V indicated in the operational sections of this specihcalion is not implied
W ith Respect to Ground. . . . . .

Exposure to absolute maximum rating conditions for extended penods

Power Dissipation 1.5 Watt may affect device reliabihty

TABLE 5. D.C. CHARACTERISTICS

(TA = 0 C to 70 C; Vcc = 5V +5%; Vss = OV; un ess otherwise specified)
Symbol Parameter Min. Max. Units Test Conditions

VIL Input Low Voltage -0. 5 +0,8

VIH Input High Voltage 2.0 Vcc+O.5 V
VOL Output Low Voltage 0.45 V IOL = 2mA

Vo„ Output High Voltage 2.4 IOH = -400ftfA

Icc Power Supply Current 170 mA

Input Leakage +10 If A in Cc
ILO Output Leakage +10 ftfA 0 45V ( <Vout 4 VCC
VIER Input Low Level, RESET -0. 5 V
VIHR Input High Level, RESET 2.4 Vcc'O5
VHY Hysteresis, R ESET 0. 25 V
page D.30

TABLE 6. A.C. CHARACTERISTICS

T,=O C to 7O C; Vcc=5V 5.i.; V»-OV

8085A-2I2i
Symbol Parameter
a08SS'" (Preliminary) Units
Min. Max. Min. Max.

tcvc CLK Cycle Period 320 2000 200 2000 ns

ti CLK Low Time (Standard CLK Loading) 80 40 ns

CLK High Time (Standard CLK Loading) 120 70 ns

t(,ti CLK Rise and Fall Time 30 30 ns

IXKR Xi Rising to CLK Rising 30 120 3O 100 ns
IXKF X, Rising to CLK Falling 30 150 30 110 ns
IAC As,5 Valid to Leading Edge oi Control('I 270 115 ns
IACL Ao 7 Valid to Leading Edge of Control 240 115 ns
tAO Ao i5 Valid to Valid Data In 575 350 ns
IAFR Address Float After Leading Edge of
READ (INTA) ns
IAL As i5 Valid Before Trailing Edge of ALE('I 115 50 ns
IALL Ao r Valid Before Trailing Edge of ALE 90 50 ns
IARY READY Valid from Address Valid 220 100 ns
IGA Address (As,5) Valid After Control 120 60 ns
tcc Width of Control Low (RD, WR, INTA)
Edge of ALE 400 230 ns
ICL Trailing Edge of Control to Leading Edge
of ALE 50 25 ns
tow Data Valid to Trailing Edge of WRITE 420 230 ns
IHASE HLDA to Bus Enable 210 150 ns
IHABF Bus Float After HLDA 210 150 ns
IHACK HLDA Valid to Trailing Edge of CLK 110 40 ns
IHDH HOLD Hold Time 0 0 ns
IHDS HOLD Setup Time to Trailing Edge of CLK 170 120 ns
t IN H INTR Hold Time 0 0 ns
I IN 5 INTR, RST,and TRAP Setup Time to
Falling Edge of CLK 160 150 ns
ILA Address Hold Time After ALE 100 50 ns
ILC Trailing Edge of ALE to Leading Edge
of Control 130 60 ns
ILCK ALE Low During CLK High 100 50 ns
ILOR ALE to Valid Data During Read 460 270 ns
ILow ALE to Valid Data During Write 200 120 ns
ALE Width 140 80 ns
ILRY ALE to READY Stable 110 30 ns
 page D.31

8085A/8085A-2

Table 6. A.C. Characteristics (Cont.)

8085A-2I I
Symbol Parameter 8085AI2l (Preliminary) Units
Min. Max. Min. Max.
IRAE Trailing Edge of READ to Re-Enabling 150 90 ns
of Address
IRD READ (or INTA) to Valid Data 300 150 ns
IRV Control Trailing Edge to Leading Edge 400 220 ns
of Next Control
IRDH Data Hold Time After READ INTAITI ns
IRYH READY Hold Time ns
IRYS READY Setup Time toLeading Edge 110 100 ns
of CLK
'WD Data Valid After Trailing Edge of WRITE 100 ns
'WDL LEADING Edge of WRITE to Data Valid 40 20 ns

Notes
AS Ats addre.,s Specs app/y to 10/M. So, and Sl exCept AS-Ats are undef ined during T4 TS of OF ryr:le
whereas IO/M So. andS> are stablr
2 Tes t c o n d i tions t oyo = 320ns (8085Al/200ns 18085A 2l. C< = 150 pF
3 For a l l o u t pu t t i m ing whr.re CL = 150pF use lhe fo l lnwinq correction l a c t o r s
25pF CL 150pF -0 10ns/pF
150pF 0 C < 3 00 p F 4 0 3 0 n s/ p F
4 Outp u t t i m i n rls are measured with pu rely capacitive load
A ll timinqs ar i m e a s u r erl at o u t pu t v o t aqe VE — 0 8V VH = 2 OV, and 1 5V with 2 0 n s r is e an d f a l l t im e o n i n p i i t s
T o ca/cu/ate timinq specifications at o t he' va lues nf to y o uae Table 7
D ata hold t im e is g u a r a n teed u n der ail lo a d inq c o n d i t i o n s

Input Wat/cform for A.C. Tests:

20 20
TEST POINTS
00 00
0 40
page 0.32

8085A/8085A-2

T ABLE 7. BUS TIMING SPECIFICATION AS A Tcvc DEPEND E N T

8085 A 8085A-2 (Preliminary)

AL (1i'2) T — 45 MIN 'AL (I/2) T- 50 MIN
I LA ( I '2) T — 60 MIN LA MIN
(I/2) T — 20 Ml N LL (1/2) T — 20 MIN

LCK (1/2) T — 60 M IN (1/2) T — 50 MIN

(1 2) T — 30 M IN 'LC (1/2) T — 40 MIN
t—- - -
.

AD
(5/2 + N) T — 225 MAX 'AO (5/2 T N) T — 150 MAX
( 3/2 t N) T 180 MAX tRD (3/2 + N) T — 150 MAX
'RAE (1/2) T — 10 M IN RAE (I/2) T — 10 M IN
(1/2) T — 40 IVI I N I CA (I /2) T — 40 MIN
(3/2 s N) T — 60 M IN 'tow ( 3/2 + N) T 7 0 MIN
'wo (1/2) T — 60 MIN 'wo (I /2) T — 40 MIN
(3/2 + N) T - 80 M IN '(:c (3/2 + N) T — 70 MIN
(I/2) T — 110 MIN - (1/2) T - 75 MIN
CL cL
ARY (3/2) T — 260 MAX ARv (3/2) T — 200 MAX
HA C K (I/2) T — 50 MIN - (I /2) T — 60 M IN
~ HA K
(I /2) T + 50 MAX tHABE
- ( I/2) T + 5 0 MAX
HABI
K
- (1/2) T t 50 MAX - (1/2) T + 50 MAX
t HA B E HABE
K

AC
(2/2) T — 50 M IN Ac (2/2) T — 85 MIN
(I/2) T — 80 MIN (I/2) T — 60 MIN
(I /2) T — 40 MIN (1/2) T — 30 MIN
(3/2) T — 80 MIN tnv
- (3/2) T — 80 M IN
RV
LDR (4/2) T — 180 MAX ILDR - (4/2) T — 130 MAX
N OT E N i s eq u a l t o t h e t o t a l W A I T s t a t e s NOT E N is eq u a l t o t h e t o t a l W A I T s t a t es.
T tC Y C . tcvc

Xi I NKI>t

t'I K
ott taut

iKKf

Figure 10. Clock Timing Waveform

 page 0.33

8085A/8085A-2

Read Operation

CLK

I LCK 'La

AB A)s ADDRESS
I RAT
'an ROH

ADB-aDI ADDRESS DATA IN

La

)as Ij ' LOR -

'CL
ALE
-

AL HI)

'cc
RD/INTA
'I C

- 'ac

Write Operation
TS

CLK

+ )Les — H (
AB-A)S ADDRESS

— 'ca
'LOW — ~
t
ADB-ADI ADDRESS DATA DUT

LL E Isa DVI 'wo H

I)v n L
ALE

— 'cc
,L 'Lc 'CL
'ac

Read operation with Wail Cycle (Typical) — same READY timing applies to WRITE operation.
T)V*I \

CLK

I I (' K 'ca

Av Ais ADDHI SS

I ass
'ao Iaoa

AD), ao) ADOHLSS OA I A IN

I I — ILK
Iara ICI
ALE 'Loa

IKL — — 'ao
ICC
RO INTA

Icav
'ac
taav Iavs Iava Iavs Ia YH

RL ADY

NOTE I READv I OST RENAHV STABLE OUR)NO SEIUI AIVD HOLD TRKES

Figure 11. 8085A Bus Timing, With and Without Wait

page 0.34

8085A/8085A-2

Hold Operation

Tz Tz HOLD THoLo

CLK

HOLD

IHOS I HDH IHACK

HLDA
HAD F
IHABE

BUS (ADDRESS, CONTROLSI

Figure 12. 8085A Hold Timing.

Tz Tz T4 Ts THOLo Ti Tz

AB-is

AD/Fz CALL INST

BUS FLOATING'
ALE

RD

INTA

HABE

/
I NTR/ , /

I INK I INH

HOLD I

HOS ~ HDH

HLDA

IH 4 CK HABF 'IO/M IS ALSO FLOATING OUHING THIS TIME

Figure 13. 8085A Interrupt end Hold Timing

 page 0.35

8085A/8085A-2

8085A INSTRUCTION SET SUMMARY BY FUNCTIONAL GROUPING

Table 6-1
Instrucuon Code ill Instruction Cade ill
Mnemonic D e scnption D) D6 D5 D4 D3 D 2 0 1 Op Page Mnemonrc D escnpt on D) DB 05 D4 D3 DZ Dt Op Page

MOVE, LOAD, AND STORE

MOVrl r2 M ove register to rr qiste 0 I O 0 0 S 9 S SC CZ Call an r ro I I 0 0 I I 0 0 'i 14

MOV Mt Move agisterto memory 0 I I I 0 5 5 5 54 CVZ Call on no rero I 0 0 0 n O S id

MOV r M S t o v e e m ory to req sle 0 D D n 54 CP Cai on nos t ve I I I P I C Sin
MVI r Move rnmediale register 0 0 O D 0 I 1 0 54 CV Call on m nus I I I I I 0 0 5 11
MVI ill Move mmediate memorv 0 0 I 0 I I 0 54 CPE Call on panty even 1 I I 0 I I 0 0 5 1I
L XI 8 Load mmedrate register 0 0 0 0 0 0 0 55 CPO Call on panty odd I I 0 0 I 0 0 5 14
Petro& C RETURN
LXI G Load mmdd ale ieg ster 0 0 0 I 0 0 0 I 55 RET Rerum I I 0 0 I f,' 0 I 5 11
Pair 0 & E RC Re lorn on carry I I 0 I 1 0 0 0 5 14
L XI H Load immediate registe 0 0 I 0 0 0 0 I S5 RNC Return on no carry I I 0 I 0 fl 0 0 5 la
Pair H & L
RZ Return un cero I 1 0 0 I 0 fl 0 5 14
Sl AX 8 Store A indirect 0 0 0 0 0 0 0 56
RVZ Return on no fera o 0 o 0 e e 54
STAX 0 Store A,ndirect 0 0 0 I 0 0 I 0 56
RP Return on poutive I I I I 0 0 0 0 Sta
LOAX 8 Luad A indirect 0 0 0 0 I 0 I 0 55
RM Return nn minus I I I I I 0 0 0 5 14
LOAX D Load A ndirect 0 0 0 I I 0 0 'i5
RPE Return un flanty even I I I 0 I 0 0 0 5 14
STA Store A direct 0 0 I I fl 0 I 0 d5
RPO Return on parity odd I I I 0 0 0 U 0 5 14
LDA Load A 4 rect 0 55
RESTART
SHLD Store H & I d rect 0 0 I 0 0 0 I 0 S5
RST Restart I I A A A 5 14
LHLO Load H & L d rect 0 0 I 0 I 0 I 0 55
XCHG I I I 'i 6
INPUT/0 U T P
UT
Exchange D & E H 8 I 0 I 0
IN Input I I 0 I I 0 I I 5th
Reg stirs
STACK 0PS QUT Gutput 0 I 0
PIISH 8 Push rr.gister Pair 8 8 I I D 0 0 I 0 I 5 15 INCREMENT AND DECREMENT
C on \Idea IN R Increment registr 0 0 D D D 0 0 5'
PUSH D Push reg ster Pa r D 8 I 0 I 0 I 0 I : 15 DCR r Decremenl regoler 0 0 0 D D 0 I 5 P.
T on stark INR I' c orn rme o v 0 0 p 'i O D ! 8
PUSH H Piish rr') ster Pair H 8 I I I 0 0 I 0 I 'i 15 DCR M Oecremenr memory 0 0 I I 0 0 'I 54
L nr ildck INX 8 increment 8 8 C 0 0 0 0 0 0 I I 5
PUSH PSW Push A and Piers I I I 0 I 0 registers
on stark INX D increment D & E 0 0 0 I 0 I)
pnl 8 ooo eq str I n D 9 D e ' 515 g st,eri
C oft stark INX H Increment H 8 L I 5 'I
0 0 I 0 0 fl I
Pnp 0 Pop re lister Pair D 8, I I D I 0 0 G I S15 registers
E on srack
OCX 8 Decr e mrnt 8 8 C 0 0 0 0 I il I I 59
PGP H PoO reqstrr Pa r H 8 I I 0 0 r, 0 I 5 15
DCX D Dec a ment 0 8 E 0 0 0 I I D I I 5I
L )'f i'aci
' OCX H Oec r eme I H & L 0 0 I 0 I I) I I 5 'i
I OP PSVi Pop A .i. d Ciaqs G 0 0 515
on sit<I ADO
XTHL Exchd oe tnp ot I I I 0 0 0 I I 5 '6 Ao() Aud req iir r to A I 0 G 0 0 S' 5 5 5'
steed tl 8, L AOC A rlrt e i it rn A I 0 tl 0 I S 5 S S'
SP if 0 Cd''i

LXI SP Load m e d ate stark 0 0 I n n o Ann s i Arlil m n a r y to A n r D 0 0

pn ntrr ADr. Sl A oiJ » i or v ' 0 A fl t) 0 0 5'
INX SP Incrr ment stark pointe 0 0 I I 0 0 I I S9 r i ili i d u y

orx sp Derre .»mt stark 0 0 I I I 0 I I 59 Anl A (iu 4 ate t n A I I tl 0 0 I I 0

AC ' Jx r I di i 1A
i mii Cd
JUMP
J i,i p Jumli unco d t n a n o n n I ' I3
OAO 8 Arlr,' 8 8 C t i H & ' o o n n Q I 5

JC Jump u cdrry I I 0 I I fi I) '13

OAf) D A ud Dr, E inH B, L 0 n 0 I I 0 n
DAI) H Ail p I ' n H I SI fi 0 I Ti I li I ''I
J'fC 5 I'i
OAO SP 0 I I i il 0
JZ J unp m i c r o {I I 9 0 513
H
JNZ J u o on n o r e n I I D 0 0 0 I 0 d 13
Jump nn pos tive I I I I 0 0 I 0 'i13 SUBTRACT
5 I) I'. S litrd i r )sti I 0 i) fl ', 5 S ')i
Jump n • m nus I I I I I 0 I in 513
JPE Jump o par ly evrn I I 0 I D 0 'i13
Si i ilra ' r i , stir I r n n G tl 5 5 I )
Jpn ! imp nn panty odd 1 I 0 0 Q I 0 S 13
A nil t o iw
PCH I H & i. tn program I I 0 I 0 0 I 5 15 SUP, ' :
S it ) i mr v 0 D 0 ', i
CO or' I '
CALL 5 .I
CALL Cau u rond I nnal I G 0 I I 0 I 5 13 A n t i ' h ir n w
CC Call o car v I I 0 I I I tl 0 'i14 SUi lit a 0 G
C'f C earl n no carrv I I fl I 0 Q ' 14 fr i 4

'AU mnemonics copyrighted I n t e l T:orporation 1976

page 0.36

8085A/8085A-2

8085A INSTRUCTION SET SUMMARY (Cont'd)

Table 6-1
Instsuction Code (I) Instrucbon CodeIll
Mnemonic Descnption Df 08 Dri 04 DS 02 01 DO P tge Mnemomc Oescnption DT 06 05 D4 08 02 O l 00 Page

S BI Subtract m rrediate I 0 I I I I 0 58 RRC Rotare A nght 0 0 0 I I I I 5 12

frn n A w tl borrow RAL Rotate
A leftthrough 0 0 I 0 I I I 5 12
LOCICAL carry
ANA And req ster v th A I 0 I 0 0 6 S S 58 RAR flotale A nghlthrough 0 0 0 I I I I I 5 12
XRA E xcluuve 0 R reg ster I 0 I 0 I S 5 6 5 10 carry
will A
ORA r OR re spect w pi A
SPECIALS
I 0 I I 0 6 6 6 5 10
CMA Complement A 0 I 0 'I I I I 5 12
Co pare e Inter with A I 0 I I I 6 S 6 5 11
ANA M A id memo y will A STC Set carry 0 I I 0 I I I 512
I 0 I 0 0 I I 0 5 10
CMI.' Complemenl carry 0 0 I I I I I I 5 12
XRA M Exclusive 0 8 mr mory I 0 I 0 I I I 0 5 10
w th A DAA Decimal adlurt A 0 0 I 0 0 I I I 59
ORA M OR me m o ry w th A I 0 I I 0 I I 0 5 11
CONTROL
CMP M Cnmoa r e memory w th A I 0 I I I I I 0 5 11
El Enable Intenupn I 'I I I I 0 I I 5 11
ANI A id immediate w tl A I I I 0 0 I I 0 5 10
X 81 Excluuve OR immediate I I I 0 I I I 0 5 10 Ol Doable Interrupt I I I I 0 0 I I 5 11
wilts A NOP No operatmn 0 0 0 0 0 0 D 5 11
ORI OR mmedatew t h A I I I 0 I I 0 5 11 HLT Hall I I I 0 I I 0 5 11
CPI Compareimmediate I I I I I I I 0 5 11
widt A NEW 8085A INSTRUCTIONS
ROTATE RIM Read Interrupt Mask 0 I 0 0 0 0 0 5 11
RLC Rotate A left 0 0 0 0 0 I I I 5-11 SIM Set Interrupt Maik 0 I I 0 0 0 0 5 18

NOTES I DOS or SSS 8 000, C 001, 0 010, 6011, H '100, L 101, Memory 110, A 111
2 Two ponible cycle times 16112) mdicate instruction cycles dependent on condition Rags,

All mnemontcs copyrighted I n t e l Corporatton 1976

 Page 0.37

intei
8259A
P ROG RANIMABLE INTERRUPT CONTROLLER

• MCS-86™ Compatible • Programmable Interrupt Modes

• MCS 80/85™ Compatible • Individual Request Mask Capability
• Eight-Level Priority Controller • Single + 5V Supply (No Clocks)
• Expandable to 64 Levels • 28-Pin Dual-ln-Line Package

The Intele 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 84 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intele 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

PIN CONFIGURATION BLOCK DIAGRAM

INTA IN T
CS 28 VCC
WR 2 21

RD 3 26 INTA
25 IR7
5 24 IR6 DATA CONTROL LOGIC
De D1-04 BUS
De I R5 BUFFER

D4 7 22 IR4
B259A
De 6 21 IR3

D2 20 IR2
DI 10 19 IR I

De 18 IRO
IRO
CAS 0 12 IN T RD
IR I
WR- READ/ IR2
CAS I 16 SP/EN WRITE NTERR
IN
LOGIC SERVICE PRIORITY REQUEST IR3
GND 14 15 CAS 2
Ae REG ESOLVER REG IR4
(I SR I (IRRI ~ IRS
IRB
CS IR7
PIN NAMES

D1-00 DATA BUS (BI DIRECTIONAL)

C ASO ~ - INTERRUPT MASK REG
RD READ INPUT
CASCADE UMRI
WR WRITE INPUT CAS I BUFFER/
Ae COMMAND SELECT ADDRESS COMPARATOR
CAS 2
CS CHIP SELECT
CAS2 CASO CASCADE LINES
SP/frI SLAVE PROGRAM INPUT/ENABLE SP/EN INTERNAL BUS
INT INTERRUPT OUTPUT
INTA INTERRUPT ACKNOW LEDGE INPUT
IRO-IR7 INT ER R UPT REQUEST INPUTS
page 0.38

8259A

I NTERRUPTS IN MICROC O M P U T E R
SYSTEMS
Microcomputer system design requires that IIO devices
such as keyboards,displays, sensors and other com-
ponents receive servicing in an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on through-
put.
The most common method of servicing such devices is
the Polled approach. This is where the processor must
match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time dur.
ing the main program. This means that the complete in.
terrupt structure can be defined as required, based on
the total system environment.
CPU DRIVEN
IA U C T I PCEX0 R
CPU

test each device in sequence and in effect "ask" each

one if it needs servicing. It is easy to see that a large por-
tion of the main program is looping through this con-
tinuous polling cycle and that such a method would
have a serious, detrimental effect on system through- RAM I/O Ii)
put, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.
A more desirable method would be one that would allow
the microprocessor to be executing its main program ROM I/O I2)
and only stop to service peripheral devices when it is
told to do so by the device itself. In effect, the method
would provide an e x ternal asynchronous input t h at
would inform the processor that it should complete 1
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting I/O IN)

device. Once this servicing is complete, however, the I

L
processor would resume exactly where it left off.
This method is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to Polled Method
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests CPU IN T
is of t h e h i g hest i m portance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special RAM
program or "routine" that is associated with its specific
functional or operational requirements; this is referred
to as a "service routine". The PIC, after issuing an Inter-
rupt to the CPU, must somehow input information into
the CPU that can "point" the Program Counter to the
ROM I/O (I)
service routine associated with the requesting device.
This "pointer" is an address in a vectoring table and will
often be referred to, in this document, as vectoring data.

8259A BASIC FUNCTIONAL DESCRIPTION I/0 (2)

GENERAL
The 8259A is a device specifically designed for use in
real time, interrupt driven microcomputer systems. It
manages eight levels or requests and has built-in fea-
tures for expandability to other 8259A's (up to 64 levels).
It is programmed by the system's software as an IlO
peripheral. A selection of priority modes is available to
the programmer so that the manner in which the re-
quests are processed by the 8259A can be configured to Interrupt Method
 page 0.39

8259A

INTERRUPT REQUEST REGISTER (IRR)AND / • TA

IN SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled by two
O/ D,
registers in cascade, the Interrupt Request Register DATA CONTROL LOG/(
BUS
(IRR) and the In-Service Register (ISR). The IRR is used BUFFER
to store all the interrupt levels which are requesting ser-
vice; and the ISR is used to store all the interrupt levels
which are being serviced.

PRIORITY RESOLVER IRO

IR I
This logic block determines the priorities of the bits set READ/ IR2
IV R I T E IF/TERRUPT
in the IRR. The highest priority is selected and strobed L OG I C Sf RVICI PRIORITV REQUEST IR3
RIr, R 1 SO L V E R REG IR6
into the corresponding bit of the ISR during INTA pulse. IISR IIRRI IRS
IR6
CS
INTERRUPT MASK REGISTER (IMR) IR7

The IMR stores the bits which mask the interrupt lines
rnso
to be masked. The IMR operates on the IRR. Masking of I f TI I R U PT MASK R/ / ;
CASCADE
a higher priority i nput w il l no t a f f ect th e i n t errupt CAS I BUFFER'
I IFIR I

request lines of lower priority. COMPA

CAS 2 RATOR

INT (INTERRUPT) SP/FN

INTERNAL BUS
This output goes directly to the CPU interrupt input. The
Voh level on this line is designed to be fully compatible
with the 8080A, 8085A and 8086 input levels.
8259A Block Diagram
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring INTA INT

information onto the data bus. The format of this data

depends on the system mode (3 PM) of the 8259A. DI Dn
DATA CONTROL LOGIC
DATA BUS BUFFER BUS
BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter-

face the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.
RD IRB
IR I
READ/WRITE CONTROL LOGIC READ
AR IT E IN
IR2
INTERRUPT
LOGIC SFRVICE PR 10 R I T7 REQUEST IR3
The function of this block is to accept OUTput com- REG RESOLVER REG I RA
( ISA
) /IRR)
mands from the CPU. It contains the Initialization Com- IRS
IR6
mand Word (ICW) registers and Operation Command IRT
Word (OCW) registers which store the various control
formats for device operation. This function block also CASn
allows the status of the 8259A to be transferred onto the INTERRUPT MASK REG
CASCADE II MRI
Data Bus. GAS I BUFFER
COMPA
CAS 2 RATOR

CS (CHIP SELECT)
SP/ I N
INTERNAL BUS
A LOW on this input enables the 8259A. No reading or
writing of t h e c hi p w i l l o c cur u nless the device is
selected.

WR (WRITE) 8259A Block Diagram

A LOW on this input enables the CPU to write control
words (ICWs and OCWs) to the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.
Ao
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as reading the various status registers
of the chip. This line can be tied directly to one of the ad-
dress lines.
page 0.40

8259A

THE CASCADE BUFFER/COMPARATOR If no interrupt request is present at step 4 of e i ther

This function block stores and compares the IDs of all sequence (i.e., the request was too short in duration) the
8259A's used in the system. The associated three I/O 8259A will issue an interrupt level 7. Both the vectoring
pins (CASO-2) are outputs when the 8259A is used as a bytes and the CAS lines will look like an interrupt level 7
master and are inputs when the 8259A is used as a was requested.
slave. As a master, the 8259A sends the ID of the inter-
rupting slave device onto the CASO-2 lines. The slave
thus selected will send its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the INTA

8259A".)
DI -DO
INTERRUPT SEQUENCE DATA CONTROL LOGIC
BUS
BUFFER
The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to th e s pecific interrupt routine requested
without any polling of the interrupting devices. The nor-
IRO
mal sequence of events during an interrupt depends on IR I
READ/
the type of CPU being used. WRITE IN INTERRUPT
IR2
LOG IC SERVICE PRIORITY REQUEST IR3
The events occur as follows in an MCS-80/85 system: REG RESOLVER REG IR4
(ISR I IIRRI IR5
1. One or more o f t h e I N TERRUPT REQUEST lines I RE
CS
(IR7-0) are raised high, setting the corresponding IRR IRT

bit(s).
2. The 8259A evaluatesthese requests, and sends an CAS 0
INTERRUPTIVIASK REG
INT to the CPU, if appropriate. CAS I
CASCADE
BUFFERI
( I MR I
COMPA
3.The CPU acknowledges the INT and responds with an CAS 2 RATOR
INTA pulse.
4. Upon receiving an INTA from the CPU group, the SP/EN
INTERNAL BUS
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL in-
struction code (11001101) onto the 8-bit Data Bus
through its D7-0 pins. 8259A Block Diagram
5, This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8-bit address is released at the first ADDRESS BUS116I

INTA pulse and and the higher 8-bit address is re-

leased at the second INTA pulse.
CONTROL BUS
7. This completes the 3-byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at I /OR I/OW IN T INTA

the end of the third INTA pulse. Otherwise, the ISR bit DATA BUS (BI
remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.
The events occurring in an MCS-86 system are the same
until step 4. CS A O DT DO RD WR I NT I NTA
CAB 0
4. Upon receiving an INTA from the CPU group, the high- CASCADE CAS I 6259A
est priority ISR bit is set and the corresponding IRR LINES
bit is reset. The 8259A does not drive the Data Bus CAS 2 I RQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ
SPIEN 7 6 5 4 3 2 I 0
during this cycle.
5. The MCS-86 CPU will initiate a second INTA pulse.
During this pulse, the 8259A releases an 8-bit pointer
SLAVE
onto the Data Bus where it is read by the CPU. FROG
IN T E R R UPT
REQLIESTS
6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INTA
pulse, Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine. 8259A Interface to Standard System Bus
 page 0.41

8259A

INTERRUPT SEQUENCE OUTPUTS During the third INTA pulse the higher address of the ap-
MCS-80/85 SYSTEM propriate service routine, which was programmed as
byte 2 of the initialization sequence (AO-AI5), is enabled
This sequence is timed by three INTA pulses. During the onto the bus.
first INTA pulse the CALL opcode is enabled onto the
data bus.
Content of Third Interrupt
Content of First Interrupt Vector Byte
Vector Byte DT D6 D5 D4 D3 D2 D1 DO
D7 D6 D5 D4 D3 D2 D1 DO A 15 A 14 A 13 A 12 A 11 A 10 A9 A6

CALL CODE 1 I 0 0 I 1

MCS.86 SYSTEM
During the second INTA pulse the lower address of the MCS-86 mode is similar to MCS.80 mode except that
appropriate service routine is enabled onto the data bus. only two Interrupt Acknowledge cycles are issued by
When Interval = 4 bits A5-AT are programmed, while AO- the processor and no CALL opcode is sent to the proc-
A4 are automatically inserted by the 8259A. When Inter- essor. The first interrupt acknowledge cycle is similar to
val = 8 only A6 and AT are programmed, while AO-A5 are that of MCS-80/85 systems in that the 8259A uses it to
automatically inserted. internally freeze the state of the interrupts for priority
resolution and as a master it issues the interrupt code
Content of Second Interrupt on the cascade lines at the end of the INTA pulse. On
Vector Byte this first cycle it does not issue any data to the proc-
IR Interval = 4 essor and leaves its data bus buffers disabled, On the
second interrupt acknowledge cycle in MCS-86 mode
DT D6 D5 D4 D3 D2 D1 DO
the master (or slave if so programmed) will send a byte
A7 A6 A5 I 1 1 0 0
of data to the processor with the acknowledged inter-
A7 A6 A5 1 1 0 0 0
rupt code composed as follows (note the state of the
A7 A6 A5 1 0 1 0 0 ADI mode control is ignored and A5-A« are unused in
AT A6 A5 1 0 0 0 0 MCS-86 mode):
A7 A6 A5 0 1 I 0 0
A7 AF) A5 0 1 0 0 0
A7 A6 A5 0 0 1 0 0
A7 A6 A5 0 0 0 0 0 Content of Interrupt Vector Byte
for MCS-86 System Mode
IR Interval = 6 DT D6 D5 D4 D3 D2 Dl DO
DT D6 D5 D4 D3 D2 Dl DO IR7 A15 A14 A13 A12 A«
AT A6 1
IR6 A15 A14 A13 A12 A«
AT A6 1 00
IR5 A15 A14 A13 A12 A«
AT A6 1
63 0 I R4 A15 A14 A13 A12 A«
A7 A6 I 0 0
0 0 I R3 A15 A14 A13 A12 A«
A7 A6 0
2 A7 A6 0 0 I R2 A15 A14 A13 A12 A«
00 I R1 A15 A14 A13 A12 A« 0
A6 0 0 1 0
A6 0 0 0 0 IRO A 15 A 14 A13 A12 A« J 0
page 0.42

8259A

PROGRAM M ING THE 8259A INITIALIZATION

The 8259A acceptstwo types of command words gener-
ated by the CPU:
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 8259A in the system must
be brought to a starting point — by a sequence of 2 to
4 bytes timed b y W R p u lses. This sequence is
described in Figure 1.
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to oper-
ate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after
initialization.
GENERAL
Whenever acommand is issued with A0 = 0 and D4 = 1 ,
this is interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization sequence during
which the following automatically occur.
a. The edge sense circuit is reset, which means that
following initialization, an interrupt request (IR) input
must make a low-to-high transition to generate an
interrupt.
b. The Interrupt Mask Register is cleared.
c. IR 7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set
to IRR.
f. If IC4 = 0, then all functions selected in ICW4 are set
to zero. (Non-Buffered mode', no Auto-EOI, MCS-80/
85 system).
Note: Master/Slave in ICW4 is only used in the buttered mode

Ap D4 D3 RD NIR CS INPUT OPERATION (READ)

IRR, ISR or Interrupting Level~ D A T A BUS (Note 1)
IMR ~ D A T A BUS

OUTPUT OPERATION ()NRITE)

DATA BUS ~ O CW2
DATA BUS ~ O C W3
DATA BUS ~ ICW1
DATA BUS ~ O C W1, ICW2, ICW3, ICW4 (Note 2)
DISABLE FUNCTION
DATA BUS ~ 3-STATE
DATA BUS ~ 3-STATE
Notes: 1. Selection of lRR, ISR or Interrupting Level is based on the content of OCW3 wntten before the READ operation
2. On.chip sequencer logic queues these commands into proper sequence

8259A Basic Operation

 page 0.43

8259A

INITIALIZATION COMMAND WORDS 1 AND 2 INITIALIZATION COMMAND WORD 3 (ICW3)

(ICW1, ICW2)
As-A». Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (Ao-A»). When the
routine interval is 4, Ac-AA are automatically inserted by
the 8259A, while As-A» are programmed externally.
When the routine interval is 8, Ao-As are automatically
inserted by the 8259A, while As-A» are programmed
externally.
The 8-byte interval will maintain compatibility with cur-
rent software. while the 4.byte interval is best for a com-
pact jomp table.
In an MCS-86 system A)s-A» are inserted in the five
m ost significant bits o f t h e v ectoring byte and t h e
8259A sets the three least significant bits according to
the interrupt level. AID-As are ignored and ADI (Address
interval) has no effect.
L TIM: I f L T I M=1, then the 8259A will operate in the
level interrupt mode. Edge detect logic on the
interrupt inputs will be disabled.
ADI: CA L L address interval. ADI =1 then interval =4;
ADI = 0 then interval = 8.
SNGL: Single. Means that this is the only 8259A in the
system. If SNGL = 1 no ICW3 will be issued.
IC4: If t h i s bit is set — ICW4 has to be read. If ICW4
is not needed, set IC4 = 0 .
This word is read only when there is more than one
8259A in the system and cascading is used, in which
case SNGL =O. It will load the 8-bit slave register. The
functions of this register are:
a. In the master mode (either when SP = 1, or in buffered
mode when M/S =1 in ICW4) a "1" i s se t fo r each
slave in the system. The master then will release byte
1 of the call sequence (for MCS-80/85 system) ar d will
enable the corresponding slave to release bytes 2 and
3 (for MCS-86 only byte 2) through the cascade lines.
b. In the slave mode (either when SP=O, or if BUF= 1
and M/S=O in ICW4) bits 2-0 identify the slave. The
slave compares its cascade input with these bits and,
if they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for MCS-86) are released by it on the Data
Bus.
INITIALIZATION COMMAND WORD 4 (ICW4)
FNM: If FNM = 1 the fully nested mode is programmed.
BUF: If BUF = 1 the buffered mode is programmed. In
buffered mode SP/EN becomes an enable output
and the master/slave determination is by M/S.
M/S: I f b u f fered mode is selected: M/S = 1 means the
8259A is programmed to be a m aster, M/S= O
means the 8259A is programmed to be a slave. If
BUF = 0, M/S has no function.
AEOI: If AEOI= 1 the automatic end of interrupt mode
is programmed.
)IPM: M i croprocessor mode: HPM =O sets the 8259A
for MCS.80/85 system operation, )IPM = 1 sets
the 8259A for MCS-86 system operation.

AQ DT D6 DS D4 D3 D2 DI DO

0 AT A6 AS I LT I M AD I SNGL I C4 ICWI

\ A16 A14 A13 A12 AI I A10 AS AS ICW2

YES SINGLE
(SNGL = I)

NO I SNGL = 0)

ST 66 S4 62 SI SO ICW3

NO ICW4
(IC4 = 0)

YES IIC4 — I)
I 0 0 0 FNM SUF MIS AEOI y PM I C W 4

READY TO ACCEPT REQUESTS

IN THE FULLY NESTED MODE

Figure 1. Initialization Sequence

page 0.44

8259A

I CW I
Ao I Do Do Do Do DT D, Do

0 AT Ao /V, I LTIM F S 0

I I CW4 NEEDED
0 = NO ICW4 NEEDED

SINGLE
0.- NOT SINGLE

CALL ADDRESS INTERVAL

I • INTERVAL OF 4
0 • INTERVAL OF 8

I" LEVEL TRIGGERED INPUT

0. EDGE TRIGGERED INPUT

AT — ASOF LOWER
ROUTINE ADDRESS
IMCS-80/85 MODE ONLYI

ICW 2
Ao DI Do D Do Do DT D, Do

I A/o AI • A/3 AM A» A/o 4 Ao

UPPER ROUTINE
ADDRESS

ICW3 (MASTER DEV ICE I

Ao DI Do D Do 03 DT 0/

I ST So So So So ST SI

. IR INPUT HAS A SLAVE

0 - IR INPUT DOES NOT HAVE
A SLAVE

ICW3 ISLAVE DEVICE)

A DT Do D Do Do Do DI Do

I 0 0 0 0 0 I DT ID/ I Do

X X X X X
SLAVE ID//I

0 I 2 3 4 5 6 7
DON' T 0 I 0 I 0 I 0 I
CARE 0 0 I I 0 0 I I
0 0 0 0 I I I I

ICW4
AO DT DB DS D4 D3 02 DI 00

I 0 0 0 FN M BU F M/ S A EOI y FM

I M C S 86 MODE
0 — IIICS 80/85 MODE

I A U T OEOI
0 N O R M A L EOI

0 X — NON BUFFERED MODE

I 0 — BUFFERED MODE/SLAVE
I I — BUFFERED MODE/MASTER

I F U L LY NESTED MODE
0 NOT FULLY NESTED MODE

NOTE I: SLAVED ID ISEQUAL TO THE CORRESPONDING MASTER IR INPUT.

NOTE 2: X INDICATED "DON'T CARE".

Initialization Command Word Format

 page 0.45

8259A

O PERATION CO M M A N D W O R D S (OCW s ) OPERATION CONTROL WORD 1 (OCW1)

Atter the Initialization Command Words (ICWs) are pro-
grammed into the 8259A, the chip is ready to accept
interrupt requests at its input lines. However, during the
8259A operation, a selection of algorithms can com-
mand the 8259A to operate in various modes through
the Operation Command Words (OCWs).
OCW1 sets and clears the mask bits in the Interrupt
Mask Register (IMR). M7-M0 represent the eight mask
bits. M = I indicates the channel is masked (inhibited).
M = 0 indicates the channel is enabled.

OPERATION CONTROL WORD 2 (OCW2)

OPERATION CONTROL WORDS (OCWs) R, SEOI, EOI — These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Opera-
OCW1 tion Command Word Format.
AO DT D6 D5 D4 D3 D2 D1 DO Lz, Li, Lp — These bits determine the interrupt level
1 M7 M6 M5 M4 M3 M2 M1 MO ] acted upon when the SEOI bit is active.

OPERATION CONTROL WORD 3 (OC)N3)

OCW2 ESMM — Enable Special Mask Mode. When this bit is
• l QEQ E D 0 0 EQ ] set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM =0 the SMM bit becomes a
"don't care".
SMM — Special Mask Mode, If ESMM = 1 and SMM = 1
the 8259A will enter Special Mask Mode. If ESMM = 1
OCW3
and SMM = 0 the 8259A will revert to normal mask mode.
0
~ QS SMM MM 0 SSIS • 0
l When ESMM = 0, SMM has no effect.
page 0.46

8259A

OCWI
A Dl Da Da Oe Dt Dt Dt Do

I M7 MB IRS Ma M3 ME Ml Mo

INTERRUPT MASK
I M A S K SET
0 M A S K RESET

OCW2

o DI Da De De 01 Dt Or e

0 R SEO I EO I 0 0 LI Lr Lo

BCO LEVEL TOBE RESET

OR PUT INTO LOWEST PRIORITY
0 I 2 3 6 6 6 7
0 I 0 I 0 I 0
0 0 I I 0 0 I I

0 0 0 0 I I I I

0 0 I No rp c hc EOI
0 I I Spechc EOI LGL2 code or IS FF r I»
0 I Rotate • I TOI A r omatrcdre IMod AI
I I Rotate at EOI ( od B l LDL2 od ol I
0 0 Ser Rolal • A FF
0 0 Crea Rotate A FF
I 0 Rol le 0 o t y 1 o d e 01 I depe d lly o I E U I
I 0 No Op r •roc

DI Da I Oa Da DT Dr

0 - ESMM S MM 0 I P ERIS RIS

READ IN SERVICE REGISTER

DON' T
CARE

0 0
READ READ
IR REG IS REG
NO ACTION ON NEXT ON NEXT
AD PULSE RD PULSE

PO L LING
A HIGH ENABLES THE NEXT RD PULSE
TO READ THE BCD CODE OF THE HIGH
EST I.EVEL REOUESTING INTEIIRUPT

SPECIAL MASK MODE

0 I

RESET SET
NO ACTION SPECIAL SPECIAL
MASK MASK

Operation Command Word Format

 page 0.47

8259A

0 CW I

I Ml MS MS M4 Me ME AH MD

INTERRUPT MASK
I M AS K S E T
0 M A S K R E S ET

<)CW7

Ad Dl Df Dt D Dl Dl D Od

0 R SEOI EOI 0 0 Ll L, Ld

e<D LEVEL TO eE R<sl.l

GR PUT INTO L<1WI ST PRIORI I <
0 I 2 2 4 5 6 7
0 I 0 I 0 I 0 I

0 0 I I 0 0 I I

0 0 0 0 I I I

(0 0 I
0 I I Sl • ' EQI I T L E M « S F<t
I 0 11
I I I R I I, • I E OI I o 4 Bl L G L 2 d t l
I 0 0 S IR I A FF
0 0 CI • Hd t I A FF
1 I 0 R I I. P 4 l y t d Bl l l • d K T o I E OI
0 I O' Ol

O<WS

Ad Ol DE DE DI Dl Dt Dt Dd

0 - ESMM SMM 0 I P ERI S RI B

READ IN SERVICE REGISTER

DON' T
CARL 0

READ READ
IR REG IS Rt I
NO ACTION ON NE X T ONIVIX T
RD PULSE RD PIH SE

PO L L IVC
A HIGH ENAtH f 1 Tl E NEXT RU PULSE
TO READ THE HCD CODE OF THE HIGH
f ST LEVEL Rf <IUES1ING INTE Rfll 'T

SPECIAL MASK MODE

0 I

RESET SE 1
NO ACTION SP f.C I A L SPECIAL
MASK MASK

Operation Command Word Format

page 0.46
8259A
INTERRUPT MASKS
Each Interrupt Request input can be masked individu-
ally by the Interrupt Mask Register (IMR) programmed
through OCW1. Each bit in the IMR masks one interrupt
channel if it is set (1). Bit 0 masks IRO, Bit 1 masks IR1
and so forth. Masking an IR channel does not affect the
other channels operation.
SPECIAL MASK MODE
Some applications may require an i n terrupt service
routine to dynamically alter the system priority struc-
ture during ii s e x ecutio~ under software control. For
example, the routine may wish to inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
The difficulty here is that i f a n I nterrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine),
the 8259A w o uld h ave i n h ibited al l l o we r p r i ority
requests with no easy way for the routine to enable
them
That is where the Special Mask Mode comes in. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables inter-
rupts from a/I other levels (lower as well as higher) that
are not masked.
Thus, any interrupts may be s e lectively enabled by
loading the mask register.
The special Mask M ode i s s e t b y O C W 3 w h ere:
SSMM = 1, SMM = 1, an d c l e a red w h er e S S M M = 1,
SMM = 0.
BUFFERED MODE
When the 8259A is used in a large system where bus
driving buffers are required on the data bus and the cas-
cading mode is used, there exists the problem of enabl-
ing buffers.
The buffered mode will structure the 8259A to send an
enable signal on SP/EN to enable the buffers. In this
mode, whenever the 8259A's data bus outputs are ena-
bled, the SP/EN output becomes active.
This modification forces the use of software program-
ming to determine whether the 8259A is a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 in ICW4 determines whether it is a master or a slave.
NESTED MODE
This mode is entered atter initialization unless another
mode is p r o grammed. The i n terrupt r equests a re
ordered in priority from 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Addition-
ally, a bit of the Interrupt Service register (IS0-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be acknowl-
edged only i f t h e m i croprocessor internal Interrupt
enable flip-flop has been re-enabled through software).
After the initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained, in the rotating priority mode.
THE SPECIAL FULLY NESTED MODE
This mode will be used in the case of a bi g system
where cascading is used, and the priority has to be con-
served within each slave. In this case the fully nested
mode will be programmed to the master (using ICW4).
This mode is similar to the normal nested mode with the
following exceptions:
a. When an interrupt request from a certain slave is in
service this slave is not locked out from the master' s
priority logic an d f u rther i nterrupt requests from
higher priority IR's within the slave will be recognized
by the master and will initiate interrupts to the proc-
essor. (In the normal nested mode a slave is masked
out when its r equest is i n s e rvice and no h i gher
requests from the same slave can be serviced.)
b. When exiting the Interrupt Service routine the soft-
ware has to check whether the interrupt serviced was
the only one from that slave, This is done by sending
a non-specific End of Interrupt (EOI) command to the
slave and then reading its In. Service register and
checking for zero. If it is empty, a non-specific EOI
can be sent to the master too. If not, no EOI should be
sent.
 page 0.49

8259A

POLL second in MCS-86). Note that from a system standpoint,

this mode should be used only when a nested multilevel
In this mode th e m i croprocessor internal Interrupt interrupt structure is not required within a single 8259A.
Enable flip-flop is reset, disabling its interrupt input.
Service to devices is achieved by programmer initiative To achieve automatic rotation (Rotate Mode A) within
using a Poll command. AEOI, there is a special rotate flip-flop. It is set by OCW2
w ith R = 1 , S E O I= 0, E = O , a n d c l e a red w i t h R = O ,
The Poll command is issued by setting P = "1" in OCW3. SEOI = 0 . E = 0 .
The 8259A treats the next RD pulse to the 8259A (i.e.,
R D=O, C S =O) as an interrupt acknowledge, sets the ROTATING PRIORITY MODE A (AUTOMATIC
appropriate IS bit if there is a request, and reads the ROTATION) FOR EQUAL PRIORITY DEVICES
priority level. Interrupt is frozen from WR to RD. In some applications there are a number of interrupting
The word enabled onto the data bus during RD is: devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
D7 D6 DS D4 D3 D2 D1 DO requesting an interrupt will have to wait, in the worst
W2 Wt WO case until each of 7 other devices are serviced at most
once. For example, if the priority and "in service" status
WO-W2: Binary code o f t h e h i ghest priority level IS:
requesting service.
I: Equal to a "1" if there is an interrupt. Before Rotate (IR4 the highest priority requiring service)
This mode is useful if there is a routine command com-
mon to several levels so that the INTA sequence is not I S7 IS 6 1 5 5 I S 4 I S 3 I5 2 IS1 ISO
needed (saves ROM space). Another application is to "IS" Status o~ oo o ',
use the poll mode to expand the number of priority
levels to more than 64. Lowest Priority Highest Priority

o .- I f Ioo o o tol W o l
END OF INTERRUPT (EOI)
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when AEOI bit in ICW1 is set) or by a command After Rotate (IR4 was serviced, all other priorities
word that must be issued to the 8259A before returning
from a service routine(EOI command). An EOI command rotated correspondingly)
must be issued twice, once for the master and once for IS7 IS 6 I S 5 I S 4 I S 3 I S 2 IS1 I SO
the corresponding slave if slaves are in use. "IS" Status loi ' • ~o i ~ o o 3
There are two forms of EOI command: Specific and Non-
Specific. When the 8259A is operated in modes which Highest Priority Lowest Priority
preserve the fully nested structure, it can determine Poor3ty Status 2I 0 o 3
which IS bit to reset on EOI. When a Non-Specific EOI ~
command is issued the 8259A will automatically reset
the highest IS bit of t hose that are set, since in the
nested mode the highest IS level was necessarily the
The Rotate command mode A is issued in OCW2 where:
last level acknowledged and serviced.
R= I, E= 1, SEOI =O. Internal status is updated by an
However, when a mode is used which may disturb the End of Interrupt (EOI or AEOI) command. If R = 1, E = 0,
fully nested structure, the 8259A may no longer be able SEOI =0, a "Rotate-A" flip-flop is set. This is useful in
to determine the last level acknowledged. In this case a AEOI, and described under Automatic End of Interrupt.
Specific End of Interrupt (SEOI) must be issued which
includes as part of the command the IS level to be reset.
EOI is issued whenever E = 1, in OCW2, where LO-L2 is ROTATING PRIORITY MODE B (ROTATION BY
the binary level of th e IS bit t o b e r eset. Note that SOFTWARE)
although the Rotate command can be issued together
The programmer can change priorities by programming
with an EOI where E = 1, it is not necessarily tied to it.
the bottom priority and thus fixing all other priorities;
It should be noted that an IS bit that is masked by an i.e., if IR5 is programmed as the bottom priority device,
IMR bit will not be cleared by a non-specific EOI if the then IR6 will have the highest one.
8259A is in the Special Mask Mode, The Rotate command is issued in OCW2 where: R = 1,
SEOI =1; LO-L2 is the binary priority level code of the
AUTOMATIC END OF INTERRUPT (AEOI) MODE bottom priority device.
If AEOI = 1 in ICW4, then the 8259A will operate in AEOI Observe that in this mode internal status is updated by
mode continuously until reprogrammed by ICW4. In this software control during OCW2. However, it is independ.
m ode the 8259A will a u tomatically perform a n o n - ent of the End of Interrupt (EOI) command (also exe-
specific EOI operation at the trailing edge of the last cuted by OCW2). Priority changes can be executed dur-
interrupt acknowledge pulse (third pulse in MCS-80/85, ing an EOI command or independently.
page D.50

8259A

ACTINI BIT TO 01 HF R PRIOR TY CELLS

0 = EDGE CLR ISR
LEVEL
CLR ISR BIT

EDGE SET
SEIYSE P R I O 0 I TY
LATCH SE T ISR
RESOI VER
IIV SE RVICF
LATCH
CLR
Q

) CONTROL
LOGIC

0
SET REQUEST
LATCH
NON
D Q MASKED
MASH
LATE I REQ

C U D 0

0
CLR

FHI '1 INTI HNAL

DATA HUS

N Y
U 1
C>
0 CI CI
N 11 v,
IX

NOTES
I M A S T ER CLEAR ACTIVE ONLY DURING ICYTI
2 F R E EZE/IS ACTIVE DURING INTA/ AND POLL SEQUENCES ONLY
3 T R U T H TABLE FOR 0 LATCH

C
~ D Q 0 P E R A T0I N
I D D FQLLOTY
0 i X Qn-I HOLD

Priority Cell

LEVEL TRIGGERED MODE
This mode is programmed using bit 3 in ICW1.
If LTM = '1', an interrupt request will be recognized by a
'high' level on IR Input, and there is no need for an edge
detection. The i n t errupt request m us t b e r e m oved
before the EOI command is issued or the CPU interrupt
is enabled to prevent a second interrupt from occurring.
The above figure shows a conceptual circuit to give the
reader an understanding of the level sensitive and edge
sensitive input circuitry of the 8259A. Be sure to note
that the request latch is a transparent D type latch.
READING THE 8259A STATUS
The input status of several internal registers can be read
to update the user i nformation on th e s ystem, The
following registers can be read by issuing a suitable
OCW3 and reading with RD.
In-Service Register (ISR): 8-bit register which contains
the priority levels that are being serviced. The ISR is
updated when an End of Interrupt command is issued.
Interrupt Mask Register: 8-bit register which contains
the interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a WR
pulse is issued with OCW3 (ERIS = 1, RIS = 0.)
The ISR can be read in a similar mode when ERIS = 1,
RIS =1 in the OCW3.
There is no need to write an OCW3 before every status
read operation, as long as the status read corresponds
with the previous one; i.e., the 8259A "remembers"
whether the IRR or ISR has been previously selected by
the OCW3
After initialization the 8259A is set to IRR.

Interrupt Mask Register: 8-bit register whose content
specifies the interrupt request lines being masked.
acknowledged. The highest request level is reset from
the IRR w hen a n i n t e rrupt i s a c k nowledged. (Not
affected by IMR.}
For reading the IMR, no OCW3 is needed. The output
data bus will contain the IMR whenever RD is active and
AO = 1.
Polling overrides status read when P = 1, E R IS = 1 i n
OCW3.
 page 0.51

8259A

SUMM ARY OF 8259A INSTRUCTION SET

Inst. /I Mnemonic AO D7 D6 D5 D4 D3 D2 Dl DO Operation Description

ICW1 A7 AS 1 1 0 Format = 4, single, edge triggered

B
A
ICW1 A7 A6 A5 Format = 4, single, level triggered
ICW1 00 A7 A6 A5 B yte 1 Initialization F o r m a t= 4, not single, edge tnggered
ICW I A7 A6 A5 Format = 4, not single, level triggered
F
E
D
C
ICW1 A7 A6 N o ICW4 Required Fo r m a t= 8, single, edge trigiJered
ICW I A7 A6 Format = 8, single, level triggered
0
ICW I A7 A6 Format = 8, nol single, edge tnggered
H
G Format = 8, not single, level triggered
ICW1 A7 A6

9 ICW1 A7 A6 A5 Format = 4 single edge Iriggered

10 ICW1 A7 A6 A5 Format = 4, single, level triggered
BYte 1 Initialization = 4, not single, edge tnggered
11 ICW I A7 A6 A5
12 ICW1 N
M
L
JK A7 A6 A5 Format = 4, not single, level tnggered
ICW4 Required Format = 8, single, edge tnggered
13 ICW1 A7 A6
14 ICW1 A7 A6 Format = 8, single, level lriggered
00 Format = 8, not single, edge tnggered
15 ICW1 A7 A6
P
0
16 I CW I A7 A6 Format = 8, nol single, level triggered

17 ICW2 A15 A14 A13 A12 A 1 1 A10 AQ A8 B yte 2 in i t i a l izatio n

18 ICW3 M S7 86 S5 S4 S3 S2 Sl SO Byte 3 initialization — master

19 ICW3 62 Sl SO Byte 3 initialization — slave
20 ICW4 B
A
S No action, redundant
01
21 ICW4 00 00 00 00 01
I Non.buffered mode, no AEOI, MCS-86
00
1
22 ICW4 01
I Non-buffered mode, AEOI, MCS-80/85
0I
23 ICW4 Non-buffered mode, AEOI, MCS.86
F
E
D
C No action, redundant
24 ICW4
01
25 ICW4 01 Non-buffered mode, no AEOI. MCS.86
26 ICW4 0 Non-buffered mode, AEOI, MCS-80/85
G
H
27 ICW4 Non-buffered mode, AEOI, MCS-86
28 ICW4 Buffered mode, slave, no AEOI, MCS-80/85
29 ICW4 Buffered mode, slave, no AEOI. MCS-86
30 ICW4 Buffered mode, slave, AEOI, MCS-80/85
31 ICW4 JK
N
M
L Buffered mode, slave, AEOI, MCS-86
32 ICW4 Buffered mode, master, no AEOI, MCS-80/85
33 ICW4 Buffered mode, master no AEOI MCS.86
34 I CW4 Buffered mode, master AEOI, MCS.80/85
35 ICW4 NA
P
0 1 Buffered mode, master, AEOI, MCS-86
36 ICW4 Fully nested mode, MCS.60, non buffered, no AEOI
37 ICW4 NB 0 0 01
II ICW4 NB Ihrough ICW4 ND are identical to
38 I CW4 NC 0I1 ICW4 B through ICW4 D with the addition of
39 ICW4 ND Fully Nested Mode
40 ICW4 NE Fully Nested Mode, MCS-80/85,non buffered, no AEOI
41 ICW4 NF
42 ICW4 NG
43 ICW4 NH
44 ICW4 Nl
45 ICW4 NJ I11
I
ICW4 NF through ICW4 NP are identical to
46 ICW4 NK
ICW4 F through ICW4 P with the addition ol
47 ICW4 NL Fully Nested Mode
48 ICW4 NM
49 ICW4 NN
50 ICW4 NO 1
51 ICW4 NP
36 OCW1 M7 M6 M5 M4 M3 M2 Ml MQ Load mask register, read mask register
37 OCW2 E I 0 0 0 Non-specific EOI
01
38 OCW2 SE 0I 0 L2 Ll LO Specific EOI. LO-L2 code of IS FF to be reset
39 OCW2 RE 1 00 0 0 0 0 Rotate at EOI Automatically (Mode A)
0I
40 OCW2 RSE 1 L2 Ll LO Rotate at EOI (mode Bl LO-L2 code of line
41 OCW2 R 0 Set Rotate A FF
0 0
42 OCW2 CR 01 0 Clear Rotate A FF
01
43 OCW2 RS 0 L2 Ll LO Rotate pnonty (mode B) independently ol EOI
44 OCW3 P 01
I 1 0 Poll mode
0 0 01
45 OCW3 R IS 0 1 Read IS register
page 0.52

8259A

SUMMARY OF 8259A INSTRUCTION SET (Cont.)

Inst. TT M nemonic AO D 7 D 6 DS Da D3 D2 D1 DO Operation Description

46 OCW3 R R 0 0 0 0 0 1 0 1 0 Read request register

47 OCW3 S M 0 0 1 I 0 1 0 0 0 Set special mask mode
48 OCW3 AS M 0 0 1 0 0 I 0 0 0 Reset specialmask mode

Note. 1 I n t h e master mode SP pin = 1 in slave mode SP = 0

Cascading to release the device routine address during bytes 2 and

The 8259A can be easily interconnected in a system of
one master with up to eight slaves to handle up to 64
priority levels.
A typical MCS.80/85 system is shown in Figure 2. The
master controls, through the 3 line cascade bus, which
one of t h e s l aves w il l r e lease th e c o rresponding
address.
As shown in Figure 2, the slave interrupt outputs are
connected to the master interrupt request inputs. When
a slave'request line is activated and afterwards acknowl-
edged, the master will enable the corresponding slave
3 of INTA. (Byte 2 only for MCS-86).
The cascade bus lines are normally low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the trailing edge of the third pulse. It is
obvious that each 8259A in the system must follow a
s eparate i n itialization s e quence an d c a n b e p r o .
grammed to work in a different mode. An EOI command
must be issued twice: once for the master and once for
the corresponding slave. An address decoder is required
to activate the Chip Select (CS) input of each 8259A.
The cascade lines of the Master 8259A are activated for
any interrupt input, even if no slave is connected to that
input

ADOR ESS BLIS I16)

CONTROL BUS

OAT A BUS I 8)
L1 INT REO

CS Ae INT CS Ac INT CS Ae IN 1
CAS 0 CAS 0 CAS 0

92994 5299A 9299A

CAS I SLAVE B CAS I CAS I : AS E R
SLAVE A

CAS 2 CAS 2 CAS 2

S PIEN7 6 5 4 3 2 I 0 SPiENT 6 5 4 3 2 I 0 S PiENM7 M 6 r r15 M4 M 3 M 2 M l MO

7 6 6 4 3 2 I 0 7 6 5 4 3 2 I 0 5 4 3 2 I 0

INTERRUPT REOUESTS

Figure 2. Cascading the 8259A

 page D.53

8259A

PIN FUNCTIONS CS 1 Chip S e l ect: RD and WR are en-

Name I / O P i nf f
Vcc 28 + 5V supply.
GND 14 Ground.
Dp-7 I /O 1 1 - 4 Bidirectional data bus, used for:
a) programming the mode of the
8259A (programming is done by
software); b) the microprocessor
can read the status of the 8259A;
c) the 8259A will send vectoring
data to the microprocessor when
an interrupt is acknowledged.
IRP 7 I 18- 2 5 I nterrupt R equests: T h ese a r e
asynchronous inputs. A positive-
going edge will generate an i n-
terrupt request. Thus a r equest
can be generated by raising the
l ine and h o l d ing i t h i g h u n t i l
acknowledged, or by a negative
pulse. In level triggered mode, no
edge is required. These lines are
active HIGH.
RD 3 R ead (generally f r o m 8 2 2 8 i n
MCS-80 system or from 8086 in
MCS-86 system).
WR I 2 W rite (generally f ro m 8 228 i n
M CS-80 sytem or f ro m 8 086 i n
MCS-86 system).
I NTA I 26 Interrupt Acknowledge (generally
from 8228 i n M C S -80 s y stem,
8086 in MCS-86 system).The 8288
g enerates t h re e d i s t i nct I N T A
pulses when a CALL is inserted,
the 8086 produces two d i s tinct
INTA pulses during an interrupt
cycle.
abled by Chip Select, whereas In-
Function
t errupt A c k n o w l edg e i s in d e -
pendent of Chip Select.
AO I 27 Usually the least significant bit of
the microprocessor address out-
p ut. When A O= 1 th e I n t e r rupt
Mask Register can be loaded or
r ead. W he n A O= 0 t h e 8 259A
mode can be programmed or its
status can be read. CS is active
LOW.
IN T 0 17 G oes d i r ectl y t o t he mic r o -
processor interrrupt i nput. This
o utput w i l l h a v e h i g h V p „ to
match the 8080 3.3V Viih INT is
active HIGH.
CO-C2 I/O 12 Three cascade lines, outputs in
13 master mode and inputs in slave
15 m ode. The m a s ter i s s ues t h e
binary code of the acknowledged
interrupt level on these lines.
Each slave compares this code
with its own.
S P/EN I/ O 16 SP/EN is a dual function pin. In
the buffered mode SP/EN is used
to enable bus transceivers (EN). In
the non-buffered m od e S P/EN
determines if this 8259A is a mas-
ter or a slave. If SP = 1 the 8259A
is master; SP = 0 indicates a slave.

A BSOLUTE MAXIMUM RATINGS '

Ambient Temperature Under Bias . — 40 C to85 C COMM ENr
Storage Temperature. . . . . . . . . . . — 65 C to + 150 *C S tresses above those listed under " A bsolute Maximum Ratings" m a y
cause permanent damage lo the device This is a stress rating only and
Voltage On Any Pin functional operation of the device at these or any other conditions above
With Respect to Ground . . . . . . . — 0.5V to + 7V t hose indicated in th e o p erational sec t ions o f t hi s s p e c i f i c ation is n o t
Power Dissipation . . I Watt implied

D.C. CHARACTERISTICS
TA — O'C to 70' C V c c = 5 V ~ 5% (8259A-8) V( c= 5Ves 10% (8259A)
Symbol Parameter Min. Max. Units Test Conditions
V(L Input Low Voltage
Input High Voltage 2.0 Vcc+ .5V V
Vor Output Low Voltage .45 lpL = 2.2 mA

Vpft Output High Voltage 2.4 V I oft - — 400 frA

Interrupt Output High 3.5 Ipft = — 100 fxA
VpH(INT)
Voltage 2.4 V I pft - — 400 frA
Input Load Current 10 fr A VLhf — Vcc to OV
ibob Output Leakage Current — 10 RA Vpur = 0 45V
I Loft Output Leakage Current 10 fr A VpuT — VCC
lcc Vcc Supply Current 85 mA
page 0.54

8259A

8259A A.C. CHARACTERISTICS

TA= O'C to 70 C Vcc= 5V+ 5% (8259A.8) Vcc = 5V+ 10% (8259A)
TIMING REQUIREMENTS 8259A.8 8259A
Symbol Parameter M in. M ax. Min. Max. Unit s Test Conditions
TAHRL AO/CS Setup to RD/INTA( 50 0 ns
TRHAX AO/CS Hold atter RD/INTAf 5 0
TRLRH RD Pulse Width 420
TAHWL AO/CS Setup IDWR>
TWHAX AO/CS Hold after WRt
TWLWH WR Pulse Width
TDVWH Data Setup to WRt 300 240 ns
TWHDX Data Hold after WRt 40 0
TJLJH te rdqt Req est Width trq i t 00 100 ns See Note 1
TCV I AH Cascade Setup to Second or Third
55
tN~T At 0th e 0 t y j
TRHRL End of RD to Next Command 160 160
TWHRL End of WR to Next Command J 190 190 ns
Note: 1. This is the low time required to clear the input latch in the edge tnggered mode

TIMING RESPONSES 8259A.8 8259A

Symbol Parameter Min. Max. Min. M ax. U n its Test Conditions
TRLDV Data Valid from RD/INTA( 300 200 ns C of Data Bus = 100 pF
TRHDZ Data Float after RD/INTAt 20 200 100 ns C of Data Bus
TJ HIH Interrupt Output Delay 0 350 Max. test C = 100 pF
e 0~ t Min. test C = 15 pF
TIAHCV Cascade Valid from First INTA' 565
565 ns CiNr 100 pF
(Master Only)
TRLEL Enable Active trom RD> or INTA/ 160 125 ns CASCADE
TRHEH Enable Inactive from RDt or INTAt 325 150 ns
TAHDV Data Valid from Stable Address 350 200 ns
TCVDV Cascade Valid to Valid Data 300 ~ 300 s

CAPACITANCE
T A=25 O' Vc c = G N D = O V
Symbol Parameter Min. Typ. Max. Unit Test Conditions
CIN Input Capacitance 10 pF t c= 1 M H z
C I/O I/O Capacitance 20 pF Unmea s ured pins returned to Vss

Input Waveforms for A.C. Tests

2,4
2.2 2.2

TEST POINTS
0.8 0.8
0. 45
 page 0.55

8259A

WRITE MODE
TWLWH
WR

TAHWL TWHAX
CS

ADDRESS SUS
Ap
TDVWH ~ TW H D X

DATA SUS

READ/INTA MOD E
TRLRH
RD/INTA

TRLEL TRHEH

TAHRL TRHAX
CS
ADDRESS BUS
Ap
TRLDV TRHDZ
TAHDV-
DATA SUS-

OTHER TIMING

.TRHRL

TWHRL

INTA SEQUENCE
— TJHIH
IR

TJLJH

INT

INTA

oe

TCVIAH TCVIAH
i
TCVDV
CO2
— TIAHCV-
page 0.56

MC6$21
(1.0 MHz)
M Mor o a o az
MC6$A21
(1.5 MHz)

MC6$B21
(2.0 MHz)
PERIPHERAL INTER FACE ADAPTER (PIA)

The MC6821 Peripheral Interface Adapter provides the universal

means of interfacing peripheral equipment to the MC6800 Micro- MOS
processing Unit (MPU). This device is capable of interfacing the MPU
to peripherals through two 8-bit bidirectional peripheral data buses INcHANNEL, sILIcoN-GATE,
and four control lines. No external logic is required for interfacing to DEPLETION LOAD)
most peri phera I devices.
The functional configuration of the PIA is programmed by the
P ERIPHERAL I N T E R F A C E
MPU during system initialization. Each of the peripheral data lines
can be programmed to act as an input or output, and each of the ADAPTER
four control/interrupt lines may be programmed for one of several
control modes. This allows a high degree of flexibility in the over.all
operation of the interface.
• 8- B it Bidirectional Data Bus for Communication with the MPU
• Tw o B idirectional 8-Bit Buses for Interface to Peripherals
• Tw o Programmable Control Registers
• Tw o P rogrammable Data Direction Registers L SUFFIX
CERAMIC P A C K A G E
• Fo u r I n dividually. Controlled Interrupt Input Lines; Two Usable CASE 715
as Peripheral Control Outputs
• Ha ndshake Control Logic for Input and Output Peripheral
Operation
• Hi g h-Impedance 3-State and D irect T ransistor Drive Peripheral
Lines
• Pr o gram Controlled Interrupt and Interrupt Disable Capability
P SUFFIX
• CM OS Drive Capability on Side A Peripheral Lines PLASTIC P A C K A G E
C ASE 7 1 1

• Tw o T TL Drive Capability on All A and B Side Buffers

• TT L - Compatible
• St a tic Operation PIN ASSIGNMEN T

O CA1 40
vss
PA0 CA2 39
P A1 iR OA 38
P A2 IR O B 37
P A3 RS O 36
PA4 35
ORDERING INFORMATION
PA5 Re se t 34
Device Temperature Range PA6 DO 33
1.0 MHz MC6821P, L 0 to+700C PA7 Di 32
MC6821CP, C L -40 to +850C 10 PBO D2 31

M I L-STD-8838 — 55 to+1250C P81 D3 30

MC6821BQCS
D4
M I L-STD-883C MC6821CQCS 12 P82 29
13 P83 DS 28
1.5 MHz MC68A21P, L 0 to+700C
14 P84 D6 27
MC68A21CP, CL -40 to +850C
15 PBS D7 26
2.0 MHz MC68821P, L 0 to +700C
16 PB6 5 25
17 P 87 CS 1 24
18 C81 CS2 23
19 C82 CS0 22
20 Vcc R/W 21
 page 0.57

MC6821

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -0.3 to + 7.0 Vdc T his device cont ains circuitr y t o p r o t ect t h e

Input Vo ltage Vin -0.3 to +7.0 Vdc inputs against damage due to high static voltages
or electric f i e lds; however, i t i s a d v ised t h at
Operating Temperature Range TA TL to TH
'C normal precautions be taken to avoid application
MC6821, MC68A21, MC68821 0 to 70
'C o f an y v o l t age h i gher t h a n m a x i mu m r a t e d
MC6821C, MC68A21C — 40 to 85
'C voltages to this high impedance.
MC6821CQCS, MC6821BQCS -55 to 125
Storage Temperature Range Tstg -55 to +150 'C
Thermal Resistance aJA 82.5 C/W

ELECTRICAL CHARACTERISTICS (VCC = 5 .0 V 5 ' . V SS = 0, TA = TL to T H u n l ess otherwise noted)

Characteristic Symbol Min Typ Max Unit

BUS CONTROL INPUTS (R/W, Enable, Reset, RSO, RS1, CSO, CS1, CS2)
Input High Vo ltage V IH VSS + 2,0 VCC .Vdc
Input Low Vo ltage VSS -0 3 VSS + 0.8 Vdc
Input Leakage Current I in 1.0 2.5 rr Ado
( Vin : 0 t o 5 ,25 Vdc l
Capacitance C I rl 7.5 pF
(V,n = 0, T A = 25 C, f = 1.0 M H z l

INTERRUPT OUTPUTS (IRQA, IRQB)

Output Low V o ltage VOL VSS + 0.4 Vdc
(ILoad = 3.2 mAdc)
Output Leakage Current (Off State) ILOH 1.0 10 Ir Adc
(VOH = 2,4 Vdc)
Capacitance Cout 50 pF
0, TA = 25 C, f = 1.0 M H z l

DATA BUS (DO-D7)

Input High V o l t age VIH VSS + 2.0 VCC Vdc
Input Low V o l t age VIL VSS — 0.3 VSS + 0.8 Vdc
Three-State (Off State) Input Current ITS) 2.0 10 /zAdc
(Vin = 0 4 to 2 4 Vdc)
Output H igh V o l t age VOH VSS + 2.4 Vdc
'll I oad = - 205 PAdc)
Output Low Vo ltage VOL VSS + 0.4 Vdc
(I Load = 1.6 mAdc)
Capacitance Cin 12.5 pF
V ~n'O T A 25 C, ( 1,0 MH z )
PERIPHERAL BUS (PAO-PA7, PBO-PB7, CA1, CA2, CB1, CB2)
Input Leakage Current R/ W, R e set, RSO, RSI, CSO, CS1, CS2, CA1, I in 1.0 2.5 rr Adc
( Vin 0 t o 5 . 2 5 V d c ) CB1, Enable
Three State (Off State) Input Current PBO-PB7, CB2 ITS I 2.0 10 )r Adc
(V,„ = 0.4 to 2.4 Vdc)
Input High Current PAO-PA7, CA2 -400 Ir AdC
(VIH = 2.4 Vdc)
Darlington D r ive Current PBO-PB7,CB2 IOH — 1.0 — 10 mAdc
= 1.5 Vdc
Vo
Input Low Current PAO-PA7, CA2 — 1.3 — 2.4 mAdc
(VIL = 0.4 Vdc)
Output High Vo ltage VOH Vdc
(ILoad = - 200 IrAdc) PAO-P7, PBO-PB7, CA2, CB2 VSS + 2.4
(I I oad = 10 IrAd&) PAO-PA7, CA2 VCC — 1.0
Output Low V o ltage VOL VSS + 0.4 Vdc
()Load= 3.2 mAdc)
Capacnance Cin 10 pF
(V in 0 TA 25 C f 1,0 M Hz )
POWER REQUIREMENTS
Power Dissipation PD 550 mW
page 0.58

MC6821

BUS TIMING CHARACTERISTICS IvCC = s.O v s)s, vSS=O, TA = TL to THunie.s othe~i sa specified.)
MC6621 MC68A21 MC66B21 Ref.
Charact
eristic Symbol Min Max Min Max Max Unit Fig. No.
Enable Cycle Time tcycE 1 000 666 500 ns
Enable Pulse Width, High PWEH 280 220 ns
Enable Pulse Width, Low PWEL 430 260 210 ns
Enable Pulse Rise and Fall Times t Er t E I 25 25 25 ns
Setup Time, Address and R/W valid tAS 160 140 70 ns 2,3
to Enable positive transition
Address Hold Time tAH 10 10 10 ns 2,3
Data Delay Time, Read IDDR 320 220 160 ns 2,4
Data Hold Time, Read tDHR 10 10 10 ns 2,4
Data Setup Time, Write tDSW 195 80 ns 3,4
Data Hold Time, Write tDHW 10 10 1P 3,4

FIGURE 2 — 6US READ TIMING CHARA C T E R ISTICS

FIGURE 1 — ENABLE SIGNAL CHARACT ERISTICS (Read Information from PIA)

20

tcycE Enable 0.8 0.8

PWEH PWE L tAS tAH

tEr tFf
RS, 20V 2.0 V
2.0 V 2.0 V Cs,
R/W 08 V 08 V
Enable
tDD R IDHR
0,8 V 0.8 V 0.8 V
Data Bus 24 V 24 V

04 V 0,4 V

FIGURE 3 — BUS WRITE TIMING CHARA C T E RISTICS

FIGURE 4 — BUS TIMING TEST LOADS
)Write Information into P IA)

2.0 2.0 )DO —

D7)
0.8 0.8 5.0 V

tAS tA H RL 2 5 k

Rs, 2.0 2.0 MMD6150

Test Point
Cs, or Equiv.
R/W 0.8 0.8
C R
tDS tDHW 130 PF t1.7 k MMD 7000
or Eouiv.
2.0 2.0

0.8 0.8
 page 0.59

MC6821

PERIPHERAL TIMING CHARACTERISTICS (VCC = 5.0 V S5'/ , V S S 0 V , T A = TL to TH unless otherwise specified.)

MC6821 MC68A21 MC68 B21 Reference
Ch arac ter i stic Symbol Min Max Min Max Min Max Unit Fig. No.
Peripheral Data Setup Time tPDSU 200 135 ns
Peripheral Data Hold Time tPDH 0 ns
Delay Time, Enable negative transition to CA2 ICA2 1.0 0.670 0.500 ps 5,9, 10
negative transition
D elay Time, Enable negative transition to C A 2 tRS1 1.0 0.670 0.500 si s 5,9
p ositive transit io n
Rise and Fall Times for CAI and CA2 input signals 1.0 1.0 1.0 5, 10
Delay Time from CAI a ct ive transition to CA2 tRS2 2.0 1.35 1.0 rr s 5, 10
positive transition
Delay Time, Enable negative transition to Peripheral IPDW 1.0 0.670 05 ps 5, 11, 12
Data Valid
Delay Time, Enable negative transition to Peripheral ICMOS 2.0 1.35 1.0 6, 11
CMOS Data Valid PAO-PA7, CA2
D elay Time, Enable positive transition to C B 2 ICB2 1.0 0.670 0.5 Jr S 5, 13, 14
n egative transitio n
Delay Time, Peripheral Data Valid to CB2 tDC 20 20 20 ns 5, 12
negative transition
Delay Time, Enable positive transition to CB2 'RSI 1.0 0.670 0.5 ps 5, 13
posit ive transit ion
Peripheral Control Output Pulse Width, CA2/CB2 PWCT 550 550 ns 5, 13
Rise and Fall Time for CBI and CB2 input signals 1.0 1.0 1.0 14
Delay Time, CBI active transition to CB2 IRS2 2.0 1.35 1.0 5, 14
o sitive transit io n
Interrupt Release Time, IRQA and IROB I IR 1.60 1.10 0.85 rr s 7, 16
Interrupt Response Time tRS3 1.0 1.0 10 7, 15
Interrupt I n pu t P ulse Width PWI 500 500 ns 15
R eset Low Tim e ' tRL 1.0 0.66 0.5 17
'The Reset line must be high a minimum of 1.0 rrs before addressing the PIA.

FIGURE 5 — TTL EQUIV. TEST LOAD FIGURE 6 — CMOS EQUIV. TEST LOAD F IG U R E 7 — NMOS EQUIV. TEST LOAD

(PAO — PA7, PBO —

PB7, CA2, CB2) (PAO-PA7, CA2) ( I R Q Only )

Vcc
5.0 V
Ru
Test
P oin t MMD6 I 50 T est P o i n t 3k
o r Equ i v .
Vi

30 pF T est Po i n t

C 4 0 p F , R —t 2 k
M MD 7 0 0 0
o r Equ i v .
I 1 00 P F

A dlust R L s o t h a t I I — 3.2 m A
W ith V l — 0 4 V a n d V C C = 5.2 5 V
page D.60

MC6821

FIGURE 8 — PERIPHERAL DATA SETUP AND HOLD TIMES FIGURE 9 — CA2 DELAY TIME
(Read Mode) (Read Mode; CRAW C R A- 3 1 ,C RA 4 0)

PAO.PA 7 2.0 V
E nable 0.8 V
PBO P87 0.8 V

tposu tPDH tCA2 tRS1

PWCA 2.4 V
2.4 V CA2
E nable 0.4 V
08 V

Assumes part was deselected during

the previous E p u lse.

FIGURE 10 — CA2 DELAY TIME FIGURE 11 — PERIPHERAL CMOS DATA DELAY TIMES
(Read Mode; CRA-5 n 1, CRA-3 = CRA 4 0) (Write Mode; CRA-5 ~ CRA-3 = 1, CRA4 ~ 0)

E nable
0.8 V
E nable
08 V
tCMOS
2.0 V --- - - - - v c c -eo"- vcc
CAI tpow
0.8 V
PAO PA 7 2 4 V
'CA2 IRS2 CA2 04 V
2.4 V
CA2
0.4 V

FIGURE 12 — PERIPHERAL DATA AND CB2 DELAY TIMES FIGURE 13 — CB2 DELAY TIME
(Write Mode; CRB-5 = CRB-3 1 , C R B 4 = 0) (Write Mode; CRB-5 = CRB-3 1 , C R B 4 n 0)

E nable
0.8 V
E nable
2.0 V
tpow
24 V i- iCO7 tRS I
PBO PB7
04 V
PWCA 2.4 V
IDC CB2 0 4V

2.4 V
CB2

C 82 N o t e . C 8 2 g o e s low ss 4 result of t h e ' Assumes part was deselec ted during th e

positive transition of E n a ble. previous E pulse

FIGURE 14 — CB2 DELAY TIME

FIGURE 15 — INTERRUPT PULSE WIDTH AND IRQ RESPONSE
(Write Mode; CRBW n 1, CRB-3 ~ CRB4 0)

E nable 2.0 V

CA1, 2 20V
CBI 2.0 V C81, 2 0.8 V
0.8 V
tc82
2.4 V I RGA/8 I 0.4 V
CB2
0.4 V RS3
'Assumes pert was deselected dur ing 'Assumes Interrupt Enable Bits sre set.
sny previous E pulse.
 page 0.61

MC6821

FIGURE 16 — IRG RELEASE TIME FIGURE 17 — RESET LDW TIME

2.0 V
F nal>le

'iR Reset 0.8 V

24 V

I RQ
' Th e R e set l i n e m u s t b e a V I H f o r a m i n i m u m o f
1.0 Its bef or e ad d r essing th e PI A.

EXPANDED BLOCK DIAGRA NI

IRQA 38 40 CA)
I nter r u p t S t a t u s
Contro l A
3 9 CA 2
C on t r o l
R egiste r A
DO 33 ( CRA )
DI 32 D ata D i r e c t i o n
D2 3 1 Register A
D ata B u s
( DDRA )
D3 30
Buf fers
D4 29 ( DBB ) O utpu t B u s
D5 28
06 2/ 2 PAO
O utp u t 3 PA 1
D7 26
R egiste r A
4 PA2
( OR A )
Peripheral 5 PA3
Interface 6 PA4
A
3 7 PA5
B us I n p u t lb
Registe r 8 PA6
3
( BIR ) c
Q 9 PA 7

Pin 2 0
10 PBO
V SS = P n I
O utpu t 11 P81
R egiste r 8
12 P82
( ORB )
C SO 2 2 Per i p her aI 13 P83
Cs l 24 Interface
8 14 P84
C S2 23 C hi p
15 P85
Select
R SO 3 6 16 P86
and
RS I 35 RW 17 P87
C ont r o l
R /W 21
5 nable
Reset 34
D ata Direct io n
C ont r o l Register 8
Register 8 (DDRB)
(CRB )

18 CB1
I nterr up t S t a t u s
I RQB 3 7 C ontro l 8
19 C82
page 0.62
MC6821
PIA INTER FACE SIGNALS FOR MPLI
The PIA in terfaces to the M C6800 MPU with an eight
b it b i d i r e c t i o na l d a t a b u s , t h r e e c h i p s e l ec t l i n es, t w o
register select lines, two in t err upt request lines, read/writ e
l ine, enable line and reset line. T hese signals, in co n j u n c
t ion w i t h t h e M C 6 8 0 0 V M A o u t p u t , p e r mi t t h e M P U t o
h ave complete control over the PI A V M A s h o ul d be u t i
lized in co nj unct io n w i t h a n M P U a d d ress line into a chip
select of the PIA.
P IA B i D i r e c t i o na l D a t a ( D O - D 7 ) T h« h i d ii « c t i o n a l
<lat,> lii>«s (DO D7) a l lo w t h e t i a n s fe i o f d a t a h e <we«i> tli«
MPU arid t h e P I A T l> « d a t a h u s o u t p u t d r i v er s ai « t h r««.
sta<«d«v ic«s t h a t i e n i a in ii > t he hi gh i n i p i i d a n c « ( o f f ) s t a t e
except w l i « n t h e M P U pe< forn>s a PIA i «a<) op<>ratio<i Th«
Read/Write l i i i e i s ii> the Read ( h i gh ) stat<.' wh«i> the Pl A
i s select«d fo r a R « a d o p e i a t i o i >
P IA E n a ble (E ) Th e en a b l e p u l se, E , i s t h « o n l y
timii>g s i gi>al t h a t i s s < i p p l i e d t o t he P I A Ti m ii i g o f a l l
other s<g»als is i<".fei«nc«d t o t h « l « a d in g ai>d tra i l ii>g «<lg«s
of <h« E p u l s « T I » s s i g nal w i l l i i o i <nally l>«a <l«i<va«v< of
<h«MC6800 C>2 Clock
P IA R e ad/Write ( R / W ) Th is s i g i ia l i s gene<at«<l hy
t he MP U t o c o n t r o l t h e < l i r e c t i o i i o f d a t a t r a n s f ers oi i t h «
Data Bu s A l o w s t a t « o » t h e P I A R e ad / W r it e l in e «i>able>
tli« iiiput t>Offers and <fata is transferred tron> the MPU to
t he PI A oi> the E s i g i ial i f t h e d e v i « « h a s been selected A
high oii t l i « R e a d / W r i t e l i i i « s e t s «p th e P I A f o r a t i a i l s f <ir of
d ata to t h « h u s T h e P I A o u t p u t h u f f « i s are «iiahled w h « n
t h« p r o p « i ,i d d i « s s an d t h e e n a b l e p u l s e E a r e p i « s e n t .
Reset — The ac t iv e l o w R e s e t l i n e i s u s e d t o r e s e t
, >II ii.'gist«i h i t s i n t h e P I A t o a l o g i c a l z er o ( l o w ) T h i s l i n e
< 'aii t>e used as a power on reset and as a iiiastei reset d u r i n g
s ystf'n> OP«rdt l o l >
PIA Chip Select (CSO, CS1 and CS21 16« s e t h r «« iiipiit
signals are used t o s e lect th e PI A C S O arid CS I i n u s t h <.
Iiigh a<id C S 2 i n u s t h e l o w f o r s «l«ctioi> o f t h « d«v i c e
D ata transfers are then performed under the cont rol of t h e
Enable and R e ad /W r it e signals. The c hi p select l i i ies must
lie stable fo r t h e d u r a t io n o f t h e E p u l s e T h e d e v ice is
d eselected w h e n a n y o f t h e c h i p s e l e ct s a r e i n t h e
inactive state.
PIA Register Select (RSO and RS1) — The two reg ister
s elect lines are used t o s e l ect t h e v a ri ous registers in side
t he P IA . T h es e t w o l i n e s ar e u sed i n c o n ) u n c t io n w i t h
internal ( ontro l R e g isters t o s e l ec t a p a r ticular r e g ister
t hat is to b e w r i t t e n o r r e a d .
The register and c hi p select lines should be stable for
the duration of the E pulse while in the read or write cycle.
Interrupt Request (IRQA and IRQB) The a c t i ve low
Interrupt Request lines (IRQA and IRQB) act to interrupt
t he MP U e i t h e r d i r e c tl y o r t h r o u g h i n t e r r up t p r i o r i t y
circuitry T h ese lines are "open drain" (no load device on
the chip) T h i s p e rm its all i n t errupt r equest lines to be
tied together in a wire-OR configuration
Each Interrupt R e q uest l ine has tw o i n t e r nal interrupt
flag bits t hat ca n c ause the I n t errupt R equest line to go
low. Each flag bi t i . associated w it h a p a r t i c u lar peripheral
interrupt l i ne . A lso f ou r i n t e r r upt enable bits are provided
in t h e P I A w h i c h m ay h e u s e d t o in h i b i t a par t i c u l a r
interrupt f ro m a peripheral device.
Servicing an i n t e r rupt b y t h e M P U m a y b e a c com-
plished by a software routine that, on a pr ioritized basis,
sequentially reads and tests the tw o c o n t ro l r egisters in
each PIA for interrupt flag bits that are set.
The interrupt flags are cleared (zeroed) as a result of an
MPU Read Peripheral Data Operation of the corresponding
d ata register. A f t e r b e in g c leared, th e i n t errupt f l ag b i t
cannot be enabled t o b e se t u n t i l t h e P I A i s d e selected
d uring an E p u l se. Th e E p u l s e i s used to c o n d i t io n t h e
i nterrupt c o n t ro l l i n e s ( C A 1 , C A 2 , C B 1 , C B 2 ) . W h e n
t hese lines ar e u se d a s i n t e r r up t i n p u t s a t l e ast on e E
p ulse must o c c u r f r o m t h e i n a c t iv e e dg e t o t h e a c t i v e
edge of t h e i n t e r r up t i n p u t s i g nal t o c o n d i t i o n t h e e d ge
sense network. I f t h e i n t errupt f lag has been enabled and
the edge sense c i r cui t h a s b e e n p r o p erly c o n d i t i o ned,
t he int er r up t f l a g w i l l b e se t o n t h e n e x t a c t ive t r ansit io n
o f the in t e r r up t i n p u t p i n

MC6821
P IA PERIPHERAL I N T E R F AC E L I N E S
The PIA p r o v i des tw o 8 b i t b i - d irectional data buses
a nd four i n t e r r u p t / c o n t ro l l i nes fo r i n t e r f acing to p e r i p h
eral devices.
Section A Peripheral Data IPAO-PA7) — E ach of t h e
peripheral data lines can be programmed to act as an input
o r ou t p ut . T h i s i s a c c o m p l ished b y s e t t in g a " 1 " i n t h e
c orresponding D a t a D i r e c t io n R e g ister hi t f o i t h o s e l i n e s
w hich are t o b e o u t p u t s . A " 0 " i n a h it o f t h e D a t a
Direction R e g i ster c a u ses t h e c o r r e spoiidin g p e r i p heral
data lir~ to act as an input. During an MPU Read Pei ipheral
Data Operation, th e d ata on p e r i p heral lirtes programmed
to act a s i n p u t s a p pears directly o n t h e c o r r esponding
M PU Data B u s l i n es. I n t h e input mode t h e i n t e i n al
pullup resistor on these lines represents a maximum of 1.5
standard TTL loads.
The data in O u t pu t R egister A w i l l a ppear on the data
l ines that are p r ogrammed t o b e o u t p u ts. A l o g i cal " I "
w ritten i n t o t h e r e gister w il l c ause a " h i gh " o n t h e c o r
r esponrfing data line w h ile a " 0 " r e s u lt s iii a " l o w " . D a t a
in Out pu t R e g ister A m a y b e r e a d b y a n M P U " R e a rl
Peripheral D at a A " o pe r a t io n w h e n t h e c o r r esponding
lines are programmed as o u t p uts. T his <fata will be reail
properly i f t h e v o l t a g e o n t h e per i p h e ra l d a t a l i n e s
i s greater t h a n 2 . 0 v o l t s f o r a lo g i c "1" o utput a n r l
l ess than 0. 8 v o l t f o r a l o g i c " 0 " o u t p u t . L o a d ing t h i'
output l i nes such t hat t h e v o l t age on t h iise lines does not
reach full voltage causes the data transferred into the MPU
o n a Read operation t o d i f f e r f r o m t h a t c o n t a i ned in t h e
respective bit of O u t p u t R e gister A.
Section B Peripheral Data (PBO-PB7) —The peripheral
data lines in th e B Section of t h e PIA can be programmed
page 0.63
to act as either i n p uts or o u t p ut s in a similar manner to
PAO-PA7. However, the output buffers driving these lines
differ from those driving lines PAO-PA7. They have three
state capability , a l l o w in g t he m t o e n t e r a Ii igh im pedaitce
state when th e p e r i pheral data l in e is used as an i nput I n
a ddition, d at a o n t h e p e r i p h eral d at a l i nes PBO PB7 wi l l
be read I>roperly fro m t l i ose lines prograrnrned as outputs
e ven if t h e v o l t ages are below 2.0 v o lts fo r a " h i g h" . A s
outputs, these lines are compatible with standard TT L and
may also be used as a source of up to 1 ni i l liampere at I 5
v olts t o d i r e c t l y r l r i v e t h e b a s e o f a t ra i i s i s to r s w i t c h
Interrupt Input (CA1 and CB1) — Peripheral lii p ut l i n e s
CA1 and CB 1 ar e i n pu t o n l y l i nes that set the i n t errup t
flags of the control registers. The active traiisition fo r t h ese
signals is also p rogrammed hy the tw o c o n t r o l r e gisters.
Peripheral Control ICA2) — The peripheral control line
C A2 can be p r o gramme(3 to act as an interrupt i n pu t o i a s
a peripheral con t ro l o u t p u t . A s an ou t p ut , t h is line is corn
p atihle w i t h s t a n d ard T T L , as an in pu t t h e i n t e r rial pu l l u p
resistor on t hi s l ine represents 1.5 standard TTL loads.
T he function o f t h i s s i gnal l ine i s p r ogrammed w it h
Control Register A.
Peripheral Control IC 82) — Per i pher a I Con tr o I line C B2
m ay also h e p r o g r am med t o a c t a s an i n t e r r up t i n p u t o r
p eripheral c o n t r o l o u t p u t . A s a n i nput , t h i s l i n e h a s
h igh i n p u t i m p e d a nc e a n d is co m p a t i b l e w i t h s t a n d .
ard T T L A s an o u t p i i t i t i s c o m p a t i bl e w i t h s t andard
T TL an d m a y a lso b e u sed as a source of u p t o 1 m i l l i
ampere at 1.5 volts to directly drive the base of a transistor
s witch. T h i s l i n e i s p r o g r a m me d b y C o n t r o l R e g i ster B
page 0.64

MC6821

INTERNAL CONTROLS

There are six locations within the PIA accessible to the CONTROL REGISTERS (CRA and CRB)
M PU data b u s : t w o P e r i pheral Registers, tw o D a t a The two Control Registers (CRA and CRB) allow the
Direction Registers, and two Control Registers. Selection MPU to c o n t ro l t h e o p eration o f t h e f o u r p e ripheral
of these locations is controlled by the RSO and RS1 inputs control lines CA1, CA2, CB1 and CB2. In addition they
together w it h b i t 2 i n t h e C o n t r o l R e gister, as shown allow the MPU to enable the interrupt lines and monitor
in Table 1 t he status of th e i n terrupt flags. Bits 0 through 5 of t h e
two registers may be wr i t ten or r ead by th e MPU when
TABLE 1 — INTE RNAL ADDRESSING the proper c h i p s e lect a n d r e gister select signals are
Cont roI applied. Bits 6 and 7 o f t h e tw o r egisters are read only
Register Bir and are modified b y e x t ernal i n terrupts occurring on
RSI RSO CRA 2 CR B.2 Location Selected control lines CA1, CA2, CB1 or CB2. The format of the
Peripheral Register A control words is shown in Table 2.
Data Direcuon Register A
T ABLE 2 — CONTROL WOR D FO R M A T
Control Register A
5 4 3 I 0
Peripheral Register B
CRA IRQA1 IRQA2 CA2 Control DORA CA1 Co ntrol
Data Direction R egister 8
Access
Control Register B
5 4 3 I 0
X — Don't Care CRB I ROB 1IRQB2 CB2 Control DDR B CB 1 Control
Access
I NI TIA LI ZATION
A low reset line has the effect of zeroing all PIA regis-
ters. This will set PAO-PA7, PBO-PB7, CA2 and CB2 as Data Direction Access Control Bit (CRA-2 and CR B2)-
inputs, and all interrupts disabled. The PIA m ust be con- Bit 2 i n each Control register (CRA and CRB) allows
figured during the restart program which follows the reset. selection of either a Peripheral Interface Register or the
Details of possible configurations of the Data Direction Data Direction Register when the proper register select
and Control Register are as follows. signals are applied to RSO and RSl.
Interrupt Flags (CRA-6, CRA-7, CRB-6, and CRB-7)-
DATA DI RECTION R EGISTERS (DORA and DDRB) The four interrupt flag bits are set by active transitions of
T he tw o D a t a D i r e c t ion R e gisters allow t h e M P U t o signals on the four Interrupt and Peripheral Control lines
control the direction of d ata through each corresponding when those lines are programmed to be inputs. These bits
peripheral data l i ne. A D a t a D i r ection Register bit set at cannot be set directly f ro m t h e MP U D ata Bus and are
" 0" c o n f igures the corresponding peripheral data line as reset indirectly b y a R e ad Peripheral Data Operation on
a n input; a "1 " r esults in an output . the appropriate section.

TABLE 3 — CONTROL OF INTERRU PT INPUTS CA1 AND CB1

MPU Interrupt
CRA-1 CRA-0 Interrupt Input Interrupt Flag Request
(CRB-I ) (CRB-0) CA1 (C81) CRA-7 (CRB-7) I%Pi (IROB)
Active Set high on s of CA1 Disabled — KQ re-
(CB1) mains high
, Actwe S et high on l o f C A 1 G oes lo w w h e n t h e
(CB1) interrupt flag bil CRA-7
(CRB-7) goes high
Aclive Set high on ' of CA 1 Disabled — ITAL re-
(CB1) mains high
Act we S el high on I o f C A 1 G oes low w he n t h e
(CB1) interrupt flag bit CRA-7
(CRB-7) goes high
N otes I I indicates positive transition (low to high)
I indicates negative transition (high Io low)
The Interrupt liag bit CRA.7 is cleared by an MPU Read of the A Data Reg ister,
and CRB-7 is cleared by an MPU Read of the B Data Register
If CRA-0 (CRB-0) is low when an interrupt occurs (Interrupt disabled) and is later brought
high, IRQA (IRQBI occurs after CRA-0 ICRB-0) is written Io a "one".
 page 0.65

MC6821

Control of CA1 and CB1 Interrupt Input Lines (CRA-O, used to enable the MPU interrupt signals IRQA and I ROB,
CRB-O, CRA-1, and CRB-1) — The two lowest order bits respectively. Bits CRA 1 an d C R B. 1 determine the active
of the control r egisters are used to control the interrupt t ransition o f t h e i n t e r r up t i n p u t s i g nals CA 1 a n d C B 1
input lines CA 1 an d C B1 . B it s C RA O an d C R B-0 are (Table 3).

TABLE 4 — CONT RO L OF CA2 ANO CB2 AS INTER R U P T INPUTS

CRA5 ICR85) is low

MPU Interrupt
CRA-5 CRA-4 CRA-3 Interrupt Input interrupt Flag Request
(CRB-5) (CRB-4) (C R 8-3) CA2 (CB2) CRA-6 (CRB-6) IRRA (I~RB)
Active S et high on i o f C A 2 Disabled — 1RU re-
(CB2) mains high
Active Set high on , o f C A2 G oes low w hen I h e
(CB2) interrupt tlag bit CRA.6
( CRB-6) goes h i g h
Active S et high on ' o f C A 2 Disabled — le% re-
ICB2) mains high
' Active S et high on ' o t C A 2 G oes low w hen t h e
iCB2) rpt flagbil C RA-6
interu
( CRB-6) g oe s h i g h

N otes I ' indicates positive transition liow to high)

. indicates negative transition thigh to low)
The Interrupt flag bit CRA-6 isclearedby an MPU Read of the A Data Register and CRB-6 is
Cleared by an MPU Read of the B Data Register
If CRA-3 (CRB-3) is low when an interrupt occurs (Interrupt disabled) and is later brought
h igh, IRQ A l I R Q B l o c c urs aftei CR A 3 l C R B 3 l i s w r i t t e n t o a " o n e "

TABLE 5 — CONT RO L OF C82 AS A N OUTP U T

CRB-5 is high

CB2
CRB-5 CRB-4 CR B-3 Cleared Set
Low on the posilive transition of High when lhe interrupt flag bit
t he first E p u ls e f o l lowing a n CRB-7 is set by an active transi-
MPU Write B D ata R e g i ster tion of the CBI signal
o'peration
L ow on th e po sit ive transit ion o f I -ligho n t he p o s itive e dg e o f
t he f i rst E p u l se af ter a n M P U t he first " E " p u l s e f o l l o w i n g an
Write " B " D a t a R e g i ster op era- "E" p u l se w h ic h o c c u r red w hile
tion the part was desefected
Low when CRB-3 goes low as a Always low as long as CRB-3 is
result of an MPU Write in Control IOW Will gO high on an MPU Write
Register B i n Control R e g i s te r B t ha t
changes CRB-3 to one
Always high as long as CRB-3 is High when CRB-3 goes high as a
h igh W i l l b e c l e a red w h e n a n r esult of an M PU Wr i t e i nt o
MPU Wnte Control Register B C ontrol Register "B" .
results in c l e a r ing C R B -'3 to
zero
page 0.66

MC6821

Control of CA 2 an d CB 2 Pe ripheral Control L i n es is low, CA 2 ( C B2 ) i s an i n terrupt input line similar to

(CRA-3, CRA-4, CRA-S, CRB-3, CRB-4, and CRB-5)-
Bits 3, 4, and 5 o f t h e tw o control registers are used to
control the CA2 and CB2 Peripheral Control lines. These
bits determine if t h e c o n t rol l i nes will be an i nterrupt
input or an output control signal. If bit CRA-5 (CRB-5)
CA1 (CB1) (Table 4). When CRA.5 (CRB-5) is high, CA2
(CB2) becomes an output signal that may b e u sed to
c ontrol p eripheral data t r ansfers. When i n t h e o u t p u t
mode, CA2 and CB2 have slightly different characteristics
(Tables 5 and 6),

TABLE 6 — CONTROL OF CA-2 AS AN OUTPUT

CRA-5 is high
CA2
CRA-5 CRA4 CRA-3 Cleared
Low on negative transition of E High when the interrupt flag bit
a fter an M P U R ea d " A " Da t a CRA.7 is set by an active transi-
operation. tion of the CA I signal.
Low on negative transition of E High on t h e n e gative edge of
a fter an M P U R ea d " A " Da t a the first "E" p ulse which occurs
operation. during a deselect.
Low when CRA-3 goes low as a Always low as long as CRA-3 is
result o f an M PU W r ite to l ow. Will g o h i gh o n a n M P U
C ontrol Register "A " . W nte t o C o n t ro l R e gister " A "
t hat changes CRA.3 t o " o n e " .
Always high as l ong as CRA .3 High when CR A.3 goes high as
i s high. W il l b e c l e ared o n a n a result o f a n M P U W r i t e t o
MPU Write t o C o n t r o l R e gister C ontrol Register "A" .
"A" t hat c l e a r s C R A 3 to
a "zero".

PACKAGE DIMENSIONS

•0
MILLIMETERS INCHES
CASE 711-01 DIM MIN MAX MIN MAX
P LAST IC 51.82 52,32 2. 040 2.060
13 72 14 22 0 540 0 560
4. 57 5.08 0.180 0.200
0 20
0. 36 0. 51 0.014 0.020
1.02 1. 52 0.040 0.060
2.41 2. 67 0.095 0,105
1. 65 2.16 0.065 0.085
0,20 0. 30 0.008 0.012
3.68 4. 19 0.145 0.165
14.99 15,49 0. 590 0,610
100 100
0.51 1. 02 0.020 0.040
— lel-- 3! D S EATING -' ~ M
PLANE

MIL L I ME
TE RS INCHES
DIM MIN MAX MIN MAX
NOTE 50.29 51.31 1,980 2.020
1. LEADS, TRUE POSITIONED WITHIN 14.86 15.62 0.585 0.615
0.25 mm (0.010) DIA IAT SEATING 2.54 4.19 0.100 0.165
PLANE), AT MAX. MAT'L 0. 38 0. 53 0.015 0.021
CONDITION. 0.76 1.40 0.030 0.055
2.54 BSC 0.100BSC
0.76 1.78 0.030 0.070
C 0.20 0.33 0.008 0.013
2.54 4.19 0.100 0.165
(t CASE 71542 14.60 15.37 0.575 0.605
SEATING PLANE 7 I K
C ERAM I C 100 10
I — L~ 051 152 0.020 0.060
 page 0.67

96S02 • 96LS02
CONNECTION DIAGRAM
PINOUT A

96S02
96LS02 Cxi 1 16 Vcc
D UAL RETRIGGERABLE RESETTA B L E Rxi 2 15 Cxo
MO N O S T A BLE MULTIVI BRATOR CO1 3 14 Rxx

4 13 C07

DESCRIPTION — The 96S02 and 96LS02 are dual retriggerable and reset- lo 5 12

table monostable muitivibrators. These one-shots provide exceptionally wide Q| 6 11 lo

delay range, pulse width stability, predictable accuracy and immunity to Gx 7 10 07
noise. The pulse width is set by an external resistor and capacitor. Resistor
GNO 6 9 a,
values up to 1.0 Mft for the 96LS02 and 2.0 Mf) for the 96S02 reduce required
capacitor values. Hysteresis is provided on both trigger inputs of the 96LS02
and on the positive trigger input of the 96S02 for increased noise immunity.

0 REQUIRED TIMING CAPACITANCE REDUCED BY FACTORS

OF 10 TO 100 OVER CONVENTIONAL DESIGNS
• BROAD TIMING RESISTOR RANGE — 1.0 kD to 2.0 Mft LOGIC SYMBOL
0 OUTPUT PULSE WIDTH IS VARIABLE OVER A 2000:1 RANGE
BY RESISTOR CONTRO L
• PROPAGATION DELAY OF 35 ns 96LS02, 12 ns 96S02
• 0.3 V HYSTERESIS ON TRIGGER INPUTS Cx Rx
vcc
• OUTPUT PULSE WIDTH INDEPENDENT OF DUTY CYCLE 16
(15) 1 2 (14)
• 35 ns TO ~ OUTPUT PULSE WIDTH RANGE
6 (10)
ORDERING CODE: See Section 9
(12) 4
COM M E R C IAL GRADE MfLITARY GRADE (11) 5
PIN PKG
7 (9)
PKGS Vcc = +5.0 V +5%, Vcc = +5.0 V +10%,
OUT TYPE Co
T A = 0 C to + 70' C TA = - 55' C to +125' C
Plastic (13) 3
DIP (P)
A 96 S 0 2PC, 96LS02PC 9B

Ceramic
96S02DC, 96LS02DC 96S02DM, 96LS02DM 6B Vcc = Pln 1 6
DIP (D)
GND = Pln 8
Flatpak
(F)
96S02FC, 96LS02FC 96S02FM, 96LS02FM 4L

INPUT LOADING/FAN-OUT: See Section 3 for U L. definitions

PIN NAMES DESCRIPTION 96S (U.L.) 96LS (U.L.)

HI GH/LOW HI G H/L OW
IO Trigger Input (Active Falling Edge) 0. 5/0. 625
IO Schmitt Trigger Input (Active Falling Edge) 0. 5/0. 25
ll Schmitt Trigger Input (Active Rising Edge) 0. 5/0. 625 0.5/0.25
Cp Direct Clear Input (Ac(ive LOW) 0. 5/0. 625 0 5/0.25
Q True Pulse Output 25/12. 5 10/5.0
(2.5)
Complementary Pulse Output 25/12. 5 10/5.0
(2.5)
page 0.68

96S02 • 96LS02
LOGIC DIAGRAM
Vc 16
I (0>

POSITIVE
• (12) (SCNMITT)
TAIGGE4 6 (10>
2 (I • )
NEGATIVE C,~
5 (11>
TAIGGE4 S02
50 Cn
I (15)
L 3 (13)

L6502g

FUNCTIONAL DESCRIPTION — The 96S02 and 96LS02 dual retriggerable resettable monostable multivibra-
tors have two dc coupled trigger inputs per function, one active LOW(lp) and one active HIGH(11). The()i nput of
both circuit types and the ip input of the 96LS02 utilize an internal Schmitt trigger with hysteresis of 0.3 V to
provide increased noise immunity. The use of active HIGH and LOW inputs allows either rising or falling edge
triggering and optional non-retriggerable operation. The inputs are dc coupled making triggering independent
of input transition times. When input conditions for triggering are met the Q output goes HIGH and the external
capacitor is rapidly discharged and then allowed to recharge. An input trigger which occurs during the timing
cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated (Q to the
LOW state) at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q
output to lp or the Q output to 11. Differential sensing techniques are used to obtain excellent stability over
temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes
pulse width variation from unit to unit. Schottky TTL output stages provide high switching speeds and output
compatibility with all TTL logic families.

Operation Notes
T I MI N G
1. An external resistor (Rx) and an external capacitor (Cx) are required as shown in the Logic Diagram. The
value of Rx may vary from 1.0 kft to 1.0 Mft (96LS02) or 2.0 Mft (96S02),
2. The value of Cx may vary from 0 to any necessary value available. If, however, the capacitor has significant
leakage relative to VCC/Rx the timing equations may not represent the pulse width obtained.
3. Polarized capacitors may be used directly. The (+) terminal of a polarized capacitor is connected to pin 1
(15), the (-) terminal to pin 2 (14) and Rx. Pin 1 (15) will remain positive with respect to pin 2 (14) during the
timing cycle. In the 96S02, however, during quiescent (non-triggered) conditions, pin 1 (15) may go negative
with respect to pin 2 (14) depending on values of Rx and Vcc. For values of Rx ~ 10 kft the maximum amount
of capacitor reverse polarity, pin 1 (15) negative with respect to pin 2 (14) is 500 mV. Most tantalum electro-
lytic capacitors are rated for safe reverse bias operation up to 5% of their working forward voltage rating;
therefore, capacitors having a rating of 10 WVdc or higher should be used with the 96S02 when Rx ~ 10 kfi.
4. The output pulse width t f o r Rx ~ 10 kft and Cx ~ 1000 pF is determined as follows:
(96S02) t w = 0.55 RxCx
( 96LS02) t v v = 0.43 RxCx
Where Rx is in kH, Cx is in pF, t is in ns or Rx is in kfi, Cx is in )IF, t is in ms.
5. The output pulse width for Rx < 10 kft or Cx < 1000 pF should be determined from pulse width versus Cx or
Rx graphs.
6. To obtain variable pulse width by remote trimming, the following circuit is recommended:

1.0 k()
PIN 2 (14)
Rx -'I.5 kil
~ AS C L O S E AS POSSIBLE
To DEVICE
PIN I (15)
V- Q-
 page 0.69

96S02 • 96LS02
Operation Notes (Cont'd)
7. Under any operating condition, Cx and Rx (Min) must be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
8. Vcc and ground wiring should conform to good high frequency standards so that switching transients on
Vcc and ground leads do not cause interaction between one shots. Use of a 0.01NF to 0.1NF bypass capaci-
tor between Vcc and ground located near the circuit is recommended.

TRIGGERING
1. The minimum negative pulse width into I() is 8.0 ns; the minimum positive pulse width into II is 12 ns.
2. Input signals to the 96S02 exhibiting slow or noisy transitions should use the positive trigger input II which
contains a Schmitt trigger. Input signals to the 96LS02 exhibiting slow or noisy transitions can use either
trigger as both are Schmitt triggers.
3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable
state, input latching is used to inhibit retriggering.

ci ci
+
vcc vcc

OUTPUT ~ OUTIUT ~

INPUT
INPUT

Co Co

NEGATIVE EDGE TRIGGER POSITIVE EDGE TRIGGER

4. An overriding active LOW level direct clear is provided on each multivibrator. By applying a LOW to the clear,
any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed, Trigger
inputs will not produce spikes in the output when the reset is held LOW. A LOW-to-HIGH transition on Co
will not trigger the 96S02 or 96LS02. If the Co input goes HIGH coincident with a trigger transition, the circuit
will respond to the trigger.

TRIGGERING TRUTH TABLE

PIN NO'S.
5 (11) 4 (12) 3 (13)
OPERATION

H~L L H Trigger
H L~ H H Trigger
X X L Reset
H = HIGH Voltage Level a Vm
L = Low voltage Level < vie
X = Immatenal letther H or LI
H «L = HIGH to LOW Voltage Level transition
L«H = LOW to HIGH Voltage Level transition
page D.70

96S02 • 96LS02
TYPICAL CHARACTERISTICS
96S02

OUTPUT tw vs Rx and Cx I( DELAY TIME vs TA

103 17

Vrc — 5.0 V Vrt, — 5.0 V

TA = 25'C w 16 Ct = 15 p F
C

2
I- 15 tr,e — COMPLEMENT OU TPUT (0)
IC I pc
0 8
Ut AE3 I0
14
UE
EU
EC I-
0
0 2 Ex' 13
Z
10
I- I! EU
e 0 12 It'E 8 TRUE 0 UTPUT (0>
t

11

1.0 10
I 0 2 8 6 8 10 2 8 6 8 Pt . C 6 8 10 . 0 25 50 75

I„— OUTPU7 PULSE WIDTH — As TA — AMBIENT TEMPERATURE — C

Ip DELAY TIME vs TA OUTPUT tw vs TA

15 42
C
V c, 5 0 V Rx . I k l !
14 40 Cx -SpF
C, 15 pF Z
C
I- CE 1 5PF
0
Ea UTPU 36
tlt

EL
0
a. 36
0 I
0
Pcc
34 Sp p
(01
OU.IPU 0 pcc
RUE 8 25
10 32
0
0
0 9P 30
8

80 28
0 25 50 75 0 25 50 75

TA — AMBIENT TEMPERATURE — C TA — AMBIENT TEMPERATURE - ' C

NORMALIZED Atw vs TA PULSE WIDTH vs RxCx

• 1.0 108
8 20 kll
Z 6
0.8 Rx — 10 kll C 15 kl!
Cx 1 0 00 pF
3 10 IEII
0.6 I. - 5 5 8 8
8.2 It
0
04 2k
Z Vcc — 4.7S V 103
8
-0.2 Ut

EU P V cc 50 V 3
0
0 -02 I- 39 IE
0 0 102
EU -0.4 Vcc — 5.25 V tl
N 6
-0.6 k 2.0 IE
Es
0 1.5 IE
0 -08 C. I 0 IE
Z
• 1.0
0 • 25 "75 10
50 1.0 2 t ' 6 P 2 3 A 6 t P2 : 3 E e 8 I PI
I

TA — AMBIENT TEMPERATURE - "C TIMING CAPACITOR Cx — pF

 page 0.71

96S02 • 96LS02
TYPICAL CHARACTERISTICS
96LS02

OUTPUT tw vs Rx Bnd Cx II DELAY TIME vs T*

103 52
6 Vcc — 50 V
50 Ci— 15 pF
C
OO 48
2

K 0
N 46
102 C.
Ih
0 8
6 44 IPI H — TRUE OUT PUT (0)
IN
U I0-80
It 42
OL
2
I-
zs
0 40
10
ij IU 38
X 6 0
It 4 36

34 IPHL COMPLEMENT OUTPUT (II)

1.0 32
' -5
Q 2 4 6810 2 4 6SI P2 2 BBIP3 -55 35 -15 25 45 65 85 105 1 2 5 1 4 5

I* — OUTPUT PULSE WIDTH (I • ) TA — AMBIENT TEMPERATURE — 'C

I() DELAY TIME vs TA OUTPUT tw vs TA

48 100
Vcc 5.0 V C Rx - I k(l
46
C 15 pF Cx 1 0 0 pF
C
44 CL 15 PF
90
I-
N V cc 5.0
Ul
0
Z
C.
0 42

40 80
I PL H RUE OUT PUT (0) IL
0
0-PI 38 IL
0

36 70
C 0
IU
34
I-
0Il 32 Ih
60
ik IP i — COMPLEMENT OUTPUT (0)
0ILk
30

28 50
-55 -35 -1 5 5 25 45 6 5 85 105 1 25 1 4 5 -75 -25 25 75 125

TA — AMBIENT TEMPERATURE — 'C TA — AMBIENT TEMPERATURE — 'C

NORMALIZED Iitw vs TA PULSE WIDTH vs RxCx

6 42.0 IQA

20 kfl
Rx = 10 k(I C
U 88
3
4 '1.5 IE
I-
z0
Cx = 1000 pF
-1.0 I - 4.3 • Z
It
I- 2 10 kI
42 0
P
6 103
Z
I- IU
=8pp Ih 8
0 0
$ P 0
IL
IU 4S P
2
3
IL
0
IL
N -'1.0 I-
0 102
0
IU UI
0
64 8
Qk
-2.0 I Ih
43
2
It C.
0 1.0 k
zk
0
-3.0 10
-7 -25 • 25 75 • 125 10 2 3 • 8 8 10 2 I 4 8 8 I Q2 2 3 4 6 8 I Q3

TA — AMBIENT TEMPERATURE — 'C TIMING CAPACITOR Cx — pF

page D.72

96S02 • 96LS02
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
96S 96LS
SYMBOL PARAMETER UNITS CONDITIONS
M in M a x M in M a x

VT.
Positive-going Threshold 2.0 2.0 Vcc = 5 0 V
Voltage, T0, 11 (96LS02) 11 (96S02)
Negative-going XM 0.8 0.7
VT- Threshold Voltage V Vcc = 5.0 V
XC 0.8 0.8
10, 11 (96LS02) 11 (96S02)
Vcc = Min, VIN = VIH or VIL
XM 2.7 2.5
VoH Output HIGH Voltage IpH = -400 pA ('LS02)
XC 2.7 2.7
IpH = -1.0 mA ('S02)

XM 0.5 0.5
VoL Output LOW Voltage Vcc = Min, VIN = VII-I or VIL
XC 0.5 0.4
Capacitor Voltage - 0.85 3.0 0 3.0 Rx = 1,0 kft
Vcx Pin 1 (15) Referenced - 0.5 3.0 0 30 Rx = > 1 0 k f t
to 525 V
to Pin 2 (14) - 0.4 3.0 0 30 Rx > 1.0 MA
20 20 pA VIN = 2.7 V
IIH Input HIGH Current VIN = 5.5 V ('S02)
0.1 0,1 mA
VIN = 10 V ('LS02)
IIL Input LOW Current -1.0 -0.4 mA VIN = 0.4 V, Vcc = Max
los Output Short Circuit Current -40 -100 -20 -100 mA Vcc = Max, VouT = 0 V
Icc Power Supply Current 75 36 mA VIN = Open, Vcc = Max

100 ns I N P UT P ULSE
f = 100 kHz
Amp ~ 3.0 V
Width = 100 ns
1.5 V
tr= ( 1 s 5 ns
VIN

IPLH

1.5 V

Iw

1.5 V

IPHL

Fig. a
 page 0.73

96S02 • 96LS02
AC CHARACTERISTICS: Vcc = +5.0 V, TA = +25'C (See Section 3 for waveforms and load configurations)
96S 96LS
SYMBOL PARAMETER CL = 1 5 p F CL =15 pF UNITS C 0 ND IT I 0 NS
M in M a x M in M a x
Propagation Delay
IPLH 15 55 ns
lotoQ
Propagation Delay 19 50
IPHL ns
10to Q
Propagation Delay
(PL H 19 60 ns
l lto Q
Propagation Delay 20
IPHL 55 ns
Il to Q Fig. a
Propagation Delay
IPHL 20 30 ns
Co to Q
Propagation Delay 14 35
IPLH ns
Co to Q
tw (L) 10 Pulse Width LOW 8.0 15 ns
tw (H) lf Pulse Width HIGH 12 30 ns
tw (L) Co Pulse Width LOW 7.0 22 ns
Rx = 1 0 k f t C x = 1 0 p F
tw (H) Minimum Q Pulse Width HIGH 30 45 25 55 ns including jig and stray
tw Q Pulse Width 5.2 5.8 4.1 4.5 us Rx = 10 kth C x = 1000 PF
TA = -55' C to +125' C,
Rx Timing Resistor Range' 1 .0 2 0 00 1 .0 1 0 0 0 kft
Vcc = 4.5 V to 5.5 V
C hange in Q Pulse Width XM 3.0
Rx = 10 kfL C x = 1000 pF
over Temperature XC 1.0 1.0

TA = 25 C, Vcc =4.75 V to
1.0 0.8 5.25 V, Rx = 10 k(L
Change in Q Pulse Width Cx = 1000 pF
over Vcc Range T A = 25 C, Vc c = 4.5 V to
1.5 5.5V, Rx = 1 0 k D ,
Cx = 1000 pF
Applies only over commercial Vcc and Ta range for 96602.
page 0.74

e • • •
MC2661A/MC68661A
(Baud Rate Set A)
• •
MC2661B/MC68661B
(Baud Rate Set B)
MC2661C/MC68661C
(Baud Rate Set C)
A dv a n c e I n f o r m a ti o n

ENHANCED PROGRAM M A B LE COMM UNICATIONS MOS

INTERFACE (EPCI) (N-CHANNEL, SILICON-GATE)

The MC2661/MC68661, Enhanced Programmable Communications

Interface (EPCI), is a u n iversal synchronous/asychronous data com- E NHANCED PROGRA M M A B L E
munications controller chip that is an enhanced version of the Signetics COMMUNICATIONS INTERFACE
2651. The EPCI directly interfaces to most 8-bit MPUs and easily to the I EPCI)
MC68000 MPU and other 16-bit MPUs. It may be used in either a polled or
interrupt dnven system Programmed instructions can be accepted from
the host MPU while supporting many synchronous or asynchronous senal-
data communication protocols in a full or half-duplex mode Special sup-
port for BISYNC is provided
T he EPCI converts parallel data c haracters, accepted f ro m t h e
microprocessor data bus, into transmit-senal data. Simultaneously, the
EPCI can convert receive-senal data to parallel data characters for input to
the microprocessor L SUFFIX
A baud rate generator in the EPCI can be programmed to either accept CERAMIC PACKAGE
an external clock, or to generate internal transmit or receive clocks Sixteen CASE 719
different baud rates can be selected under program control when operating
in the internal clock mode. Each version of the EPCI (A, B, C) has a dif-
ferent set of baud rates.
FEATURES
• Sy n chronous Operation
• Single or Double SYN Operation
• Internal or External Character Synchronization P SUFFIX
PLASTIC PACKAGE
• Transparent or Non-transparent Mode
CASE 710
• Transparent Mode DLE Stuffing (Tx) and Detection (Rx)
• Au t omatic SYN or DLE-SYN Insertion
• SY N, DLE, and DLE-SYN Stripping
• Baud Rate dc to I M bps (1X Clock)
• As ynchronous Operation
• 1, I '/z, or 2 Stop Bits Transmitted
• Panty, Overrun, and Framing Error Detection C SUFFIX
• Line Break Detection and Generation CEROIP PACKAGE
• False Start Bit Detection CASE 733
• Au tomatic Serial Echo Mode (Echoplex)
• Baud Rate. dc 1M bps (1X Clock)
dc to 62.5k bps (16X Clock) PIN ASSIGNMENT
dc to 15.625k bps (64X Clock)
• Co m mon Features D2 28 Dl
• Internal or Fxternal Baud Rate Clock; No System Clock Required
D3 27 DO
• 3 Baud Rate Sets (A, B, C); 16 Internal Rates for Each Set
• 5- to 8-Bit Cltaracters plus panty, Odd, Even, or No Parity RxD 26 YCC
• Double Buffered Transmilter and Receiver GND 25 RxC/BKDET
• Dynamic Character Length Switching
D4 24 DTR
• Full- or Half Duplex Operation
• Local or Remote Maintenance Loop-Back Mode D5 23 RTS
• TTL-Compatible Inputs and Outputs D6 22 DSR
• RxC and Tx(. Pins and Short Circuit Protected
• 3 Open-Drain MOS Outputs can be Wire ORed D7 21 RESET
• Single 5 V Power Supply TxC/XSYNC 20 BRCLK
• Ap p lications Al 10 19 TxD
• Intelligent Terminals
• Network Processors CE 18 TxE MT/ DSCHG
• Front End Processors AO 12 17 CTS
• Remote Data Concentrators
R/W 13 16 DCD
• Computer tn Computer Links
• Senal Penpherals RxRDY 14 15 TxRDY
• BISYNC Adaptors
 page 0.75

BLOCK DIAGRAM

DATA SUs STN OLE CONTROL

DATA DUS
DO — DT SUFFER
STN I REGISTER
(21 28 I 2
\ 6 I 8) SVN 2 REGISTER

OLE REGISTER

O PERATION CON T R O L
RESET (21)

(12)
AO MODE REGISTER I
(rn)
AI MODE REGISTER 2
TRANSMITTER 116) 3 • RDV
(13)
COMM AN D REGISTER

STATUS REGISTER TRANSMIT DATA

HOLDINC REGISTER

TRANSMIT (19)
SHIFT REGISTER

SRCLK (28)

SAUD RATE
GENERATOR
AND
CLOCK CONTROL (14) ie
RECEIVER R ROV

RECEIVE DATA
HOLDING REGISTER
DSR (22)
RECEIVE
DCD (16) SHIFT REGISTER

CTS
MODEM
RTS (231 CONTROL

DTR (24)

(ial u6)
TFEMT/
DSCHG
(4)

NOTE
reOpen drain output pm

BLOCK DIAGRAM Table 1 BAUD RATE GENERATOR CHARACTERISTICS

The EPCI consists of six major sections. Set A (BRCLK = 4.9152MHz)
These sre the transmitter, receiver, timing,
o peration c o n t r ol, m o de m c o n t ro l s n d ACTUAL
SY N iDLE control These sections communic- BAUD FREQUENCY PERCENT
atee with each other via an internal data bus MR23 — 20 RATE 16X CLOCK ERROR DIVISOR
and an mternal control bus. The internal data 0000 50 0 8kHE 6144
bus interfaces to the microprocessor data 0001 75 12 4096
bus via a data bus buffer. 0010 110 1 7598 — 001 2793
001 1 134 5 2 152 2284
Operation Control 0100 150 24 2048
This functional block s t ores c o nfiguration 0101 200 3.2 1536
snd operation commands from the CPU and 0110 300 4.8 1024
generates appropriate signals to vanous in- 0111 600 96 512
lernsl sections to control the overall device 1000 1050 16 8329 0 196 292
operation. It contains read and write circuits 1001 1200 19.2 256
t o p e r m i t c o m m u n i c a t i o n s w i t h t he 1010 1800 28 7438 — 0 19 171
microprocessor via the data bus snd con- 1011 2000 31.9168 — 0 26 154
tains mode registers I and 2, the command 1 100 2400 38 4 128
register, and the status register. Details of 1 101 4800 76 8 64
register addressmg and protocol are pre- 1110 9600 153 6 32
sented in the EPCI programming section of 1111 19200 307 2 16
this data sheet.
page 0-76

Timing Table 1 BAUD RATE GENERATOR CHARACTERISTICS (Cont'd)

The EPCI contains a b aud rate generator Set B (BRCLK = 4/9152MHz)
(BRG) which is programmable to accept ex
ternal transmit or recewe clocks or lo divide ACTUAL
an external clock to perform data communi BAUD FREQUENCY PERCENT
cations. The unit can generate 16 commonly MR23-20 RATE 16X CLOCK ERROR DIVISOR
used baud rates, any one of which can be 0000 45 5 0 7279kHz 0 005 6752
selected fo r f ul l d u plex o p e ration. See 000 I 50 08 6144
table 1. 0010 75 1.2 4096
0011 110 1 7598 — 001 2793
Receiver 0100 134 5 2. 152 2284
The iecewer accepts senal data on the RXD 0101 150 24 2048
pin, converts this serial input to parallel for- 0110 300 4.8 1024
mat, checks for bits or characters that are 0111 600 96 512
unique to the communication technique and 1000 1200 19 2 256
s ends an " a s sembled" c h aracter to t h e 1001 1800 28 7438 — 0 19 171
CPU. 1010 2000 31.9168 — 0 26 154
1011 2400 38 4 128
Transmitter I 100 4800 76. 8 64
The transmitter accepts parallel data from 1101 9600 '53 6 32
the CPU, converts it to a senal bit stream, 1110 19200 307 2 16
inserts the appropnate characters or bits 1111 38400 8
(based on the c ommunication technique)
and outputs a composite serial stream of
data on the TxD output pin. Set C (BRCLK = 5/0688MHz)

Modem Control ACTUAL

The modem control section provides inter- BAUD FREQUENCY PERCENT
facmg for three input signals and three out MR23-20 RATE 16X CLOCK ERROR DIVISOR
put signals used for "handshaking" and sta 0000 50 0 8kHz 6336
t us in d i c a t io n b e t w e e n t h e C P U a n d a 0001 75 12 4224
modem. 0010 110 1. 76 2880
0011 134.5 2. 1523 0 016 2355
SYN/DLE Control 0100 150 2.4 2112
This section contains control circuitry and 0101 300 4.8 i056
t hree 8 - bi t r e g i s t er s s t o r in g t h e S Y N 1 , 0110 600 96 528
SYN2, and DLE characters provided by the 0111 1200 19 2 264
CPU. These registers are used in the syn 1000 1800 28.8 i76
chronous mode of operation to provide the 1001 2000 32.081 0 253 158
characters required for synchronization, idle 1010 2400 38 4 132
fill and data transparency 1011 3600 57 6 88
I 100 4800 76.8 66
1101 7200 115 2 44
1110 9600 153.6 33
1111 19200 316.8 3 125 16

• QTE
l6X c lock s s e d n a s y n chrono s mode In synchrnnous mode cl o ck un p l e r s 1 x and
ann can be se d oniy for r«c

ORDERING CODE

COMMERCIAL RANGES
PACKAGES
VCC = SV a 5 % , T A = 0 C t o 7 0C
Ceramic DIP MC2661A/MC68661A
MC2661 B/M C68661 8 See table 1 for baud rates
MC2661 C/MC68661 C
Plastic DIP M C2661 A/MC68661 A
MC2661 B/MC68661 B See table 1 for baud rates
MC2661C/MC68661C

MO T O R O L A Se m i conduclor Products inc


Table 2 C PU-RELATED SIGNALS
INPUT/
PIN NAME PIN NO. OUTPUT FUNCTION
26 +SV supply input
VCC
GND Ground
RESET 21 A high on this input performs a ma ster
reset on the 266 1 T his signal asynchro-
nously terminates any dewce activity and
clears the mode, command and status reg-
isters. The dewce assumes the idle state
and remains there until initialized with the
approppate control words
A I -Ap 10, 12 Address lines used to select mternal EPCI
registers
R/W 13 Read command when low, write command
when high
CE Chip enable command. When low, i ndi-
cates that control and data lines to the
EPCI are valid and t hat t h e o p e ration
specified by the R / W , A l a n d A p i n p uts
should be performed When high, places
the Dp-D7 lines in the three-state condi-
tion.
D7-Dp 8 ,7,6 , 5 , I /0 8-bit, three-state data bus used to transfer
2,1,28,17 commands, dataand status between EPCI
and the CPU. Dp is the least significant bit,
D7 the most significant bit.
TxRDY 15 This output is the complement of status
register bit SRP W hen low, it indicates
that the t r a nsmit d at a h o l d ing r e g ister
(THR) is ready to accept a data character
from the CPU. It goes high when the data
character is loaded. This output is valid
only when the transmitter is enabled. It is
an open drainoutput which can be used as
an interrupt to the CPU.
RxRDY 14 This output is the c o mplement of s t atus
register bit SR i W h e n l ow, i t i n dicates
t hat th e r e c e iv e d a t a h o l d in g r e g i s t e r
(RHR) has a character ready for input to
the CPU. It goes high when the RHR is read
by the CPU and also when the receiver is
disabled I t i s a n o pe n drain output which
can be used as an interrupt to the CPU.
TxEMT/
DSCHG 18 This output is the c o mplement of s tatus
r egister bi t SR 2 W h e n l ow, it i n dicates
that the transmitter has completed senal-
ization of the last character loaded by the
CPU, or that a change of state of the DSR
or DCD inputs has occurred This output
goes high when the status register is read
by the CPU, if the TxEMT condition does
n ot ex is t O t h e r w i se , t h e T H R m u s t b e
loaded by the CPU for this line to go high It
is an open dram output which can be used
as an interrupt to the CPU
page D.77
OPERATION
The functional operation of the 2661 is pro-
grammed by a set of control words supplied
by the CPU. These control words specify
items such as synchronous or asynchronous
mode, baud rate, number of bits per charac-
ter, etc. The programming procedure is de-
scnbed in the EPCI programming section of
the data sheet.
After programming the EPCI is ready to per-
form the desired communications functions
The receiver performs senal to parallel con-
version of data received from a modem or
equivalent device. The transmitter converts
parallel data received from the CPU to a
sepal bit stream. These actions are accom-
phshed within the framework specified by
the control words.
Receiver
The 2661 is c o nditioned to r e ceive data
when the DCD input is low and the RxEN bit
in the command register is true In the asyn-
chronous mode, the receiver looks for a high
to low (mark to space) transition of the start
bit on the RxD input line. If a t ransition is
detected, the state of the RxD line is sam-
pled again after a delay of one half of a bit
time. If RxD is now high, the search for a
valid start bit is begun agam. If RxD is still
low, a valid start bit i s a s s umed and the
receiver continues to sample the input line
at one bit time intervals until the proper num-
ber of data bits, the parity bit, and one stop
bit have been assembled. The data are then
transferred to the receive data holding reg-
ister, the RxRDY bit in the status register is
set, and the RxRDY output is asserted. If the
character length is less than 8 bits, the high
order unused bits in the holding register are
set to zero. The parity error, framing error,
and overrun error status bits are strobed
into the status register on the positive going
edge of RxC corresponding to the received
c haracte r b o u n d ar y I f t h e s t o p b i t i s
present, the receiver will immediately begin
its search for the next start bit If the stop bit
is absent (framing error), the receiver will
interpret a space as a start bit if it persists
into the next bit time interval lf a break con-
dition is detected (RxD is low for the entire
character as well as the stop bit), only one
character consisting of all zeros (with the
FE status bit SR5 set) will be transferred to
the holding register. The RxD input must re-
turn to a high condition before a search for
the next start bit begins.
Pin 25 can be programmed to be a break
d etect o u t put b y a p p r o p riate s e t t ing o f
MR27-MR24 l f s o , a d e t e c ted b r eak w i ll
cause that pin to go high When RxD returns
to mark for one RxC time, pm 25 will go low.
Refer to the break detection timing diagram.
page D.78
Table 3 DEVICE-RELATED SIGNALS
INPUT i
PIN NAME PIN NO. OUTPUT FUNCTION
BRCLK 20 Clock input to the internal baud rate gener-
ator (see table I ) N o t r equired if external
receiver and transmitter clocks are used
'RxC/BKDET 25 liO Receiver clock l f e x ternal receiver clock
is programmed. this mput controls the rate
at which the character is to be r e c ewed
Its frequency is I X , 16X or 64X the baud
rate, as programmed by mode register 1
Data are sampled on the nsing edge of the
c lock I f i n t ernal receiver c lock i s p r o -
grammed, this pin can be a IX i 16X clock
or a break detect output pin
'TxCiXSYNC I iO Transmitter cloc k I f e x t e r nal t ransmitter
clock is programmed, this input controls
the rate at which the character is transmit-
t ed Its f r equency is I X , 16 X o r 64 X t h e
baud rate, as programmed by mode regis.
ter 1. The transmitted data changes on the
falling edge of the clock I f i nternal trans
m itter clock is p r ogrammed, this pin ca n
be a 1Xi 16X clock output or an external
tarn synchronization input
RxD Serial data input to the recewer " M a rk" is
high, "space" is low
TxD 19 Serial data o u tput f ro m th e t r a n smitter
' Mark ' i s h i g h , 'space' i s lo w H e l d i n
mark condition when the transmitter is dis-
abled
DSR 22 General purpose input which can be used
for data set ready or ring indicator condi
tion It s complement appears asstatus
register bit SR7 C a uses a low output on
TxEMTiDSCHG when its state changes if
CR2 or CRO = I
DCD 16 D ata earner detect input M us t b e lo w i n
order for the receiver lo operate Its corn.
p lement appears a s s t a tus r e gister b i t
SR6 C au s e s a l ow ou t p ut o n
TxEMT 'DSCHG when its state changes if
CR2 or CRO = I I t D C D g o e s h ig h w h i le
recewing, the RxC is internally inhibited
CTS 17 Clear to send input M ust be low in order
f or the transmitter to o p e rate I f i t g o e s
high dunng transmission, the character in
the transmit shift register will be transmit-
ted before termination
DTR 24 0 General purpose output which is the com-
plement of command register bit CR i Nor.
malty used to indicate data terminal ready
RTS 23 0 General purpose output which is the com-
plement of command register bit CR5 Nor-
mally used to indicate request to send
t he transmit s h if t r e g i s te r i s n o t e m p t y
when CR5 is reset ( I t o 0) , t hen RTS will
go high one TxC time after the last serial
bit is transmitted
NOTE
RxC and ~Tx output • have ahorl circwt proiechon max CL tgcpp Oulpula become
open circutted upon dalac lion ol a aero pulled high or a one pulled low
When the EPCI is initialized into the synchro-
nous mode, the receiver first enters the hunt
mode on a 0 to I transit~on Ol RxEN(CR2) In
this mode, as data are shifted into the re-
ceiver shift register a bit at a time, the con.
tents of the register are compared to the
contents of the SYI41 register If the two are
n ot equal, the next bit is s h i fted in and th e
comparison is repeated When the two reg.
isters match, the hunt mode is t e rminated
and character assembly mode begins If sin-
gle SYN operation is programmed, the SYN
DETECT status bit is set I f double SYN op-
eration is programmed, the first c haracter
assembled after SYNI must be SYN2 in or.
der lor the SYN DETECT bit to be set. Other.
w ise, the E PC I r e t urns t o t h e h u n t m o d e
(Note that the sequence SYN1-SYNI-SYN2
will not achieve synchronization ) When syn.
chronization has been ac hieved, the EPCI
c ontinues t o a s s e m bl e c h a r a c t er s a n d
transfer them to the holding register, setting
t he RxRDY s t a tus b i t a n d a s s e r t ing t h e
R xRDY output e ac h t i m e a c h a r a c te r i s
transferred The PE and OE status bits are
s et as appropnate F u rther receipt of t h e
appropnate SYN sequence sets the SYN
DETECT status bi t I f t h e S Y N s t r i p p i ng
mode is commanded, SYN characters are
not transferred to the holdmg register Note
that the SYN characters used to e s tablish
initial synchronization are not transferred to
the holdmg register in any case
E xternal I a m s y n c h r o n i z a t i o n c a n b e
achieved via pin 9 by appropriate setting of
MR27-MR24 When pin 9 is an XSYNC input,
tne internal SYNI , S Y N I - SYN2, and DLE-
SYNt detection is disabled E ac h p o s itive
going signal on XSYNC will cause the re.
ceiver to e s t a blish synchronization on the
hsing edge of the next RxC pulse Character
assembly will start with the RxD input at this
edge XSYNC may be lowered on the next
nsing edge of RxC This externat synchroni.
zation will cause the SYN DETECT status bit
t o be set until the st atus register is r e a d
Refer to XSYNC timing diagram
Transmitter
The EPCI is c o n ditioned t o t r a nsmit d a ta
w hen the CTS i nput is lo w a n d t h e T x E N
command register bit is set Th e 2 66 1 mdi-
cates to the CPU that it can accept a char.
aeter for transmission by setting the TxRDY
status bit and asserting the TxRDY output
When the CPU wntes a character into the
transmit data holding register. these condi-
tions are negated Data are transferred trom
the holding register to the transmit shift reg-
ister when it is idle or has completed trans.
m ission o f t h e p r e v i ous c h a r a c te r T h e
TxRDY conditions are then asserted again
Thus, one full character lime of buffering is
provided
 page 0.79

L
• •

In the asynchronous mode, the transmitter Table 4 MC2661/MC68661 REGISTER ADDRESSING

automatically sends a start bit followed by
the programmed number of data bits, the CE Af Ap R/W FUNCTION
least significant bit bemg sent first It t hen I X Three -state data bus
appends an optional odd or even panty bit Read recewe holding register
and the programmed number of stop bits If, 0 0
Write transmit holding register
f ollowing transmission of th e d a t a b i le , a Read status register
new character is not available in the trans- Write SYNI/SYN2~DLE registers
mit holding register, the TxD output remains 0 Read mode registers '/2
i n the m a r k ing ( h i gh ) c o n d i t io n an d t h e 0I Wnte mode registers na
TxEMT/DSCHG output and its correspond. Read command register
ing status bit ar e a s serted. Transmission Write command register
resumes when the CPU loads a new charac.
NOTE
ter into the holding register The transmitter See AC cheractenslics nacho t o r I ming Iequ Laments
can be forced to o utput a c o ntinuous low
( 8REAK) condition by s e t t ing th e s e n d
MC2661/MC68661 INITIALIZATION FLOW CHART
break command bit (CR3) high.
INITIAL RESET
ln the synchronous mode, when the 2661 is
initially conditioned to transmit the TxD out.
LOAD
put remains high and the TxRDY condition is
MODE REGISTER I
asserted until the first character to be trans-
mitted (usually a SYN character) is loaded
by the CPU. Subsequent to this, a continu- LOAD NOTE
ous stream of characters is transmitted No MODE REGISTER 2 Mode register i mu st be wntten
before 2 can bn wxn en Mode Iegisie 2
extra bits (other than parity, if commanded) need not be programmed d external
are generateo by the EPCI unless the CPU i ocxs are s e d
N
fails to send a new character to the EPCI by EYNGHADNous
the time th e t r a n smitter ha s c o m p l eted
sending the previous character Since syn-
chronous communication does not a l l ow LOAD
gapa between characters, the EPCI asserts SYNI REGISTER NOTE
TxEMT and automatically "fills" the gap by SYN I Iegisler must be wnllen
c elo e SYN2 ca b n w i l t e and
transmitting SYNIs , S Y N I . S YN2 doublets, SYN2 be/ore DLE can be wnllsn
or DLE-SYNI doublets, depending on the OOURLE
SYNC
state of MR16 and MR IT. Normal transmis-
sion ofthe message resumes when a new
Y TAANSPARENT
character is available in the transmit data LO D MODE
holding register. If the SEND Dl E bit in the SYN2 REGISTER
command register is true, the DLE character
is automatically transmitted pnor to trans-
m ission of th e m essage character in t h e TRANSPARENT
THR. In 0 D E

EPCI PROGRAMMING LOAD

DLE REGISTER
Prior to initiating data c o mmunications, the
2 661 o p e r a t i o nal m od e m u s t b e p r o -
grammed by performing wnte operations to
the mode and command registers In addi. LOAD
t ion, i f s y n c h r o n ous o p e r a t i o n i s pr o - CO M M A N D AE G I STER
grammed, the appropnate SYN/DLE regis.
t ers must b e l o a d ed. The EPCI can b e r- — -

OPERATE
reconfigured at sny time during program ex-
ecution. A flowchart of the intialization proc-
ess appears in figure I
T he internal r e g i s t er s o f t h e E P C I a r e RECONFIGURE

accessed by applying specific signals to the

CE. R/W, At and Ap mputs The conditions
necessary to a d dress each r egister are OISASIE
shown in table 4 RCYR AND XMTR

The SYNI, S YN2, and DLE registers are

accessed by p erforming wnte operations
= 0, Ap = I , and Figure 1
w ith the c o n d itions A I
page D.80
R /W = I The f i r s t o p e r a t io n l o ad s t h e
SYNI register Th e n ext l o ads th e S Y N2
register, and the third loads the DLE regis.
ter. Reading or loading the mode registers is
done in a similar manner. The first write (or
read) operation addresses mode register I,
and a subsequent operation addresses
mode register 2 It more than the required
number of accesses are made, the mternal
sequencer recycles to point at the first reg.
ister The pointers are reset to SYN I regis.
ter and mode register I by a RESET input or
by performing a read command register op-
eration, but are unaffected by any other read
or write operation
The 2661 register formats are summarized
in tables 5, 6, 7 and 8. Mode registers I and
2 define the general operational character.
istics of the EPCI, while the command regis-
ter controls the operation within this basic
framework. The EPCI indicates its status in
t he status re gister T h es e r e g isters a r e
cleared when a RESET input is applied
Mode Register 1 (MR1)
T able 5 illustrates Mode Register I Bi t s
MR I I and MR 10 select the commumcation
format and baud rate multiplier. 00 specifies
s ynchronous mode and I X m ultiplier I X ,
16X, and 64X multipkers are p rogramm able
for asynchronous format However the mul-
tiplier in asynchronous format applies only if
the external clock input option is selected
by MR24 or MR25
MR13 and MR12 select a character length
of 5, 6, 7 o r 8 b i t s T h e c h aracter length
d oes not i n c l ude t h e p a r it y b i t , i f p r o -
grammed, and does not mclude the start and
stop bitsm asynchronous mode.
MR14 controls panty generation If enabled,
a parity bit is added to the transmitted char-
Table 5 M ODE REGISTER 1 (MR 1)
MR17 MR16
Sync Async
Async: Stop Bit Length
00 = Invalid
01 = I stop bit
1 0 = 1 v s to p b i t s
11 = 2 stop bits
Sync: Sync:
Number of Transparency
SYN char Control
0 = Double 0 = Normal
SYN I = Transparent
I = Single
SYN
NOTE
Baud rate factor n avy vh n o u s appl es only re t e r n al clock v selected F s c l o «s
nternal clock x se l ected M o ue must be 9elecied (Mal 1 Ma l o ) w a ny case
a eter and th e r e c eiver performs a p a n t y
check on incommg data MR15 selects odd
or even parity when panty is enabled by
MR 14.
In asynchronous mode, MR17 and MR16 se-
lect character frammg of I , 1.5, or 2 stop
bits (I f I X b a u d rate i s p r ogrammed, I 5
stop bits defaults lo I stop bits on transmit )
In synchronous mode, MR17 controls the
number of SYN characters used to establish
synchronization and for character fili when
the transmitter is idle S YN I a lone is used if
MR17 = I , a n d SY N I -SYN2 is used when
MR17 = 0 If the transparent mode is speci.
fied by MR16, DLE-SYNi is used for charac-
ter fill and SYN detect, but the normal syn-
chronization sequence is used lo establish
character sync W hen transmitting, a DLE
character in the transmit holding register will
cause a second DLE character to be trans-
mitted. This DLE stutfing eliminates the soft.
ware DLE compare and stuff on each trans-
parent mode data character If the send DLE
c ommand (CR3) is a c tive when a DL E i s
loaded into THR, only one additional DLE will
be transmitted. Also, DLE stnpping and DLE
detect (with MR14 = 0) are enabled
The bits m the mode register affecting char.
aeter assembly and disassembly (MR12.
MR i6) can be changed dynamically (during
a ctive r e c e i v e / t r a n s mit o p e r a t ion ) T h e
c haracter mode register affects both t h e
transmitter and receiver, therefore in syn-
chronous mode, changes should be made
o nly in half d u plex mode ( R xEN = I or
TxEN = I, but not both simultaneously = I )
In asynchronous mode, character changes
should be made when RxEN and TxEN =O or
when TxEN = I and the transmitter is mark-
ing m halt duplex mode (RxEN = 0)
MR15 MR14
Parity Type Parity Control
0 = Od d 0 = Disabled
i = Even 1 = Enabled
! 10 = 7 bits
ls x I
To effect assembly/disassembly of the next
received/transmitted c h aracter, MR 12.15
must be changed within n bit times of the
actwe going state of RxRDY/TxRDY. Trans-
parent and non-transparent mode changes
(MR16) must occur within n- I bit times of the
character to be affected when the receiver
o r transmitter is active ( n = smaller of the
new and old character lengths )
Mode Register 2 (MR2)
T able 6 illustrates mode register 2 M R 2 3 ,
MR22, MR21 and MR20 control the frequen.
cy of the internal baud rate generator (BRG).
Sixteen rates are selectable for each EPCI
version (A, B, C). Versions A and B speci-
fy a 4 9152 MHz TTL input at BRCLK (pin
20); version C specifies a 5.0688 MHz input
w hich is i d entical to t h e S i gnetics 2 6 5 1
MR23-20 are don't cares if external clocks
are selected (MR25 MR24 = 0) The individ-
ual rates are given in table I
MR24-MR27 select the recewe and transmit
clock source (either the BRG or an external
input) and the function at pins 9 and 25. Re.
fer to table 6.
Command Register (CR)
Table 7 illustrates the command register
Bits CRO (TxEN) and CR2 (RxEN) enable or
disable the transmitter and receiver respec.
tively. A 0 to I transition of CR2 forces start
bit search (async mode) or hunt mode (sync
mode) on thesecond RxC rismg edge. Dis-
abling the receiver causes RxRDY to go
high (inactive). If the transmitter is disabled,
it will complete the transmission of the char-
acter in the transmit shift register (if any)
prior to terminating operation. The TxD out-
put will then remain in tho markmg state
M R13 MR12 MR11 MR10
Character Mode and Baud
Length Rate Factor
00 = 5 bits 00 = Synchronous IX rate
Oi = 6 bits 01 = Asynchronous IX rate
11 = 8 bits
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
 page 0.81

Table 6 MODE REGISTER 2 (MR2)

MR27-MR24 MR23-MR20
T xC R xC Pin 9 Pin 2 5 T xC R xC Pin g Pin 25 Mode Baud Rate Selection
0000 E E TxC RxC 1000 XSYNC' RxC/TxC sync
0001 E I TxC IX 1001 TxC BKDET async
0010 I E 1X RxC 1010 XSYNC' RxC sync
001 1 I I IX IX 1011 IX BKDET async See baud rates in table !
0 100 E E TxC RxC I 100 XSYNC' RxC /TxC sync
0 10 1 E I Tx C 16X 1101 TxC BKDET async
0 1 10 I E 16X RxC 1110 XSYNC' RxC sync
0 11 1 I I 16X 16X 1111 16X BKDET ssync
NOTES
When pia 9 ia programmed aa XSYNC input, SYNi, SYNl SYN2. and OLE SYNl dafam
hon ia disabled
E = Ekiaiaaf clock
I//famal clock (BRGl
1 x aad lsx are clock ovlpvfa
Table 7 COMMAND REGISTER (CR)
CR7 CR6 CRS CR4 CR3 CR2 CR1 CRO

Receive Transmit
Request Control Data Terminal Control
Operating Mode To Send Reset Error Sync/Async (RxEN) Ready (TxENI
00 = Normal operation 0 = Force RTS 0 = Normal Aaync:
0'1 = Async output high f = Reset Force break
Automatic one clock time error flags 0 = Normal 0 = D sable 0 = Force DTR 0 = Di s a b l e
echo mode after TxSR m status register f = Force bieak f = Enable output high i = Enable
Sync SYN and/or aer/af/zation IFE, OE, PE/DLE 1 = Force DTR
DLE atnpping mode 1 = Force RTS detect) output low
10 = Locslioop back output low
11 Remote loop back

Sync:
Send DLE
0 = Normal
i = Send DLE

Table 8 STATUS REGISTER (SR)

SR7 SR6 SRS SR4 SR3

Data Set Data Carrier

Ready Detect Overrun P E DLE Detect TxE M T D S C H G RkRDY TxRDY
0 = DSR input 0 = DCD input Aaynix 0 = Normal Aaync:
IS higfl is high 0 = Normal f= Ovarian 0 = No r m a l 0 = Norm,/I Receive 0 = Transmit
f = DSR input f — DCD input i = Fr aming Error f = Panty error I = C h a nge in h 0 1 ff i /l g holding
is fow is low Er/ar DSR, or DCD or register empty re<mater busy
t ransmit shif t f Receive f = Transmit
/ egis l u / 6 hald ag rag Ster i loiding /e g s t e r
empty has /fata empty

Sync:
0 N o rmal
1 = SY N i = P a r ity ur ror or
delecfvd DLE received

(high) while TxRDY snd TxEMT will go high
(mactive). If the receiver is disabled, it will
terminate operation immediately. Any char-
acter being assembled will be neglected. A
0 to I transition of CR2 will initiate start bit
search (async) or hunt mode (sync).
Bits CRI (DTR) and CR5 (RTS) control the
DTR and RTS outputs, Data at the outputs
are the logical complement of the register
data.
In asynchronous mode, setting CR3 w i ll
force and hold the TxD output low (spacing
con(litton) at the end of the current transmit-
ted character. Normal operation resumes
when CR3 is cleared. The TxD hne will go
high for at least one bit time before begin.
mng transmission of the next character in
the transmit data holding register. In syn-
chronous mode, setting CR3 causes the
transmission of the DLE register contents
prior to sending the character m the transmit
data holding register. Since this is a one
time command, CR3 does not have to be
reset by software. CR3 should be set when
entering and exiting transparent mode and
for all DLE — non-DLE character sequences.
Setting CR4 causes the error flags in the
status register (SR3, SR4, and SR5) to be
cleared. This is a one time command. There
fs no internal latch Ior this bit.
page D.82

Table 9 MC2661/MC68661 EPCI vs SIGNETICS 2651 PCl only the first DLE of a DLE-DLE pair is
stopped.
FEATURE EPC I PCI
Note that automatic stnpping mode does not
1. MR2 Bit 6, 7 Control pin 9, 25 Not used affect the setting of the DLE detect and SYN
2 DLE detect-SR3 SR3 = 0 for DLE-DLE, SR3 = i fo r DLE DLE detect status bits (SR3 and SR5)
DLE SYNCI DLE-SYNC I
Two diagnostic sub-modes can also be
3. Reset of SR3, DLE Second character after Receiver disable, or CR4 = I
configured In local loop back mode (CR7.
detect DLE, or receiver disable, CR6 = 10), the following loops are connect-
orCR4 = 1 ed internally:
4. Send DLE-CR3 One time command Reset via CR3 on next TxRDY
1. The transmitter output is c onnected to
5. DLE stuffmg in Automatic DLE stuffing when None
the receiver input
transparent mode DLE is loaded except if
2. DTR is connected to DCD and RTS is con-
CR3 = I
nected to CTS
6. SYNC I stnpping AII SYNC I First SYNC1 of pall 3. The receiver is clocked by the transmit
m double sync clock.
non-transparent 4. The DTR, RTS and TxD outputs are held
mode high
7 Baud rate Three One 5. The CTS, DCD, DSR and RxD inputs are
versions ignored
8 Terminate ASYNC Reset CRS in response to Reset CRO when TxEMT Additional requirements to operate in the fo.
transmission TxRDY changing from 0 to I goes from 1 to 0 Then reset cal loop back mode are that CRO (TxEN),
(drop RTS) CR5 when TxEMT goes from
CR1 (DTR), and CR5 (RTS) must be set to 1.
Oto I CR2 (RxEN) is ignored by the EPCI.
9 Break detect Pin 25' FE and null character
The second diagnostic mode is the remote
10 Stop bit searched One Two
loop back mode (CR7 CR6 = 11) I n t h i s
External jam sync Pin 9. No mode
12 Data bus timing improved over 2651
D ata assembled by t h e r e c e iver are
13 Data bus drwers Sink 2 2mA Smk 1 GmA
automatically placed in the transmit hold-
Source 400fxA Source IOOTTA i ng register an d r e t r a nsmitted b y t h e
NOTES transmitter on the TxD output.
Inlernel SRG used for Rxo 2 The transmitter is clocked by the recewe
2 Inlernel SRG used for Txo
c lock
W hen CR5 (RTS) is s e t , t h e RT S pi n i s D ata assembled b y t h e r e c e i ver a r e 3 No data are sent to the local CPU, but the
forced low and the t ransmit serial logic is automatically placed in the transmit hold. error status conditions (PE OE, FE) are
enabled. A 1 to 0 transition of CR5 will cause i ng register an d r e t r a nsmitted b y l h e set.
RTS to go high (inactive) one TxC time after transmitter on the TxD output 4 The RxRDY, TxRDY, and TxEMTT DSCHG
the last serial bit has been transmitted (if 2 The transmitter is clocked by the receive outputs are held high
the transmit shift register was not empty). c lock. 5. CRI (TxEN) is ignored
3 TxRDY output = 1. 6. All other signals operate normally.
The EPCI csn operate in one of four sub-
4. The TxEMTTDSCHG pin will reflect only
modes within each mslor mode (synchro-
the data set change condition
nous or a synchronous). The o p erational Status Register
5. The TxEN command (CRO) is ignored
sub-mode is determined by CR7 and CR6 The data contained in the status register (as
CR7-CR6 = 00 is the normal mode. with the In synchronous mode, CR7-CR6 = 01 places s hown in t a bl e 8 ) i n d i cate r e c eiver a n d
transmitter and receiver operating indepen- the EPCI in the automatic SYNr DLE stRP- transmitter conditions and modem rdata set
dently in accordance with the mode and sta- pmg mode The exact actiontaken depends status
tus register instructions on the setting of bits MR17 and MR16
SRO is the transmitter ready (TxRDY) status
In asynchronous mode, CR7 CR6 = 0 1 1. In the non-transparent, single SYN mode hit It, and its corresponding output, are valid
p laces t h e E P C I i n t h e a u t o m a ti c e c h o (MR17.MR16 = 1 0), characters i n t h e only when the transmitter is enabled If equal
mode Clocked r e generated received data d ata st r eam m a t c hing S Y N I a r e n o t to 0, it indicates that the transmit data hold
are automatically directed to the TxD line transferred to the receive data holding ing register has been loaded by the CPU and
while normal receiver operation continues. register (RHR). t he data has not b een transferred to t h e
The receiver must be enabled (CR2 = I), but 2 In the non-transparent, double SYN mode t ransmit shift register I f s e t e q ual t o 1 , it
the transmitter need not be enabled. CPU to ( MR17-MR16 = 0 0 ) , c h a racters in t h e indicates that the holding register is ready
receiver communications continues normal- data stream matching SYNI, or SYN2 if t o accept d at a f ro m th e CP U T h i s b i t i s
l y, but th e CP U t o t r a nsmitter link i s d i s . immediately preceded by SYNI, are not initially set when the transmitter is enabled
abled. Only the first character of s b reak transferred to the RHR. by CRO, unless a character has previously
condition is echoed. The TxD output will go 3 In transparent mode (MR16 = 1), charac- been loaded into the holding register. It is
high until the next valid start is detected ters in the data stream matching DLE, or not set when the automatic echo or remote
The following conditions sre true while in SYN1 if immediately preceded by DLE, loopback modes are programmed When
automatic echo mode are not transferred to the RHR However, this bit is set, the TxRDY output pin is low In
 page 0.83

the automatic echo and remote loop back
modes, the output is held high.
SR1, the receiver ready (RxRDY) status bit,
indicates the condition of the receive data
holding register. If set, it indicates that 8
character has been loaded into the holding
register from the receive shift register and is
ready to be read by the CPU. If equal to
zero, there is no new character in the hold-
ing register. This bit is cleared when the
CPU reads the receive data holding register
or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set, indi-
cates either a change of state of the DSR or
DCD inputs (when CR2 or CRO = 1) or that
the transmit shift register has completed
transmission of a character and no new
character has been loaded into the transmit
data holding register. Note that in synchro-
nous mode this bit will be set even though
the appropriate "fill" character is transmit-
ted. TxEMT will not go active until at least
one character has been transmitted. It is
cleared by loading the transmit data holding
register. The DSCHG condition is enabled
when TxEN = 1 or RxEN = 1. It is cleared
w hen the status register is read by t h e
CPU. If the status register is read twice and
SR2 = 1 w h il e SR 6 an d SR7 re main un-
changed, then a TxEMT condition exists.
When SR2 is set, the TxEMT/DSCHG output
is low.
SR3, when set, indicates a received panty
e rror when parity is enabled by MR i4 . In
synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a char.
aeter matching DLE register was received
and the present character is neither SYN1
nor DLE This bit is cleared when the next
character followmg the above sequence is
loaded into RHR. when the receiver is dis-
abled, or by a reset error command, CR4.
The overrun error status bit, SR4, indicates
that the prewous character loaded into the
receive holding register was not read by the
CPU st the time a new received character
was transferred into it. This bit is cleared
when the receiver is disabled or by the reset
error command, CR4.
In asynchronous mode, bit SR5 signifies that
the received character was not framed by a
s top b i t , i e , o n l y t h e fi r s t s t o p b i t i s
checked If RHR = 0 when SR5 = 1, a break
condition is present. In synchronous non-
transparent mode (MR16 = 0), it indicates
receipt of the SYN1 character m smgle SYN
mode or the SYN1-SYN2 pair in double SYN
mode. In synchronous transparent mode
(MR16 = I), this bit is set upon detection of
the initial synchronizing characters (SYN1
or SYNI-SYN2) and, after synchronization
has been achieved, when s DLE-SYN1 pair
is recewed The bit is reset when the recew-
er is disabled, when the reset error com-
mand is gwen in asynchronous mode, or
when the status register is read by the CPU
in the synchronous mode.
SR6 and SR7 reflect the conditions of the
DCD snd DSR inputs respectively A low in-
put sets its corresponding status bit, and a
high input clears it.

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNIT
Operatmg ambient temperature" Oto +70 *C
0
Storage temperature — 55 to +150 C
All voltages with respect to ground" — 0.3 to + 7.0 V

THERMAL CHARACTERISTICS
CHARACTERISTIC SYMBOL VALUE UNIT
Thermal Resistance
Ceramic 50
Plastic 6JA 100 'C/W
Cerdip 60

DC ELECTRICAL CHARACTERISTICS TA = O'C to+70'C, VCC = S.ov 5o%%d'''

LIMITS
PARAMETER TEST CONDITIONS UNIT
Min Typ Max
Input voltage
VIL Low — 0.3 0.6
VIH High 2.0 VCC
Output voltage
VOL IOL 2. 2mA 0.4
VPH/ High IPH = - 4 0 0 P A 2,4

Input leakage current VIN = 0 to 5.5 V 10 PA

3.state output leakage current PA
Data bus high 10
VOUT = 0 to 5.25 V
Data bus low 10

ICC Power supply current 'I 50 mA

CAPACITANCE T „ = 25'C, VCC = ov

LIMITS
PARAMETER TEST CONDITIONS UNIT
Min Typ Max
Capacitance pF
VIN = VCUT = 0 V
GIN Input 20
COUT Output fc = 1MHz 20
CII0 Input /Output Unmeasured pins tied to ground 20
noise oa followmg page

O MO T O R O L A Se m i conducfor Products Inc

page D.84

Ac ELECTRICAL CHARACTERISTICS T A= 0' c to +70'c, vcc = 5 ov 2 5cb ' ' 6

PARAMETER TEST CONDITIONS Min Typ Max UNIT

Pulse width ns
tRES Reset 1000
ICE Chip enable 250
Setup and hold time ns
IAS Address setup 10
IAH Address hold 10
ICS R/W control setup 10
ICH R/W control hold 10
IDS Data setup for write 150
IDH Data hold for write 0
IRXS Rx data setup 300
IRXH Rx data hold 350

tDD Data delay time for read CL = 150pF 200 ns

tDF Data bus floating time for read CL = 150pF 100
tCED CE to CE delay 600
Input clock frequency MHz
IBRG Baud rate generator
(MC2661A,B/MC68661A,B) 1.0 4.9152 4.9202
IBRG Baud rate generator
(MC2661C/MC68661C) 1,0 5.0688 5.0738
TxC or RxC dc 1.0
Clock width ns
IBRH Baud rate high (MC2661A,B/MC68661A,B) 75
IBRH Baud rate high (MC2661C/MC68661C) 70
IBRL Baud rate low (MC2661A,B/MC68661A,B) 75
IBRL Baud rate low (MC2661C/MC68661C) 70
tR/TH TxC or RxC high 480
IR/TL TxC or RxC low 480

ITXD TxD delay from falling edge of TxC CL = 150pF 650 ns

Skew between TxD changing and falling edge of TxC
output8 CL = 150pF TBD TBD
NOTES
1. Stresses above those bated underAbsolute Maximum Rabngs may cause permanent damage to lhe device This is a slress rabng only and functional operaten ol the dewce at these or
al any other condnen above those indicated in the operaten section ol this speahcabon is not imphed
2. For operabng at elevated temperatures, the device must be derated based on 150'c maximum funchon temperature and thermal resislance of 60'cnu luncbon lo ambient fto ceramic
pacxage)
3 This product nciudes rvrcutry speoficafiy desxtnsd for Ihe protecten of ns internal devices from lne damagng effects of sxcesstve slate charge Nonetheless n is suggested that
convsnhonal precautens be taKen to avoe applymg any voltages larger than ills rated max ma
4. Parameters are valid over operating temperature range unless othenvise specibed.
5. All voltage measurements are referenced toground. All arne measurements are at the 50% level for inputs (except tsRH and lenb) and at 0.8 V and 2 0 V for outputs. Input levels swing
between 0.4 v and 2.4 v, wnha transnion time ot 20ns maximum.
6. Typeat values are al + 25"C, typeal supply voltages and typical processing parameters
T. TxRDY, RxRDY and TxEMTrDSCHG outputsare open drain.
8. Parameter applies wlien inlernal transmitter clock is used.
g. Under lest conditions of 5.0688 MHz fane (Mc2661ciMc68661c) and 4 9152 MHz f eno (Mc2661A,s.Mc68661A,S), laRH and taRE measured at viH and vfb respectively

POWER CONSIDERATIONS

The average chip )unction temperature, TJ, in 'C can be obtained from.
TJ = TA+ (POef)JA) (I)
Where:
TAas Ambient Temperature, 'C
eJAsa Package Thermal Resistance, Junction-to-Ambient, 'C/W
PD= PINT+ PPORT
PiNT saICC x VCC, Watts — Chip Internal Power
PPORT — Port Power D issipation, Watts — User Determined
For most applications PPORTe PINT and can be neglected. PPOR T may become significant if the device is configured to
dnve Darlington bases or sink LED loads.
An approximate relationship between PD and TJ (if PPORT is neglected) is
PP = K (TJ+ 273'Cl (2)
Solvfng equations I and 2 for K gives;
K = PDe(TA+ 273'C) + 8JA • P D2 (3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K the values of PD and T J can be obtained by solving equations (1) and (2) iteratively for any
value of TA.
MO T O R O L A Se m i conductor Products Inc
 page 0.85

• • •

TIMING DIAGRAMS
RESET CLOCK

leRH IBRL
I fl I T H IRITL

RESE T
IREE B RCLK T*C A C

R BAG
NR/T

TRANSMIT RECEIVE

e I I UE
I* O A I f C L O C K P E RIOOSI
I C
I INPU I I

R.O

T•D
I fl I S IRKH

'I,O I'f O

' TC\

E.c
(OUT PU T I

READ AND WRITE

CE

'CE ICED ~

I AH

Riw

ICH~

DP DT
(WIRTE)

IDS

OP.DT BU S NOT DATA VALID

(READ) F L O A TING VALID BUS FLOATING
I
IDO IDF
page D.86

TIMING DIAGRAMS ( Cont'd)

TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode] )

T C Its i

I 3 3 J S I 3 3 • 5 I 3 3 • S I 3 J • 5 I 3 3 • \

I 0 DATA DATA 3 DATA 3 SYN DATA •

T • EN
0

0Z
0

0Z T ROY
0Z
IJ
3
T Eer

CE FOR
WRITE
01 THR
OAT* I DATA 3 DATA 3 DATA •

D ~ A 3 3 1 S e C A I 3 3 • S a C A I 3 3 • S B C m— 0 ~ A I

I D DATA DATA 3 DATA 3 DATA I

T • EN

T RD

T Elf

CE FOR
WRITE
OF THR
DAT* I OATS 3 DATA J DATA •

NOTES
A = Start b I
a = Slop b i
C = Stop b I 2
o = Txo mark ng condition
T xEMT goes low at th e b e g mn no ot Ihe Iasl d al e bi t or I p, i t y i s e n e b ie d a t t h e b e g nmng ot lhe party b it
 page D.87

Y • •

TIMING DIAGRAMS (Cont'd)

EXTERNAL SYNCHRONIZATION WITH XSYNC

I XR C

tes XSYNC SETUP TIME Soo

IH X S YNC HOLD TIME O N E R • C

XSTHC

IH

R0

CHARACTER ASSEMBLY

BREAK DETECTION TIMING

R • CHARACTER 6 B I T S N O PARITY

R C I 6 w 66

LOOK FOR START BIT L O W RF R 0 IS HIGH, LOOK FOR HIGH TO LOW TRAHSITIONi
I
FALSE START BIT CHECK MADE IR*O LOW)
t
t
MISSING STOP BIT
OETECTEO SET FE BITB
IST DATA BIT MISSiNG STOP BIT DETECTEO SET FE BIT
SAMPLED 0 - RHR ACTIVATE R RDY SET BKDET PIN

R •
D INPUT — R SR UNTIL A MARK TO SPACE TRANSITION OCCURS

NOTE
e It fhe slop bil is ptesenl Ih e s le it bit seetch
wib commence immedielely
page 0.88

• • • • •

TIMING DIAGRAMS (Cont'd)

R(ERDY (Shown for 5-bit characters, no panty, 2 stops bits [in asynchronous mode) )

R*C

I 2 3 • 3 I 2 3 • S I 2 3 4 1 I 2 3 • 3 I 2 3 • 1 I 2 3 • 3

RD SFN I DATA I DATA 2 DATA 3 DA TA • DATA 3

IGNORED
8
0 R • EN

?
0 STNOET
STATUS 8
8
0
8
U

R RD

CE FOR
I
READ
READ READ READ READ READ READ
STATUS STATUS RHA RHR RHR AHR
(DATA II IOATA 21 (DATA 3) IDATA 31
D
4 I 2 3 4 \ 8 C A I 2 3 • 1 8 C D A I 2 3 4 \ 8 C A I 2 3

DATA I DATA 2 DATA 3 DATA •

R • EN
0

08
0
8 RDT
0Z

0Z OVERRUN
S TATUS 8 1
UZ
R

CE FOR
READ
READ READ
RHR RHR
(DATA I) (DATA 31

NOTES
A SI 8 r t t l I
a = Stop b,l
C S lo p b t 2
o T o ma r k nocond(non
O nly o e s to p b I 3 d e t e c t e d
 page D.89

• • • • • •

TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL

ADDRESS BUS

CONTROLeus

oATAeus

RO
CONVERT

TD
L J

BAUD RATE CLOCK CRT

OSCILLATOR TE RM I N A L

ASYNCHRON OUS INTERFACE TO TELEPHONE LINES

ADDRESS BUS

CONTROL BUS

DATA BUS

RKD

OSR PHONE
ASTRO LINE
DTR MODEM INTERTACE

CTS

RTS

DCD

BAUD RATE CLOCK

OSCILLATOR
T E L E P H 0 N E.
L IN E
page 0.90

TYPICAL APPLICATIONS <Cont'tt)

SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE

ADDRESS BUS

CONTROL BUS

tDATA BUS

SYNCHRONOUS
T E 8 MIN A L
2661 OR PERIPHERAL
DEVICE

SYNCHRONOUS INTERFACE TO TELEPHONE LINES

tj: CONTROL BUS

DATA BUS

TD

R•C PHONE
LINE
I N T E 8 r AC E
SYNC
MODEM
DCO

CTS

RTS

DTR

TELEPHONE
LINE
 page 0.91

• • • •
r
• •

MC68000 MPU-TO-EPCI INTERFACE
REQUIREMENTS
The circuit shown in Figure 2 interfaces the
EPCI to the MC68000 MPU. The 8-bit data
bus of the EPCI is connected to the low order
8 bits of the MPU data bus (DO-D7). Due to
this, the EPCI's registers are addressed on
word (even byte) boundaries and so address
line A1 of the MPU is connected to the AO
address line of the EPCI. Similarly, A2 of the
MPU is connected to Al of the EPCI. R/W on
the MC68000 is inverted and connected to R/
W of the EPCI.
The CEs~inal must be generated for the EPCI
and the DTACK signal must be supplied to the
MPU. To allow for the data setup time on a
read of the EPCI, CE must be delayed one-
half clock cycle and DTACK generated on the
next rising edge of the system clock. This
causes the processor to insert one wait state
in the bus cycle. In addition to this, CE must
not be reasserted until the chip enable period
tCE has expired, Since some instructions on
the MC68000 can cause access to consecu-
tive addresses on consecutive bus cycles
(e.g., MQVEP), an INHIBIT signal must be
generated to hold-off an access during this
period. A state machine consisting of a 74LS161
binary counter and a 74LS74 D flip-flop is con-
figured as a digital "one shot," The rising edge
of CE starts the counter which times out after
given riumber of clock cycles. Since tCE is 600
ns, a minimum of 5 clock cycles at 8 MHz (625
ns) is required. The timing for two consecutive
read bus cycles is shown in Figure 3. The IN-
HIBIT signal prevents CE from being gener-
ated and DTACK from being asserted, causing
the processor to generate wait states until IN-
HIBIT is negated.
M6809 FAMILY MPU-TO-EPCI
INTERFACE REQUIREMENTS
The M6809 family of microprocessors can be
easily interfaced to the EPCI as shown in Fig-
ure 4.

FIGURE 2 — MC68000-TO-EPCI INTERFACE — EXAMPLE CIRCUIT

5 MHs

CLK
+ SV
CLK
+5 CARRY
UDs A
CLR B 5 CYCLE DELAY
D c
0 LOAD

PRE
TSLSiei
A i /22
+5 V
INHIBIT 75LS 7 5
Mceeooo ENABLE
Mpu
ADDR
DO DT DECODE EPCI
+ev +5 V
Ai Ao
CLR CLR
D D Ai
0 0
PRE PRE
re V DO-DT
TSLS75
+5V

ttw

RESET

R/W
RESET
page 0.92

I • • r

FIGURE 3 — MC88000-TO-EITCIREAD 8US CYCLE TIMING

So Sl S2 S3 64 w w ss ss sr so sl s2 s3 s4 w w w w w w w w ss s6 sr

UDS IL Ds

INHIBIT (SEE NOTE)

ENABLE

CE

DTACK

AI A3
VA LID VALID

OO-OT
VALID VALID

[ w— 200 4 4

NOTE: INSERTION OF INHIBITPERIOD DELAYS NEXT READ CYCLE FOR 5 CLOCK CYCLES

FIGURE 4 — INTERFACE CONNECTIONS TO MC8809

HIGH ORDER ADDRESS

ADDRESS DECODE CE

DATA 00-Dr

MC66661
MC6606 EPCI

Rav

Aa AO

Al

RESET RESET

TO (IESET CIRCUITRY

Motorola reserves the nght to make changesto any products herein to improve reliability, function or design Motorola does nut assume any liability an sing
out of the application or use of any product or circuit descnbed herein, neither does it convey any license under its patent rights nor the rights of others
 page D.93

•
• •
• •

NOTES.
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm(0.010) AT MK L I MET ER6 INCHES
MAXIMUM MATERIAL CONDITION, IN DIM MIN MAX MIN MAX
RELATION TO SEATING PLANE AND
EACH OTHER. 36.45 37.21 1.435 1.465
13.72 14.22 0 540 0.560
2. DIMENSION L TO CENTER OF LEADS 3.94 5.08 0 155 0. 200
WHEN FORMED PARALLEL. 0.36 0.56 0.014 0.022
3. DIMENSION 8 DOES NOT INCLUDE 1.02 1,52 0.040 0.060
MOLD FLASH. 2.54 BSC 0 100 BSC
0 1.65 2. 16 0.065 0.085
0 20 0 . 38 0 008 0.015
2.92 3 . 43 0 115 0,135
(c 15.24 BSC 0.600 BSC
Oc 15 4 Oc 155
0.51 1 . 02 0.020 0.040

CASE 110
— )H' - I G I-- M
K
F D s ( L ( Ls

NOTES
I. LEADS, TRUE POSITIONED WITHIN
MI L L IME TERS INCHES
0.25 mm (0.010) DIAMETER (AT
SEATING PLANE) AT MAXIMUM DIM MIN MAX MIN MAX
MATERIAL CONDITION. 35. 20 35.92 l. 386 1.414
2. DIMENSION "L" TO CENTER OF 14.73 15.34 0.580 0.604
LEADS WHEN FORMED PARALLEL. 3.05 4. 19 0.120 0.165
0.38 0.015 0.021
0. 76 1.40 0.030 0,055
BSC 0 100BSC
0. 76 1. 78 0.030 0.070
0. 20 0.30 0.008 0 012

I= I
4.19 0 100 0.165
14 99 15.49 0 590 0.610
105 105
0 51 1 . 5 2 0 020 0 060

G F D P EEA(inc CASE 719

PLANE

NOTES
1. OIM ~A. I S DATUM,
2. POSITIONAL TOL FOR LEADS MILLIMETERS INCHES
ts 15 )I 025(0.010 M T A M DIM MIN MAX MIN MAX
3 ~T. I S SEATING PLANE. A 3 6 . 45 37 85 1.435 1.490
4. DIM AAND 8 INCLUDES MENISCUS. 8 1 270 15.37 0. 500 0.605
5. DIM L TO CENTER OF LEADS
WHEN FORMED PARALLEL. C 4 . 06 584 0.160 0.230
6 DIMENSIONING ANO TOLERANCING D 0 . 3 8 0 56 0 015 0,022
PE 8 ANSI Y14 5, 1973 F 127 1 65 0.050 0 065
G 2 54 B SC 0 100 BSC
L J 0 20 0 30 0 008 0.012
rC K 2 54 4 06 0.100 0 160
L 152 4 BSC 0600 BSC
M 5c 155 55 155
N 0 51 1 21 0 020 0 050

CASE 133

Published by Motorola Inc. with portions copied by permission of Signetics Corporation

O MO T O R O L A Se m i conductor Products Inc

3501 ED BLUESTEIN BLVD AUSTIN. TEXAS 78721 • A SUBSIDIARY OF MOTOROLA INC
page D.94

8253/8253-5
PROGRAM M A BLE INTERVAL TIMER
• MCS-85™ Compatible 8253-5 • Count Binary or BCD

• 3 Independent 16-Bit Counters

• Single + 5V Supply
• DC to2 MHz

• Programmable Counter Modes • 24-Pin Dual In-Line Package

The Intele 8253 is a programmable counter/timer chip designed for use as an Intel microcomputer peripheral. It uses
nMOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a count rate of up to 2 MHz. All modes of operation are soft-
ware programmable.

PIN CONFIGURATION BLOCK DIAGRAM

DT I 24 Vcc
CLK 0
D4 22 WR
DATA COUNTER
Ds 22 DI Dc BUS =0 GATE 0
BUFFER
D4 OUT 0
OT AI

OT 8 S 253 18 Ao
DI 7 18 CLK 2
DP OUT 2
CLK 0 GATE 2 CLK I
OUT 0 CLK I READ/
COUNTER
WRITE =I GATE I
GATE 0 GATE I LOGIC
Ac
GND OUT I OUT I

PIN NAMES
CLK 2
D7 D DATA BUS (8 BIT I CONTROL
WORD COUNTER
CLK N COUN T ER CLOCK INPUTS =2 GATE 2
REGISTER
GATE N CO U N T E R GATE INPUTS
OUT 2
OUT N COUN T ER OUTPUTS
RD READ COI NTER
WRITE COMMAND OR DATA
CS CHIP SELECT
COUNTER SELECT
V 5 VOLTS
GND INTERNAL BUS
 Page 0.95

8253/8253-5

FUNCTIONAL DESCRIPTION AO, A1

General These inputs are normally connected to the address bus.
The 8253 is a p r o g rammable interval timer/counter Their function is to select one of the three counters to be
s pecifically designed for use w ith th e I nte l M i c r o - operated on and to address the control word register for
computer systems. Its function is t hat o f a g e neral mode selection.
purpose, multi-timing element that can be treated as an CS (Chip Select)
array of I/O ports in the system software. A "low" on this input enables the 8253. No reading or
The 8253 solvesone of the most common problems in any writing will occur unless the device is selected. The CS
microcomputer system, the generation of accurate time i nput has no effect upon the actual operation of t he
delays under software control. Instead of setting up timing counters.
loops in systems software, the programmer configures the
8 253 to m atch hi s r equirements, initializes one of t h e
counters of the 8253 with the desired quantity, then upon
command the 8253 will count out the delay and interrupt
the CPU when it has completed its tasks. It is easy to see CLK 0
OATA
that the software overhead is minimal and that multiple BUS
COUNTI.R
GATE 0
=0
delays can easily be maintained by assignment of pnority BUFFER
OUT 0
levels.
O ther counter/timer f u nctions t hat a r e n o n -delay i n
nature but also common to most microcomputers can be
implemented with the 8253. RO
• Programmable Rate Generator WR
CLK I
REAOI COUNT I 1.
• Event Counter WRITE =I GATE I
LOGIC
• Binary Rate Multiplier Ao
OUT I
• Real Time Clock AT

• Digital One-Shot
• Complex Motor Controller
Cs
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface . CLK 2
CONTROL
the 8253 to the system data bus. Data is transmitted or WORD COUNT I H
GATE 2
=2
RE GIST I 0
received by the buffer upon execution of INput or OUTput
OUT 2
CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the 8253,
2. Loading the count registers.
3. Reading the count values.
INTERNAL BUS
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus Figure 1. Block Diagram Showing Data Bus Buffer and
and in turn generates control signals for overall device Read/Write Logic Functions
operation. It is enabled or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
RD (Read) CS RD WR At Ap
A "low" o n t h i s i n put i n f orms the 8253 that the CPU is
Load Counter No. 0
inputting data in the form of a counters value.
Load Counter No, t
WR (Write) Load Counter No. 2
A "low" on this input informs the 8253 that the CPU is
Write Mode Word
outputting data in the form of mode information or loading
counters. Read Counter No. 0
Read Counter No. I
Read Counter No. 2
No-OpsrBtion 3-State
Disable 3-State
No-OperBtion 3-State
page D.96

8253/8253-5

Control Word Register

The Control Word Register is selected when AO, A1 are 11.
It then accepts information from the data bus buffer and CLK 0
s tores it i n a r e g i ster. The i n f ormation stored i n t h i s DT DATA COUNTER
BUS GATE 0
register controls the operational MODE of each counter, OA
BUFFER
=0

selection of binary or BCD counting and the loading of OUT 0

each count register.

The Control Word Register can only be written into; no
read operation of its contents is available
CLK I
Counter «0, Counter «1, Counter «2 READ/ COUNTET
WRITE =I GATE I
These three functional blocks are identical in operation so LOGIC
only a single Counter will be described. Each Counter OUT I

consists of a single, 16-bit, pre-settable, DOWN counter.

The counter can operate in either binary or BCD and its
input, gate and output are configured by the seiection of CS
MODES stored in the Control Word Register.
The counters are fully independent and each can have CLK 2
CONTROL
separate Mode configuration and counting operation, WORD COUNTER
GATE 2
= 2.
binary or BCD. Also, there are special features in the REGISTER
OUT 2
control word that handle the loading of the count value so
that software o verhead ca n b e m i n i mized fo r t h e se
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
INTERNAL BUS
counting applications and special commands and logic
are included in the 8253 so that the contents of each
counter can be read "on the fly" without having to inhibit
the clock input.
Figure 2. Block Diagram Showing Control Word
8253 SYSTEM INTERFACE Register and Counter Functions
The 8253 is a component of the Intel'" Microcomputer
Systems and interfaces in the same manner as all other
ADDRESS BUS116l
peripherals of the family. It is treated by the systems
software as an array of peripheral I/O ports; three are AI A0
counters and the fourth is a control register for MODE
CONTROL BUS
programming.
I 'OR I 'OW
Basically, the select inputs AO, A1 connect to the AO, A1
address bus signals ofthe CPU. The CS can be derived DATA BLIS IBI

directly from the address bus using a linear select method.

Or it can be connected to the output of a decoder, such as
an Intel> 8205 for larger systems
A, A CS DO DI RD WR
6253
COUNTER COUNTER COUNTER
0 2

0\IT GATE CLK OUT GATE CLK

Figure 3. 8253 System Interface

 page 0.97

8253/8253-5

M — MODE:
OPERATIONAL DESCRIPTION M2 M 1 MO
Mode 0
General
The complete functional definition o f the 8 253 i s Mode 1
programmed by the systems software. A set of control Mode 2
words must be sent out by t he CPU to initialize each
counter of the 8253 with the desired MODE and quantity Mode 3
information. Prior to initialization, the MODE, count, and Mode 4
output of all counters is undefined. These control words
Mode 5
program the MODE, Loading sequence and selection of
binary or BCD counting.
Once programmed, the 8253 is ready to perform whatever BCD:
timing tasks it is assigned to accomplish.
T he actual c ounting o peration o f e a c h c o unter i s 0 Binary Counter 16-bits
completely independent and additional logic is provided
on-chip so t hat th e u s ual p roblems associated with Binary Coded Decimal (BCD) Counter
(4 Decades)
efficient m o nitoring an d m a n agement o f e x t e rnal,
asynchronous events or r ates to t h e m i crocomputer
system have been eliminated.
Programming the 8253 Counter Loading
All of the MODES for each counter are programmed by the The count register is not loaded until the count value is
systems software by simple I/O operations. written (one or two bytes, depending on the mode
selected by the RL bits), followed by a rising edge and a
Each counter of the 8253 is individually programmed by
falling edge of the clock. Any read of the counter prior to
writing a control word into the Control Word Register.
that falling clock edge may yield invalid data.
(AO, A1 = 11)
Control Word Format MODE Definition
D7 De Ds D4 Ds Dz Dt Dp MODE 0: Interrupt on Terminal Count. The output will
be initially low after the mode set operation. After the
SC1 S C O R L1 RLO M2 M1 MO BC D count is loaded into the selected count register, the out-
put will remain low and the counter will count. When ter-
minal count is reached the output will go high and re-
Definition of Control main high until the selected count register is reloaded
with the mode or a new count is loaded. The counter
SC — Select Counter.
continues to decrement after terminal count has been
SC1 SCO reached.
Select Counter 0 Rewriting a counter register during counting results in
Select Counter 1 the following:
Select Counter 2 (1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
I llega I
MODE 1: Programmable One-Shot. The output will go
RL — Read/Load: low on the count following the rising edge of the gate in-
RL1 RLO put
Counter Latching operation (see The output will go high on the terminal count. If a new
count value is loaded while the output is low it will not
READ/WRITE Procedure Section)
affect the duration of the one-shot pulse until the suc-
Read/Load most significant byte only, ceeding trigger. The current count can be read at any
time without affecting the one-shot pulse.
Read/Load least significant byte only.
The one-shot is retriggerable, hence the output will re-
Read/Load least significant byte first,
main low for the full count after any rising edge of the
then most significant byte.
gate input.
page 0.98

8253/8253-5

MODE 2: Rate Generator. Divide by N counter. The out- If the count register is reloaded between output pulses,
put will be low for one period of the input clock. The counting will continue from the new value. The count
period from one output pulse to the next equals the will be inhibited while the gate input is low. Reloading
number of input counts in the count register. If the the counter register will restart counting beginning with
count register is reloaded between output pulses the the new number.
present period will not be affected, but the subsequent
period will reflect the new value.
The gate input, when low, will force the output high. MODE 5: Hardware Triggered Strobe. The counter will
When the gate input goes high, the counter will start start counting after the rising edge of the trigger input
from the initial count. Thus, the gate input can be used and will go low for one clock period when the terminal
to synchronize the counter. count is reached. The counter is retriggerable. The out-
put will not go low until the full count after the rising
When this mode is set, the output will remain high until
after the count register is loaded. The output then can edge of any trigger.
also be synchronized by software.
MODE 3: Square Wave Rate Generator.Similar to MODE
2 except that the output will remain high until one half Signal Low
the count has been completed (for even numbers) and StaIUS Or Going
go low for the other half of the count. This is accom- Modes Low Rising High
plished by decrementing the counter by two on the fall- Disables Enabies
ing edge of each clock pulse. When the counter reaches counting c 0 U n I i il g
terminal count, the state of the output is changed and 1 1 inil i a l e S
the counter is reloaded with the full count and the whole counting
process is repeated. 2) Resets output
afternext clock
If the count is odd and the output is high, the first clock I) Disables
pulse (after the count is loaded) decrements the count c 0 U fl I i n g
1) Reloads Enables
by 1. Subsequent clock pulses decrement the clock by 2) Sets output
counter counling
2) initiates
2. After timeout, the output goes low and the full count immedialely
counting
Il gil
is reloaded. The first clock pulse (following the reload)
decrements the counter by 3. Subsequent clock pulses I) Disables
c 0 U il I i n g Initiates Enables
decrement the count by 2 until timeout. Then the whole 2) Sets oulput counting counting
process is repeated. In this way, if the count is odd, the immediately
output will be high for (N+ 1)/2 counts and low for high
(N — 1)/2 counts. Disables Enables
counting counting
MODE 4: Software Triggered Strobe. After the mode is Initiates
set, the output will be high. When the count is loaded, counting
the counter will begin counting. On terminal count, the
output will go low for one input clock period, then will
go high again. Figure 4. Gate Pin Operations Summary
 page 0.99

8253/8253-5

MODE 0: Interrupt on Terminal Count MODE 3: SquareWave Generator

CLOCK CLOCK
4 2 4 2 4 2 4 2 4 2 4 2 4
OUTPUT (n • )
5 4 2 5 2 5 4 2 5 2 5 4 2
4 3 2 I 0
OUTPUT (INTERRUPT) OUTPUT (n 5)
(n • >

GATE
5 4 3 2 I 0
OUTPUT llNTERRUPT)
(m 5)
A 5
An B m

MODE 1: Programmable One-Shot MODE 4: Software Triggered Strobe

CLOCK CLOCK

WR n•4

4 3 2 I 0
TRIGGER
OUTPUT
4 3 2 I 0
OUTPUT
(n • 4)

LOAD n n 4
TRIGGER
4 3 2 4 3 2 1 0 GATE
OUTPUT 4 4 3 2 1 0
OUTPUT

MODE 2: Rate Generator MODE 5: Hardware Triggered Strobe

CLOCK CLOCK
4
WR n GATE
• 3 7 I 0 (4 3 7 I OI ) 7 I 0
OUTPUT 3 2 I 0
OUTPUT (n 4>
0(3I 3 7 I 0( 3) 2 I 0(3) 2 I
OUTPUT (n - 3)

RESET
GATE
• 3 4 3 2 I 0
OUTPUT In • l

Figure 5. 5253 Timing Diagrams

page 0.100

8253/8253.5

8253 READ/WRITE PROCEDURE

Write Operations
MODE Control Word
The systems software must program each counter of the Counter n
8253 with the mode and quantity desired. The program-
mer must write out to the 8253 a MODE control word and Count Register byte
the programmed number of count register bytes (1 or 2) Counter n
prior to actually using the selected counter. Count Register byte
The actual order of the programming is quite flexible. Counter n
Writing out of the MODE control word can be in any
sequence of counter selection, e,g., counter ¹0 does not Note; Format shown is a simple example of loading the 8253 and
have to be first or counter ¹2 last. Each counter's MODE does not imply that it is the only format that can be used.
control word register has a separate address so that its
loading is completely sequence independent. (SCO, SC I) Figure B. Programming Format
The loading of the Count Register with the actual count
value,however, must be done in exactly the sequence
programmed in the MODE control word (RLO, RL1). This
loading of the counter's count register is still sequence A1 AO
independent like the MODE control word loading, but
when a selected count register is to be loaded it must be MODE Control Word
No. 1
loaded with the number of bytes programmed in the Counter 0
MODE control word (RLO, RL1). The one or two bytes to MODE Control Word
be loaded in the count register do not have to follow the No. 2
Counter 1
associated MODE control word. They can be programmed
at any time following the MODE control word loading as MODE Control Word
No. 3
long as the correct number of bytes is loaded in order. Counter 2
All counters are down counters. Thus, the value loaded Count Register Byte
into the count register will actually be decremented. No. 4
Counter 1
Loading all zeroes into a count register will result in the
maximum count (2 ta for Binary or 10' for BOD). In MODE 0 Count Register Byte
No. 5 MSB Counter 1
the new count will not restart until the load has been
completed. It will accept one of two bytes depending on Count Register Byte
how the MODE control words (RLO, RL1) are program- No. 6
Counter 2
med, Then proceed with the restart operation.
Count Register Byte
No. 7
Counter 2
Count Register Byte
No. 8
Counter 0
Count Register Byte
No. 9
Counter 0

Note: The exclusive addresses of each counter's count register make

the task of programming the 8283 a very simple matter, and
maximum effective use of the device will result if this feature
is fully utilized.

Figure 7. Alternate Programming Formats

 Page D.101

8253/8253-5

Read Operations Read Operation Chart

In most counter applications it becomes necessary to read
A1 AO RD
t he v alue o f t h e co u n t i n pr o g r ess a n d m a k e a
c omputational decision based o n t h i s q u a ntity E v e n t Read Counter No. 0
counters are probably the most common application that
Read Counter No. 1
uses this function The 8253 contains logic that will allow
the programmer to easily read the contents of any of the Read Counter No. 2
t hree counters without d i sturbing th e a c tual c o unt i n
progress.
Ill ega
I
There are two methods that the programmer can use to Reading While Counting
read the value of the counters The first method involves
In order for the programmer lo read the contents of any
the use of s i mple I/O re ad o p e rations of t he s e lected
counter w i t hout e f f ecting o r d i s t u r bing t h e c o u n t ing
counter. By controlling the AO, A1 inputs to the 8253 the
operation the 8253 has special internal logic that can be
programmer can select the counter to be read (remember
that no read operation of the mode register is allowed AO. a ccessed using simple WR c o m mands to t h e M O D E
A1-11) The only requirement with this method is that in register Basicaily, when the programmer wishes to read
order to assure a stable count reading the actual operation the contents of a selected counter "on the fly" he loads the
of the s e lected c o u nter mu s t be in h i b i ted e i t h er b y MODE register with a s p e cial code w h ic h l atches the
controlling the Gate input or by external logic that inhibits present count value into a st o r age r e gister so t h at i ts
the clock input The contents of the counter selected will c ontents c o n tain a n a c c u r ate, s t able q u a ntity T h e
be available as follows programmer then issues a normal read command to the
selected counter and the contents of the latched register is
first I/O Read contains the least significant byte (LSB) available
s econd I/ O R e a d c o n t ains th e m o s t s i g n ificant b y t e
(MSB) MODE Register ior Latching Count
Due to t h e i n t e rnal l o gi c o f t h e 8 2 5 3 i t i s ab s o l u t ely AO,A1 = 11
necessary to complete the entire reading procedure If two
bytes are programmed to be read then two bytes must be D7 D6 D5 D4 D3 D2 D1 DO
read before any loading WR command can be sent to the
SC1 SCO 0 0 X X X X
same counter.
SC(,SCO — specify counter to be latched
D5.D4 — 00 designates counter latching operation
X don't care
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.

3MHz ' 1.5MHz

CLK 2 CLK

8085 8253-5

'll an 8085 clock output Is to drive an 8253.5 clock inpul, il must be reduced to 2 MHz or less.

Figure 8. MCS-85™ Clock Interlace'

page 0.102

8253/8253-5

ABSOLUTE MAXIMUM RATINGS' COMMENT S t resses above rhose listed under "Absolute
Maximum Ra tings" may cause pernianent damage ro the
device. This is a stress rating only ann' funcrional opera-
Ambient Temperature Under Bias O'Cto 70 C
— 65'C to+150" C tion of the ilevice ar these or any other condi rions above
Storage Temperature
Voltage On Any Pin those indicarcil in rhe operational secrions of rhis specifi.
With Respect to Ground — 0.5Vto i 7V cation i s n o t u n p l i ed. E x p osure t o a b solute m a xi m um
Power Dissipation 1 Watt rating conditions for exrended penorls inay affecr device
reliahili ty

D.C. CHARACTERISTICS ( TA = O'C to 70"C; Vcc = 5V +10%}

SYMBOL PARAMETER M I N. MAX. UNITS TEST CONDITIONS
VIL Input Low Voltage -0.5 0.8
Vrn Input High Voltage 2. 2 Vcc+ 5V
VoL Output Low Voltage 0. 45 V Note I
VoH Output High Voltage 2.4 Note 2
I'LL Input Load Current +10 pA VIN = Vcc to OV

IOFL Output F loat Leakage +10 pA VpuT = VCC to OV

icc Vcc Supply Current mA
N ote I: I p L = 2.2 mA.
N ote 2: I p H = -400 pA.

CAPACITANCE TA = 25 C; Vcc = GND = OV

Symbol Parameter Min. Typ. Max. Unit Test Conditions

Ci N Input Capacitance 10 pF fc = I MHz

CI/0 I/O Capacitance 20 pF Unmeasured pins returned to Vss

 Page D.103

8253/8253-5

A.C. CHARACTERISTICS T a = 0 C to 70 C; Vcc = 5.0V + 5%; GND = OV

Bus Parameters (Note 1)

Read Cycle:
8253 8253-5
SYMBOL PARAMETER M I N, MAX. MIN. MAX. UNIT
tAR Address Stable Before R EAD 50 30 ns
tRA Address Hold Time for READ ns
tRR READ Pulse Width 400 300 ns
tRD Data Delay From R EADI2I 300 200 ns
tDF READ to Data Floating 25 125 25 100 ns

tRV Recovery Time Between READ

and Any Other Control Signal

Write Cycle:
8253 8253-5
SYMBOL PARAMETER MIN. MAX. Ml N. MAX, UNIT
taw Address Stable Before WR ITE 30
twa Address Hold Time for WR ITE 30 30 ns
WR ITE Pulse Width 400 300 ns
tDW Data Set Up Time for WRITE 300 ns
tWD Data Hold Time for WRITE 40 30 ns
tRV Recovery Time Between %ZITI fss
and Any Other Control Signal

Notes' .1. AC timin e s measured at VpH 2 , 2 , V p L= 0.8

2. CL = 150PF.

Write Timing: Read Timing:

Ae s,CB

i- IAw AR RA

IRR
DATA BUS RD

'RW 'WO

DATA BUS HIGH IMPEDANCE VALID H I G H IRIPEDANCE

Input Waveforms for A.C. Tests:

2.4
2.2 2.2
TEST POINTS
0.8 0.8
0.45
page 0.104

8253/8253-5

Clock and Gate Timing:

8253 8253-5
SYMBOL PARAMETER M I N. MAX. MIN. MAX. UNIT
tCLK Clock Period dc dc ns
tPWH High Pulse Width 230 230 ns
Low Pulse Width 150 ns
tGW Gate Width High 1 50 150 ns
tGL Gate Width Low 100 ns
tGS Gate Set Up Time to CLKf 100 100 ns
tGH Gate Hold Time After CLKf 50 ns
too Output Delay From CLKSitf 400 ns
tOOG Output Delay From Gate(It I 300 ns

Note 1: C L = 1SOPF.

Pet H tet tt 'as

CLK

'as toH

GATE G

aH at too — H

OUTPUT 0

tppa
 Page D. 1 05

Programmable Array Logic Family

PAL®Series 20
U.S. Patent 4124899
March 1981

Features/Benefits PART
DESCRIPTION
NUMBER
PALIOHS OCTAL 10 INPUT AND-OR GATE AR AY
• Programmable replacement for conventional TTL
PAL12H6 HEX 12 I N PUT AND-OR GATE ARRAY
logic.
PAL14H4 QUAD 14 INPUT AND-OR GATE ARRAY
• Reduces IC inventories substantially and simplifies PAL16H2 DUAL 1 6 INPUT AND-OR GATE ARRAY
their control. PAL16CI 16 INPUT AND.ORr AND OR. INVERT GATE ARRAY
PAL IOLS OCTAL 10 INPUT AND-OR-INVERT GA'rE ARRAY
• Reduces chip count by 4 to 1. HEX 1 2 INPUT AND-OR-INVERT GATE ARRAY
PAL12L6

• Expedites and simplifies prototyping and board PAL14L4 QUAD 14 INPUT AND OR-INVERT GATE ARRAY
PAL16L2 DUAL 16 INPUT AND OR-INVERT GATE ARRAY
layout.
PAL 16LS OCTAL 16 INPUT AND-OR. INVERT GATE ARRAY
• Saves spacewith 20-pin SKINNY DIM packages. P4L IVRS OCTAL 16 INPUT REGISTERED AND-OR GATE ARRAY
PAL16R6 HEX 1 6 INPUT REGISTERED AND-OR GATE ARRAY
• High speed: 25ns typical propagation delay. PAL16R4 QUAD 16 INPUT REGISTERED AND-OR GATE ARRAY
• Programmed on standard PROM programmers. PAL16X4 QUAD 16 INPUT REGISTERED AND-OR-XOR GATE ARRAY
PAL16A4 QUAD 16 INPUT REGISTERED AND-CARRY-OR-XOR GATE ARRAY
• Programmable three-state outputs.
• Special feature reduces possibility of copying by
competitors.
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
Description terms connected to both true and complement of any single
input assume the logical low state. Registers consist of D type
flip-flops which are loaded on the low to high transition of the
The PAL family utilizes an advanced Schottky TTL process and clock. PAL Logic Diagrams are shown with all fuses blown,
the Bipolar PROM fusible link technology to provide user pro- enabling the designer use of the diagrams as coding sheets.
grammable logic for replacing conventional SSI/MSI gates and
flip-flops at reduced chip count.
The entire PAL family is programmed on inexpensive con-
ventional PROM programmers with appropnate personakty and
The family lets the systems engineer "design his own chip" by socket adapter cards. Once the PAL is programmed and ver-
blowing fusible links to configure AND and OR gates to perform ified, two additional fuses may be blown to defeat venfication.
his desired logic function. Complex interconnections which This feature gives the user a proprietary circuit which is very
prewously required time-consuming layout are thus "lifted" from difficult to copy.
PC board etch and placed on silicon where they can be easily
modified during prototype check-out or production.
Ordering Information
— PROGRAMMABLE ARRAY LOGIC FAMILY
The PAL transfer function is the familiar sum of products. Like — NUMBER OF ARRAY INPUTS
the PROM, the PAL has a single array of fusible links. Unlike the OUTPUT TYPE
H - ACTIVE HIGH
PROM, the PAL is a programmable AND array dnving a fixed L A C T IVE LOW
OR array (the PROM i s a f i xe d AN D a r ray driving a C C O M PLEMENTARY
R R E GISTERED
programmable OR array). In addition the PAL provides these X E X C LUSIVE-OR REGISTERED
A A R ITHMETIC REGISTERED
options. NUMBER OF OUTPUTS
TEMPERATURE RANGE
C 0C T O +T S C
• Vanable input/output pin ratio M -55C TO+125C
PACKAGE
N P L A S TIC DIP
• Programmable three-state outputs J C E R AMIC DIP
OPTIONAL Hl-REL PROCESSING
• Registers with feedback 8838 MIL-STD-883, METHOD 5004 8 5005 LEVEL 8
883C MI L-STD-883, METHOD 5004 8 5005 LEVEL C
8 M I L -STD-883, METHOD 5004 EQUIVALENT
• Anthmetic capability t
VAL' . e «.. 'Fle ee r eeermr e et kl , n t f e M
PAL14 L4 CJ 8838

Mononthlc
1165 East Arques Avenue, Sunnyvale, CA 94086 Tel: (408) 739-3535 TWX: 910-339-9229 M emOriea
Page 0.106

P AL Series 2 0

J20 Ceramic DIP

9 JA = 75'C/W
//JC = 35'C/W
20
2.65-.300
6.73-7.62
10

. 000
.000 .~
MAX .955-.990 MIN.
.290-.320
7.37-8.13

.015-.035
.38-.89 190
4.83
MAX
.150

MAX.
.125-.165 ' .006-.012
4 19
',

0 15
.20-.31
.090-.110 . 01 6-. 020 .055-.065
2. 29-2. 79 41 —.51 1.40-1 65

UNLESS 0 rhFRVlnSE SPECIFIED:

ALL DIMENSIONS MIN.-MAX, IN INCHES
ALL DIMENSIONS MRV..MAX, IN IRILLIMETERS,

N20 Plastic Kool Dip'"

OJA = 75'C/W
// JC — 35' C/W

0 . 240-. 290
6. 10-7.37
01 10

.080
2.03
MAX.
1,000-1.075
25.40-27.30

015- 060
38-1.52

U UJ J J
. 008-. 0 I 2

090-. I ten
t 016-.020 055-.065
2. 29-2. 79 .41-.51 1.40-1 65

UNLESS OTHERWISE SPECIFIEO

ALL DIMENSIONS MIN.-MAX. IN INCHES.
ALL DIMEIVSIONS MIN.-MAX. IN MILLIMF TERS.

Monol tt M lm o r e s e s e rves the i oht lo m ake c h a nqes in o r de r t i r r p r ove r rc u I y a n d s u p p ly t hc I I p rc d c t pn v , hi r

M onolithic Memor e. canr ot assu n v l i nsi b i t ly l o t h e use or any circi ilry descr hed oilier ln i r u il y n n t e i y e m hod c d , n tl r , p r ' c l No otnr r r rc« t patent nc a<sa r mpn d
 Page 0.107

P AL Series 2 0

PAL10H8 PAL12H6 PAL14H4 PAI 16H2 PAL16C1

20 20 20
20 I
19
19 2 19

18 18
18 3 18

17 17 17
17 4

AND 16 5 AND AND 16 AND AND

GATE GATE GATE GATE GATE
15 15 ARRAY ARRAY 15
ARRAY 15 6 ARRAY ARRAY
14 7 14 14 14

13 8 13

12 12 12 12

10 10 10 10 10

PAL10L8 PAL12L6 PAL14L4 PAL16L2 PAL16L8

20 20 20 20 20

19 19 19 19 19

18 18 18 18 18

17 17 17 17 17
AND
AND 16 AND 16 AND ANO 16 16
OR
GATE GATE GATE GATE
GATE
ARRAY 15 ARRAY 15 ARRAY 15 ARRAY 15
ARRAY
14 14 14 14 14

13 13 13 13 13

12 12 12 12 12

10 10 10 10

PAL16R8 PAL16R6 PAL16R4 PA L16X4 PA L16A4

20 20 20 20 20

19 19 19 19 19

18 18 18 18 16

17 17 17 17 AND 17
AND CARRY
AND AND AND 16
16 16 16 OR 16
OR
OR OR OR
XOR XOR
GATE 15
GATE 15
GATE 15 OD 15 15
GATE GATE
ARRAY ARRAY ARRAY
ARRAY ARRAY 14
14 14 14 14

13 13 13 13 13

12 12 12 12 12

10 10 10 10 10
Page 0.108

PAL Series 20

A bsolute Max i mu m R a t i n g s Operating P r ogramming

Supply Voltage, VCG 7 . .. .. .. . . . 12V
Input Voltage 5.5V .. . . . . . . . . 1 2V +
Off-state output Voltage 5 .5V .. . . . . . . . . 1 2 V
Storage temperature . — 65' to 1150'C

Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
M IN NOM MAX M IN NOM M A X

VGC Supply voltage 45 5 55 4 75 5 5 25

TA Operating free-air temperature 0 75 C

TC Operating case temperature —55 125 oC

EleCtr i Ca l C h a r a C t e r i S t iCS Over Operating Conditions

SYMBOL PARAMETER TEST CONDITIONS M IN T Y P M A X UNIT

VIL Low-level input voltage 0.8

VIH High-level input voltage

= MIN — 18mA —1.5
VIC Input clamp voltage VCC
Low-level input current = MAX
f VCC Vl — 0 4V — 0 25 mA
= =
High-level input current f VGG MAX Vl 24V 25 fyA

Maximum input current VCC MAX Vl 55V mA

10HB, 12H6, 14H4 Ml L
VCC = MIN 16H2, 16C I, IOLB BmA
Low-level output voltage 12L6, 14L4, 16L2 COM
VOL VIL — 0 BV 05
1 6LB 16R B I pL — 12mA
= 2V
VIH 1 6R6 16R 4
1 6X4 16A 4 COM IOL — 24mA

V CC — MI N MIL lpH = -2 m A

VOH High-level output voltage VIL — 0 BV 24

2V COM I pH — 3 2mA
VIH

VCC MAX 1 6LB 16R B Vp — 0 4V — 100

IOZL fyA
= OBV
Off-state output current f VIL 1 6R6 16R 4
2V Vp = 24V 100
IOZH VIH 1 6X4 16A 4 fyA

Output short-circuit current s * = 5V Vp = OV —30 —130

IOS VCC mA

IOHB, 12H6, 14H4, 16H2, 16C1

55 90
IOLB, 12L6, 14L4, 16L2

16R4, 16R6,
COM 120 180
16RB, 16LB
ICC Supply current VCC MAX mA
16LB MIL 140 210

16R4 16R6, 16RB MIL 150 225

16X4 160 225

170 240

P n 1 , l n r l 1 1 m, ly lrr r n r xr 11 trl WV max

only m r o r r t ttrrt o o r t ort 11 n lrmc

 Page 0.109

PAL Series 20

Switching Characteristics
Over Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER TEST CONDITIONS UN I T,
MIN TYP M A X M IN TYP MA X
I
10HB 12H6 14H4
Input to 16H2 IOLB 12L6 25 45 25 35 ri s
IPO 14L4 16L2 R2 I Iki i
output
16C1 25 45 25 40
T
'PO Input Or feedbaCk tn Output 25 45 25 35 ns
tCLK Clock to output nr feedback 15 25 15 25 ns
'pzx Pin 11 to output I nable 15 25 15 25 ns
'pxz Pin 11 to output disable 15 25 15 25 ns
16RB 16R6 16114 16LB 35 ns
'pzx Input to output enat>le 25 45
16X4 16 A4
'pxz Input to output disttble 25 45 25 35 ns
I
T Lovv 25 25
l'> irttn Ol
R, 200 I i 1-
clocl Hig ri 25
R2 390i> l 25
Setup time 16RB 16R6 16R4 45 35
from input ns
SU 16X4 16 A4 55 4.>
or feedback
IH Hold time 0 — 15 0 ns
Maximum 16RB 16R6 16R4 14 16
IMAx MHz
liequency 16X4 16 A4 12

Test Load
5V
A vailable Program m e r s
PERSONALITY SOCKET ADAPTER
MANUFACTURER
OUTPUT TEST POINT CARD SET CONFIGURATION
Cybernetic CYMPC 1
5I>PF
Proqramming
Systems Inc
909-1427 715 1428-1
715 1428-2
715 1428-3
Schematic of Inputs and Outputs
Pro-Log Corporation P M9068
EQUIVALENT INPUT TYPICAL OUTPUT AM10HB A M 1 0 LB
Stag Systems PM202
AM12H6 A t 1 l2LO
El N OM '5 NOVI
A M14H" A M '4L4
A M16H2 A M 16L2
AM16C1
S tiilc t u ie d p e • q n SD20>24
1

T ,OU T I U T
Page 0.110

PAL Series 20

Programming
PAL fuses are programmed using a low-voltage linear-select
procedure which is common to all 15 PAL types The array is
divided into two groups, products 0 thru 31 and products 32 thru
63, for which pin identifications are shown in Pin Configurations
below To program a particular fuse, both an input line and a
product line are selected according to the following procedure
Step 5 Program the fuse by pulsing the output pins, 0. of the
selected productgrouptoVIMM as shown in Program-
ming Waveform.
Step 6 Lower VCC (pin 20) to 6.0 V
Step 7 Pulse the CLOCK pin and verify the output pin. 0, to be
Low for active Low PAL types or High for active High
PAL types.

Step 8 Lower VCC (pin 20) to 4 5 V and repeat step 7.

Step 1 Raise Output Disable, OD, to VIMM
Step 9 Should the output not venfy, repeat steps 1 thru 8 up to
Step 2 Select an input line by specifying lp, I1, 12, 13, l4, 15, 16, 17 five (5) times.
and L/R as shown in Table 1.
This procedure is repeated for all fuses to be blown (see
Programming Waveforms).
Step 3 Select a product line by specifying Ap, A1 and A2 one of-
eight select as shown in Table 2. To prevent further verification, two last fuses may be blown by
raising pin1andpin11toVP.VCC is not required dunng this
Step 4 Raise VCC (pin 20) to VIHH operation.

L = Low-level input voltage, VIL = High-level program voltage, VIHH

Voltage Legend HH
H = High-level input voltage, VIM Z = High impedance (e.g, tpkf) to 5.0V)

INPUT PIN IDENTIFICATION PRODUCT PIN IDENTIFICATION

LINE LINE
NUMBER 15 14 13 12 , 11 Ip L/R NUMBER 03 02 01 00 A2 A1 Ap

HH HH HH HH HH HH HH L 0 32 Z Z HH Z
01 Z Z
HH HH MH HH HH HH HH 1 33 Z Z ZZ MH HH
H
L Z
HH HH HH HH HH HH HH HH Z Z HH I-IH Z
23
HH HH HH HH HH HH HH H HH 3. 35 Z Z HH HH HH
HH HH HH HH HH HH L HH 4, 36 Z Z Z HH HH Z Z
Z
HH HH HH HH HH HH HH 5. 37 Z Z HH HH Z HH
67
5
4 H
L
HH HH HH HH HH HH HH HH 6, 38 Z Z HH HH HH Z
HH HH HH HH HH HH H 7. 39 Z HH
HH HH Z Z HH HH HH
8 HH HH HH HH HH L HH HH 8, 40 Z Z HH Z Z
Z Z
9 HH HH HH HH HH HH HH 9 4 1
Z Z HH Z Z HH
L
H
10 HH HH HH HH HH HH HH HH 10. 42 Z Z HH HH Z
11 HH HH HH HH MH H HH HH HH 11, 43 Z Z HH Z HH HH
12 HH HH HH HH L HH HM 12, 44 Z
HH Z Z HH HH Z
Z Z
13 HH HH HH HH HH HH HH 13. 45 Z Z HH HH HH
L
H
14 HH HH HH HH HH HH HH HH 14. 46 Z Z HH HH HH Z
15 HH HH HH HH H HH HH HH HH 15, 47 Z HH HH HH HH
16 HH HH HH L HH HH HH HH Z 16. 48 HH Z Z Z
17 17, 49 Z HH
HH HH HH HH HH HHHH Z HH Z Z
H
L
18 HH HH HH HH HH HHHH HH 18. 50 HH HH Z
19 HH HH HH H HH HH HHHH HH 19, 51 Z HH Z HH HH
20 HH HH L HH HH HH HHHH Z 20, 52 Z , HH Z ZZ HH Z
Z
21 HH HH HH HH HH HH HH Z 21, 53 Z HH HH HH
L
H
22 HH HH HH HH HH HH HH HH 22. 54 HH HH HH Z
I-I Z
23 HH HH HH HH HH HH HH HH 23, 55 HH HH HH HH
24 HH L HH HH HH HH HH HH 24, 56 HH ZZ Z Z
Z Z Z
25 HH HH HH HH HH HH HH 25. 57 HH Z HH
HL ZZ
26 HH HH HH HH HH HH HH HH 26. 58 HH HH Z
27 HH H HH Z
HH HH HH HH HH HH 27. 59 HH HH HH
28 L H H HH HH HH HH HH HH 28. 60 HH Z HH Z Z
Z
29 H H H HH HH HH HH HH HH 29. 61 HH HH Z HH
30 L H H HH HH HH HH 30. 62 Z
HH HH HH HH HH HH Z
31 H H H HH MH HH HH HH 31. 63 Z ZZ
HH HH HH MH MM MH
Table 1 Input Line Select Table 2 Product Line Select
 page 0.111

PAL Series 20

DUCTS 0 THRU 31 PRODUCTS 32 THRU 63 '

Pin Configurations
OO "cc C, OCK )CC

0) Ap

02 A)

A2

Ap Op

Al 0

A2

GNO CLOCK ONO OO

P rogramm ing Pa ra m e t er s TA 25 c
LIMITS
SYMBOL PARAMETER UNIT
M IN T YP MAX
V I HH Program-level input voltage 11 11 5 12
Outpu'. Program Pulse 50
I lff H Program-level input current OD. LI'R 25 n1A

All Other Inputs

'CCH Program Supply Currer ', /nA

Program Pulse Width 10 50 /IS

tD Delay time 100 )16

DV Delay Time to Verify 100 );S

Program Pulse duty cycle 25 ')/0

Vp Verify-Protect-input voltage 20 21 22
lp Verify-Protect-input cr/rrent 400 mA
Venfy-Protect Pulse Width 20 50 nl sec

P rogramming W a v e f o rm s
V I HH

oo
VIL
IO
V IHH +
I. L/R A

VIHH

vcc
6.0V
5 OV
io iov
4. SV
V I HH VERIFY
VOH

VOL
VERIFY

CLOCK
IO IO Io Ip
Page D.112

PAL Series 20

Logic Diagram PAL16LS

INPUTS (0-31)
0 I 2 I 4 5 6 I 8 9 10 11 12 13 1 4 1 5 1 6 1 7 1819 2 0 2 1 22 73 2 4 2 5 26 21 2 8 2 '130)I

9
8
10

12
lj
14
15

16
17
18
79 17
20
21
22
7)

Z4
25
26
27
78
29 0
3I

32
33
34
35 15
36
37
78
39

40
41
42
4)
44
45
46
47

48
49
50
51 13
52
51
54
55

56
57
58
59
40
61
62
63

0 I 2 I 4 I I I 8 9 10 11 12 1 3 1 4 1 5 1 6 1 7 IS 19 2 0 2 1 27 71 2 4 2 5 Z6 27 2 8 2 9 30 31
 page D.113

PAL Series 20

Logic Diagram PAL12HS

INPUTS (0-31)
0 I 2 3 4 ' 6 I 8 9 12 13 16 11 2021 2 4292621 2 87 9 1 0 31

32
31

40
41

48
49
60

0 I I ' 6 I 8 'I II IJ I t, I l 7077 74 76 76 I

Page 0.114

PAL Series 20

Logic Diagram PAL16L2

INPUTS (0-31)
0 I 2 3 4 9 6 I 8 9 IO I I 12 13 1 4 1 6 16 1 1 18 19 2 0 2 1 77 71 2 4 2 6 2 62 7 28 2 9 3 0 3 1

19

38

17

24
29
I 26
ID 21 36
28
CO 29
30
31
K
QJ 6
I-
I- 32
33
0 34
36 35
36
31
0IZ 38
tL

14

13

12

0 I Z 3 4 66 I 8 9 10 11 12 13 1 4 1 9 16 1 7 1 8 1' I 2 02 1 7 2 2 1 7 2 92 6 2 7 28 2 9 1 0 3 1
 page D.115

PAL Series 20

Logic Diagram PAL14L4

INPUTS (0-31)
0 I 7 3 I ) b I 8 'I lb l l 17 13 16 11 2021 ZZ 23 2 4 2 ) 2 6 71 28 2 ' 13011

IS

17

24
2)
76
21

40
41 14
42
-' I

0 I 7 3 4 ) b I 8 9 10 1 1 17 1 3 202177Z) 7 4 7 ) 7 6 7 1 76 7 9 1031
Page D.116

4rn27S20 • Am27S21
1024-Bit Generic Series Bipolar PROM

DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION

• High Speed — 45ns max commercial range access time
• Excellent performance over full MIL and commercial ranges
• Highly reliable, ultra-fast programming Platinum-Silicide
fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures.
The Am27S20 and Am27S21 are high speed electrically pro-
grammable Schottky read only memories. Organized in the
industry standard 256 x 4 configuration, they are available in
both open collector Am27S20 and three-state Am27S21 out-
put versions. After programming, stored information is read on
outputs Oti — Oa by applying unique binary addresses to
Ao — A2 and holding Ihe chip select inputs, CSS and CE2, at a
logic LOW. If either chip select input goes to a logic HIGH,
Oo — 03 go to the off or high impedance state.
BLOCK DIAGRAM

GENERIC SERIES CHARACTERISTICS

The Am27S20 and Am27S21 are members ofan Advanced 32 • 32
FUSE ARRAY
104 34
PROM series incorporating common electrical characteristics ROW
DECODER
and programming procedures. All parts in this series are pro-
duced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logic
HIGH by applying appropriate voltages to the circuit, TEST WORD I

All parts are fabricated with AMD's fast programming highly

reliable Platinum-Silicide Fuse technology. Utilizing easily im-
plemented programming (and common programming personal- I OF •
ity card sets) these products can be rapidly programmed to COLUMN OUAO I OF 4 MULTIPLEXER
OECODEFI
any customized pattern. Extra test words are pre-programmed
during manufacturing to insure extremely high field program-
ming yields, and produce excellent parametric correlation. CS,
CSz
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large non-
conductive gaps that ensure very stable long term reliabilty. 04 0 OZ 0I 8PM.027
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible link LOGIC SYMBOL
PROMs.
Common design features include active loading of all critical Ap
AI
AC paths regulated by a built-in temperature and voltage A

compensated bias network to provide excellent parametri A3

A4 A 27820 A 27621
performance over MIL supply and temperature ranges. Selec- As 266 X 4 PROM
46
tive feedback techniques have been employed to minimize de- 7
lays through all critical paths producing the fastest speeds
Cs C. DI 37
possible from Schottky processed PROMs.
= Pin 16
VCC
GNO — Pin 8 12 11 10 9
ORDERING INFORMATION BPM-028

Package Temperature Order CONNECTION DIAGRAM

Type Range Number Top View
Open Collectors A7 CS2 Csi op Ql 02 03
VCC
Hermetic DIP O'C to +75'C AM27S 2 0DC
Hermetic DIP — 55'C to +125'C AM27S20DM
16 16 14 13 12 11 IP 9

Hermetic Flat Pak — 55'C to +125'C AM27S20FM

Three-State Outputs
3 4 8 6 I 8
Hermetic DIP O'C to +75'C AM27S 2 1DC
Hermetic DIP — 55'C to +125'C AM27S21DM AS A A4 A3 Ap Ai A 2 CN D

Hermetic Flat Pak — 55'C to +125'C AM27S21FM

Note. Pin 1 is marked for orientation,
BPM.029
 page 0.117

Am27S20 • Am27S21
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature — 65'C to +150 C
Temperature (Ambient) Under Bias — 55'C to +125'C
Supply Voltage to Ground Potential (Pin 16 to Pin 6) Continuous -O.SV to +7.0V
DC Voltage Applied to Outputs (Except During Programming) — 0.5V to +Vcc max.
DC Voltage Applied to Outputs During Programming 21V
Output Current into Outputs During Programming (Max. Duration of 1 sec.) 200mA
DC Input Voltage — O.SV to +5.5V
DC Input Current — 30mA to +5mA

OPERATING RANGE
COM'L Am27S 2 0XC, Am27S21XC TA = O'C to +75'C Vcc = 5.0V 45%
MIL Am27S20XM, Am27S21XM TA = — 55'C to +125'C VCC = 5.0V ~10%

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)

PRE L I MI NA R Y DATA
Typ.
Parameters Description Test Conditions Min . (Note I ) MaX. Units

VOH V CC — MIN., Ip H = — 2.0mA

Ou tpu t H I G H Vo I t age 2.4 Volts
(Am27S21 only) VIN = VIH or V I L
VCC = MIN., I p L = 16mA
VOL Output LOW Voltage 0.45 Volts
VIN = VIH or V I L
Guaranteed input logical HIGH
Input HIGH Level 2.0 Volts
voltage for all inputs
Guaranteed input logical LOW
VIL Input LOW Level 0.8 Volts
voltage for all inputs
Input LOW Current VCC = MAX „ V IN = 0 , 4 5 V -0.010 — 0. 250 mA
IIH Input HIGH Current VCC — MAX., VIN = 2.7V 25 It A
Input HIGH Current VCC = MA X . , V I N = 5.5V 1.0 mA

'sc O utput S h or t C i r c u i t Current VCC — MAX., VOUT — O.OV (Note 2( -20 -40 — 90 mA
(Am27S21 only) ,

All inputs — GNP

ICC Power Supply Current 95 130 mA
VCC — MAX.
Input Clamp Voltage VCC MIN„ II N - — 18mA — 1.2 Volts
Vp = 4.5V 40
Output Leakage Current VCC = M A X .
ICEX ' A m27S2 1 0 =24 40 It A
VCSI - 2.4V only Vp = 0.4 V -40
GIN Input Capacitance VIN — 2 OV Ca f = I MHz ( N ote 3)
CouT Output Capacitance 2,0V ta f = I MHz (Note 31
pF
VOUT

Note 1. T y P i c a l l i m i t s ar e a t V C C . 5 . 0 V a n d T A = 2 5 C
2 . Not m o r e t h a n o n e o u t p u t s h o u l d b e s h o r t e d a t a t i m e . D u r a t i on of t h e s h o r t c i r c u i t s h o u l d n o t b e m o r e t h a n o n e s e c o n d .
3. These parameters are not 1 0 0 % t e sted, bu t are p eriodica lly sampled,
page 0.118

SWITCHING CHARACTERISTICS OVER OPERATING RANGE Am27S20 • Am27S21

PRELIMINARY DATA
Typ Max
SV
Parameter DescriPtion Test Conditions 25'C COM'L MIL Units
IAA Address Access Time 25 45 60 ns
AC Test Load
IEA Enable Access Time 15 20 30 ns
ISee Notes 1-3)
tER Enable Recovery Time 15 20 30 ns

Notes: 1. tAA iS teSted with switch SI Closed and CL= 30pF.

2. For open collector outputs, tEA and tER are tested with St Closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA is tested with CL -— 30pF to the 1.5V level; SI is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = SPF. HIGH to high impedance tests are made with SI Open tO an OutPut voltage of VOH
— 0.5V; LOW to high impedance tests are made with SI dosed to the VDL + 0.5V level,

S WITCHING WAVEFOR M S

3.OV

Ap-Ap I.SV

ov

CS1-CS2 1.SV

ov
I Q
IEA
VOH
— Vo i i — O.SV
OP-03 I.SV
voL+ osv
VOL

Note: Level on output while either CS is HIGH is determined externally.

BPM-030

KEY TO TIMING DIAGRAM

WAVEFORM INPUTS OUTPUTS WAVEFORM INPUTS OUTPUTS

DON'T CARE; CHANGING;

MUST BE WILL BE
ANY CHANGE STATE
STEADY STEADY
PERMITTED UNKNOWN

CENTER
WILL BE DOES NOT LINE IS HIGH
MAY CHANGE
CHANGING APPLY IMPEDANCE
FROM H TO L
FROM H To L "OFF" STATE

MAY CHANGE WILL BE

CHANGING
FROM L TO H
FROM L TO H

AC TEST LOAD

SI
R1
30011

ouTpuT
R2
soon

BPM-031
 Page 0.119

Am27S20 • Am27S21

PROGRAMMING
The Am27S20 and Am27S21 aremanufactured witha conduc-
tive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the de-
vice, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS, input is at a logic HIGH. Current
is gated through the addressed fuse by raising the CS, input
from a logic HIGH to 15 volts. After 50 /ssec, the 20 volt sup-
ply is removed, the chip enabled, and the output level sensed
to determine if the link has opened. Most links will open within
50 psec. Occasionally a link will be stronger and require addi-
tional programming cycles. The recommended duration of ad-
ditional programming periods is 5 msec. If a link has not
opened after a total elapsed programming time of 400 msec,
further programming of the device should not be attempted.
Successive links are programmed in the same manner until all
desired bit locations have been programmed to the HIGH
level.
Typical current into an output during programming will be ap-
proximately 140mA until the fuse link is opened, after which
the current drops to approximately 40mA. Current into the
CS, pin when it is raised to 15 volts is typically 1.5mA,
The memories may become hot during programming dus to
the large currents being passed. Programming cycles should
not be applied to one device more than 5 seconds to avoid
heat damage. If this programming time is exceeded, all power
to the chip including Vcc should be removed for a period of 5
seconds after which programming may be resumed.
When all programming has been completed, the data content
of the memory should be verified by sequentially reading all
words. Occasionally this verification will show that an extra
undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all de-
vice pins are firmly contacting the programming socket, that
the input signal levels exhibit sufficient noise margins, and
that the programming voltages are within the specified limits.
All of these conditions must be maintained during program-
ming. AMD PROMs are thoroughly tested to minimize un-
wanted fusing; fusing extra bits is generally related to pro-
gramming equipment problems.

PROGRA M M ING PARAM ETERS

Parameter Description Min. Max. Units
Vccp VCC During Programming 5.0 5.5 Volts
V(HP Input HIGH Level During Programming 2.4 5.5 Volts
V(LP Input LOW Level During Programming 0.0 0.45 Volts
Vcsp CS, Voltage During Programming 14.5 15.5 Volts
Vop Output Voltage During Programming 19.5 20.5 Volts
VONp Voltage on Outputs Not to be Programmed Vccp+0.3 Volts
loNr Current into Outputs Not lo be Programmed 20 mA
d(vop)/dt Rate of Output Voltage Change 20 250 V/rssec
d(vcs)/dt Rate of CST, Voltage Change 100 1000 V/(ssec
Programming Period — First Attempt 50 100 (Lsec
tp
Programming Period — Subsequent Attempts 5.0 15 msec
Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints,
2, Delays ti, tz, (3 and t4 must be greater than 100 ns; maximum delays of 1 Msec are recommended to minimize heating during
programming.
3. During t„, a user defined penod, the output being programmed is switched to the load R and read to determine it additional pulses
are required.
4. Outputs not being programmed are connected to VoNp through resister R which provides output current limiting.

PROGRAMMING WAVEFORMS SIMPLIFIED PROGRAMMING DIAGRAM

ADDRESS YCCv Yonv

INPUTS SELECTED ADDRESS STABLE
R IP P ,
Op
"csv
4 Ap A ,
41(Yes(
CSI
ENABLE
YI Hv
Anvzzszs
Yfpv CSz OR
22 In Iv AP 22S1I

"ov CS,
02
PROORAMISED
OUTPUT 4
41 (Yoni "OH
OUTPUT
S 2ER IF Y
YOL
PROORAIIMINO CYCLE Ycs Jl

BPM-032 BPM.033
Page 0.120

Am27S20 • Am27S21

PROGRA M M ING EQUIPMENT

Generic programming boards and device adapters are avail- pro g r ammers to program all AMD generic series bipolar
able from the sources listed below. In each case, the pro- PRO M s ; individual adapters are required for each basic part
gramming boards are used in these manufacturer's automatic ty p e in the series.
SOURCE AND LOCATION Data IIO COrp Pro-Log Corp
P.O. Box 308 2411 Garden Road
Issaquah, Wash. 98027 Monterey, Ca 93940
PROGRAMMER MODEL(S) Model 5, 7 and 9 M900 and M920
AMD GENERIC BIPOLAR 909-1286-1 PM9058
PROM PERSONALITY BOARD
Am27S20 • Am27521 715-1408-1 PA16-5 and 256 x 4 (L)
ADAPTERS AND
CONFIGURATOR

OBTAINING PROGRAM MED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can
be delivered with your order or may be transmitted over a
TWX machine or time-sharing terminal. ASCII BPNF is our
preferred paper tape format.
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

ASCII BPNF
An example of an ASCII tape in the BPNF format is shown 3. A trailer of at least 25 rubouts.
below. Theycan be punched on any Teletypes or on a TWX A P is a HIGH logic level — 2.4 volts.
or Telex machine. The format chosen provides relatively good An N is a LOW logic level = 0.4 volts.
error detection. Paper tapes must consist of:
1. A leader of at least 25 rubouts.
A convenient pattern to use for the data words is to prefix the
2. The data patterns for all 256 words, starting with word 0, in
word (or every few words with the word number, then type the
the following format
data word, then a comment, then carriage return and line feed
a. Any characters, including carnage return and line feed,
as shown below. There must be no characters between the B
except "B".
and the F except for the four Ps and Ns. If an error is made in
b. The letter "B", indicating the beginning of the data
a word, the entire word must be cancelled with rubouts back
word.
c. A sequence of four Ps or Ns, starting with output 03. to the letter B, then the word re-typed beginning with the B.
d. The letter "F", indicating the finish of the data word.
e. Any text, including carriage return and line feed, except When TWXing your tape, be sure the tape is in even parity.
the letter "B". Parity is not necessary if the tape is mailed.

TYPICAL PAPER TAPE FORMAT RESULTING DEVICE TRUTH TABLE (CST 8I CS2 = LOW)
A7 As A5 A4 AJ A2 Ai Ap 03 0 2 OI Op
BIVJNPF 'O'ORDZERO® Q L L L L L L L L L L L L H
B PPNILF COxXENT FIEI.D® QL L L L L L L L H H H L L
(Jkf(2 BPPPNF QI.
AIL Y R L L L L I L H L H H H L
BN!(IJIIF TEXT R +L L L L L L L H H L L L L
(J(P 4 Bfnr! I'J PF C m! R L L L L L L H L L L L L H
BPETJNF GO R L L L L L L H L H H H L L
II((J(6 BPPNNF I(ERE R QL I L H H L H H L L

255 E PPPNF E .' D® Q

L H H H H Ii H H H H H H L

ASCII PAPER TAPE

ASCII 0 ASCII
I 0'
WORO '0 WORO ' I

0 0 • 0 0 0 0 0
O O O O 0 0 0 0 0

0 0 0 0 0 0 0 * 0 0 0 0
OOO O 0 0 0 0 0 0

• P • OR 'H' • • 'P' • OR H'

OPROHAL COASREHTS MAT SE IHSERTEO HEAT

epM.034
 Page 0.121

Am27S20 • Am27S21

APPLYING THE Am27S20/21

Typical application of the Am27S20/21 is shown below. The
Am27S20/21's are employed as mapping ROMs in a micro-
program computer control unit. The eight-bit macroinstruction
from main memory is brought into the Ac r inputs of the
mapping ROM array. The instruction is mapped into a 12-bit
address space with each PROM output supplying 4 bits. The
12 bits of address are then supplied to the "D" inputs of the
Am2910 as a possible next address source for microprogram
memory. The MAP output of the Am2910 is connected to the
CS, input of the Am27S20/21 such that when the CS, input is
HIGH, the outputs of the PROMs are either HIGH in the case
of the Am27S20 or m the three-state mode in the case of the
Am27S21. In both cases the CSs input is grounded, thus data
from other sources are free to drive the D inputs of the
Am2910 when MAP is HIGH.

OTNER DATA INPUTS

AI

Az
MACRO AS Op
INSTRUCTION
OF CODE A< A 27520
OR
A 27521 O z

03
Az

Dp

Al Dz
Az
AS Op D4 A 2910
A< A 27520 OI DE 12 MICROPROORAM
OR Yo — 11 MEMORY
AE A 2 7S 2 1 DS ADDRESS
AS 03 Dz
AT
OS
CSI Dp

010

DI I

MAP

Al

A2
Az Op
A• A 2752 0 OI
OR
A 27521 OZ

AT

CSI
CS2

MICROPROGRAMMING INSTRUCTION MAPPING

BPM-035

PHYSICAL DIMENSIONS
Duahln-Line
16-Pin Ceramic 16-Pin Flat Package
0 975
0 99'
0 245 0 335 0 245
0 255 0 310

• I 7

0 050 0 015
00 0 0 OT9 0 310
0 425

0 130 0 145
0 200 0 1115
9 9
0 015
) so 5(A" NG 0 045
4 :A 5 0 055 ~ 0 290 ~ 00<5
O<A
0 009 0 335
03771
4
0 015
0 ilo 0 020
Page D.122

Am27S1 8 • Am27S1 9
256-Bit Generic Series Bipolar PROM

DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION

• High Speed — 40ns max commercial range access time
• Excellent performance over full MIL and commercial ranges
• Highly reliable, ultra-fast programming Platinum-Silicide
fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures.
The Am27S18 and Am27S19 are high speed electrically pro-
grammable Schottky read only memories. Organized in the
industry standard 32 x 8 configuration, they are available in
both open collector Am27S18 and three-state Am27S19 out-
put versions. After programming, stored information is read on
outputs Oti — 0, by applying unique binary addresses to
Ap A4 and holding the chip select 14Put, CS, at a l ogic LOW.
lf the chip select input goes to a logic HIGH, 00-0, go to the
off or high impedance state

GENERIC SERIES CHARACTERISTICS BLOCK DIAGRAM

The Am27S18 and Am27S19 are members ofan Advanced
Ap
PROM series incorporating common electrical characteristics
32 x 8
and programming procedures. All parts In this series are pro- Aq
1 0F 34 FUSE ARRAT
duced with a fusible link at each memory location storing a A7 ROW
A.l DECODER
logic LOW and can be selectively programmed to a logic TEST WORD 8
A4
HIGH by applying appropriate voltages to the circuit. TEST WORD I

All parts are fabricated with AMD's fast programming highly

reliable Platinum-Silicide Fuse technology. Utilizing easily im- CS

plemented programming (and common programming personal-

ity card sets) these products can be rapidly programmed to
any customized pattern. Extra test words are pre-programmed
during manufacturing to insure extremely high field program-
ming yields, and produce excellent parametric correlation. Op 0, 02 03 04 01 06 07

Platinum-Silicide was selected as the fuse link material to BPM-018

achieve a well controlled melt rate resulting in large non-

conductive gaps that ensure very stable long term reliabilty. LOGIC SYMBOL
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible link
Ap
PROMs. Al

Common design features include active loading of all critical A2

Am2/S18/Am2/S19
AS 32 X 8 PROM
AC paths regulated by a built-in temperature and voltage A4
compensated bias network to provide excellent parametric
CS Op 01 0 2 0 3 0 4 0 5 08 0 7
performance over MIL supply and temperature ranges. Selec-
tive feedback techniques have been employed to minimize de-
lays through all critical paths producing the fastest speeds = Pin 16 1 2 3 • 5 6 7 9
Vcc
possible from Schottky processed PROMs. GND .- Pin 6
BPM-019

ORDERING INFORMATION CONNECTION DIAGRAM

Top View
Package Temperature Order
Type Range Number
VCC CS A4 A3 A2 Al Ap 07
Open Collectors
16 15 14 13 12 11 10 9
Hermetic DIP O'C to +75'C A M2 7S 1 8DC
Hermetic DIP — 55'C to + 125'C AM27S18DM
Hermetic Flat Pak — 55'C to +125'C AM27S18FM
1 2 3 4 5 6 7 8
Three-State Outputs
Hermetic DIP O'C to +75'C AM2 7S 1 9DC Op O l 02 03 04 05 08 GN D
Hermetic DIP — 55*C to +125'C AM27S19DM
Hermetic Flat Pak — 55'C to +125'C AM27S19FM
Note Pin 1 is marked for orientation.
BPM-020
 page D.123

Am27S18 • Am27S19
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature — 65'C to +150'C
Temperature (Ambient) Under Bias — 55'C to + 125'C
Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous — 0.5V to +7.0V
DC Voltage Applied to Outputs (Except During Programming) — 0.5V to + Vcc max.
DC Voltage Applied to Outputs During Programming 21V
Output Current into Outputs During Programming (Max. Duration of 1 sec.) 200mA
DC Input Voltage -0.5V to +5.5V
DC Input Current — 30mA to. +SmA

OPERATING RANGE
COM'L Am27S18XC, Am27S19XC TA = O'C to +75'C VCC = 5.0V ~5%
MIL Am27S18XM, Am27S19XM TA = -5 5 0 to + 1 25' C V CC = 5.0V I e%%uo

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)

PR E L I MI NAR Y DATA
TVP.
Parameters Description Test Conditions Min. (Not e I I M ax. Un it s

VOH VCC = MfN., I p H = — 2.0mA

Output HIGH Vo ltage 2.4 Volts
(Am27 LS19 only) VIN = VIH or V I L

VCC = MIN., I p L = 18mA

VOL Output LOW Voltage 0.45 Volts
VIN VIH or VI L
Guaranteed input logical HIGH
Input HIGH Level 2.0 Volts
voltage for all inputs
Guaranteed input logical LPW
Input LOW Level 0.8 Volts
voltage for all inputs
IIL Input LOW Current VCC = MA X . , V I N = 0.45V — 0.010 — 0.250 mA
IIH Input HIGH Current V CC ™ A X , V I N = 2.7V 25 IrA
= 5.5V
Input HIGH Current VCC = MA X . , V I N 10 mA

ISO Output Short C i r c uit C u r rent VCC = MAX,, V p ( J T = O.OV INote 2) — 20 — 40 — 90 mA

(Am27LS19 only l
A ll input s = GND
ICC Power Supply Current 90 mA
VCC = MA X .
Input Clamp Voltage VCC MIN., I IN = — 18rnA —12 Vo Its
Vp = 4.5V 40
Output Leakage Current VCC = M A X .
ICEX Am27LS19 Vp = 24V 40 IiA
VCS = 2.4V
only Vp 0,4V — 40

C IN Input Capacitance VIN = 2.0V Le f = I MHz (Note 3)

= pF
CouT Output Capacitance VOLIT 2,0V La f 1 MHz (Note 3)

Notes: I T y P i cal limits are at VCC= S.OV and TA = 25'C .

2. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
3. These parameters are not 100%, tested, but periodically sampled.
Page 0.124

Am27S18 • Am27S19
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PRELIMINARY DATA
Typ Max
5V
Parameter Description Test Conditions 25'C COM'L MIL Units
1AA Address Access Time 25 40 50 ns
AC Test Load 30 ns
tEA Enable Access Time 15 25
(See Notes 1-3)
tER Enable Recovery Time 15 25 30 ns

Notes: 1. tAA is tested with swrtCh St Closed and CL = 30pF.

2. For open collector outputs, tEA and tER are tested with SI Closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA iS teSted with CL = 30pF to the 1.5V level; SI iS Open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = SpF. HIGH to high impedance tests are made with SI open to an output voltage of VDH
— 0.5V; LOW to high impedance tests are made with SI Closed to the VDL + 0.5V level.

S WITCHING WAVEFORM S
3.0V

1.5V

0V

1.5V

Ov

— Vp r 1— 0.5V
I IEA + VOH

OIror I Sv
VOL+ 0 5 V
VOL

Note: Level on output while CS is HIGH is determinedexternally.

BPM 02!

KEY TO TIMING DIAGRAM

WAVEFORM INPUTS OUTPUTS WAVEFORM INPUTS OUTPUTS

DON'T CARE; CHANGING,

MUST BE WILL BE
ANY CHANGE STATE
STEADY STEADY
PER MITT ED UNKNOWN

CENTER
WILL BE DOES NOT LINE IS HIGH
MAY CHANGE
CHANGING APPLY IMPEDANCE
FROM H TO L
FROM H TO L "OFF" STATE

WILL BE
MAY CHANGE
CHANGING
FROM L TO H

AC TEST LOAD

SI
R1
300! I

OUTPUT

CL R2

I
BPM.022
 page D.125

Am27S18 • Am27S19

PROGRAMMING
The Am27SI8 and Am27S19 are manufactured with a conduc-
tive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the de-
vice, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS input is at a logic HIGH. Current
is gated through the addressed fuse by raising the CS input
from a logic HIGH to 15 volts. After 50 /ASec, the 20 volt sup-
ply is removed, the chip enabled, and the output level sensed
to determine if the link has opened. Most links will open within
50 /Asec. Occasionally a link will be stronger and require addi-
tional programming cycles. The recommended duration of ad-
ditional programming periods is 5 msec. If a link has not
opened after a total elapsed programming time of 400 msec,
further programming of the device should not be attempted.
Successive links are programmed in the same manner until all
desired bit locations have been programmed to the HIGH
level.
Typical current into an output during programming will be ap-
proximately 140mA until the fuse link is opened, after which
the current drops to approximately 40mA. Current into the CS
pin when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to
the large currents being passed. Programming cycles should
not be applied to one device more than 5 seconds to avoid
heat damage. If this programming time is exceeded, all power
to the chip including Vcc should be removed for a period of 5
seconds after which programming may be resumed.
When all programming has been completed, the data content
of the memory should be verified by sequentially reading all
words. Occasionally this verification will show that an extra
undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all de-
vice pins are firmly contacting the programming socket, that
the input signal levels exhibit sufficient noise margins, and
that the programming voltages are within the specified limits.
All of these conditions must be maintained during program-
ming. AMD PROMs are thoroughly tested to minimize un-
wanted fusing; fusing extra bits is generally related to pro-
gramming equipment problems.

PROGRA M M ING PARAM ETERS

Parameter Description Min. Max. Units
Vccr Vcc Dunng Programming 5.0 5.5 Volts
VIHP Input HIGH Level Dunng Programming 2.4 5.5 Volts
ViLP Input LOW Level During Programming 0.0 0.45 Volts
Vcsp CS Voltage During Programming 14.5 15.5 Volts
Vor Output Voltage During Programming 19.5 20. 5 Volts
VONp Voltage on Outputs Not to be Programmed Vccp+0 0 Volts
IONP Current into Outputs Not to be Programmed 20 mA
d(Vop)/dt Rate of Output Voltage Change 20 250 V/Msec
d(Vcs)/dt Rate of CS Voltage Change 100 1000 V/Asec
Programming Period — First Attempt 50 100 Msec
tp
Programming Period — Subsequent Attempts 5.0 15 msec
Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
2. Delays ti, tz, ta and t4 muSt be greater than 100 ns; maximum delays of 1 /Aaec are reCOmmended to minimize heating during
programming.
3. During t„, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses
are required.
4. OutPutS nat being PrOgrammed are COnneCted tO Vonp thrOugh reSiStOr R WhiCh PrOVideS OutPut Current limiting.

PROGRAMMING WAVEFORMS SIMPLIFIED PROGRAMMING DIAGRAM

Yror YONP

YOIP R 3 00ll
AOO RESS SELECTEO AOORESS STABLE
INPUTS Op

Ap Ar
"CSP
4
Ei iYCSi
CS
ENABLE Am2TSIS
YIHP
OR
YRP Am27919
II IZ lr ty
CS
Yor Or

PROORAIIMEO
OUTPUT 4
BI ivor i "ON
OUTPUT
Y
S YERIF~
"OI
PROORAMMINO CYCLE
YCSP o.

BPM 023 BPM 024

Page 0.126

Am27S18 • Am27S19

PROGRAMM ING EQUIPMENT

Genenc programming boards and device adapters are avail- programmers to program all AMD generic senes bipolar
able from the sources listed below. In each case, the pro- PROMs; individual adapters are required for each basic part
gramming boards are used in these manufacturer's automatic type in the series.

SOURCE AND LOCATION Data I/O Corp Pro-Lo9 Corp

P 0 Box 308 2411 Garden Road
Issaquah, Wash 98027 Monterey, Ca 93940
PROGRAM M E R MO DEL(S) Model 5, 7 and 9 M900 and M920
AMD GENERIC BIPOLAR 909 1286-1 PM9058
PROM PERSONALITY BOARD
Am27S18 • Am27S19 715-1407-1 PA16-6 and 32 x 8 (L)
ADAPTERS AND
CONF IGURATOR

OBTAINING PROGRAM M E D UNITS

Programmed dewces may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can
be delivered with your order or may be transmitted over a
TWX machine or time-sharing terminal. ASCII BPNF is our
preferred paper tape format.
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distnbutor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

ASCII BPNF
An example of an ASCII tape in the BPNF format is shown
below. They can be punched on any Teletypes oron a TWX
or Telex machine. The format chosen prowdes relatively good
error detection. Paper tapes must consist of:
t. A leader of at least 25 rubouts.
2. The data patterns for all 32 words, starting with word 0, in the
following format:
a. Any characters, including carnage return and kne feed,
except "B".
b. The letter "B", indicating the beginning of the data
word.
c. A sequence of eight Ps or Ns, starling with output 07.
d. The letter "F", indicating the finish of the data word.
e. Any text, including carriage return and line feed, except
the letter "B".
3. A trailer of at least 25 rubouts.
A P is a HIGH logic level = 2.4 volts.
An N is a LOW logic level = 0.4 volts.
A convenient pattern to use for the data words is to prefix the
word (or every few words with the word number, then type the
data word, then a comment, then carriage return and line feed
as shown below. There must be no characters between the B
and the F except for the eight Ps and Ns. If an error is made
in a word, the entire word must be cancelled with rubouts
back to the letter B, then the word re-typed beginning with the
B.
When TWXing your tape, be sure the tape is in even parity.
Parity is not necessary if the tape is mailed.

TYPICAL PAPER TAPE FORMAT RESULTING DEVICE TRUTH TABLE (CS = LOW)
BPNPPNNNPF WORD ZERO® QL AA AS At AI AP Or O s Os OA Os 02 OI Op
BPPPPPPNNF C O M MENT FIELD QR QL
f)y)2 B i i NNPPPPNI' A N Y R L L L L L L H L H H L L L H
BNNNNtINNTIF' TEXY R L L L L L H H H H H H H L L
y )II 4 B PNNtINiVN PF C ILV R L L L L H L L L L H H H H L
B iIPPNPPNNF GO R L
L L L H H L L L L L L L L
IIII)6 B P NNPPPNNF MERE R QL L L H L L H L L L L L L H

f )31 B N NN;IPPPNF E N DQR QL L L H L H L H H L H H L L

L L H H L H L L H H H L L
R = CARRIAGE RETURN
L — LINE FEED H H H H H L L L L H H H L

ASCII PAPER TAPE

ASCII S' ASCII 'e' 'F'
'F'
LEADER WORD '0' WORD I ' CR TRAILER

O O O O O OO O 0 0
O O O O 0 op 0 0

o pp o o op o p 0 op
o o oo p o op o o

S P' • OR N' • S P' • OR N' • LF

OPTIONAL COMM E NTS MAT SE INSERTED HERE epM-D26

 page 0.127

Am27S18 • Am27S19

APPLYING THE Am27S18 AND Am27S19

The Am27S18 and Am27S19 PROMs may be used as code
converters. Examples include conversion of hexadecimal,
octal or BCD to seven segment display drive format. In many
code conversion applications an extra PROM address input is
available and may be used as a polarity control, blanking con-
trol or code selector input. The use of a single Am27S18 or
Am27S19 to convert the outputs of a binary counter to either
excess three or gray code format is illustrated below. In this
case both codes are generated in true and complemented
form simultaneously.

TRUTH TABLE

ADDRESS COMPLEMENT TRUE

Ap A S A 2 A i AO O T 06 O s 0 4 OS 02 0 , OO
0 0 0 0 0 1 1 0 0 0 0 1 1
Am26LS2669 0 0 0 0 1 1 0 1 1 0 1 0
4-BIT COUNTED 01
0 0 0 1 0 1 0 1 0 0 1 0
0 0 0 1 1 1 0 0 1 0 1 1 m
x
Yo- Yp 0 0 1 0 0 1 0 0 0 0 1 1 m
O
0 0 1 0 1 0 1 1 1 1 0 0 0 CD
CODE SELECT CD
INPUT 0 0 1 1 0 0 1 1 0 1 0 0
0 0 1 1 1 0 1 0 1 1 0 1
A4 Ao-Ap
0 1 0 0 0 0 1 0 0 1 0 1 37
z
0 1 0 0 1 0 0 1 1 1 1 0 m
0 1 0 1 0 X X X X X X X
CS Am2TS19219
0 1 0 1 1 X X X X X X X O
A
rn
O
0 1 1 0 0 X X X X X X X
0 1 1 0 1 X X X X X X X
02-04 03-Op 0 1 1 1 0 X X X X X X X
4
0 1 1 1 1 X X X X X X X
1 0 0 0 0 1 1 1 1 0 0 0
CODE COD E
1 0 0 0 1 1 1 1 0 0 0 0
1 0 0 1 0 ' 1 1 0 0 0 0 1
BPM 626
1 0 0 1 1 1 1 0 1 0 0 1
1 0 0 0 1 0 0 1 0 1 1 0
1 0 1 0 1 1 0 0 0 0 1 1 Cb
1 0 1 1 0 1 0 1 0 0 1 0 1 at
1 0 1 1 1 1 0 0 1 0 0
11
1 1 0 0 0 0 0 1 1 1 0
1 1 0 0 1 0 0 1 0 1 1 0 Ci
o
1 1 0 1 0 , 0 0 1 1 1
O
0 0 rn
1 1 0 1 1 0 0 0 1 1 1 1
1 1 1 0 0 0 1 0 1 1 0 1
1 1 1 0 1 0 1 0 0 1 0 1
1 1 1 1 0 0 1 1 0 1 0 0
1 1 1 1 1 0 1 1 1 1 0 0

PHYSICAL DIMENSIONS
Dual-In-Line
16-Pin Ceramic 16-Pin Flat Package
0 92A
0 994
0 \45 0 339 0 24'
Crli5 b 3'20 0 28'

i 8
• I I to

0 080 0 OI 9
Oajo 0 Qoo
onto t n jjo
li 4 2 8

0 130I 0 '44 0 290

0 jip 0 III9 PT26
8 9

A IA I N t j
0 048 0 290 0 INU
i I AI t
0 O'V,
0 OI24 AIAI2 0 CI88 i j 020
0 Ooii I i
• 040

0 090
9 I ill
Page 0.128

intei
2764
(8K x 8) UV ERASABLE PROM
• 200 ns (2764-2) Maximum Access a Pin Compatible to 2732A EPROM
T ime. . . H M OS*-E Technology
• Industry Standard Pinout.. . JEDEC
• Compatible to High Speed 8mHz Approved
8086-2 MPU.. . Zero WAIT State • Low Active Current...100mA Max.
• Two Line Control • ~ 1 0 / 0 Vcc Tolerance Available

The Intels 2764 is a 5V only, 65,536-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The
standard 2764 access time is 250ns with speed selection available at 200ns. The access time is compatible to high
performance microprocessors, such as intel's 8mHz 8086-2. In these systems, the 2764 allows the microprocessor to operate
without the addition of WAIT states.
An important 2764 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP-72 is available from Intel's
Literature Department.
The 2764 has a standby mode which reduces the power dissipation without increasing access time. The active current is
100mA, while the standby current is only 40mA. The standby mode is achieved by applying a TTL-high signal to the CE
input.
10% VCC tolerance is available as an alternative to the standard • 5% VCC tolerance for the 2764. This can allow the system
designer more leeway in terms of his power supply requirements and other system parameters.

The 2764 is fabricated with HMOS'-E technology, Intel's high-speed N-channel MOS Silicon Gate Technology,

2764
BLOCK DIAGRA M 2732A PIN CONFIGURATION
DATA OUTPUTS
PIN CONFIGURATION Vi 4 28 VCC
VCC o
0 0-0 2 A 12 22 PGM
GNDo Ai 24 "cc AT N C I')
VPP 0
23 AB As 25
22 As 2• Ag
OE OUTPU T ENABLE
CHIP ENABLE PH
A4 23 A
PGM AND OUTPUT SUFFERS 20 OE Vp„
WE PROG LOGIC Ag 22 OE
At 19 nip A2 A10
Y Ai 18 CE
Y GATING Ai 20 CE
DECODER
Ao A i Ap
ADDRESS Ap 19 OT
INPUTS Op 15 Oe
x Op 18 os
DECODER 65 536-6 I I 15 Oe Oi 05
CELL MATRIX
Ot 04 02 13 04
GND 13 01 GND 03

III For upgiadabiiity to JEDEC approved

326K EPRQMs, prowde anaddress lme
to pin 26. For compatibihly with the
2732A and32K ROMs, provide a trace
MOD E SELECTION from VCC to pin 26

PINS CE OE PGM Vpp Vcc Outputs

MODE (20) (22) (27) (1) (28) (11-13, 15-19)
Read Vii V,„ Vcc Vcc DG„,
PIN NAMES
Standby Vcc Vcc High Z ADDRESSES
Program Vi, V„ V.p Vcc D, CE CHIP ENABLE
Program Venfy Vi, V» Vpp Vcc Dain OE OUTPUT ENABLE
Program Inhibit Vpp Vcc High Z 0 -0 OUTPUTS
x can be either V„or V,„ PGM PROGRAM
N.C NO CONNECT
'HMOS is a patented process of Intel Corporation.
 Page 0.129

intei 2764

'COMMENT
A BSO L U T E MAX IMUM R A T INGS "
Stresses above those listed under ' Absolute Max imum Ratings may cause
Temperature Under Bias . . . . . . . . . . . — 10 C to +80 C. . .
p ermanent , i a rnage to the device T h i s i s a stress ruling only ann lunc l ii>nal
o peration o f t h e d e n c e a t t h e s e o r a n y o t h e r c o n di tions s h ov e t h o s e
Storage Temperature — 65'C to +125'C
i ndicate<t in th e o p e r a t i o na l s e r t i i >ns of t h i s s p e cifir.atio n i s n o t i m pl i < u
. .

All Input or Output Voltages with Fxposure l o a b s o l u t e m a x i rrrurr> raring c o n d i t i on s fo r < xtenned p< rrodv
+6V to — 0.6V may affect d e n c e i e l i a h i l ity
Respect to Ground
V„ S u p ply Voltage with Respect to Ground
During Programming .. . . . +22V to — 0.6V
. . .

D .C. AND A.C. OPERATING C O N D ITIONS D U R ING R E A D

2764-2 2764 2764-3 2764-4 2764-25 2764-30 2764-45
Operating Temperature 0*C-70" C 0" C —
70" C 0"C — 70 C 0 C —70"C 0" C-70 oC 0" C —
70" C 0 C — 70 C
Range
<,2 5V 5% 5V 5' / o 5V 5 /o 5V • 5 /o 5V ' 1 0'/o 5V 10o / o 5V ' 10 o /o
Vcc Power Supply '
2
Vpp Voltage VPP VPP VCC VPP VCC VPP VCC VPP VCC VPP VCC Vpp V.c

READ OPERATION

D.C. AND OPERATING CHA R A C T E RISTICS

Limits
Symbol Parameter Min Typ' Max Unit Conditions

Input Load Current 10 yA Vru = 55V

I<o Output Leakage Current 10 yA Vi>u r

I oo,' V„ C u r r ent Read mA Voe = 5 5V

icc ' V<-c Current Standby 40 mA CE — V ie

Ice>' Vc, Current Active 70 100 mA C E — OE V„

Input Low Voltage 6

V IH Input High Voltage 2.0 Vcr i 1

Voi Output Low Voltage .45 I, — 2.1 mA

Vou Output High Voltage 2.4 lo„ -

— 400 yA

A .C. CHA R A C T E R I S T I C S
2764-25 8 2764-30 Sr 2764-45 8
2764-2 Limits 2764 Limits 2764-3 Limits 2764-4 Limits
Test
Symbol Parameter Min Max Min Max Min Max Min Max Unit Conditions
' ACC Address to Output Delay 200 250 300 450 ns CE OE V <C
1 CE CE to Output Delay 200 250 300 450 ns OE Vfr
1 OE OE to Output Delay /5 100 120 150 ns CE Vii

tDF OE High to Output Float 60 85 105 130 ns CE ViL

'OR Output Hold from Addresses, ns CE O E V fr

CE or OE Whichever Occurred
First
NOTES: I V „ m ust b e a p p h ed simultaneously or before Vxo and removed simultaneously or after Vxo
2 V „ „ m a y b e c o n n e c ted d i r e c tly to V,, e x c ept d u r in g p r o g r a m m i n g . The sup ply cu r r ent w o ul d t he n be the sum of 1,, and fvv
3 Typical values are for t, — 25" C and nominal supply voltages
4 T h i s p a r ameter is only sam p led an d no t 100'/o tested
Page D. l30

iRtei 2764

CAPACITANCE TA = 25'C, f = 1MHz

Symbol Parameter Typ.' Max. Unit Conditions
GIN input Capacitance pF ViN=OV

Cour Output Capacitance 12 pF V U,=OV

A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT
1.3V

2.4 TN014
2.0 2.0

00
TEST POINTS
Q o.e DEVICE
3.3KI I

0.45 UNDER OUT

TEST
Ci 1 0 0P P
AC E S T /N G I N P UTS ARE DRIVEN AT 2 4V FOR A LOGIC I A NDS 45V FOR
A LCGiC D T / M i NG MEASUREMPNTS ARE MADE AT 2OV FOR A LQGiC
ANO O SV FOR A LOGic O
Z
CL l c o PF
CL INCLUDES JIG CAPACITANCE

A.C. WAVEFORMS

ADDRESSES
Anonrsses VALID

CE

ICE

',4I
— IOE l31 I OF

IACC
l3 IOH

HIGH 2 HIGH 2
OUTPUT VALID OUTPUT

NOTES: 1. T ypical values are for T, = 25'C and nominal supply voltages
2. This parameter is only sampled and is not 100'/P tested.
3. OE may be delayed up to t,« — t« a f ter the falling edge of CE without impact on t„«.
4, t« is specified from OE or CE, whichever occurs first
 page 0.131

2764

P ROG RAMMING
D.C. PROGRAMM ING CHARA C T ERISTICS: T„ = 25 — 5V ~5%, V„ =
5' C, V« - 2 1 V = 0 .5V (see Note 1)
Limits
Symbol Parameter Min. Typ. Max. Unit Test Conditions
iu Input Current (All Inputs) 10 fEA VIN V lc or V I H

VQ. Output Low Voltage During Verify 0.45 V IQE = 2.1 mA

Voa Output High Voltage During Verify 2.4 V 400 fEA

Y«Supply Current (Active) 100 mA

Input Low Level (All Inputs) — 0.1 0.8 V
VI H Input High Level 2.0 Vcc+1 V
VppSupply Current 30 mA C E: Vi c = P G M

A.C. PROGRAM M ING CHARA C T ERISTICS: T, = 25 5 'C, V« -

— 5V 5%, V„, = 21V =0.5V (see Note 1)
Limits
Symbol Parameter Min. Typ. Max. Unit Test Conditions'
tES Address Setup Time fES

IDES OE Setup Time

tDS Data Setup Time fES

tAH Address Hold Time

tDH Data Hold Time fES

tDF Chip Enable to Output Float Delay 130 ns

tvs VppSetup Time
tFW PGM Pulse Width During Programming 45 50 55 ms
tCES CE Setup Time
toE Data Valid from OE 150 ns

'A.C. CONDITIONS OF TEST

Input Rise and Fall Times (10% to 90 E%) . . . 20ns
. . . .

Input Pulse Levels .0.45V to 2.4V

Input Timing Reference Level . ...1V and 2V
Output Timing Reference Level . . . . . . . 0.8V and 2.0V

NOTE:
1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp
Page 0.1 32

2764

P ROGR A M M ING W A V E F O R M S

PROGRAM
PROGRAM
VERIFY

ADDRESSES ADDRESS N

V,

'2'
ol

DATA IN STABLE DATA OUT VALID

DATA ADD N ADD N
to
(0 131
l2l l2) MAX

I2I

CE
V,

I2l
V„

PGM

V„

l45i i2l
V, lo 15I
MAX

OE

I ALL TIMES SHOWN IN [ l ARE MINIMUM AND IN PSEC UNLESS OTHERWISE SPECIFIED
2. THE INPUT TIMING REFERENCE LEVEL IS IVFOR A V„AND 2V FOR A V,„.
3. L» AND I~ ARE CHARACTERISTICS OF THE DEVICE BUT MUST B E ACCOMMODATED BY THE PROGRAMMER

ERASURE CHARACTERISTICS inch of the lamp tubes during erasure. Some lamps have a
filter on their tubes which should be removed before erasure
The erasure characteristics of the 2764 are such that erasure
begins to occur when exposed to light with wavelengths DEVICE OPERATION
shorter than approximately 4000 Angstroms ()I,). It should be
noted that sunlight and certain types of fluorescent lamps The five modes of operation of the 2764 are listed in Table 1. A
have wavelengths in the 3000 — 4000 A range. Data show that single 5V power supply is required in the read mode. All
constant exposure to room level fluorescent lighting could inputs are TTL levels except for V„
erase the typical 2764 in approximately 3 years, while it would
take approximately 1 week to cause erasure when exposed to
direct sunlight. If the 2764 is to be exposed to these types of TABLE 1. MODE SELECTION
lighting conditions for extended periods of time, opaque PINS CE OE PGM VPP Vcc Outputs
labels are available from Intel which should be placed over MODE (2o) (22) (27) (1) (2II) (11-13, 15-19)
the 2764 window to prevent unintentional erasure. Read Vic Vic Viu Vcc Vcc Dour
The recommended erasure procedure for the 2764 is expo- Standby Viu Vcc Vcc High Z
sure to shortwave ultraviolet light which has a wavelength of
Program Vic Vic VPP Vcc DIN
2537 Angstroms ()I,). The integrated dose (i.e., UV intensity X
exposure time) for erasure should be a minimum of 15 Program Verify Vic Vi VIH VPP Vcc Dour
W-sec/cm'. The erasure time with this dosage is approxi-
Program Inhibit VPP Vcc High Z
mately 15 to 20 minutes using an ultraviolet lamp with 12000
IXW(cm2 power rating. The 2764 should be placed within 1 x can be either V L or V„

irttei
READ MODE
The 2764 has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip
Enable (CE) is the power control and should be used for
device selection. Output Enable (OE) is the output control
and should be used to gate data to the output pins, indepen-
dent of device selection. Assuming that addresses are stable,
address access time (tx«) is equal to the delay from CE to
output (t„). Data is available at the outputs after a delay of t„
from the falling edge of OE, assuming that CE has been low
a nd addresses have been stable for at least t„ , - t Qf.
Standby Mode
The 2764 has a standby mode which reduces the active
power current from 100mA to 40mA. The 2764 is placed in
the standby mode by applying a TTL high signal to the CE
input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
Output OR-Tieing
Because EPROMs are usually used in larger memory arrays,
Intel has provided 2 control iines which accommodate this
multiple memory connection, The two control lines allow for.
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To use these two control lines most efficiently, CE (pin 20)
sl ould be decoded and used as the primary device selecting
function, while QE (pin 22) should be made a common con-
nection to all devices in the array and connected to the READ
line from the system control bus. This assures that all de
selected memory devices are in their low power standby
mode and that the output pins are only active when data is
desired from a particular memory device.
System Consideration
The power switching characteristics of HMOS-E EPROMs
require careful decoupling of the devices. The supply cur-
rent, ICC, has three segments that are of interest to the sys-
tem designer — the standby current level, the active current
level, and the transient current peaks that are produced on
the falling and rising edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output
capacitance loading of the device. The associated transient
voltage peaks can be suppressed by complying with Intel's
Two-Line Control, as detailed in Intel's Application Note,
AP-72, and(or by properly selected decoupling capacitors. It
is recommended that a 0.1 pF ceramic capacitor be used on
every devicebetween VCC and GND. This should be a high
Page 0.1 33
2764
frequency capacitor of low inherent inductance. In addition,
a 4,7 rjF bulk electrolytic capacitor should be used between
VCC and GND for each eight devices. The bulk capacitor
should be located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to overcome
the voltage droop caused by the inductive effects of the PC
board-traces.
Programming
Caution: Exceeding 22V on pin 1 (Vpp) will damage the
2764.
Initially, and after each erasure, all bits of the 2764 are in the
"1" state. Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os" will be
programmed, both "1s" and "Os" can be present in the data
word. The only way to change a "0" to a "I" is by ultraviolet
light erasure.
The 2764 is in the programming mode when V„ input is at 21V
and CE and PGM are both at TTL low. The data to be pro-
grammed is applied 8 bits in parallel to the data output pins.
The levels required for the address and data inputs are TTL.
For programming, CE should be kept TTL low at all times
while V» is kept at 21V. When the address and data are stable,
a 50 msec, active low, TTL program pulse is applied to PGM
input. A program pulse must be applied at each address
location to be programmed. You can program any location at
any time — either individually, sequentially, or at random. The
program pulse has a maximum width of 55 msec.
Programming of multiple 2764s in parallel with the same data
can be easily accomplished due to the simplicity of the pro-
gramming requirements. Like inputs of the paralleled 2764s
may be connected together when they are programmed with
the same data. A low level TTL pulse applied to the PGM input
programs the paralleled 2764s.
Program Inhibit
Programming of multiple 2764s in parallel with different data
is also easily accomplished. A high level CE or PGM input
inhibits the other 2764s from being programmed. Except for
CE (or PGM), all like inputs (including OE) of the parallel
2764s may be common. A TTL low level pulse applied to a
2764 CE and PGM input with V» at 21V will program that
2764.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The venfy is
accomplished with CE and OE at Viu However, PGM is at V,„.
page 0.134

8041A/8641A/8741A
UNIYERSAL PERIPHERAL INTERFACE
8-BIT MICROCOMPUTER
• 8-Bit CPU plus ROM, RAM, I/O, Timer • Fully Compatible with MCS-48™,
and Clock ina Single Package MCS.80™, MCS-85™, and MCS.86™
Microprocessor Families
• One 8-Bit Status and Two Data Regis-
ters for Asynchronous Slave-to.Master • Interchangeable ROM and EPROM
Interface Versions
• 3.6 MHz 8741A.8 Available
• DMA, Interrupt, or Polled Operation
Supported • Expandable I/O
• RAM Power-Down Capability
• 1024x 8 ROM/EPROM, 64x 8 RAM,
8-Bit Timer/Counter, 18 Programmable • Over 90 Instructions: 70% Single Byte
I/O Pins • Single 5V Supply
The Intelo 8041A/8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, I/O
ports, timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85'", MCS-86™, and other 8-bit systems.
The UPI-41A™ has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041A are fully pin compatible for easy transition from prototype to production level designs. The 8641A is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new 8041A order. The
substitution of 8641A's ior 8041A's allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible I/O ports and two test inputs. Individual port lines can function as either in-
puts or outputs under software control. I/O can be expanded with the 8243 device which is directly compatible and has
16 I/O lines. An 8-bit programmable timer/counter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include; single 5V supply, low power standby mode (in the 8041A),
single-step mode for debug (in the 8741A), and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI inter-
face devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include key-
board scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.

PIN CONFIGURATION BLOCK DIAGRAM

NTEINAI
SUS
DSS
•I 5TATUS
I I OI5 TKI
TEST 0 I •0 UCC PIDDIAN
5TAIUS 0
XTAL I 2 35 TEST I IO • '

XTAL2( PTTIOICK
DA A
RESET PSSIDRO N IN O I V
IE5IOENT
SS P25II EE I EO I Nl I II •
IANDON
CS( PKSIOSP 0 5 ACK
ACCESS
NA5TEI
112 I fo 1 * N 5 NKNOIIT
EA f 5 51KN
I N I I II I AC f
Ro( PIS 00 I I 5 I I U0 TI0 N
Of<ODEA
Ao ( , PIE CS Pf I • I E A A
A N Tflf A< f
Wli 10 501 I AI 31 PI • CDI 110L
Sf • IA IOQIC VO
SYNC I KA ACCUEIULATDI POIT I
SIN<
DO KS
OT( PIT PIOO I POIIT •-
SmT k I I TINE
TIC EKPANOIII
02 ( Pl o OOIC UNIT I NIEIf * C T
K •
Voo IIOWI ON
D• ( PROD PIOQI AN

a
CITSTAI I KT AII Nf NDI T CONDI'I ION I
DS ( (123 LC DI U IININQ SIANCN
Clol'I KTALI LDQI
01( 122 i \ l I POI I II I
TEST I
IEOISTKK
Dt ] P21
ID • 11
YSS I P20 ( V PION PI O O I A N W P P LV • IoolkN
• ONKA V« I WPPI T COUNTEI

VII OIIOUNO
I • IT
I NE N
ll l N T COUNTEI
 page D.135

8041A/8641A/8741A

UPI-41A™ FEATURES ANO

ENHANCEMENTS

1. Two Data Bus Buffers, one for input and one for out- If"EN FLAGS" has been executed, PESbecomes the
put. This allows a much cleaner Master/Slave pro- IBF (Input Buffer Full) pin. A "1 " w r itten to P2>
tocol. enables the IBF pin (the pin outputs the inverse of the
IBF Status Bit). A "0" written to PES disables the IEP
INTERNAL pin (the pin remains low).',This pin can be used to
DATA BUS
indicate that the UPI-41A is ready for data.
INPUT
DATA
BUS
BUFFER
(8)
OBF
Dp-DT P24 OBF (INTERRUPT REDDEST)
OUTPUT P24
DATA
BUS
P25
BUFFER
(8) P25 )IF (INTERRUPT REDDEST)
IBF

DATA BUS BUFFER INTERRUPT CAPABILITY

2. 8 Bits of Status

EN FLAGS Op Code: OFSH

STT ST8 ST5 ST4 FI Fp IBF O BF
D'r Dp D5 D4 D3 D2 DI Dp I I I I 0 I 0 I

DT Dp
ST4-STT are uSer definable status bits. These bits are
defined by the " MOV STS, A" single byte, single
cycle instruction. Bits 4-7 of the accumulator are
moved to bits 4-7 of the status register. Bits 0-3 of
the status register are not affected. S. PEB and PET are port pins or DMA handshake pins for
use with a DMA controller. These pins default to port
p(ns on Reset.
MOV STS, A Op Code 90H

I 0 0 I 0 0 0 0
If the "EN DMA" instruction has been executed, PEB
DT Dp becomes the DRQ (DMA ReQuest) pin. A "1" written
to PEB causes a DMA request (DRQ is activated). DRQ
is deactivated by DACK RD, DACK WR, or execution
of the "EN DMA" instruction.
3. RD and WR are edge triggered. IBF, OBF, F, and INT
change internally after the trailing edge of RD or WR.
If "EN DMA" has been executed, P2r becomes the
FLAGS AFFECTED DACK (DMA ACKnowledge) pin. This pin acts as a
chip select input for the Data Bus Buffer registers
RD or WW( during DMA transfers.

DRO P25 DROn

8041AI
4. P24 and PESare port pins or Buffer Flag pins which 8241A
8257
can be used to interrupt a master processor. These DAO K P2T DACK
pins default to port pins on Reset.
If the "EN FLAGS" instruction has been executed, DMA HANDSHAKE CAPABILITY
P>4 becomes the OBF (Output Buffer Full) pin. A "1"
written to P24 enables the OBF pin (the pin outputs
the OBF Status Bit). A "0" written to P24 disables the EN DMA Op Code: OESH
OBF pin (the pin remains low). This pin can be used
I I I
to indicate that valid data is available from the UPI- 0 0 I 0 I

41A (in Output Data Bus Buffer). DI Dp

Page 0.136

8041A/8641A/8741A

PIN DESCRIPTION UPI '"INSTRUCTION SFT

Mnemonic Description Bytes Cycles
ACCUMULATOR
Signal D e scription ADD A,Rr Add register to A
ADD A,(BRr Add data memory to A
Do- Dr Th ee-state, bidirectional DATA BUS BUFFER lines ADD A irdata Add immediate to A
(BUS) used to interface the UPI-41A to an 8-bit master ADDC A,Rr Add register to A with carry
system data bus. ADDC A.NRr Add data memory to A with carry
Pio B-bit, PORT I quasi-bidirectional IIO lines. ADDC A,¹data Add immed to A with carry
ANL A,Rr AND register to A
Pzo- Pzr B.bit, PORT 2 quasi-bidirectional I/O lines. The lower ANLA,@Rr AND data memory Io A
4 bits (Pzo Pzs) Interface directly to the 8243 I/O ex- ANL A,¹data AND immediate to A
pander device and contain address and data infor- ORL A.Rr OR register lo A
mation during PORT 4-7 access. The upper 4 bits ORL A,@Rr OR data memory to A
(Pz4-Pz,) can be programmed to provide Interrupt ORL A.¹data OR immediate to A
Request and DMA Handshake capability. Software XRL A,Rr Exclusive ORregister to A
control can configure Pz4 as OBF (Output Buffer XRL A,@Rr Exclusive OR data memory to A
Full), Pzs as IBF (Input Buffer Full), Pzs as DRQ XRL A,¹data Exclusive OR immediate to A
( DMA R e q uest), a n d P z , a s DA C K ( D M A INC A Increment A
ACKnowledge). DEC A Decrement A
WR I/O wnte input which enables the master CPU to CLR A Clear A
write data and command words to the UPI.41A IN- CPL A Complement A
PUT DATA BUS BUFFER. DA A Decimal Adjust A
SWAP A Swap nibbles of A
RD I/O read input which enables the master CPU to RL A Rotate A lett
read data and status words from the OUTPUT DATA RLC A Rotate A left through carry
BUS BUFFER or status register BRA Rotate A right
CS Chip select input used to select one UPI-41A out of RRC A Rotate A right through carry
severalconnected to a common data bus.
INPUT/OUTPUT
A it Address input used by the master processor to in-
dicate whether byte transfer is data or command. IN A.Pp Input port lo A
OUTL Pp A Output A to port
TEST 0, input pins which can be directly tested using condi- ANL Pp.¹data AND immediate io port
TEST I tional branch instructions. ORL Pp ¹data OR immediate to port
T, also functions as the event timer input (under IN A.DBB input DBB IO A Clear IBF
software control). To is used during PROM program- OUT DBB A Output A to DBB set OBF
ming and verification in the 8741A. MOV STS,A A4-Ar to Bits 4-7 of Status
MOVD A.Pp Input Expander port to A
XTALI, inputs for a crystal, LC or an external timing signal MOVD Pp A Output A to Expander port
XTAL2 to determine the internal oscillator frequency. ANLD Pp,A AND A to Expander port
SYNC Output signal which occurs once per UPI-41A in- ORLD Pp A OR A to Expander port
struction cycle. SYNC can be used as a strobe for
external circuitry; it i s a lso used to s y nchronize DATA MOVES
single step operation.
MOV A,Rr Move register to A
EA External access input which a l lows e m ulation, MOV A,@Rr Move data memory to A
testing and PROM/ROM verification. MOV A,¹data Move immediate to A
MOV Rr,A Move A to register
PROG Muttrfunction pin used as the program pulse input
MOV @Rr A Move A to data memory
during PROM programming.
MOV Rr ¹data Move immediate to register
During I/O expander access the PROG pin acts as MOV @Rr.¹data Move immediate to data memory
an address/data strobe to the 8243, MOV A,PSW Move PSW to A
MOV PSW,A Move A to PSW
RESET Input used to reset status flip-flops and to set the
XCH A Rr Exchange A and register
program counter to zero,
XCH A,@Rr Exchange A and data memory
RESET isalso used dunng PROM programming and XCHD A,@Rr Exchange digit of A and register
venfication. MOVP A.@A Move to A from current page
MOVP3, A.@A Move to A from page 3
SS Single step input used in the 8741A in conjunction
with the SYNC output to step lhe program through
each instruction. TIMER/COUNTER
MOV A,T Read Timer/Counter
Vcc + 5V main power supply pin.
MOV T,A Load Timer/Counter
Voo + 5V during normal operation + 25V during pro- STRT T Start Timer
gramming operation. Low power standby pin in STRT CNT Start Counter
ROM version. STOP TCNT Stop Timer/Counter
EN TCNTI Enable Timer/Counter Interrupt
Vss Circuit ground potential. DIS TCNTI Disable Timer/Counter Interrupt
 page 0.137

8041 AI8841 AI8741 A

Bytes C y cles Mnemonic Description Bytes C ycles

CONTROL CPL FO Complement Flag 0

EN DMA Enable DMA Handshake Lines CLR F1 Clear F1 Flag
EN I Enable IBF Interrupt CPL F1 Complement F1 Flag
DIS I Disable IBF Intenupt
EN FLAGS Enable Master Interrupts
SEL RBO Select register bank 0 BRANCH
SEL RB1 Select register bank 1 JMP addr Jump unconditional
NOP No Operation JMPP ©A Jump indirect
DJNZ Rr, addr Decrement register and jump
REGISTERS JC addr Jump on Carry = 1
INC Rr Increment register JNC addr Jump on Carry =g
INC © Rr Increment data memory JZ addr Jump on A Zero
DEC Rr Decrement register JNZ addr Jump on A not Zero
JTO addr Jump on TO = I
SUBROUTINE JNTO addr Jump on TO = 0
CALL addr Jump to subroutine JT1 addr Jump on T1 = 1
RET Return JNT1 addr Jump on T1 = 0
RETR Return and restore status JFO addr Jump on FO Flag = I
JF1 addr Jump on Fl Flag= 1
FLAGS JTF addr Jump on Timer Flag = I, Clear Flag
CLR C Clear Carry JNIBF addr Jump on IBF Flag=O
CPL C Complement Carry JOBF addr Jump on OBF Flag= 1
CLR FO Clear Flag 0 JBb addr Jump on Accumulator Bit

APPLICATIONS

SP41AI
DATA 8'741A RD RD
rrr
8885A el CS
Ap TO WR TO
SP48 8P41 Al
rc
0 PERiPHERAL PERIPHERAL
RD DEVICES 8741A
CS DEVICES
ADDR Z WR rp PORT CONTROL Ap Tp
O
0
CONTROL
088 BUS DATA BUS 8 088

Figure 1. 8085A-8041A Interface Figure 2. 8048-8041A Interface

DOT MATRIX PRINTER

rr7 FORM
P RINT L J L H OLD SOLENOIDS
P5
8243 O
0
a
Z KEYBOARD
EXPANDER MATRIX Z
I'8 O
i-
I-
0
Z Z
Vi
Pr 8 ROWS MOTOR
ip OIL
SOLENOID
IL
O
i- DRIVERS lu
o DRIVERS
I
u. Z
0IL lu
I u.
zW rc 0I- Iu
o. Z
7 OR 9
PORT 2 PROD
PORT 2
PORT 2 PORT 2 PORT 1IPORT 2
8841A/8741A
8941 AI8741 A
DBB CONTROL 088 COHTRO'

DATA BUS
DATA BUS

CONTROL BUS CONTROL BUS

Figure 3. 8041 A-8243 Keyboad Scanner Figure 4. 8041A Matrix Printer Interface
Page 0.138

8041A/8641A/8741A

ABSOLUTE MAXIMUM RATINGS'
Ambient Temperature Under Bias
Storage Temperature ... . . . . . . .
Voltage on Any Pin With Respect
to Ground
Power Dissipation .
COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the deince This is a stress
rating only and functional operation Of the device at these or any other
.. . . . . O ' C to 70 C conditions above those indicated in the operational sections of this
— 65 C to + 150'C specification is not implied Exposure to absolute maximum rating con.
diiions for extended penods may affect deince reliability.
. 0.5V to + 7V
1,5 Watt

D.C. AND OPERATING CHAR A C T ERISTICS

TA=O'C to 70 C Vss=OV 8041A. Vcc= Voo= +5V+10% 8741A. Vcc= Voo= +5V — 5%
Symbol Parameter Min. Max. Unit Test Conditions
VIL Input Low Voltage (Except XTAL1, XTAL2, RESET) — 0.5 0.8
VILI Input Low Voltage (XTAL1, XTAL2, RESET) — 0.5 0.6
Input High Voltage (Except XTAL1, XTAL2, RESET) 2.2 Vcc
VI HI Input High Voltage (XTAL1, XTAL2, RESET) 3.8 Vcc V
VoL Output Low Voltage (Dp-Dr) 0.45 loL = 2.0 mA
VOLI Output Low Voltage (P ipPir, PzpPzn Sync) 0.45 V loL= 1.6 mA
VoLz Output Low Voltage (Prog) 0.45 loL= 1.0 mA
Voff Output High Voltage (Dp-D,) 2,4 I off - — 400 rtA
-

Voff I Output High Voltage (All Other Outputs) 2.4 I off - — 50 riA
-

Input Leakage Current (Tp, Ti, RD, WR, CS, Ap, EA) +10 pA Vss = VIN
ioz Output Leakage Current (Dp-Dr, High Z State) +10 V.. + 0 4 5 = V IN — Vcc
iu Low Input Load Current (P,pptr, PzpPzr) 0.5 mA — 0.8V
ViL -
Low Input Load Current (RESET, SS) 0.2 mA VIL —
- 0.8V
ioo Vpo Supply Current 15 mA Typical = 5 mA
ice+ ioo Total Supply Current 125 mA Typical = 60 mA

A.C. CHARACTERISTICS
T A=O C to 70 C V s s = OV 8041A: Vcc= Voo= + 5 V + 1 0 % 8 7 4 1A: Vcc= Voo= + 5 V + 5 %
DBB READ
Symbol Parameter Min. Max. Unit Test Conditions
IAR CS, Ap Setup to RDI ns
tRA CS, Ap Hold After RDI ns
1RR RD Pulse Width 250 ns
IAO CS, Ap to Data Out Delay 225 ns CL-150 pF
tRO RDI to Data Out Delay 225 ns CL —
- 150 pF
top Rl5I to Data Float Delay 100 ns
tcv Cycle Time (Except 8741A-8) 2.5 15 6.0 MHz XTAL
tcv Cycle Time (8741A-8) 4.17 15 Its 3.6 MHz XTAL

DBB WRITE
Symbol Parameter Min. Max. Unit Test Conditions
tAW CS, Afl Setup to WRI ns
tWA CS, Ap Hold After W~I ns
tww WA Pulse Width 250 ns
tow Data Setup to WRI 150 ns
two Data Hold After WWl1 ns
 page 0.139

8041A/8641A/8741A

INPUT AND OUTPUT WAV E F O R M S FOR A.C. TESTS

2.4
~2 • 2
TEST POINTS~ 0 .8 CL = 150 PF
0.8~
0.45

WAVEFORMS

1. READ OPERATION — DATA BUS BUFFER REGISTER.

(SYSTEI(I' S
CS OR Ap ADDRESS BUS)

(aa I pa

(READ CONTROL(

I- - (an — -

DATA BUS
(OU TPU T I (TATA VALID

2. WRITE OPERATION — DATA BUS BUFFER REGISTER.

(SYSTEM S
CS OR Ap ADDRESS BUS(

Iav 'v v (pa

IVVR ITS CONTROL)

'n 'v n

DATA BUS DATA DATA

UIVPUTI MAY CHANGE DATA VALID
MAY CHANGE

TYPICAL 8041/8741A CURRENT

80 mA

BO mA

(p
D

+ SOmA

20 mA

20 40' 80' 80'

TEMP ('C)
Page D.140

8041A/8641A/8741A

A.C. CHARACTERISTICS — PORT 2

T a=0' C to 70' C , 8041A: Vcc= + 5 V - 1 0 % , 8 7 41A: Vcc=+ 5 V + 5 %

Symbol Parameter Min. Max. Unit Test Conditions

tcp Port Control Setup Before Falling
Edge of PROG 110 ns
tpc Port Control Hold After Falling
Edge of PROG 100 ns
PROG to Time P2 Input Must Be Valid 810 ns
IPF Input Data Hold Time 150 ns
tor Output Data Setup Time 250 ns
tpo Output Data Hold Time 65 ns
PROG Pulse Width 1200 ns

PORT 2 TIMING

SYNC

EXPANDER IDP
PORT
OUTPUT PORT 2P 2 DATA PORT CONTROL OUTPUT DATA

EXPANDER Ivp IPP

PORT
INPUT
INPUT PCRT 2P I DATA PORT CONTROL DATA

ICP - IPC

PROC

A.C. CHARACTERISTICS — DMA

Symbol Parameter Min. Max. Unit Test Conditions
tace DACK to WR or RD ns
tcac RD or WR to DAAR ns
taco DACK to Data Valid 225 ns — 150 pF
CL -

ICRa RD or WR to DRQ Cleared 200 ns

WA V E F O R M S — DMA
DACK

RD

— ' IACC I- — IICACI-

WR

— I IAcC I ICAC
DATA SUS
VALID VALID

IACD
DRO

IICROI — IICR -
 Page D.14i

8041A/8641A/8741A

C RYSTAL OSCILLATOR MO D E D RIVING FROM EXTERNAL SOU R C E

+ 5V
r XTALI
I 6 etHz 470Q
15 pF
IINCLUDES XTAL,
SOCKET STRAY) XTALI
+ sv
L XTAL2
470Q
15 — 25 pF
IINCLUDES SOCKET,
STRAY) I XTAL2

CRYSTAL SERIES RESISTANCE SHOULD BE 475Q AT 6 MHz, s160Q AT 3 6 MHz

BOTH XTALI AND XTAL2 SHOULD BE DRIVEN.

RESISTORS TO Vcc ARE NEEDED TO ENSURE Vfe= 3.6V
IF TTL CIRCUITRY IS USED

L C OSCILLATOR MO D E
L C NOMINAL I I
4 5 pH 20 p F 5.2 MHz 2 LC '
1 20 H 20 p F 3.2 MHz
XTALI
2

Cpp - 5 — 10 pF PIN TO PIN

XTAL2 CAPACITANCE

EACH C SHOULD BE APPROXIMATELY 20 pF. INCLUDING STRAY CAPACITANCE

WARNING'
PROGR A M M I N G, VERIFYING, AND
An attemp t t o p r o g ra m a m i s socketed 8 7 4 1 A w i l l r e sult ir i severe
ERASING THE 8741A EPROM d amage to t h e p a r t A n i n d i c a t i o n o f a p r o p e rl y so c k e ted p ar t i s t fi e
a ppearance of th e S YN C cl ock o u t p ut . Th e lack o f t h i s clock m a y
be used to disable the programmer.
Programming Verif ication
In brief, the programming process consists of: a c t ivating The Program/Verify sequence is:
t he program mode, applying an a ddress, latching th e
I, A O = O V, CS 5 V , E A = 5V, B E S E T = OV, TESTO = 5V,
address, applying data, and applying a programming pulse. Vpp = 5V, clock ap p l ied oi i n t r.rhal oscillator operating,
Each word is programmed completely before moving on to BUS and PROG floating.
the next and is followed by a verification step. The follow- 2. Inse r t 8 7 4 1 A fn programming socket
ing is a list of the pins used for programming and a descrip-
3. T E S T 0 — Ov (select program inode)
tion of their functions:
4. EA = 23V (activate program model
5. A ddr e ss applied to BUS and P20.1
6. R ESE T = 5v (latch address)
Pin Function
7. Da t a applied to BUS
XTAL 1 Clock Input (1 to BMHz)
8. V p p = 25v (programming power)
Reset Initialization and Address Latching
9. PR O G = Ov followed by one 50ms pulse to 23V
Test 0 Selection of Program or Verify Mode
10, Vpp = Sv
EA Activation of Program/Verify Modes
1 1. T E S T 0 = 5v (verify mode)
BUS Address and Data Input
12. R e a d and verify data on BUS
Data Output During Verify
1 3. T E S T 0 = Ov
P20-1 Address Input
1 4. R ES E T = Ov and repeat from step 5
Vpp Programming Power Supply
1 5. Pr o g r a m mer should be at co nd i t i ons of step 1 wh en
PROG Program Pulse Input
8741A is removed from socket
Page D.142

8041A/8641A/8741A

8741A Erasure Characteristics
The erasure characteristics of the 8741A are such that
e rasure begins to o c cur w hen exposed to l i ght w i t h
w avelengths s h orter t ha n a p p roximately 4000 A n g-
strom- (/). It should be noted that sunlight and certain
t ypes of f l uorescent lamps have wavelengths in t h e
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8741A in approximately 3 years while it would take ap-
proximatelyone week to cause erasure when exposed
to direct sunlight. If the 8741A is to be exposed to these
t ypes of l i g h ting c o nditions fo r e x tended periods o f
t ime, opaque l a bels ar e a v ailable f ro m I n te l w h i c h
should be placed over the 8741A window to p revent
unintentional erasure.
The recommended erasure procedure for the 8741A is
exposure to s h ortwave ultraviolet light w h ich has a
wavelength of 2537>IL. The integrated dose (i.e., UV inten-
sity x exposure time) for erasure should be a minimum
of 15 w-sec/cm . The erasure time with this dosage is
approximately 15 t o 2 0 m i n utes using an u l traviolet
lamp with a 12,000 IIW/cm p o we r rating. The 8741A
should be placed within one inch of the lamp tubes dur-
ing erasure. Some lamps have a filter on t heir tubes
which should be removed before erasure.

A.C. TIMING SPECIFICATION FOR PROGRAMMING

T * — 25 C a 5 C , V c c = 5V a 5 % , V p p = 2 5 V a I V

Symbol Parameter Min. Max. Unit Test Conditions

IAW Address Setup Time to RESET I 4>cy
IwA Address Hold T ime A f ter RESET I 4>cy
Iow D ata in Se tu p T i m e t o P R O G I 4>cy
Iwo D ata in H ol d T i m e A f t e r P RO G I 4>cy
R ESET H o l d T i m e I o V e r i f y 4icy
Ivoow Vpp Setup Time to PROG I 4>cy
IvOOH V oo Hold T i m e A f t e r P RO G I
IPW P iog r ai n P u l s e W i d t h 60 mS
Iiw T est 0 Setup T ime fo r P r o g ram M o d e 4icy
tWT T est 0 Hold T im e A f ter Program M o d e 4>cy
too Test 0 to Data Out Delay 4icy
tww R ESET Pulse W i dt h i o L a t c h A d d r e s s 4lcy
Vop and PROG Rise and Fall Times 20
tcv C PU Operation C y cle T i m e 50
IRF RESET Setup T i mi> Before EA I 4icy

Note: If TEST 0 is big>i, 'Ipo can be triggered by RESET I .

D.C. SPECIFICATION FOR PROG RAMM IN G

T A = 2 5 C — 5 C V c c = 5V — 5% V o o = 2 5 V + 1V

Symbol Parameter Min. Max. Unit Test Conditions

VOQH Vpp Program Voltage High Level 24 0 260
VcoL Vpp Voltage Low L e ve l 4 75 5 25
VPH PROG Program Voltage High Level 21 5 24 5
VPL PROG Voltage Low Level 02
VEAH EA Program or Verify Voltage High Level 21 5 24.5
VEAL EA Voltage Low Level 5 25
Ioo Vpp High Vo ltage Su p ply C u r r e nt 30 0 mA
IPROG PROG High Voltage Supply Current 160 mA
IFA EA High Voltage Supply Current 10 mA
 Page 0.143

8041A/8641A/8741A

N/AVEFORMS FOR PROGRAMM ING

COMBINATION PROGR A M / V E R IFY MODE IEPROM'S ONLY)

23Y
EA
5Y
PROGRAM VERIFY PROGRAM
t tw -

TESTS

IWW

R~EE T

Iaw tWA too

ADDRESS DATA TO BE DATA NEXT ADDR

DBp DBI Io-7) VALID PROGRAIIIMED VALID VALID VALID

LAST NEXT
Ptp-Pt ADDRESS (8-9I VALID ADDRESS
ADDRESS

tvoott
Q twt
'25
Voo

tpw
tovt two
23
FROG
'50

VERIFY MODE IROM/EPROMI

RESET

ADDRESS DAT 4 OUT Iv 7 X T NEXT DATA

DBp DB t
(0 7) VALID VALID ADDRESS DUT VALID

Ptp Pt ADDRESS,8-9) VALID N EXT ADDRESS VALI D

NOTES:
1. PROD MUST FLOAT IF EA IS LOW II. • ., c23V7, OR IF TO SV FOR THE 871IA. FOR THE
SBAIA PROD MUST ALWAYS FLOAT.
XTALI AND XTAL 2 DRIVEN BY 3.8MHT CLOCK WILL GIVE 417 «pec ICY, THIS ISACCEPT.
ABLE FOR 87AIA.S PARTS AS WELL AS STANDARD PARTS,
3. AO MUST BE HELD LOW II. • ., OV) DURING PROGRAM/VERIFY MODES.

The 8741A EPROM can be programmed by either of two

Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellecpo Development System with a UPP-848
Personality Card.
page D.144
 page D.145

Video Logic Board

Page 0.146

H D6 8 4 5 S , H D 6 8 4 4 5 S ,
H D6 8 B 4 S S
CRTC (CRT Controller)
The CRTC is a LSI controller which is designed to provide an
interface for microcomputers to raster scan type CRT displays.
The CRTC belongs to the HMCS6800 LSI Family and has full
compatibility with MPU in both data lines and control lines. its
primary function is to generate timing signal which is necessary
for raster scan type CRT display according to the specification
programmed by MPU. The CRTC ii al so designed as a
programmable controller, so applicable to wide-range CRT
display from small low-functioning character display up to
raster type full graphic display as well as large high-functioning
limited graphic display.

• F EATURES
• Nu mber of Displayed Characters on the Screen, Vertical HD6845SP, HD68A45SP, HD68845SP
Dot Format of One Character, Horizontal and Vertical
Sync Signal, Display Timing Signal are Programmable
• 3.7 MHz High Speed Display Operation
• Line Buffer-le
ss R efreshing
• 14 -bit Refresh Memory Address Output (16k Words
max. Access)
• Programmable Interlace/Non-interlace Scan Mode
• Bu ilt-in Cursor Control Function
• Programmable Cursor Height and its Blink (D P-40)
• Bu i lt-in Light Pen Detection Function
• Paging and Scrolling Capability
• TT L Compatible • PIN ARRANGEMENT
• Si ngle +BY Power Supply "ss YSYNC
Trrs NSY NC
• Up ward compatible with MC6845 LPSTS RA
MA, RA,
MA, RA
• SYSTEM BLOCK DIAGRAM MA, RA
MA, RA
A AP • MA D,
A A„
MAI D,
HD6845S
MA, D,
MA, D,
VA IPA
MA D,
MA, D,
MA„ D,
o
1
CCA HDSSSSSP MA„ l ar
! MIf
RS
DISPTMC l S
A,- CUDISP 1
IIA, "cc CLK

0
C (Top View)
Y4

• OR DERING INFORMATION
PAP Y C o o
CYP •
• C
• C
CRTC CRT Display
I•
Bus Timing
CP I Timing
o
HD6845SP 1.0 MHz
HD68A45SP 1.5 MHz 3.7 MHz max.
HD68845SP 2.0 MHz
 Page 0.147

HD6845S, HD68A458, HD68845S

• ABSOLUTE MAXIMUM RATINGS

Item Symbol Value Unit
Supply Voltage Vcc -0.3 — +7.0 V
Input Voltage Vn -0,3 — +7.0
Operating Temperature Top — 20-+ 75 C
Storage Temperature — 55 — +1 50 C
With respect to VSS {SYSTEM GND)
[NOTE) permanent LSI damage mey occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions ere exceeded, it could affect reliability of LSI.

• RECOM M E N D ED OPERATING CONDITIONS

Item Symbol min typ max Unit
Supply Voltage Vcc 4.75 5. 25 V
-0.3 0.8 V
Input Voltage
2.0 Vcc V
Operating Temperature Too. — 20 25 75
With reapeCt tO VSS {SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc S V + 5%, VSS = OV, Ta -20-+75 C, unless otherwise noted.)
Item Symbol Test Condition min typ max Unit
Input "High" Voltage 2.0 V V
Input "Low" Voltage -0.3 0.8
Input Leakage Current l)n Vln =0 5 . 2 5 V (EXCeP't DO Dt ) -2. 5 2.5 ){A
Three-State Input Current V,n = 0.4- 2 . 4 V
ITS i — 10 10
(off-state) Vcc = 5.25V (Do D t )
I LpAp = 205 S{A (Do D t )
Output "High" Voltage Vprf 2.4 V
I QAp 100 ){A (Other Outputs)
Output "Low" Voltage VOL ILpaD = 1.6 mA 0.4
Vi. = 0 D - D 12.5 pF
Input Capacitance Cin Ta =25 C
f = 1.0 MHz Other Inputs 10.0 pF
Output Capacitance Co.t Vln = OV, Ta = 25 C, f = 1.0 MHz 10. 0 pF
Power Dissipation Pp 600 1000 mW
Page 0.148

HD6845S, HD68A45S, HD68845S

• A C CHARACTERISTICS (Vcc 5V + 5 %, Vss= OV, Ta = -20-+75 C, unless otherwise noted.)

1. TIMING OF CRTC SIGNAL
Item Symbol Test Condition min tyP max Unit
Clock Cycle Time tcycc 270 ns
Clock "High" Pulse Width 130 ns
Clock "Low" Pulse Width PWcL 130 ns
Rise andFall Time for Clock Input tCr, tC1 20 ns
Memory Address Delay Time tMAD 160 ns
Raster Address Delay Time t RA D Fig. 1 160 ns
DISPTMG Delay Time 250 ns
CUD ISP Delay Time tcoo 250 ns
Horizontal Sync Delay Time tHSD 200 ns
Vertical Sync Delay Time tvso 250 ns
Light Pen Strobe Pulse Width 60 ns
Light Pen Strobe t LPD1 70 ns
Fig. 2
Uncertain Time of Acceptance tLPD2 ns

2. MPU READ TIMING

Test HD6845SP HD68A45SP HD68845SP

Item Symbol Unit
Condition min tyP max min tyP max min tyP max
Enable Cycle Time rycE 1.0 0.666 0.5
Enable "High" Pulse Width PWE H 0.45 0.280 0.22
Enable "Low" Pulse Width PWE L 0.40 0.280 0.21
Enable Rise and Fall Time t Er t s f 25 25 25 ns
Address Set Up Time tas Fig. 3 140 140 70 ns
Data Delay Time t DD R 320 220 ns
Data Hold Time tH 10 10 10 ns
Address Hold Time tAH 10 10 10 ns
Data Access Time tace 460 360 250 ns

3. MPU WRITE TIMING

Test HD6845SP HD68A45SP HD68845SP

Item Symbol Unit
Condition min tyP max min tyP max min tyP max
Enable Cycle Time tcy~ 1.0 0.666 0.5
Enable "High" Pulse Width PWEH 0.45 0. 280 0. 22
Enable "Low" Pulse Width PWEL 0.40 0.280 0. 21
Enable Rise and Fall Time t Er t E f 25 25 25 ns
Fig. 4
Address Set Up Time tA 140 140 70 ns
Data Set Up Time tosw 195 60 ns
Data Hold Time tH 10 10 10 ns
Address Hold Time tAH 10 10 10 ns
 page 0.149

HD68458, HD68A458, HD68B458

tcycc

2.0V 2.0V PWcL

0.8 V 0.8V 0.8V 08V

CLK PWcH

tCr

2.4V

0.4V
M A> M A >>

t MA D >MAD

2.4V

0.4V
R A,- R A ,

t RA D RAD

2.4V

0.4V
D ISPTMG

tDT D tOTO

2.4V

0.4V
CUD I SP

tcoo 'coo

2.4V

0.4V
HSYNC
VSYNC

tHSD tHSD
tvso tvso

2.0V 2.0V

PWLP>t

LPSTB
This Figure shows the relation in time between
CLK signal and each output signals. Output
sequence is shown in Figs. 9 - 15.

Figure 1 Time Chart of the CRTC

Page D. l50

HDB8458, HDBBA45S, HD88845S

tLPD2
tLPDt

CLK O.BV

M As M A i s M+1 M+2

LPSTB OBV

2,OV
LPSTB

When LPSTB nses in this period

Refresh Memory Address "M+2
is set into the light pen register.
tLPD1 • tLPDg: L PSTB's uncertain time of ecceptence.

Figure 2 LPSTB Input Timing Bt Refresh Memory Address that is set into the light pen register.

PWEH
tae

2.0V 2,0V 2.0V

PWSL

OAIV OSV OSV

ter
tef
tDDR

20V 2.0V

OBV O.BV
R/W, RS
tAH
'acc
tH

2.4V 2.4V
Os-O.

0.4V 0.4V

Figure 3 Read Sequence

 page 0.151

HD68456, HD68A456, HD68845S

PWE H
tas

2.0V 2 ,0V 2.0V

PWEL

O.BV O.BV

tEr tEt

tostN
CS
R/W 2.0V 2.0V
RS (Address
Register)
O.BV O.BV
RS
tControl Register) tAH
tH

2.0V 2.0V

os-o t

O.BV O.BV

Figure 4 Write Sequence

• SYSTEM DESCRIPTION
The CRTC is a LSI which is connected with MPU and CRT
display device to control CRT display. The CRTC consists of
internal register group, horizontal and vertical timing circuits,
linear address generator, cursor control circuit, and light pen
detection circuit. Horizontal and vertical timing circuit generate
RAp RAe D I SPTMG HSYNC altd VSYNC. RAo RA4 are
raster address signals and used as input signals for Character
Generator. DISPTMG, HSYNC, and VSYNC signals are received
by video control circuit. This horizontal and vertical timing
circuit consists of internal counter and comparator circuit,
Linear address generator generates refresh memory address MAo
-MAts to be used for refreshing the screen. By these address
signals, refresh memory is accessed periodically. As 14 refresh
memory address signals are prepared, 16k words max are
accessible. Moreover, the use of start address register enables
paging and scrolling. Light pen detection circuit detects light
pen position on the screen. When light pen strobe signal is
received, light pen register memorizes linear address generated
by linear address generator in order to memorize where light
pen is on the screen. Cursor control circuit controls the position
of cursor, its height, and its blink.
Page D.152

HD6845S, HD68A45S, HD688458

DO-D,
Vcc Vss RES R /W E C S R S

Address Register
& R/W Control

CLK Character Counter Horizontal Displayed

CK fe266 ) CMP Register
MR

yr RP Honzontal Total
CMP CMP Register
HMAX

Horizontal Sync
CMP Position Register

0 st HSYNC
2r
CK Horizontal Syn CMP R3 Sync
Width Register
Width Counter
RQs 2z 27
Raster Counte RQ, CMP Rg Maximum Raster
(432) Address Register
MR

Line Counter CMP Vertical Displayed

(4128 Register
MR 'S

CMP Vertical Total

VTOTAL Control Register

R8 CMP Vertical Total Adjust

2e 2 i CMP Register
VS Skew DISPTMG
a Control
Vertical Sync CE CMP R7 Vertical Sync
5frdth Counter(-,' 16) Position Register
MR

R12 Start Address

Linear Address R'13 Register
Generator

Rt p Cursor Start
Raster Register
C ursor Ske w
o RQr CUD ISP
C ontrol Co n t r o l
VT R11 Cursor End
Raster Register

VS
R14 Cursor Register
CMP

VSYNC
Interlace 2o 2i 2s 27
RA,- Control Interlace & Skew
RAs Register

R16 L i ght Pen

R17 R egister

LPST8 SYNC

M A, MA
Figure 5 Internal Block Diagram of the CRTC

HDB845S, HDBBA45S, HD88845S
• F UNCTION OF SIGNAL LINE
The CRTC provides 13 interface signals to MPU and 25
interface signals to CRT display.
• I nterface Signals to MPU
Bi-directional Data Bus (Dp-D7)
Bi-directional data bus(Dp-Dp) are used for data transfer
between the CRTC and MPU. The data bus outputs are 3-state
buffers and remain in the high-impedance state except when
MPU performs a CRTC read operation.
Read/Write (R/W)
R/W signal controls the direction of data transfer between
the CRTC and MPU. When R/W is at "High" level, data of
CRTC is transfered to MPU. When R/W is at "Low" level, data
of MPU is transfered to CRTC.
Chip Select (CS)
Chip Select signal (CS) is used to address the CRTC. When
CS is at "Low" level, it enables R/W operation to CRTC internal
registers. Normally this signal is derived from decoded address
signal of MPU under the condition that VMA signal of MPU is at
"High" leveL
Register Select (RS)
Register Select signal (RS) is used to select the address
register and 18 control registers of the CRTC. When RS is at
"Low" level, the address register is selected and when RS is at
"High" level, control registers are selected. This signal is
normally a derivative of the lowest bit (AO) of MPU address bus.
Enable(E)
Enable signal (E) is used as strobe signal in MPU R/W
operation with th e C RTC internal registers. This signal is
normally a derivative of the HMCS6800 System 4s clock.
Reset (RES)
Reset spiel (RES) is an input signal used to reset the CRTC.
When RES is at "Low" level, it forces the CRTC into the
following status.
I) AH the counters in the CRTC are cleared and the device
stops the display operation.
2) All the outputs go down to "Low" level.
3) Control registers in the CRTC are not affected and remain
unchanged.
This signal is different from other HMCS6800 family LSls in the
followi~nfunctions and has restrictions for usage.
I) RES signal has capability of reset function only when
LPSTB is at "Low" level.
2) The CRTC starts the display operation immediately after
RES signal goes "High".
Page D.153
• I nterface Signals to CRT Display Device
Character Clock (CLK)
CLK is a standard clock input signal which defines character
timing for the CRTC display operation. This signal is normally
derived from the external high-speed dot timing logic.
Horizontal Sync (HSYNC)
HSYNC is an active "High" level signal which provides
horizontal synchronization for display device.
Vertical Sync (VSYNC)
VSYNC is an active "High" level signal which provides verti-
cal synchronization for display device,
Display Timing (DISPTMG)
DISPTMG is an active "High" level signal which defines the
display period in horizontal and vertical raster scanning. It is
necessary to enable video signal only when DISPIMG is at
"High" level.
Refresh Memory Address (MAp-MA» )
MAp MArs are refresh memory address signals which are
used to access to refresh memory in order to refresh the CRT
screen periodically. These outputs enables 16k words max.
refresh memory access. So, for instance, these are applicable up
to 2000 characters/screen and 8-page system.
Raster Address (RAp-RA4 )
RAp-RA4 are raster address signals which are used to select
the raster of t h e c h aracter generator or g raphic pattern
generator etc.
Cursor Display (CUDISP)
CUDISP is an active "High" level video signal which is used
to display the cursor on the CRT screen. This output is in-
hibited while DISPTMG is at "Low" level. Normally this output
is mixed with video signal and provided to the CRT display
device.
Light Pen Strobe (LPSTB)
LPSTB is an active "High" level input signal which accepts
strobe pulse detected by the light pen and control circuit. When
this signal is activated, the refresh memory address (MAp-
MA») which are shown in Fig. 2 are stored in the 14-bit light
pen register. The stored refresh memory address need to be
corrected in software, taking the delay time of the display
device, light pen, and light pen control circuits into account.
page 0.154

HD6845S, HD68A45S, HD68845S

• REGISTER DESCRIPTION
Table 1 Internal Registers Assignment

Address Register Data Bit

CS RS Register Register Name Program Unit READ WRITE
4 3 2 I 0

X X X X X

X X X K AR Address Register

0 0 0 0 0 RO Horizontal Total ' Character

0 0 0 0 1 Rl Horizontal Displayed Character

0 0 0 1 0 Horizontal Sync' Character

R2 Position
Vertical. Raster,
0 0 0 1 1 R3 Sync Width Horizontal- wv3 wh3 wh2 whl whO
Character

0 0 1 0 0 R4 Vertical Total ' Line

0 0 I 0 1 RS Vertical Total Adjust Raster

0 0 1 I 0 R6 Vertical Displayed Line

0 0 1 1 1 R7 Vertical Sync
Position Line

0 1 0 0 0 R8 Interlace & Skew 0 Cl CO Dl DO

0 1 0 0 I Rg Maximum Raster
Address Raster

0 I 0 I 0 R10 Cursor Start Rester Raster

0 1 0 1 Rl 1 Cursor End Raster Raster

0 1 1 0 0 R12 Start Address( H)

0 1 1 0 I R13 Start Address( Ll

0 1 1 1 0 R14 Cu rso r ( H)

0 I 1 1 I R15 Cursor (L)

1 0 0 0 0 R16 Light Pen(H)

I 0 0 0 1 R17 Light Pen(L)

[NOTE) 1 , T he Registers marked •: (Written Value) (Specified Value) — I

2. Written Value of Rg is mentioned below.
1) Non-interlace Mode ) (Written Value Nr) = (Specified Value) — I
Interlace Sync Mode i
2) Interlace Sync & Video Mode
(Written Value Nr) ( S pecified Value) — 2
3. CO and Cl specify skew of CUDISP output signal.
DO and Dl specify skew of DISPTMG output signal.
When S is "I", V specifies video mode, S specifies the Interlace Sync Mode.
4. 8 specifies the cursor blink, P specifies the cursor blink period.
5. wvO-wv3 specify the pulse width of Vertical Sync Signal.
whO-wh3 specify the pulse width of Horizontal Sync Signal.
6. RO is ordinaliy programmed to be odd number in interlace mode.
7 , 0 ; Y es,x ; N o
 page D.155

HD68458, HD68A45S, HD688456

• Address Register (AR) Table 2 Pulse Width of Vertical Sync Signal

This is a 5-bit register used to select 18 internal control
registers (RO R17). Its contents are the address of one of 18 VSW
PulseWidth
internal control reg(stars. Programming the data from 18 to 31 2' 2' 2' 2'
produces no results. Access to RO-R17 requires, first of all, to
write the address of corresponding control register into this 16H
register. When RS and WS are at "Low" level, this register is 1
selected.

• Horizontal Total Register (RO) 34

2
5
This is a register used to program total number of horizontal
characters per linc including the retrace period. The data is 8-bit
and its value should be programmed according to the specifi-
cation of the CRT. When M is total number of characters,(M-1) 67
shall be programmed to this register. When programming for
interlace mode, M must be even. 8
9
• Horizontal Displayed Reghter (R1)
10
This is a reghter used to program the number of horizontal
displayed characters per line. Data is 8-bit and any number that 11
is smaller than that of horizontal total characters can be 12
programmed. 13
14
• Horizontal Sync Position Register (R2)
This is a rcgistcr used to program horizontal sync position as 15
multiples of thc character clock period. Data is 8-bit and any H; Rester period
number that is lower than the horizontal total number can be
programmed. When H is character number of horizontal Sync
Position, (H-1) shall be programmed to this register. When pro-
grammed value of this register is increased, the display position Table 3 Pulse Width of Horizontal Sync Signal
on thc CRT screen is shifted to the left. When programmed HSW
value is decreased, the position is shifted to the right. Therefore, Pulse Width
the optimum horizontal position can be determined by this 23 22 2i 20
value. — (Note)
• Sync Width Regtst«(RS)
This is a register used to program the horizontal sync pulse 01 1 CH
width and the vertical sync pulse width. The horizontal sync 2
pulse width is programmed in the lower 4-bit as multiples of the 1 3
character clock period. "0" cannot be programmed. The
vertical sync pulse width is programmed in higher 4-bit as 45
multiples of the raster period. When "0" is programmed in
010
higher4bit, 16 raster period (16H) is specified.
8
7
6
• Vertical Total Register (R4)
This is a register used to program total number of lines per 0
frame including vertical retrace period. The data is within 7-bit 9
and its value should be programmed according to the specifica- 01
1 10
tion of the CRTC. When N is total number of lines, (N-1) shall
be programmed to this reg(ster. 11
12
• Vertical Total Adjust Regist«(RS) 13
This is a register used to program the optimum number to 01
14
adjust total number of rasters per field. This register enables to
15
decide thc number of vertical deflection frequency more
strictly. CH; Cherecier clock period
f Note) HSW "0" cennoi be used.
• Vertical Disp4yed Register (R6)
This is a register used to program the number of displayed
character rows on the CRT screen. Data is 7-bit and any number
that is smaUer than that of vertical total characters can be
programmed.
page 0.156

HO8845S, HD68A45S, HD68845S

• V ertical Sync Position Register (R7)
This is a register used to program the vertical sync position
on the screen as multiples of the horizontal character line peri-
od. Data is 7-bit and any number that is equal to or less than
vertical total characters can be programmed. When V is charac-
ter number of vertical sync position,(V-l) shall be programmed
to this register. When programmed value of this register is in-
creased, the display position is shifted up. When programmed
value is decreased, the position is shifted down. Therefore, the
optimum vertical position may be determined by this value,
• I nterlace and Skew Register (RB)
This is a register used to program raster scan mode and skew
(delay) of CUDISP signal and DISPTMG signal.
Interlace Mode Program Bit (V, S)
Raster scan mode is programmed in the V, S bit.
Skew function is used to delay the output timing of
CUDISP and DISPTMG signals in LSI for the time to access
refresh memory, character generator or pattern generator,
and to make the same phase with serial video signal.
• Maximum Raster Address Register (RQ)
This is a register used to program maximum raster address
within 5-bit. This register defines total number of rasters per
character including space. This register is programmed as fol-
lows.
Non-interlace Mode, Interlace Sync Mode
When total number of rasters is RN, (RN-I ) shall be
programmed.
Interlace Sync & Video Mode
When total number of rasters is RN, (RN-2) shall be
programmed.

This manual defines total number of rasters in non-interlace

Table 4 Interlace Mode (2', 2 ) mode, interlace sync mode and interlace sync 8c video mode as
follows:
V S Raster Scan Mode
Non-interlace Mode

I Non-interlace Mode 0
I
Total Number of Rasters 5
Programmed Value Nr = 4
Interlace Sync Mode 2 The same as displayed
Interlace Sync & Video Mode 3 (
total number of rasters~
4
Raster Address
In the non-interlace mode, the rasters of even number
I nterlaceSync Mode
field and odd number field are scanned duplicatedly. In the
Total Number of Rasters 5
interlace sync mode, the rasters of odd number field are ---- 0 Programmed Value Nr = 4
scanned in the middle of even number field. Then it is
---- I In the interlace sync mode,
controlled to display the same character pattern in two
---- 2 total number of rasters in
fields. In the interlace sync and video mode, the raster scan
both the even and odd fields
method is the same as the interlace sync mode, but it is ---- 3 is ten. On programming,
controlled to display different character pattern in two field. ---- 4 the half of it is defined as
Skew Program Bit (C1, CO, D1, DO) Raster Address total number of rasters.
These are used to program the skew (delay) of CUDISP
signal and DISPTMG signal. InterlaceSync & Video Mode
0 Total Number of Rasters 5
Skew of these two kinds of signals are programmed
separately. Programmed Value Nr = 3
-3 Total number of rasters

Table 5 DISPTMG Skew Bit (2, 2 )

4
Raster Address (displayed in the even field
and the odd field.

D1 DO D ISPTMG Signal • Cursor Start Rester Register (R10)

This is a register used to program the cursor start raster
Non.skew address by lower 5-bit (2 2 ) and the cursor display mode by
One-character skew higher 2-bit (2, 2 ).
Two-character skew
Non-output Table 7 Cursor Display Mode (2, 2 )
B P Cursor Display Mode
0 0 Non-blink
0 1 Cursor Non-display
Table 6 Cursor Skew Bit (2, 2 )
0 Blink, 16 Field Period
C1 CO Non-skew Blink, 32 Field Period
1 1
Non-skew
One-character skew Blink Period

Two.character skew light dark

Non-output
16 or 32 Field Period
 page 0.157

HD6845S, HD68A458, HD68845S

• Cursor End Raster Register (R11) 6) 2<Nr<30

This is register used to program the cursor end raster address.
• Start Address Register (R12, R13)
These are used to program the first address of refresh
memory to read out.
Paging and scrolling is easily performed using this register.
This register can be read but the higher 2-bit (2, 2') of R12 are
always "0".
• Cursor Register (R14, R15)
These two read/write registers stores the cursor location. The
higher 2-bit (2, 2') of R14 are always "0".
• Li g ht Pen Register(R16, R17)
These read only registers are used to catch the detection
address of the light pen. The higher 2-bit (2, 2') of R16 are
always "0". Its value needs to be corrected by software because
there is time delay from address output of the CRTC to signal
input LPSTB pin of the CRTC in the process that raster is lit
after address output and light pen detects it. Moreover, delay
time shown in Fig. 2 needs to be taken into account.
Restriction on Pr rammin Internal R ister
I) (KNhd<Nht + I <256
2) 0 < Nvd < Nvt + I < 128
3) 0 K Nhsp < Nht
4) 0 <Nvsp <Nvt d
5) 0 < NCSTART + NCEND ~ Nr (Non-interlace, Interlace sync
mode)
0 ~ NCSTART ~ NCEND < Nr + 1(Interlace sync &. video
mode)
7) 3 < Nht (Except non-interlace mode)
5 < Nht (Non-interlace mode only)
In the interlace mode, pulse width is changed zyr raster time when
vertical sync signal extends over iwo fields.
Notes for Use
The ruethod of directly using the value programmed in the
internal register of LSI for controlling the CRT is adopted.
Consequently, the display may flicker on the screen when the
contents of the registers are changed from bus side asyncronous-
ly with the display operation.
Cursor Register
Writing into this register at frequent intervals for moving the
cursor should be performed during horizontal and vertical
retrace period.
Start Address Register
Writing into the start address register at frequent intervals for
scrolling and paging should be performed during horizontal and
vertical display period.
It is desirable to avoid programming other registers during
display operation.
• OPERATION OF THE CRTC
• T ime Chart of CRT Interface Signals
The following example shows the display operation in which
values of Table g are programmed to the CRTC internal
registers. Fig. 6 shows the CRT screen format. Fig. 9 shows the
time chart of signals output from the CRTC.

~ N I IH (* IT I dh I I +I l

~ N h I H I CI H dh INhdl~

L I lla

+ +
Horizontal
Retrace
Zst Period
z Ih

ru .g
O
K e 'I)
o ) Z
X
e
X l-8
0 0 Display Period
I( 5
Ew
z cz
I(
E
Z

Vertical Retrace Period

Vertical Total Adjust (Nadj)

Figure 6 CRT screen Format

Page D.i 58

HD6845S, HD68A45S, HD68845S

Table 8 Programmed Values into the Registers

Register Register Name Value Register Register Name Value

RO Horizontal Total Nht Rg Max. Raster Address Nr
Rt Horizontal Displayed Nhd R10 Cursor Start Raster
R2 Horizontal Sync Position Nhsp R11 Cursor End Raster
R3 Sync Width Nvsw, Nhsw R12 Start Address (H) 0
R4 Vertical Total Nvt R13 Start Address (L) 0
RS Vertical Total Adjust Nadj R14 Cursor (H)
R6 Vertical Displayed Nvd R15 Cursor (L)
R7 Vertical Sync Position Nvsp R16 Light Pen (H)
R8 Interlace & Skew R17 Light Pen (L)
(NOTE) Nhd<Nhi, Nvd<Nvi

The relation between values of Refresh Memory Address In non-interlace mode, each field is scanned duplicatedly.
(MAo MAis ) and Raster Address (RAo-RA4) and the display The values of raster addresses (RAo-RA 4) are counted up one
position on the screen is shown in Fig. 15. Fig. 15 shows the from 0.
case where the value of Start Address is 0. Interlace Sync Mode Display
In the interlace sync mode, raster addressed in the even field
• I nterlace Control and the odd field are the same as addressed in the noninterlace
Fig. 7 shows an example where the same character is mode. One character pattern is displayed mutually and its dis-
displayed in the non-interlace mode, interlace sync mode, and played position in the odd field is set at I/2 raster space down
video mode. from that in the even field.
Non-interlace Mode Display

1
0

2
3
2
3
%--3
45 --e — — —
——------ M —4
5
6
7
6 — -e-- — — —
- ——---M--6
7
8
89
9 —W-- — — --- - — - D - - 9
A
8
A

Non-interlace Mode Interlace Sync Mode

-D - - - - - - - - - —- 0 - — I
2 I
"-3 2 - e- - - - - --- ---o- 3
4
line ¹0 — w - • — e-o -e -e-0-- line ¹0
6 -- - - - - - - - - —0 - -
7
5
8
A 0
9

2— w —
——- --- — —- -- • ---3
4 5 46 line ¹1
line ¹ 1
6 . -0- 7
-
- -
-7
— - — - - - -

8
8 -M - - — — —
— —---o- — 9
A
A

Interlace Sync & Video Mode Inierlece Sync & Video Mode
(Total number of rasters in a line is even.) (Total number of rasters in a line is odd.l

Figure 7 Example of Raster Scan Display

 page 0.159

HD8845S, HD88A458, HD88845S

Interlace Sync & Video Mode Display

In interlace sync & video mode, the output raster address
when the number of rasters is even is different from that when
the number of rasters is odd. 1
0
2
Table 9 The Output of Raster Address in
Interlace Sync & Video Mode
Field 34
7
6
5
Number of Even Field Odd Field
Rasters in a Line
Even Even Address Odd Address 8
9
8
Even Line" Even Address Odd Address 9
Otjd 10 10
Odd Line' Odd Address Even Address
Internal line address begins from 0, Cursor Start Address 9 Cursor Start Address 9
Cursor End Address 9 C ursor End Address 10

I) Total number of rasters in a line is even;

When number of rasters is programmed to be even, even
raster address is output in the even field and odd raster address
is output in the odd field.
2) Total number of rasters in a line is odd;
When total number of rasters is programmed to be odd, odd
and even addresses are reversed according to the odd and even
lines in each field. In this case, the difference in numbers of dots
displayed between even field and odd field is usually smaller the
case of I). Then interlace can be displayed more stably.
tNOTE] The wide disparity of dots between number of dots
between even field and odd field influences beam
current of CRT. CRT, which has a stable high-voltage
part, can make interlace display normal. On the con-
trary, CRT, which has unstable high-voltage part,
moves deflection angle of beam current and also dots
displayed in the even and odd fields may be shifted.
Characters appears distroting on a border of the
screen. So 2) programming has an effect to decrease
such evil influences as mentioned above. Fig. 12
shows fine chart in each mode when interlace is
performed.
• Cursor Control
Fig. 8 shows the display patterns where each value is
programmed to the cursor start raster register and the cursor
end raster register. Programmed values to the cursor start raster
register and the cursor end raster register need to be under the
following condition.
Cursor Start Raster Register $ Cursor End Raster Register +
Maximum Raster Address Register.
Time chart of CUDISP output signal is shown in Fig. 13 and
Fig. 14.
• INTERFACE TO DISPLAY CONTROL UNIT
Fig, 16 shows the interface between the CRTC and display
control unit. Display control unit i s mainly composed of
Refresh Memory, Character Generator, and Video Control
circuit. Fo r r e f resh memory, 14 M emory A ddress line
(0 16383) max are provided and for character generator, 5
Raster Address line (0-31) max are provided. For video control
circuit, DISPTMG, CUDISP, HSYNC, and VSYNC signals are
sent out. DISPTMGsignal is used to control the blank period of
video signal. CUDISP signal is used as video signal to display the
cursor on the CRT screen. Moreover, HSYNC and VSYNC
signals are used as drive signals respectively for CRT horizontal
and vertical deflection circuits.
01
23
4
56
7
8
9
10
Cursor Start Address 1
Cursor End Address 5
Figure 8 Cursor Control
Outputs from video control circuit, (video signals and sync
signals) are provided to CRT display unit to c ontrol the
deflection and brightness of CRT, thus characters are displayed
on the screen.
Fig. 17 shows detailed block diagram of display control unit.
This shows how to use CUDISP and DISPTMG signals. CUDISP
and DISPTMG signals should be used being latched at least one
time at external flip-flop FI and F2. Flip-flop FI and F2
function to make one-character delay time so as to synchronize
them with video signal from parallel-serial converter. High-speed
D type flip-flop as TTL is used for this purpose. After being
delayed at Fl and F2 DISPTMG signal isAND-ed with character
video signal, and CUDISP signal is OR-ed with output from
AND gate. By using this circuitry, blanking of horizontal and
vertical retrace time is controlled. And cursor video is mixed
with character video signal.
Fig. 17 shows the example in the case that both refresh
memory and CG can be accessed for horizontal one character
time. Time chart for this case is shown in Fig. 20. This method
is used when a few character needed to be displayed in
horizontal direction on the screen.
Page 0.160

HD6845S, HD68A45S, HD68B45S

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 Page D.161

HD6845S, HD68A45S, HD688458

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Page 0.162

HDBB45S, HDBBA45$, HDBB845S

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 Page 0.163

HD6845S, HD68A45S, HD68845S

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Page 0.164

HD8845$, HD88A45$, HDSS845$

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 page 0.165

HD8845S, HD88A45S, HD88B458

14 max Refresh
MA Memory

5 max Character
RA
CRTC Generator

D ISPTMG
Video
CUD ISP
Signals
Video Control
HSYNC Sync
Signals
VSYNC 0 0
CLK

Figure 16 Interface to Display Control Unit

F1
CUDISP
D Q
CHCP-N
F2
D lSPTMG
D Q

CRTC VIDEO

MA Refresh CG
Memory

RA
CLK

CHCP-P
DOT COUNTER OSC

Figure 17 Display Control Unit (1)

page D.166

HO8845S, HD88A45S, HD88845S

When many characters are displayed in horizontal direction
on the screen, and horizontal one-character time is so short
that both refresh memory and CG cannot be accessed, the
circuitry shown in Fig. 18 should be used. In this case refresh
memory output shall be latched and CG shall be accessed
at the next cycle. The time chart in this case is shown in Fig.
21. CUDISP and DISPI'MG signals should be provided after
being delayed by one-character time by using skew bit of
interlace & skew register (R8). Moreover, when there are sotne
troubles about delay time o f M A d u ring horizontal one-
character time on high-speed display operation, system shown in
Fig.19 is adopted. The time chart in this case is shown in Fig,22,
Character video signal is delayed for two-character time because
each MA outputs and refresh memory outputs are latched, and
they are made to be in phase with CUDISP and DISFI'MG
signals by delaying for two-character time. Table 10 shows the
circuitry selection standard of display units.

Table 10 Circuitry Standard of Display Control Unit

Interlace & Skew Register
Block Bit Programming
Case Relation among tcH, RM and CG Diagram
C1 co DI DO

toH > RM Access + CG Access + t«o Fig. 17

RM Access+ CG Access+ t»o 2 tc „ > R M A ccess+ tMAD Fig. 18
RM Access+ tMAD 2 tc„> R M A ccess Fig. 19
tCH . CHCP Period; I M A D . M A D e l ay

CUD ISP
D Q
CHCP.N
F2
DISPTMG
D Q

CRTC VIDEO
L
MA Refresh
C
T
A
H CG

(I

RA
CLK

CHCP-P
DOT COUNTER OSC

Figure 1B Display Control Unit (2)

FI
CUD I SP
D Q
CHCP.N
F2
D ISPTMG
D Q

CRTC L L VIDEO
MA A
C
T Refresh A
C
T
Memory CG
H
(I H
I)
RA
CLK

DOT COUNTER OSC

Figure 19 Display Control Unit (For high-speed display operation) (3)

 Page 0.167

HD68456, HD68A458, HD68845S

CHCP P

MA

DISPTMG

CUDISP

F2 -Q

F1-Q

RMOUT I I/ 3
/

CGOUT

VIDEO

CRT Display • OOO O • 0

Figure 20 Time Chart of Display Control Unit (1)

CHCP P

MA

D ISPTMG

One-Character
CUD ISP Skew

F2-Q

F1-Q

RMOUT

LATCH (I)

CGOUT

VIDEO

CRT Display
• 0 • OOO •

Figure 21 Time Chart of Display Control Unit (2)

page 0.168

HD88458, HD88A458, HD888458

CHOP-P

MA

DISPTMG

Two.Character skew
CUD ISP

LATCH (2)

F2Cl

F1-0

RMOUT

LATCH(1)

CGOUT

V I D EO

CRT Display • JO • •0

Figure 23 Time Chart of Display Unit 13)

• HOW TO DECIDE PARAMETERS SET ON THE CRTC

• Ho w to Decide Parameters Based on Specification of CRT Nvi + 1 (Nr + 2) + 2Nadj
Rt-
Display Unit IMonitorl 2
Number of Horizontal Total Characters
Horizontal deflection frequency fh is given by specification N vt+ I N r + 2)+ 2Nadj+I
Rt-
2
(b)
of CRT display unit. Number of horizontal total characters is
determined by the following equation. (a) is applied when both total numbers of vertical characters
(Nvt + I) and that of rasters in a line (Nr + 2) are odd.
f- t c (N hi + I) (b) is applied when total number of rasters (Nr + 2) is even, or
when (Nr + 2) is odd and total number of vertical characters
where, (Nvt + 1) is even.
: Cycle Time of CLK (Character Clock) where,
Nhi: Programmed Value of Horizontal Total Register Rt : Num b er of Total Rasters per frame
(RO) (Including retrace period)
Number of Vertical Total Characters Nvt : Pr o grammed Value of Vertical Total
Vertical deflection frequency is given by specification of Register (R4)
CRT display unit. Number of v ertical Total characters is Nr: Programm ed Value of Maximum Raster
determined by the following equation. Address Register (R9)
I) Non-interlace Mode Nadj: P r ogrammed Value of Vertical Total Adjust
Rt = (Nvt+ 1)(Nr+ I)+ Nadj Register (RS)
2) Interlace Sync Mode Horizontal Sync Pulse Width
Rt = (Nvt + 1) (Nr + I) + Nadj + 0.5 Horizontal sync pulse width is programmed to low order
3) Interlace Sync & Video Mode 4-bit of horizontal sync width register (R3) in unit of horizontal
character time. Programmed value can be selected within from I
to 15.
 Page 0.169

HD68458, HD68A45S, HD68845S

Horizontal Sync Position Vertical Sync Position

As shown in Fig. 24, horizontal sync position is normally
selected to be in the middle of horizontal blank period. But
there are some cases where its optimum sync position is not
located in the middle of horizontal blank period according to
specification of C RT. T herefore, horizontal sync position
should be determined by specification of CRT. Horizontal sync
pulse position is programmed in unit of horizontal character
time.
As shown in Fig. 25, vertical sync position is normally
selected to be in the rniddle of vertical blank period, But there
are some cases where its optimum sync position is not located in
the middle of vertical blank period according to specification of
CRT. Therefore, vertical sync position should be determined by
specification of CRT. Vertical sync pulse position is pro-
grammed to vertical sync position register (R7) in unit of line
period.

• How to Decide Parameters Based on Screen Format

Dlsprue Dot Number of Characters (Horizontal)
H O ld
V ol
tdl
P HH I l H O HO HI ~
SI~
H O o I dl
ve peed
Dot number of characters (horizontal) is determined by
character font and character space. An example is shown in Fig.
26. More strictly, dot number of characters (horizontal) N is
Figure 24 Time Chart of HSYNC determined by external N-counter. Character space is set by
means shown in Fig. 27,
Dot Number of Characters (Vertical)
Vertical Sync Pulse Width Dot number of c haracters(vertical) is determined by
Vertical Sync Pulse Width is programmed to high order 4-bit characters font and line space. An example is shown in Fig. 26.
of vertical sync pulse width register (R3) in unit of raster Dot number of characters(vertical) is programmed to maximum
period. Programmed value can be selected within from 1 to 16. raster address (register R9) of CRTC. When Nr is programmed

Vertical Vertical Vertical

Video Period Blank Video Period

D ISPTMG

VSYNC

Figure 25 Time Chart of VSYNC

Don Number of
Horizontal Character „
haracter
Character Font ce

• • •
Dot Number of
Vertical Characters
lNumber of Rasters)

Line
Space

Dot Number of Horizontal Characters 10

Dot N u mber of Vertical Characters 13
7>'9 Character generator is used.

Figure 26 Dot Number of Horizontal and Vertical Characters

page D.170

HD68458, HD68A458, HD688458

Character Font

• • •

' •
, •

' •

"0" "0" "0"

Serial Data
Shift R egister

Figure 27 How to Make Character Space

H orizontal Deflect ion Period (t h ) = - 1

fh

Horizontal Display Period Horizontal Retrace Period

Number of Horizontal Displayed Characters

'c
Horizontal Display Period
Horizontal Character Time-
Number of Horizontal Displayed Characters

Figure 28 Number of Horizontal Displayed Characters

value of R9, dot number of characters (vertical) is(Nr+1).
Number of Horizontal Displayed Characters
Number of horizontal displayed characters is programmed to
horizontal displayed register (Rl ) of the CRTC. Programmed
value is based on screen format. Horizontal display period,
which is given by specification of horizontal deflection fre-
quency and horizontal retrace period of CRT display unit,
determines horizontal character time, being divided by number
of horizontal displayed characters. Moreover, its cycle time and
access time which are necessary for CRT display system are
determined by horizontal character time.
Number of Vertical Displayed Characters
Number of vertical displayed characters is programmed to
vertical displayed register (R6). Programmed value is based on
screen format. As specification of vertical deflection frequency
of CRT determines number of total rasters (Rt) including verti-
cal retrace period and the relation between number of vertical
displayed character and total number of rasters on a screen ls
as mentioned above, CRT which is suitable for desired screen
format should be selected,
For optimum screen format, it is necessary to adjust number
of rasters per line, number of vertical displayed characters, and
total adjust raster (Nadj) within specification of v ertical
deflectionfrequency.
Scan Mode
The CRTC can program three-scan modes shown in Table l 1
to interlace mode register (RB). An example of character display
in each scan mode is shown in Fig. 7.
 page D.171

HD6845S, HD68A45S, HD688456

Table 11 Program of Scan Mode Cursor Display Method

Cursor start raster register and cursor end raster register
Scan Mode Main Usage (Rlp, Rl I) enable programming the display modes shown m
0 0 Normal Display of Characters Table 7 and display patterns shown in Fig. 8. Therefore, it is
Non inter lace possible to change the method of cursor display dynamically
1 0 & Figures
according to the system conditions as well as to realize the
Fine Display of Characters cursor display that meets the system requirements.
0 1 Interlace Sync
& Figures Start Address
Start address resisters (R12, R13) give a n offset to t h e
Display of Many Characters
Interlace Sync address of' refresh memory to read out. This enables paging and
& Figures Without Using scrolling easily.
& Video
High-resolution CRT Cursor Register
Cursor registers (R14, R(5) enable programming the cursor
display position on the screen. As for cursor address, it is not X,
[NOTE] In the interlace mode, the number of times per Y address but linear address that is programmed.
sec. in raster scanning on one spot on the screen
is half as many as that in non-interlace mode. • EXAMPLES OF APPLIED CIRCUIT OF THE CRTC
Therefore, when persistence of luminescence is Fig. 30 shows an example of application of the CRTC to
short, f)ickering may happen, It is necessary to monochrome character display. Its specification is shown in
select optimum scan mode for the system, taking Table 12. Moreover, specification of CRT display unit is shown
characteristics of C RT, r aster scan speed, and in Table 13 and initializing values for the CRTC are shown in
number of displayed characters and figures into Table 14.
account.
Table 12 Specification of Applied Circuit

Item Specification
Character Format 5 x 7 Dot
Character Space Horizontal: 3 Dot Vertical: 5 Dot
One Character Time 1 Its
Number of Displayed Characters 40 characters x 16 lines = 640 characters
Access Method to Refresh Memory Snychronous Method (DISPTMG Read)
Refresh Memory 1 kB
2 15 214 2 1 3 2 1 2 2 l 1 2 1 0 2 9 28 2 1 26 25 24 23 22 21 20

Refresh
Memory
p p p p p p • • • • * • • • •

CRTC
Address Map Address 0 0 0 1 0 0 x x x x 0
Register
CRTC
Control 0 0 0 1 0 0 • x x x x x x x x 1
Register
x . . don't care, 0 or 1
Synchronization Method HVSYNC Method

Table 13 Specification of Character Display

Item Specification
Scan Mode Non-interlace
Horizontal Deflection Frequency 15.625 kHz
Vertical Deflection Frequency 60.1 Hz
Dot Frequency 8 MVz
Character Dot (Horizontal x Vertical) 8 x 12 (Character Font 5 x 9)
Number of Displayed Characters (Row x Line) 40x 16
HSYNC Width 4 Its
VSYNC Width 3H
Cursor Display Raster 9- 10, Blink 16 Field Period
Paging, Scrolling Not used
Page D.172

HD68458, HD68A458, HD68B45S

Table 14 Initializing Values for Character Display

Initializing Value
Register Name Symbol
Hex (Decimal)
RO Horizonta I Total Nht 3F (63)
Rt Horizontal Displayed Nhd 28 (40)
R2 Horizontal Sync Position Nhsp 34 (82)
R3 Sync Width Nvsw, Nhsw 34
R4 Vertical Total Nvt 14 (20)
R5 Vertical Total Adjust Nadj 08 ( 8)
R6 Vertical Displayed Nvd 10 (16)
R7 Vertical Sync Position Nvsp 13 (19)
R6 Interlace & Skew 00
Maximum Raster Address Nr OB (11)
R10 Cursor Start Raster 8, P, Ncs7aR7 49
R11 Cursor End Raster NcENo OA (10)
R12 Start Address (H) oo ( 0)
R13 Start Address (L) 00 ( 0)
R14 Cursor (H) 00 ( 0)
R15 Cursor (L) 00 ( 0)

t c 1 us

0 123 4 5 6 7 0 1234567 0 1 2 3 4 5 6 7

Cursor
Figure 29 Non-interlace Display (Example)
 Page 0.173

HDB8458, HDBBA45S, MD88845S

5
> LV-EL'

C
0

X
I-
U
IZ

O
0

I LL-4L- 8
0

a
o* o o
0
I 'eYcbbn '«'
E
a
X
UJ

o0)

Ol
LL

P
I
page 0.174

HD88458, HD68A45S, HD688456

Differences between the HD6845R (Motorola MC6845 Compatible) and the HD6845S (Enhanced)
No. Functional Difference HD6845R HD68458

Interlace Programming Character line address Character hne address

Sync Methon
of ABC Programming 0 A B C Programming
number of unit for unit for
number of
1
vertical number of
Video Mode characters vertical 3
2 verucal
Display characters characters
5
4

7
6

9
8

In HD8845R, number of cnaraclers is vertically In HD8845S, number of characters is vertically

programmed in units of two lines, as illustrated programmed in unrt of one line, as illustrated
above. (Number of vertical total characters, above. (Number of vertical total characters,
Number of vertical displayed characters. Number of vertical displayed characters,
Vertical Sync Position) Vertical Sync Position)

Example of above figure Example of above figure

Programmed number mto Vertical Displayed Programmed number into Vertical Displayed
Register = 5 Register = 10

Number of Both even number and odd number can be

raster per Only even number can be specified specified.
character Character Character
line 0 line address line address
I
2 0
-3 I 1
4 Number of raster 2 2
6
-5
- - - - - - - - - 0- -7

C haracter 0
4
-0 - - - - - - - - — 0-
-5
—3

-- — — — 0 — 7
'ut= - - -

— 0-- — --- -- — 0- — 7
-

- i'
—3

6
-8- -0 - 0 - - - - I line address
-3 -6- -6 - 0 - — - — I —2
— --- - - - -0--5 2 3
3 — 0 - - - - - - - - - 0. — 4
4
— 0- -0- -8 — -& -——-7 I
6 - —————————————— 9 6
—0-6-- 8 - - 6 - -- - 7
5
Number of raster = 10 scanline (specrfied)
When number of raster When number of raster
However, number which is programmed into per character line per cnaracter iine
register is calculated as follows. is EVEN is ODD

Programmed number (Nr) Number of raster Number of raster

= 10 scan line = 8 scan line
= (Number specified) — 1
(specified) (specified)

However, number which is programmed into

register is calculated as follows

Programmed number (NR)

= (Number specified) — 2

Cursor Cursor is displayed in either EVEN field Cursor is displayed in both EVEN field
Display or ODD field. and ODD field.
0
I
~ EV E N number
3
I
2 M W W - 6 7 — ta-~ EVEN n u m ber — 0-0--8- 5
3 ~ EV E N number
4 4 ) — 47 —
t) —47—tt- 7
5
6 ~ H3 - H s-~ ~ EV EN n u m b er
7
I
3 ~ O D D n umber
I
5 ~ O D D n u mber
— 0 - 0- Et - -6 — 0-- 3 ~ OD D nu m b e r
4 7
— 0 -0--0 - 0 — 0--5 ~ OD D nu m b e r
6

~ EV E N number
3
5~ O D D n u mber
7
 Page 0.175

HD6845S, HD68A45S, HD68B45S

No. Functional Difference HD5645R HD6545S

Vsrhcai Sync Fixed at 16 raster scan cycle (16H) Programmable (I - 16 raster scan cycle)
Pulse Width
Specified by
fVSYNC output)
4- F i xed at 16 high Order
scan cycle 4b t s o f R3
VSYNC VSYNC

R3 R3 ~ w v 3 Wv2 Wvf Wvo

Vertical Sync H o r i zontal Sync

Not used Horizontal Sync Width Width Width

SKEW Function Not included SKEW capability is mciuded in DISPTMG,

CUDISP signals.

Attached byte

RS C Co O Ov V S
RS V S

CUDISP DISPTMG
Not used
Example of DISPTMG output
N
One character skew
Two character skew
'I character time
2 character time

Start Address Resister Wnte Only Read or Wnte

RESET Sipnsi IRESI MAs - M,s Output

-- -
RAs - ftAv Output
Other Outputs - — — - - -
- - Sy n chronous reset MA' - MA,s Output.
RAs - RA, Output - - Asynchronous reset
A synchronous reset
Other Outputs

O utput signals ol MAs M Ai s, RAs R A < ,

synchronized with CLK "LOW" level, go to Output signals of MAp M A s, RAp R A , and
"LOW" level, after RES has gone to "LOW." others go to "LOW" level immediately after
Other outputs go to "LOW" immediately after RES has gone to "LOW" level
RES has gone to"LOW" level.

AC Characterlatlc Differences between HD6845R (Motorola MC6845 Compatible) and HD6845S (Enhanced)
HD46505R HD46505S
No. Characteristic Difference Symbol min. ly p max. min. lyp max. Unit

Clock Cycle Time royce 330 270 ns

Clock Pulse Width "High" P yycrv 150 130 ns

Clock Pulse Width "Low" Pyycu 150 130 ns

Rise and Fall Time for Clock Input Tcn, Tcr 15 20 ns

Horizontal Sync Delay Time THso 250 200 ns

Light Pan Strobe Pulse Width p yyu pvv 80 60 ns

Light Pan Strobe, Ti vol 80 70 ns

Uncertain Time of Acceptance
Tvsoz 10 0 ns
Page 0.1?6

SCHOTrKY t SERIES 14 AND 18

PROMS PROGRAMMABLE READ-ONLY MEMORIES
J LINE 1 9 8 1

• Ti tanium-Tungsten (Ti-W) Fuse Link For Re- • Ap plications Include:

liable Low-Voltage Full Family Compatible Microprogramming/Firmware Loaders
Programming Code Converters/Character Generators
Translators/Emulators
• Fu ll Decoding And Fast Chip Select Simplify Address Mapping/Look-Up Tables
System Design
• P-N-P Inputs For Reduced Loading On System
Buffers/Drivers

NEW TYPE NUMBER OLD TYPE NUMBER TYPICAL PERFORMANCE

BIT SIZE OUTPUT
ADDRESS POWER
0 C to 70*C O'C to 70'C (ORGANIZATION) CONFIGURATIONt
ACCESS TIME DISSIPATION
TBP18SA030 (J, N) SN745188 (J, N) 256 Bits
25 ns 400 mw
TBP18S030 (J, N) SN745288 (J, N) (32W X 88)
TBP14510 (J, N) SN745287 (J, N) 1024 Bits
42 ns 500 mw
TBP14SA10 (J, Nl SN74S387 (J, Ni (256W X 48)
TBP18SA22 (J, N) SN745470 (J, N) 2048 Bits
50 Ils 550 mw
TBP18S22 (J, N) SN745471 (J, N) l256W X 88)
TBP18542 (J, N) SN745472 (J, N) 4096 Bits
600 mw
55 ns
TBP18SA42 (J, N) SN745473 (J, N) (512W X 88)
TBP18S46 (J, Nl SN745474 (J, N) 4096 Bits
55 ns 600 mW
TBP18SA46 (J, N) SN745475 (J, Nl (512W X 88)

For f u l l t e m p e r a t u r e p a r t s ( — 55*C i o + 1 2 5 Cl u ee s u f f i x M J For d e v i c es wi th M I L S T O 8 8 3 8 p r o c e s s ing I — 55 C io • 1 2 5 C ) ee e P a ge 2 2,

1Q — open collector, sv7 = th r e e s t o i c .

TBP18SA030, TBP18S030 T B P 14S10, TBP14SA10 TBP18SA22, TBP18822 TBP18842, TBP18SA42 TBP18546, TBP18SA46
256 BITS 1024 BITS 2048 BITS 4096 BITS 4096 BITS
(32 WORDS BY 8 BITS) ( 2 5 6 WORDS BY 4 BITS) (256 WORDS BY 8 BITS) (512 WORDS BY 8 BITS) (512 WORDS BY 8 BITS)
(TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW)

00 ie VCC A6 i ie VCC AO zo VCC AO zo VCC A7 34 VCC

01 ie G AS is A7 A1 ie A7 A1 » A8 A6 zi AS
02 8 A4 A4 3 14 G2 A2 3 » A6 A2 3 ie A7 AS zz NC
Q3 4 o A3 A3 4 iz G1 A3 » AS A3 ir A 6 A4 4 zi G4
04 4 iz A2 AO e iz 00 A4 'e G2 A4 'e AS A3 ro G1
05 4 11 A1 A1 4 01 00 ie G1 00 14 G A2 e ie G3
06 r io AO A2 7 io 02 01 " 07 Q1 u Q7 A1 ie G2
GND e 07 GND 4 Q3 02 '3 Q6 Q2 ir Q6 AO 4 11 07

03 4 Q5 03 e iz Q5 00 e 14 06
GND io 11 Q4 GND io ii 04 01 i o is 05
Q2» Q4
GND i r Q3
Pin eeelgnmente for all of these memories are the same for the J and N packages, See Product Guide, Section 7, for chip carrier pin assignments.

description
These monolithic TTL programmable read-only memories (PROMs) feature titanium tungsten (Ti JWl fuse links with
each link designed to program in 100 microseconds. The Schottky-clamped versions of these P ROMs offer considerable
flexibility for upgrading existing rlesigns or improving new designs as they feature full Schottky clamping for improved
performance, low-curl ent MOS-compatible p.n p inputs, choice of bus-driving three state or open collector outpiits, and
improved chip-select access times.
T he high-complexity 2 0 48- and 4 096-bit PROMs can I>e used to significantly i m prove system density fo r f i xed
memories as all are offered in the 20-pin dual-in-line package having pin-row spacings of 0.300 ini:h (7,62 mm)
 Page 0.177

SERIES i4 AND 18
PROGRAMMABLE READ-ONLY MEMORIES

logic symbols

TBP14810 TBP18822
TBP18S030 PROM 2ti X 4 PROM RN X 0
(5) (11
PROM 32 X • As IS(
(Ot (21 A 'V
Al 17)
(11 171 (12) AP al
A 17 Al AV A2 (31 (Sl
AP 12) lit (111 (41 AP
(10) 0 A'(7 8 Is)
0 (3) 10 15) A A 03
IIII 255 Ap M 155 III
(41 (21 IN A '\7
(12) 4 \7 *5 117( (121
31 AP Sl lll (I • I A'V
Al (131 lil (15) 11!tl (13(
(I •I AI I Al I
AP
4
I I) (101 AP (14)
(151 AP GE (141 G2 5
0 EN (sl EN EN
AP OI Gl 1131 GI 1151

TBP14SA10 TBP18SA22
TBP18SA030 PROM 250X • PROM 2MX •
PROM 33X • AO t51 III
Nl A (7 IOI
(21
I I) 171 IIN (31 (I) at
4 (7 A 3)
14( (111 ( •I 4 () I• I
(10( 4 () at 0 A() 0
(3( 131 10 (51 * A (3 (01
till 255 A «t M NS (I 'll
I IN (4I (2) I• ( (»I A (I
lil A 13 l(21
Oi t)l (10) AO
AE 113) Iil AO (13)
Al 1101 A ()
*4 11• I 171 llil
I
(101 4 ))
(141
1151 5
f. N Nl (131 EN (15) EN

TBP18846
PROM 512 X 0
Nl 0
TBP18S42 171 (st
AI AV 00
PROM 512 X • Ii) I(s)
Ap
I It 0 (dl (11(
AP (0) AP
(4) A
0 1131
13t AP (71 Ap
(01 (3) A 'V ll • I
ii
(•I AV (151
(Sl 40 AP
15) 0 AV (11 ((N
511 A P ( I (I AP
(15) (23) Ap (171
1171 AV (12)
Gi 121)
(10( AP 1131 (IN 0
I(il
iS "" AP GE (1st EN
0 " " 01 120)
EN

TBP18SA46
• ROM 5(l X •
TBP18SA42 I• I 0
PROM 512 X • (7) 4 (3 Is) 00
11) IOI 1101
0 (Ol 4 ()
AQ A3 15) 4 (3 (111
171 (•) 0 (131
(3( A (3 "5»
A0 N) (3( i(it
141 A5 )2)
10) (1 51
M ISI 0
(11) (I)
AO
II • I
(10( 8 11 A Q A (3
(121 1231 O7)
(17) A0 A 8)
113) 1211
(I • ( A(3 &
(14( II • I
110) iQ 02 11 • I EN
(15( (201
E.N
Page 0.178

SERIES 14 AND 18
PROGRAMMABLE READ-ONLY MEMORIES

description (continued)
Data can be electronically programmed, as desired, at any bit location in accordance with the programming procedure
specified. All PROMs, except the TBP14S10 and TBP14SA10 are supplied with a low logic-level output condition stored
at each bit location. The programming procedure open-circuits Ti-W metal links, which reverses the stored logic level at
selected locations. The procedure is irreversible; once altered, the output for that bit location is permanently program-
med, Outputs that have never been altered may later be programmed to supply the opposite output level. Operation of
the unit within the recommended operating conditions will not alter the memory content.
A low level at the chip-select input(s) enables each PROM The opposite level at any chip-select input causes the outputs
to be off.
The three-state output offers the convenience of an open-collector output with the speed of a totem-pole output; it can
be bus-connected to other similar outputs yet it retains the fast rise time characteristic of the TTL totem-pole output.
The open-collector output offers the capability of direct interface with a data line having a passive pull.up.
schematics of inputs and outputs

EQUIVALENT OF TYPICAL OF ALL TYPICAL OF ALL

EACH INPUT OPENC O L L EC TOR OUTPUTS THREESTATE OUTPUTS
VCC
VCC
58 n NQM
OUTPUT

INPUT
OUTPUT

P rogram m i n g c i r c u i t not show n P rogram m i n g c i r c u i t n o t s h o w n

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1) 7V
Input voltage 5.5V
Off-state output voltage 5.5V
Operating free-air temperature range: F u ll-temperature-range circuits — 55 C to 125 C
Commercial-temperature-range circuits 0 Cto7 0 C
Storage temperature range — 65 Cto150 C

recommended conditions for programming the TBP18S', TBP18SA', TBP14S', and TBP14SA' PROMs
M IN NO M MA X UNIT
Steady state 4 75 5 5.25
supply voltage. v cc (see Note 1)
Program pulse 9 9. 2 5 9 5

Input voltage High level, V IH 2.4 5

Low level, Vi L 0 05
See lOad CirCu i
Termination of all o u t p ut s except the one to be programmed
(Figure ll
Voltage applied to output to be programmed, VO( , l ( see Note 21 0 0 25 0 3
Ouration of VCC programming pulse X (see F igure 2 and Note 3) 15 25 100 ps
Programming duty cycle for Y pulse 25 35
Free-air temperature 20 25 30 'C

A bsolut e m a x i m u m r a t i ngs.
N OTE S 1 . V o lt a g e v a l u e s a r e w i t h r e s p ec t t o n e t w o r k g r o u n d t e r m i n a l . T h e s u p p l y v o l t a g e r a t i n g d o e s n o t a p p l y d u ri n g p r o g r a m m i n g .
2 T h e T B P 1 8 S 0 30, TBP18S A 0 3 0, TBP18S A 2 2, TBP18S 22, TBP18S42. TBP18S A 4 2, TBPtBS46 and TBP te S A 4 6 are suoolied with
a ll bit l o c a t i o n s co n t a i n i n g a low l o gi c level, and pr o g r a m m i n g a bi t c h a n ges th e o u t pu t o f t h e b i t t o h i g h l o g c l e v el . Th e T B P 1 4 S 1 0 ,
T BP 14SA 1 0 are supp l ied w i t h a l l b i t o u t p u t s a t a h i g h l o g i c l e v el, and p r o g r a m m i n g a bi t c h a n ges it t o a l o w l o g i c l e v e l .
3 P r o g r a m m i n g i s gu a r a n t eed i f t h e l i u l se ap p l ied as 98 ft s in d i i r a t i o n .
 page 0.179

SERIES 14 AND 18
PROGRAMMABLE READ-ONLY MEMORIES

step-by-step programming procedure for the T BP18SA030, TBP18S030, TBP14S10, TBP14SA10,

TIP18SA22, TBP18S22, TBP18SA42, TBP18S42, TBP18S46, TBP18SA46
1. A p p l y steady-state supply voltage (VCC = 5 V) and address the word to be programmed.
2. V e r if y that the bit location needs to be programmed. If not, proceed to the next bit.
3. I f t h e b i t r e quires programming, disable the outputs by applying a high-logic-level voltage to the chip-select
input(s).
Only one bit location is programmed at a time, Connect each output not being programmed to 5 V through
3.9 kQ and apply the voltage specified in the table to the output to be programmed. Maximum current into the
programmer output is 150 mA.
Step VCC to 9.25 nominal. Maximum supply current required during programming is 750 mA.
6. A p ply a low-logic-level voltage to the chip-select input(s). This should occur between 1 ps and 1 ms after VCC
has reached its 9.25 level. See programming sequence of Figure 2.
7. A f t e r t h e X p u lse time is reached, a high logic level is applied to the chip-select inputs to disable the outputs.
8. W i t hin the range of 1 ps to 1 ms after the chip.seiect input(s) reach a high logic level, VCO should be stepped
down to 5 V at which level verification can be accomplished.
9. T h e chip-select input(s) may be taken to a low logic level (to permit program verification) 1 ps or more after
VOO reaches its steady-state value of 5 V.
10. A t a Y p u lse duty cycle of 35% or less, repeat steps 1 through 6 for each output where it is desired to program
a bit.
11. V e r ify accurate programming of every word after all words have been programmed using VCC values of 4.5 and
5.5 volts,
NQTE : o n ly o n e o r ogramming attempt per bit is recommended.

SV

3.9 kn
OUTPUT

LOAD CIRCUIT FOR EACH OUTPUT

NOT BEING PROG R A M M E D O R FO R
PROGRA M V E R IFICATION

FIGURE 1 — LOAD CIRCUIT

VERIFY I- Y
NEED To ~ 9.25 V
PROGRAM I REMOVE VCC TO
REDUCE AVERAGE — — 5V
VCC POWE R
1 srs to 1 ms OV
1 peto 1 ms
I- X - I

APPLY REMOVE
VO(pri yoipri

F IGURE 2 — VOLTAGE WAV E F O R M S FOR PROGR A M M I N G

Page 0.180

SERIES 14 AND 18
PROGRAMMABLE READ-ONLY MEMORIES
WITN 3-STATE OUTPUTS
recommended operating conditions
TBP14S10, TBP18S22 TBP188030 TBP18842, TBP18846
PARAMETER UNIT
MIN NOM M AX M IN NOM M AX M IN NOM M AX
MJ 45 5 5 5 4.5 5 5.5 45 5 55
Supply voltage, VCC
J,N 4.75 5 5 25 4.75 5 5 25 4 75 5 5 25
MJ
H igh-level output current, Ip H mA
J,N
L ow level output current, Ip L 16 20 12 mA
— 55 125 — 55 125 — 55 125
Operating free air temperature, TA
70
c
J,N 70 70 0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
FULL TEMP COMM. TEMP
PA RAM ETE R TEST COND ITIONS (MJ) (J, N) UNIT
M IN T YP ' MAX M IN T Y P' MAX
V IH High level inpu t voltage
VIL Low-level input vo l t age 08 0.8
VIK Input clamp voltage VCC = MIN, Ii - — 18 mA — 1.2 1.2
= MIN, VIH — 2 V,
VCC
VpH High level output v o l t age 2 4 34 24 3 2
= 08 V, IpH = MA X
ViL
= 2V,
VCC = MI N , VIH
VpL Low-level output v o l t age 0.5 0.5
= 08 V, IpL — MAX
ViL
=
O ff-state output c u r r en t , VCC = MA X , VIH 2 V,
50 50
IOZH high-level voltage applied Vp = 24V
P ff state out pu t c u r r en t , VCC = MA X , VI H = 2 V,
lpzL — 50 — 50 IrA
low level voltage applied Vp — 0.5 V
I nput current at m a x i m u m
VCC — MAX, Vi — 5.5 V mA
input voltage
High level input cu r rent = MAX, = 27V 25 25 fr A
IIH VCC Vi

IIL L ow level in pu t c u r r e n t VCC — MAX, V i -0 5 V — 250 250 fr A

Ips Sho r t - c i rcuit ou t put current xi VCC = MAX -30 — 100 30 — 100 mA
VCC — MAX, TBP14510 100 13 5 100 13 5
C hip select(s) at 0 V , TBPI BS030 80 110 80 1 10
Supply current mA
Outputs open, TBP18522 110 15 5 1 10 15 5
See Note 4 TBPIBS42, TBP18546 120 15 5 1 20 1 55
switching characteristics over recommended ranges of TA and VCg (unless otherwise noted)
ta(A) (ns) ta(S) (ns) tf XZ (ns)
Access t i me f rom Access time from Disable time from
TYPE TEST COND ITIONS UNIT
address chip select (enable time) high or low level
MIN TY P l MAX MIN T YP i M AX MIN TY P i MA X
TBP14510MJ 42 75 15 40 12 40 ns
TBP14510 42 65 15 35 12 35 iis
= 30 pF for
TBPI BS030M J CL
25 50 12 30 8 30 ns
TBPI BS030 ta(A) and ta(S), 25 40 12 25 8 20 ns
5 pF for t p X Z ,
TBPI BS22MJ 50 80 20 40 15 35 ns
Seo Page I 12
TBP18522 50 70 20 35 15 30 ns
TBPIBS42MJ, TBPIBS46MJ 55 85 20 45 15 40 iis

TBP18542, TBP18546 55 75 20 40 15 35 ns

NOTE M J desi gn at e s f ul l - t e m p e r a t u r e - r a n g e c ircu it s (f or m e r l y 5 4 F am i l y) , J snd N desi g r i a t o c o m m er c i a l t e m p er a t u r e r a n g e c i r c u i t s

( form e rl y 7 4 F s m i l y l
l F or c o n d i t i o n s s h o w n s s M I N o r M A X , u s s t h e a p p r o p r i a t e v a l u e s n e c i f i e d u n d e r r e c o r n r n o n d o d o p e r a t i n g c o n <t i t i o n s
A il t y p i c a l v a l u e s sr e a t V C C 5 V , TA 25 C.
N ot n i o r e t h a n o n e o u t p u t s h o u l d u e s h o r t e d a t s t i m e a n d d u r a t i o n o f t h e s h o r t c i r c u i t s h o u l d n o t e x c e e d o n e s e c o n d .
NOTE 4 T h o t y p i c a l v a l ues of I CE sre wit h al l o u t p u t s l o w .
 page D. 181

SERIES 14 AND 18
PROGRAMMABLE READ-ONLY MEMORIES
WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
TBP14SA10, TBP18SA22 TBP18SA030 TBP18SA42, TBP18SA46
PARAMETER UNIT
M IN NPM M AX MIN NOM M AX M IN NOM M AX
MJ 4.5 5 5.5 45 5 55 4.5 5 55
Supply voltage, VCC
4.75 5 5 25 4,75 5 5 25 4.75 5 5.2 5
High-level output voltage, VpH 5.5 5.5 5,5
Low-level output current, lpL 16 20 16 mA
MJ — 55 125 — 55 125 — 55 125
Operating free-air temperature, TA
J,N 0 70 70 70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS1 MIN T Y P r MAX UNIT
VIH High-level input voltage
VIL Low-level input voltage 0.8
VIX Input clamp voltage VCC = MIN , li = — 18 mA — 1.2
VCC = M I N ,
VpH = 2 4 V 50
IpH High.lovel output current V,H = 2 V, JiA
V p H = 5.5 V 100
ViL = OS V
=
VCC = MI N , VIH 2 V,
VpL Low. evel output voltage 0.5 V
ViL = O B V , IpL = MAX
Input current at maximum input voltage VCC = MA X , Vi = 55 V mA
High 'avel input current VCC = MA X , Vi = 2 7 V 25 fr A
Low ivvel input current VCC = MA X , Vi = 0 .5 V — 250
VCC = MA X , TBP18SA030 80 110
Chip select(sl at 0 V, TBP14SA10 100 135
Supply current mA
Outputs open, TBP18SA22 110 155
See Note 4 TBP18SA42, TBP18SA46 1 20 15 5

switchingcharacteristics over recommended ranges of TA and V cg (unless otherwise noted)

tPLH
ta(S)
ta(A) Propagation delay time,
Access time from
TEST Access t i me f rom low-to-high-level out-
TYPE chip select UNIT
CONDITIONS address put from chip select
(enable time)
(disable time)
M IN TY PI MA X MIN TY P' MAX MIN TYPf MA X
TBP18SA030M J 25 50 12 30 12 30 ns
TBP18SA030 25 40 12 25 12 25 ns
CL = 30pF,
TBP14SA I OM J 42 75 15 40 15 40 ns
RLI = 300 f),
TBP14SA10 42 65 15 35 15 35 ns
R Lz = 600 S),
TBPIBSA22MJ 50 80 20 40 15 35 ns
See Page 1-12
TBPSA22 50 70 20 35 15 30 ns
TB PI BSA42M J, TBP1 BSA46M J 55 85 20 45 15 40 ii s
TBPIBSA42, TBPIBSA46 55 75 20 40 15 35 ns

NOTE : M J de s i gnatesfull temp e r atu re range circuits lfo r m e r ly 54 F a m i l y ) , J a nd N d e s ignate comm e r c i al te m p e r a t u re range c ircuits (fo r m e r l y
74 Family).
t For cond i t i on s show n as MI N o r M A X , us e t he appr o p r i a te value specified un d er r e co m m e n d ed o p e r a ti ng con d i t i o n s .
t All t y p i c a l v a l ues are a t V C C = 5 V , T A = 2 5 C

N OT E 4 T he t y pi c a l v a l u e s o f I C C a r e w i t h a i i o u t o u t l o w .
Page 0.182

SCHOTTKY t SERIES 24 AND 28

STANDARD, LOW-POWER, POWER-DOWN, REGISTERED
PRQMS
PROGRAMMABLE READ-ONLY MEMORIES
J UNE 1 9 8 1

New, Expanded Family of Standard, Low Power, • P-N-P Inputs for Reduced Loading On System
Power Down, And Registered PROMs Buffers/Drivers
• Titanium-Tungsten (Ti-W) Fuse Links for Re- • Each PROM Supplied With a High Logic Level
liable Low-Voltage Full-Family-Compatible Stored At Each Bit Location
Programming
• Applications Include:
• Fu ll Decoding And Fast Chip Select Simplify Microprogramming/Firm Ware Loaders
System Design Code Converters/Character Generators
Translators/Emulators
Address Mapping/Look-Up Tables
STANDARD PROMS
TYPE NUMBER OUTPUT BIT SIZE TYPICAL PERFORMANCE
CONFIGURATION 1 (ORGANIZATION) ACCESS TIMES POWER
NEW TYPE NUMBER OLD TYPE NUMBER
ADDRESS SELECT DISSIPATION
TBP24510 (J. N) 1024 Bits
35 ns 20 ns 375 mW
TBP24SAIO (J, N) (256W X 48)
TBP28542 (J, N)
TBP28SA42
4096 Bits
TBP28S45 (J, N) ta 35 ns 20 iis 500 mW
(512W X 88)
TSP28546
TBP28SA46
TBP24S41(J, Ni SN745476 (J, N) 4096 Bits
40 ns 20 rrs 475 mW
TBP24SA41 (J, N) SN745477 (J, N) (1024W X 4B)
TBP24S81 (J, Ni a SN74S454 (J, N) 8192 Bits
45 ns 20 ns 625 mW
TBP24SA81 (J, N) a SN748455 (J, N) (2048W X 48)
TBP28S86 I J, Nl a SN745478 (J, N)
TBP28SA86 (J, N) SN745479 (J, N) 8192 Bits 45 ns 20 ns 625 mW
TBP2882708 (J, N) SN7452708 (J, N) (1024W X 88)
TBP28585 (J, N) Ta 35 ns 15 ns 550 mW
TBP285166 (J, N) 16,384 Bits
35 ns 15 ns 650 mW
TBP28SA166 (2048W X 88)

LOW POWER PROMS

TYPE NUMBER OUTPUT BIT SIZE TYPICAL PERFORMANCE
CONFIGURATION ' (ORGANIZATION) ACCESS TIMES POWER
NEW TYPE NUMBER OLD TYPE NUMBER
ADDRESS SELECT DISSIPATION
TBP28L22 (J, N) 2048 Bits
45 ns 20 ns 375 mW
TBP28LA22 i256W X 88)
TBP28L42 (J,N)
4096 Bits
TBP28L45 (J, N) ta 60 ns 30 ris 250 mW
(512W X 88)
TBP28L46 (J,N)
TBP28L86 (J, N) SN74LS478 (J, N) 8192 Bits 80 ns 35 ns 350 mW
TBP28L85 (J, N) ta (1024W X 88) 65 ns 30 ns 275 mW
16,384 Bits
TBP28L166 (J, N) fa 65 ns 30 ns 350 mW
(2048W X 88)
All PR OM s are also available in chi p c a r r i ers,
N OTE — Electr i cal paramet ers for t h ese devices are design goals only .
a NOTE — These devices available as f ull-temp e ratu r e-range and as high rel p r o c essed devices (use suffix M J o r N J ) ,
I~ = open collector, three state,
m +
 Page D.183

Floppy Disk Controller Board (Z-207)

page 0.184

N ESTF]FN D / 8 / TA l
C 0 /7 P 0 h' A 7 / 0 N

FD179X-02
FLOPPY DISK FORMATTER/CONTROLLER FAMILY
FEATURES • PROGRAMMABLE CONTROLS
• TWO VFO CONTROL SIGNALS — RG & VFOE Selectable Track to Track Stepping Time
• SOFT SECTOR FORMAT COMPATIBILITY Side Select. Compare
• AUTOMATIC TRACK SEEK WITH VERIFICATION • WRITE PRECOMPENSATION
• ACCOMMO D A TES SINGLE AND DOUBLE DENSITY • WINDOW EXTENSION
FORMATS • INCORPORATES ENCODING/DECODING AND
IBM 3740 Single Density (FM) ADDRESS MARK CIRCUITRY
IBM System 34 Double Density (MFM) • FD1792/4 IS SINGLE DENSITY ONLY
Non IBM Format for Increased Capacity • FD1795/7 HAS A SIDE SELECT OUTPUT
• READ MODE 179X4)2 FAMILY CHARACTERISTICS
Single/Multiple Sector Read with Automatic Search or
FEATURES 1791 ' 1792 1793 ' 1794 1 7 9 5 'I797
Entire Track Read
Selectable 128, 256, 512 or 102< Byte Sector Lengths n~i/ e Density IFM X X X X X
• WRITE MODE Double Densit (MFM) X X X
Single/Multiple Sector Write with Automatic Sector True Data Bus X E X X
Search Inverted Data Bus X X
Entire Track Write for Diskette Formatting
• SYSTEM COMPATIBILITY Write Precomp X X X X
Double Buffering of Data 8 Bit Bi-Directional Bus for Side Selection Output X X
Data, Control and Status APPLICATIONS
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible 8" FLOPPY AND 5'/4" MINI FLOPPY CONTROLLER
On-Chip Track and Sector Registers/Comprehensive SINGLE OR DOUBLE DENSITY
Status Information CONTROLLER/FORMATTER

RAW READ
DATA (8)
RCLK
10 VDD i 1?Vi
AO RGiSSO
/NTRO

CS DRQ LATE

DDE/1' ' '

CS EARLY
AD WPRT WD
RE
A,
WE
"BALD TROD
DAL 1 WF/VFOE MR 179X
DAL 2 READY FLOPPY D/SK WF/VFDE
CONTROLLER
DAL 3 WPRT
FORMATTER
DAL • WG
WG
DAL 5 29 TG43 5V
IP
~ AL j HLD
TROD
PA 1 PAW READ
I OK I OK READY
STEP RCLK
DiRC T G43
C L II DRO STEP
LATE INTRO DIRC
MR TEST CI K
/GND/ VSS VC ( 5V)

HLD
'1791/3 = RG 1795 / 7 = SSO
'' 1793/7 TRUE BUS ONE SHOT
HLT IF USED)
'' 1792ie OPEN DDEN
VSS V D D VCC

P IN C 0 NNE CT I 0 N S
+/2 + 5V

FD179X SYSTEM BLOCK DIAGRAM

 Page D.185

PIN OUTS
PIN
NUMBER PIN NAME SYMBOL FUNCTION
NO CONNECTION NC Pin 1 is internally connected to a back bias generator and
must be left open by the user.
19 MASTER RESET MR A logic low (50 microseconds min.) on this input resets the
device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When MR is
brought to a logic high a RESTORE Command is executed,
regardless of the state of the Ready signal from the drive.
Also, HEX 01 is loaded into sector register.

POWER SUPPLIES Vss Ground

21 Vcc +5V +5%
Voo +12V +5%

COMPUTER INTERFACE:
WRITE ENABLE WE A logic low on this input gates data on the DAL into the
selected register when CS is low.
CHIP SELECT A logic low on t his input selects the chip and enables
computer communication with the device.
READ ENABLE RE A logic low on this input controls the placement of data from a
selected register on the DAL when CS is low.
5,6 REGISTER SELECT LINES AO, A1 These inputs select the register to receive/transfer data on the
DAL lines under RE and WE control:
CS A 1 AO RE WE
0 0 0 StatusReg C o m m a nd Reg
0 0 1 Track Reg Trac k Reg
0 1 0 Sector Reg Sec t o r Reg
0 1 1 D ata Reg Data R e g
7-14 DATA ACCESS LINES DALO-DAL7 Eight bit Bidirectional bu used for transfer of data, control,
and status. This bus is receiver enabled by WE or transmitter
enabled by RE. Each line will drive 1 standard TTL load.
24 CLOCK CLK This input requires a free-running 50% duty cycle square wave
clock for internal timing reference, 2 MHz ~ 1% for 8" drives,
1 MHz ~ 1% for mini-floppies.
DATA REQUEST DRQ This open drain output i ndicates that th e D R c o ntains
assembled data in Read operations, or the DR is empty in
Write operations. This signal is reset when serviced by the
computer through reading or loading the DR in Read or Write
operations, respectively. Use 10K pull-up resistor to + 5.
39 INTERRUPT REQUEST IN TRQ This open drain output is set at the completion of any com-
mand and is reset when the STATUS register is read or the
command register is written to. Use 10K pull-up resistor to
+5.

FLOPPY DISK INTERFACE:

15 STEP STEP The step output contains a pulse for each step.
16 DIRECTION DIRC Direction Output is active high when stepping in, active low
when stepping out.
17 EARLY EARLY Indicates that the WRITE DATA pulse occuring while Early is
active (high) should be s h ifted early for w r ite precom-
pensation.
18 LATE LATE Indicates that the write data pulse occurring while Late is
active (high) should be shifted late for write precompensation.
Page D.186

PIN
NUMBER PIN NAME SYMBOL FUNCTION
22 TEST TEST This input is used for testing purposes only and should be tied
to +5V or left open by the user unless interfacing to voice coil
actuated steppers.
23 HEAD LOAD TIMING HLT When a logic high is found on the HLT input the head is
assumed to be engaged. It is typically derived from a 1 shot
triggered by HLD.
25 READ GATE RG This output is u sed for synchronization of external data
(1791, 1792, 1793, 1794) separators. The output goes high after two Bytes of zeros in
single density, or 4 Bytes of either zeros or ones in double
density operation.
25 SIDE SELECT OUTPUT SSO The logic level of the Side Select Output is directly controlled
(1795, 1797) by the 'S' flag in Type II or III commands. When U = 1, SSO is
set to a logic 1. When U = 0, SSO is set to a logic 0. The SSO
is compared with the side information in the Sector I.D. Field.
If they do not compare Status Bit 4 (RNF) is set. The Side
Select Output is only updated at the beginning of a Type II or
III command. It is forced to a logic 0 upon a MASTER RESET
condition.
26 READ CLOCK RCLK A nominal square-wave clock signal derived from the data
stream must be provided to this input. Phasing (i.e. RCLK
transitions) relative to RAW READ is important but polarity
(RCLK high or low) is not.
27 RAW READ RAW READ The data input signal directly from the drive. This input shall
be a negative pulse for each recorded flux transition.
28 HEAD LOAD HLD The HLD output controls the loading of the Read-Write head
against the media.
TRACK GREATER THAN 43 TG43 This output informs the drive that the Read/Write head is
positioned between tracks 44-76. This output is valid only
during Read and Write Commands.
WRITE GATE WG This output is made valid before writing is to be performed on
the diskette.
31 WRITE DATA WD A 200 ns (MFM) or 500 ns (FM) output pulse per flux transition.
WD contains the unique Address marks as well as data and
clock in both FM and MFM formats.
32 READY READY This input indicates disk readiness and is sampled for a logic
high before Read or Write commands are performed. If Ready
is low the Read or Write operation is not performed and an
interrupt is generated. Type I o perations are performed
regardless of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7.
WRITE FAULT WF/VFOE This is a bi-directional signal used to signify writing faults at
VFO ENABLE the drive, and to enable the external PLO data separator. When
WG = 1, Pin 33 functions as a WF input. If WF = 0, any write
command will immediately be terminated. When WG = 0, Pin
33 functions as a VFOE output. VFOE will go low during a read
operation after the head has loaded and settled (HLT = 1). On
the 1795/7, it will remain low until the last bit of the second
CRC byte in the ID field. VFOE will then go high until 8 bytes
(MFM) or 4 bytes (FM) before the Address Mark. It will then go
active until the last bit of the second CRC byte of the Data
Field. On the 1791/3, VFOE will remain low until the end of the
Data Field. This pin has an internal 100K Ohm pull-up resistor.
TRACK 00 TROO This input informs the FD179X that the Read/Write head is
positioned over Track 00.

PIN
NUMBER PIN NAME SYMBOL
INDEX PULSE IP
WRITE PROTECT WPRT
37 DOUBLE DENSITY DDEN
GENERAL DESCRIPTION
The FD179X are N-Channel Silicon Gate MOS L SI
devices which performthe functions of a Floppy Disk
Formatter/Controller in a s i ngle chip implementation.
The FD179X, which can be considered the end result
of both the FD1771 and FD1781 designs, is IBM 3740
compatible in single density mode (FM) and System 34
compatible i n D o uble D ensity M ode ( MFM). The
FD179X contains all the features of its predecessor the
F D1771, plus t h e a d de d f e a tures n ecessary t o
read/write and format a double density diskette. These
include address mark detection, FM and MFM encode
and decode logic, window extension, and write precom-
pensation. In o r der t o m a i ntain c ompatibility, t he
FD1771, FD1781, and FD179X designs were made as
close as possible with the computer interface, instruc-
tion set, and I/O registers being identical. Also, head
load control is identical. In each case, the actual pin
assignments vary by only a few pins from any one to
another.
The processor interface consists of an 8-bit bi-direc-
tional bus for data, status, and control word transfers.
The FD179X is set up to operate on a multiplexed bus
with other bus-oriented devices.
The FD179X is TT L c o mpatible on a l l i n puts and
outputs. The outputs will drive ONE TTL load or three
LS loads. The 1793 is identical to the 1791 except the
DAL lines are TRUE for systems that utilize true data
busses.
The 1796/7 has a s ide select output for controlling
double sided drives, and the 1792 and 1794 are "Single
Density Only" versions of the 1791 and 1793 respec-
tively. On these devices, DDEN must be left open.
ORGANIZATION
The Floppy Disk Formatter block diagram is illustrated
on page 5. The primary sections include, the parallel
processor interface and the Floppy Disk interface.
Data Shift Register — This 8-bit register assembles
serial data from the Read Data input (RAW READ)
during Read operations and transfers serial data to the
Write Data output during Write operations.
Data Register — T his 8-bit r egister is u s ed a s a
holding register during Disk Read and Write operations.
In Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift R egister. I n D i s k W r it e o p erations i n-
f ormation is t r ansferred i n p a rallel f rom t h e D a ta
Register to the Data Shift Register.
page 0.187
FUNCTION
This input informs the FD179X when the index hole is en-
countered on the diskette.
This input is sampled whenever a Write Command is recerved.
A logic low terminates the command and sets the Write
Protect Status bit.
This input pin selects either single or d ouble density
operation. When DDEN = 0, double density is selected. When
DDEN = 1, single density is selected. This line must be left
open on the 1792/4.
When executing the Seek command the Data Register
holds the address of the desired Track position. This
register is loaded from the DAL and gated onto the
DAL under processor control.
Track Register — This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents of
the register are compared with th e r ecorded track
number in the ID field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAL. This Register should
not be loaded when the device is busy.
Sector Register (SR) —This 8-bit register holds the address
of the desired sector position. The contents of the register
are compared with the recorded sector number in the ID
field during disk Read or Write operations. The Sector
Register contents can be loaded from or transferred to the
DAL. This register should not be loaded when the device is
busy.
Command Register (CR) — This 8-bit register holds the
command presently being executed. This register should
not be loaded when the deviceis busy unless the new
command is a force interrupt. The command register can
be loaded from the DAL, but not read onto the DAL.
Status Register (STR) — This 8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed. This
register can be read onto the DAL, but not loaded from the
DAL.
CRC Logic — This logic is used to check or to generate the
16-bit Cyclic Redundancy Check (CRC). The polynomial is:
G(x) = x" + x" + x ' + 1 .
The CRC includes all information starting with the address
mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the
circuit.
Arithmetic/Logic Unit (ALU) — The ALU is a serial com-
parator, incrementer, and decrementer and is used for
register modification and comparisons with the disk
recorded ID field.
Timing and Control — All computer and Floppy Disk In-
terface controls are generated through this logic. The in-
ternal device timing is generated from an external crystal
clock.
The FD179X has two different modes of operation ac-
cording to the state of DDEN. When DDEN = 0 d ouble
density (MFM) is assumed. When DDEN = 1 , s ingle
page D.f 88

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FD179X BLOCK DIAGRAM

density (FM) is assumed. 1792 & 1794 are single density A1 - AO READ (RE) WRITE (WE)
only.
0 0 Status Register Command Register
AM Detector —The address mark detector detects ID, data 0 1 Track Register Track Register
and index address marks during read and write operations. 1 0 Sector Register Sector Register
1 1 Data Register Data Register
PROCESSOR INTERFACE
During Direct Memory Access (DMA) types of d a ta
The interface to the processor is accomplished through the transfers between the Data Register of the FD179X and the
eight Data Access Lines (DAL) and associated control processor, the Data Request (DRQ) output is used in Data
signals. The DAL are used to transfer Data, Status, and Transfer control. This signal also appears as status bit 1
Control words out of, or into the FD179X. The DAL are three during Read and Write operations.
state buffers that are enabled as output drivers when Chip
On Disk Read operations the Data Request is activated (set
Select (CS) and Read Enable (RE) are active (low logic state) high) when an assembled serial input byte is transferred in
or act as input receivers when CS and Write Enable (WE) parallel to the Data Register. This bit is cleared when the
are active. Data Register is read by the processor. If the Data Register
When transfer of data with the Floppy Disk Controller is is read after one or more characters are lost, by having new
required by the host processor, the device address is data transferred into the register prior to processor readout,
decoded and CS ismade low.The address bits A1 and AO, the Lost Data bit is set in the Status Register. The Read
combined with the signals RE during a Read operation or operation continues until the end of sector is reached.
WE during a Write operation are interpreted as selecting On Disk Write operations the data Request is activated
the following registers: when the Data Register transfers its contents to the Data

Shift Register, and requires a new data byte. It is reset
when the Data Register is loaded with new data by the
processor. If new data is not loaded at the time the next
serial byte is required by the Floppy Disk, a byte of zeroes
is written on the diskette and the Lost Data bit is set in the
Status Register.
At the completion of every command an INTRQ is
generated. INTRQ is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRQ is generated if a Force
interrupt command condition is met.
The 179X has two modes of operation according to the
state of DDEN (Pin 37). When DDEN = 1, single density is
selected. In either case, the CLK input (Pin 24) is at 2 MHz.
However, when interfacing with the mini-floppy, the CLK
input is set at 1 MHz for both single density and double
density.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, DDEN should be
placed to a logical "0." Sector lengths are determined at
format time by the fourth byte in the "ID" field.
Sector Length Table
Sector Length Number of Bytes
Field hex in Sector decimal
00 128
01 256
02 512
1024
03
*1795/97may vary — see command summary.
The number of sectors per track as far as the FD179X is
concerned can be from 1 to 255 sectors. The number of
tracks as far as the FD179X is concerned is from 0 to 255
tracks. For IBM 3740 compatibility, sector lengths are 128
bytes with 26 sectors per track. For System 34 com-
patibility (MFM), sector lengths are 256 bytes/sector with 26
sectors/track; or lengths of 1024 bytes/sector with 8
sectors/track. (See Sector Length Table)
For read operations in 8" d ouble density the FD179X
requires RAW READ Data (Pin 27) signal which is a 200 ns
pulse per flux transition and a Read clock (RCLK) signal to
indicate flux transition spacings. The RCLK (Pin 26) signal
is provided by some drives but if not it may be derived
externally by Phase lock loops, one shots, or counter
techniques. In addition, a Read Gate Signal is provided as
an output (Pin 25) on 1791/92/93/94 which can be used to
inform phase lock loops when to acquire synchronization.
When reading from the media in FM. RG is made true when
2 bytes of zeroes are detected. The FD179X must find an
address mark within the next 10 bytes; otherwise RG is
reset and the search for 2 bytes of zeroes begins all over
again. If an address mark is found within 10 bytes, RG
remains true as long as the FD179X is deriving any useful
information from the data stream. Similarly for MFM, RG is
made active when 4 bytes of "00" or "FF" are detected. The
FD179X must find an address mark within the next 16
bytes, otherwise RG is reset and search resumes.
During read operations (WG = 0), the VFOE (Pin 33) is
provided for phase lock loop synchronization. VFOE will go
active low when:
page D.189
a) Both HLT and HLD are True
b) Settling Time, if programmed, has expired
c) The 179X is inspecting data off the disk
If WF/VFOE is not used, leave open or tie to a 10K resistor
to +5.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette the Write Gate
(WG) output is activated, allowing current to flow into the
Read/Write head. As a precaution to erroneous writing the
first data byte must be loaded into the Data Register in
response to a Data Request from the FD179X before the
Write Gate signal can be activated.
Writing is inhibited when the Write Protect input is a logic
low, in which case any Write command is immediately
terminated, an interrupt is generated and the Write Protect
status bit is set. The Write Fault input, when activated,
signifies a writing fault condition detected in disk drive
electronics such as failure to detect write current flow
when the Write Gate is activated. On detection of this fault
the FD179X terminates the current command, and sets the
Write Fault bit (bit 5) in the Status Word. The Write Fault
input should be made inactive when the Write Gate output
becomes inactive.
For write operations, the FD179X provides Write Gate (Pin
30) and Write Data (Pin 31) outputs. Write data consists of a
series of 500 ns pulses in FM (DDEN = 1) and 200 ns
pulses in MFM (DDEN = 0). Write Data provides the unique
address marks in both formats.
Also during write, two additional signals are provided for
write precompensation. These are EARLY (Pin 17) and
LATE (Pin 18). EARLY is active true when the WD pulse
appearing on (Pin 30) is to be written EARLY. LATE is active
true when the WD pulse is to be written LATE. If both
EARLY and LATE are low when the WD pulse is present,
the WD pulse is to be written at nominal. Since write
precompensation values vary from disk manufacturer to
disk manufacturer, the actual value is determined by
several one shots or delay lines which are located external
to the FD179X. The write precompensation signals EARLY
and LATE are valid for the duration of WD in both FM and
MFM formats.
READY
Whenever a Read or Write command (Type II or III) is
received the FD179X samples the Ready input. If this input
is logic low the command is not executed and an interrupt
is generated. All Type I commands are performed re-
gardless of the state of the Ready input. Also, whenever a
Type II or III command is received, the TG43 signal output
is updated.
COMM AND DESCRIPTION
The FD179X willaccept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one
exception is the Force Interrupt command. Whenever a
command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated
and the Busy status bit is reset. The Status Register
indicates whether the completed command encountered
an error or was fault free. For ease of d iscussion,
commands are divided into four types. Commands and
types are summarized in Table 1.
Page D.190

TABLE 1. COMMAND SUMMARY

A. Commands for Models: 1791, 1792, 1793, 1794 B. Commands for Models: 1795, 1797
Bits Bits
Type Command 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
I R estore 0 0 0 0 V r1 rp 0 0 0 0 V r1 rp
Seek 0 0 0 1 h V r1 rp 0 0 0 1 h V '1 '0
Step 0 0 1 T h V r1 rp 0 0 1 T h V r1 rp
I S tep-in 0 1 0 T h V r1 rp 0 1 0 T h V r1 rp
I S tep-out 0 1 1 T h V '1 rp 0 1 1 T V r1 rp
I I Read Sector 1 0 0 m S E C 0 1 0 0 m L E U 0
II Write Sector 1 0 1 m S E C ap 1 0 1 m L E U ap
I I I Read Address 1 1 0 0 0 E 0 0 1 1 0 0 0 E U 0
III Read Track 1 1 1 0 0 E 0 0 1 1 1 0 0 E U 0
Ill Write Track 1 1 1 1 0 E 0 0 1 1 1 1 0 E U 0
IV Force Interrupt 1 1 0 11 13 12 lt Ip 1 1 0 1 i3 11 Ip

TABLE 2. FLAG SUMMARY

FLAG SUMMARY
Command Bit
T'ype No(s) Description
0,1 r1 rp = Stepping Motor Rate
See Table 3 for Rate Summary

V = Track Number Verify Flag 0, No verify

V
1, Verify on destination track

3 h = Head Load Flag h

0, Load head at beginning
1, Unload head at beginning

T = Track Update Flag 0, No update

1, Update track register

ap = Data Address Mark ap- 0, FB (DAM)

ap- 1, F8(deleted DAM)

C = Side Compare Flag 0, Disable side compare

C
1, Enable side compare

II & III U = Update SSO U 0, Update SSO to 0

U 1, Update SSO to 1

II & III 2 E = 15 MS Delay 0, No 15 MS delay

E
1, 15 MS delay

S = Side Compare Flag 0, Compare for side 0

S
1, Compare for side 1

3 L = Sector Length Flag

LSB's Sector Length in ID Field
00 01 10 11
L = 0 256 512 1024 128
128 256 512 1024

m = Multiple Record Flag m = 0, Single record

m = 1, Multiple records
IV 03 Ix = Int e r rupt Condition Flags
'0 = 1 N o t Ready To Ready Transition
I1 = 1 R e ady To Not Ready Transition
I2 = 1 1 n dex Pulse
(3 = 1 1 m m ediate Interrupt, Requires A Reset
(3-I1 = O Terminate With No Interrupt (INTRQ)
NOTE: See Type IV Command Description for further information.

TYPE I COMMANDS
The Type I Commands include the Restore, Seek, Step,
Step-ln, and Step-Out commands. Each of the Type I
Commands contains a rate field (r0 '1), which determines
the stepping motor rate as defined in Table 3.
A 2/zs (MFM) or 4 /zs (FM) pulse is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.
The Direction signal is active high when stepping in and
low when stepping out. The Direction signal is valid 12/zs
before the first stepping pulse is generated.
The rates (shown in Table 3) can be applied to a Step-
Direction Motor through the device interface.
TABLE 3. STEPPING RATES
CLK 2 MHz 2 MH z 1 MH z 1 M Hz 2 MH z
D DEN 0 0 1
R1 RO T E S T- 1 T ES T 1 TEST 1 T EST - 1 T EST = O T E S T - 0
0 0 3 ms 3 ms 6 ms 6 ms 1 840s
0 1 6 ms 6 ms 12 ms 12 ms 1 900s
1 0 10 ms 10 ms 20 ms 20 ms 1 980s
1 1 15 m S 15 ms 30 ms 30 ms 2 08> s 0 1 6 8 S
After the last directional step an additional 15 milliseconds
of head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms for
a 1 MHz clock. If TEST = 0, there is zero settling time.
There is also a 15 ms head settling time if the E flag is set in
any Type II or Ill command.
When a Seek,Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by settling bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of the
15 millisecond settling time after the head is loaded against
the media The track number from the first encountered ID
Field is compared against the contents of the Track
Register. If the track numbers compare and the ID Field
Cyclic Redundancy Check (CRC) is correct, the verify
operation is complete and an INTRQ is generated with no
errors. If there is a match but not a valid CRC, the CRC error
status bit is set (Status bit 3), and the next encountered ID
field is read from the disk for the verification operation.
The FD179X must find an ID field with correct track number
and correct CRC within 5 r evolutions of t h e m edia;
otherwise the seek error is set and an INTRQ is generated.
If V = 0, no verification is performed.
The Head Load (HLD) output controls the movement of the
read/write head against the media. HLD is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
the end of the Type I command if the verify flag (V = 1), or
upon receipt of any Type II or III command. Once HLD is
active it remains active until either a Type I command is
received with (h = 0 and V = 0); or if the FD179X is in an
idle state (non-busy) and 15 index pulses have occurred.
Page D.191
Head Load timing (HLT) is an input to the FD179X which is
used forthe head engage time.When HLT = 1, the FD179X
assumes the head is completelyengaged. The head
engage time is typically 30 to 100 ms depending on drive.
The low to high transition on HLD is typically used to fire a
one shot. The output of the one shot is then used for HLT
and supplied as an input to the FD179X.
HLO
50 TO 100ms
HL I I>-EIOM ONE DHOTI
HEAD LOAD TIMING
When both HLD and HLT are true, the FD179X will then
1 MHz read from or write to the media. The "and" of HLD and HLT
appears as status Bit 5 in Type I status.
In summary for the Type I commands: if h = 0 and V = 0 ,
H LD is reset. If h = 1 a n d V = 0, H L D i s se t at t h e
3680s beginning of the command and HLT is not sampled nor is
3800s there an internal 15 ms delay. If h = 0 and V = 1, HLD is
3968s
set near the end of the command, an internal 15 ms occurs,
and the FD179X waits for HLT to be true. If h = 1 and V =-
1, HLD is set at the beginning of the command. Near the
end of the command, after all the steps have been issued,
an internal 15 ms delay occurs and the FD179X then waits
for HLT to occur.
For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active, an internal 15 ms delay occurs and then HLT
is sampled until true.
RESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TROO) input is
sampled. If TROO is active low indicating the Read-Write
head is positioned over track 0, the Track Register is loaded
with zeroes and an interrupt is generated. If TROO is not
active low, stepping pulses (pins 15 to 16) at a rate specified
by the r1 r0 field are issued until the TROO input is activated.
At this time the Track Register is loaded with zeroes and an
interrupt is generated. If the TROO input does not go active
low after 255 stepping pulses, the FD179X terminates
operation, interrupts, and sets the Seek error status bit. A
verification operation takes place if the V flag is set. The h
bit allows the head to be loaded at the start of command.
Note that the Restore command is executed when MR
goes from an active to an inactive state and that the DRQ
pin stays low.
SEEK
This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The FD179X will update the Track register and
issue stepping pulses in the appropriate direction until the
contents of the Track register are equal to the contents of
Page D.1 92

HAS
A TYPE NQ
COMIAANO SEEN

YTS
DOES
ss' SUs a EsLT cac TR Q s a
SEEK E4ROR DRO INTRO

NQ

'5
H 5
DSR TR

NQ

aESET DIRECT ON SET DIRECTION

15
CQMLIANO
SET 5
A DIRECT ON DIRECT QN
STEP-IN
I

NO

5
CO Mal AND 4ESET
* 014ECTION TO TR TO TR
STEP OUI'

NQ
'5
HEAD JT
IS TRACK 0 AND
COMMAND D I 4EC TION
A 0
STEP
HQ

ISSUE
15 ONE STEP PULSE
COMMAND
A
SEEK
DELAY ACCORDING
IS TO 4 R e I 'IELD
NU .. R E s TDHE U I

IT TO TR
5
COMMAND
A STEP STEP IN
OR STEP OUT

L 4 To oa
YES

TYPE I COMMAND FLOW TYPE I COMMAND FLOW

the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.
STEP
Upon receipt of this command, the FD179X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the "1r0 field, a verification
takes place if the V flag is on. If the U flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.
STEP-IN
Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track 76. If the U
flag is on, the Track Register is incremented by one. After a
delay determined by the rlr0 field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
STEP.OUT
Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track 0. If the U flag
is on, the Track Register is decremented by one. After a
delay determined by the rlr0 field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
EXCEPTIONS
On the 1795/7 devices, the SSO output is not affected
during Type 1 commands, and an internal side compare
does not take place when the(V) Verify Flag is on.
 Page D.193

again made. If the ID field CRC is correct, the data field is

then located and will be either written into, or read from
depending uponthe command. The FD179X must find an
VERIFY ID field with a Track number, Sector number, side number,
SEQUENCE and CRC within four revolutions of the disk; otherwise, the
V
'5
NTRO RESET BUSY
Record not found status bit is set (Status bit 3) and the
command is terminated with an interrupt.
VES

ENTER
HAS
IS MS
EXPIRED

IS
TYPE R NO
VES COMMAND
RECEIVED
3

5
LT
SET BUSY.RESFT ORO LOST
DATA RECORD NOT FOUND 5
STATUS BITS 5 • 5 INTRO

HAVE IS
5 INDEX VES INTRO NO OI SK
INTRO Rf SET BUSY
HOLES SET SEEK ERROR RESET BUSY READY
PASSE[.

YES

COPY 5 FLAG TO
HAS
SSO LWE I'Tss'I ONLV
IO AM BEEN
DETECTED
SET HLO
YES

DO E 5
TR TRACK
ADDRESS OF ID NO
FIELD I SE I "

YES
YES

\5 'SEE NOTE
SE T THERE * RESET
CRC CflC ERROR CRC «0 HAS
ERROR IS MSR
EXPIREO

YES

INTRO
RESF 3 BUSY

N OTE I T E S T 0 THE R E 3 N U 'AIL CELA

I F TEST I A N D C I K M I F RI \ A TCM L D f A V

TYPE I COMMAND FLOW

IS Yf.s
T R. 4 3 TG43

NO

TYPE IICOMMANDS RESET TO43

The Type II Commands are the Read Sector and Write

Sector commands. Prior to loading the Tyge II Command IS IS
into the Command Register, the computer must load the WRITE
PflO T EC T
V ES CO MM A N D
A
Sector Register with the desired sector number. Upon ON WRITE

receipt of the Type II command, the busy status Bit is set. If NO NO

the E flag = 1 (this is the normal case) HLD is made active
NTRO RESET BUSV
and HLT is sampled after a15 msec delay. If the E flag is 0, SET WRITE PROTECT

the head is loaded and HLT sampled with no 15 msec

delay. The ID field and Data Field format are shown on page • NOTE 3 I fsi
I f TFI T
I HI RI
I AN D I ' I K
N I»
I
M nfl AV
I Hf Rf I IOLI D( LA Y
13.
When an ID field is located on the disk, the FD179X TYPE II COMMAND
compares the Track Number on the ID field with the Track
Register. If there is not a match, the next encountered ID
field is read and a comparison is again made. If there was a Each of the Type II Commands contains an (m) flag which
match, the Sector Number of the ID field is compared with determines if multiple records (sectors) are to be read or
the Sector Register. If there is not a Sector match, the next written, depending upon the command. If m = 0, a single
encountered ID field is read off the disk and comparisons sector is read or written and an interrupt is generated at the
Page D.194

completion of the command. If m = 1, multiple records are
read or written with the sector register internally updated
so that an address verification can occur on the next
recorcl The FD179X will continue to read or write multiple
records and update the sector register in numerical
ascending sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt
command is loaded into the Command Register, which
terminates the command and generates an interrupt.
For example: If the FD179X is instructed to read sector 27
and there are only 26 on the track, the sector register ex-
ceeds the number available, The FD179X will search for 5
disk revolutions, interrupt out, reset busy, and set the
record not found status bit.
pulses, the interrupt line is made active and the Record.
Not Found status bit is set.
The Type II and III commands for the 1795 97 contain a side
select flag (Bit 1). When U = 0, SSO is updated to 0.
Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the ID field. If they do not compare within 5
revolutions the interrupt line is made active and the RNF
status bit is set.
The 1795/7 READ SECTOR and WRITE SECTOR com-
mands include a 'L' flag. The 'L' flag, in conjunction with
the sector length byte of the ID Field, allows different byte
lengths to b e i m plemented in each sector. For IBM
compatability, the 'L' flag should be set to a one.

The Type II commands for 1791-94 also contain side select

compare flags. When C = 0 (Bit 1) no side comparison is
made. When C = 1, the LSB of the side number is read off
the ID Field of the disk and compared with the contents of
the (S) flag (Bit 3). If the S flag compares with the side
number recorded in the ID field, the FD179X continues with
the ID search. If a comparison is not made within 5 index
READ SECTOR
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an ID field is
encountered that has the correct track number, correct
sector number, correct side number, and correct CRC, the
data field is presented to the computer. The Data Address

READ SECTOR
SEOUENCE

YES
As
HAVE DATA ALI
INTRO RESET BUSY INTRO PE'SLT BUS»
SINDEX HOLES OCCVRED
PASSED SET RECORD-NOT FOUND SET RECORD NOT FOUND
IN TIME

NO YES

HAS PIJT RECORD TYPE N

IDAM STATUS REI' BIT S
BEEN
DETECTED

'I E S
PS
I P ET 0 F
BEEN ASSEMBLED
DOES N DSA
TR T R ACK
ADDRESS OF ID
FIELD

YES

DOES
NO SR S ECTOR
ADDRESS OFID
F ELD *S
T NEXT BTTE
BEEN ASST.METED
YES N DSR

DOES YES
S S IDE NO
QF AS
I D FIE L D
DR BEEN
AE JD 0 SET DPTX
COMPUTER LOST
TES DRQ 0

BITING IN SECTOR LENGTH FIELD ES

STORE LENGTH IN NTERNAL
REGISTER
AYE
ALL BYTES
PEEN NP UTTTD

SET CAC YES THERE A NO

RESET
STATUS ERROR CRC ERROR CAC
S
M
CRC
ERAOR

S
CCM FA ID
X I TO
*0 'E READ • ACTOR AEG

NTRO RESET BUSY

YES
SET CRC ERROR
• INTRO RESET BUST

TYPE II COMMAND TYPE II COMMAND

 Page 0.195

STATUS
WIIITE SECTOR BIT 5
SEOUEMCE
1 Deleted Data Mark
0 Data Mark

WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (HLD active) and the Busy status bit is set. When an
A iD field is encountered that has the correct track number,
DA BEEN
LOADED BY INTRO RESET BUSY correct sector number, correct side number, and correct
C0 AIPU TE R ET IOY I I AI A
(ORO 0 CRC, a DRQ is generated. The FD179X counts off 11 bytes
in single density and 22 bytes in double density from the
HO
DDEN
0"
CRC field and the Write Gate {WG) output is made active if
the DRQ is sewiced (i.e H the DR has been loaded by the
TURN ON WG A INR TE
computer). If DRQ has not been sewiced, the command is
6 BYTES Of ZERO'
terminated and the Lost Data status bit is set. If the DRQ
has been serviced, the WG is made active and six bytes of
WRITE DATA ALI
ACCORDING TO AO FIELD
TURN ON WT' S WRITE
IT BYTES Of ZEROS
zeroes in single density and 12 bytes in double density are
Of WRITE COAIMAND
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the a0
field of the command as shown below:
Data Address Mark (Bit 0)
1 Deleted Data Mark
0 Data Mark
HAS
DR BEEf
LOADED
SET DATA
LOST
The FD179X then writes the data field and generates DRQ's
IDFIO ' Ol WRITE BYTE
OF EEROS
to the computer. If the DRQ is not serviced in time for
continuous writing the Lost Data Status Bit is set and a
byte of zeroes is written on the disk. The command is not
HAYS
*LL BYTES terminated. After the last data byte has been written on the
BEEN WRITTEN WRITE CRC
disk, the two-byte CRC is computed internally and written
on the disk followed by one byte of logic ones in FM or in
MFM. The WG output is then deactivated. For a 2 MHz
clock the INTRQ will set 8 to 12I sec after the last CRC byte
TURN Off WG
is written. For partial sector writing, the proper method is to
write the data and fill the balance with zeroes. By letting the
chip fill the zeroes, errors may be masked by the lost data
status and improper CRC Bytes.

TYPE IICOMMAND TYPE III COMMANDS

Mark of the data field must be found within 30 bytes in
single density and 43 bytes in double density of the last ID
field CRC byte; if not, the Record Not Found status bit is
set and the operation is terminated.
When the first character or byte of the data field has been
shifted through the DSR, it is transferred to the DR, and
DRQ is generated. When the next byte is accumulated in
the DSR, it is transferred to the DR and another DRQ is
generated. If the Computer has not read the previous
contents of the DR before a new character is transferred
that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a CRC error at the
end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).
At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Register (Bit 5) as shown:
READ ADDRESS
Upon receipt of the Read Address command, the head
is loaded and the Busy Status Bit i s s et. The next
encountered ID field is then read in from the disk, and
the six data bytes of the ID field are assembled and
transferred to the DR, and a DRQ is generated for each
byte. The six bytes of the ID field are shown below:
TRACK SIDE SECTO R S ECTOR CR C C R C
ADDR NUM B E R A D D RESS LENGTH I 2
1 2 3 4 5 6
Although the CRC characters are transferred to the
computer, the FD179X checks for validity and the CRC
error status bit is set if there is a CRC error. The Track
Address of t h e I D f i eld i s w r i tten into th e s ector
register so that a c omparison can be made by the
user. At th e en d o f t h e o p eration an i nterrupt is
generated and the Busy Status is reset.
Page 0.196

READ TRACK is not activated during the command; no CRC checking is

Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, and
data bytes are assembled and transferred to the data
register and DRQ's are generated for each byte. The ac-
cumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.
This command has several characteristics which make it
suitable for diagnostic purposes. They are: the Read Gate
performed; gap information is included in the data stream;
the internal side compare is not performed; and the ad-
dress mark detector is on for the duration of the command.
Because the A.M, detector is always on, write splices or
noise may cause the chip to look for an A.M. If an address
mark does not appear on schedule the Lost Data status flag
is set.
The ID A.M U ID field, ID CRC bytes, DAM, Data, and Data
CRC Bytes for each sector will be correct, The Gap Bytes
may be read incorrectly during write-splice time because of
synchronization.

ENTER

IS
THIS A NC
WRITE TRACK
ODEI
0

YES
tN C IU
Sf I BUSY RESET DRO
LOST DATA STATUS
BITS • DOES wA TE 2 CaC
O SA I 0 AS CI K Fr

'5
D SK INTRO
READY RESET BUSY

DD E 5 ES A Tf I'C
YES D SR FC .I K D

SET LD

W F Tf I' 0 FE OA
DOES YES
COPY S FLAG 10 FA FB CLK Ci
O SA F D FE
SSO LINE ( 255'2 ONLYT N rlA I l f C r t C
Qa Frl FB

WHITE DSA
IS E CLK

FS

Yff P YS
HAS HAS NTAQ REST I BUSY NDEX LIAAK
IS MS I NOTK NO
EKP RED PUL LF
OCCUAED

YES
ES wa rf
5 rE or lE R05
15 T I DATA LOST
HL I

YES

TGAS UPDATE w R f Al' N Irf w

DOES w r M 5 5 rrG CLOCK
O SA f ' 5 IN I AL EE CAC
SET GRO

NO
TB
I ' A PA
wEEE 5
DOES Y ES w P I f 02' IN HI M
O SR F S WITT M155 NG CLOCK

SET DRQ

DELAY 3 BYTE DO E 5 YE'5 wa Tf 2 cac

TIMES D sa r l 0 AAS

SET ATRO NO HAS

LOST OAT* DRQ BEEN WAITE DSA
RESET BUSY SERVICE 'SBMs FFcLocK IN I • FM
I TANT
YES

TYPE III
COMMAND WRITE TRACK TYPE III
COMMAND WRITE TRACK

CONTROL BYTES FOR INITIALIZATION
DATA PATTERN FD179X INTERPRETATION
IN DR (HEX) IN FM (DDEN = 1)
00 thru F4 Write 00 thru F4 with CLK = FF
F5 Not Allowed
F6 Not Allowed
F7 Generate 2 CRC bytes
F8 thru FB Write FB thru FB, Clk = C7, Preset CRC
FC Write FC with Clk = D7
FD Write FD with Clk = FF
FE Write FE, Clk = C7, Preset CRC
FF Write FF with Clk = FF
'Missing clock transition between bits 4 and 5
WRITE TRACK FORMATTING THE DISK
(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a r elatively simple task when
operating programmed I/O or when operating under DMA
with a large amount of memory. Data and gap information
must be provided at the computer interface. Formatting the
disk is accomplished by positioning the R/W head over the
desired track number and issuing the Write Track com-
mand.
Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated im-
mediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the Lost Data Status Bit is set,
and the Interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted.
This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the FD179X detects a data pattern of
F5 thru FE in the data register, this is interpreted as data
address marks with missing clocks or CRC generation.
The CRC generator is initialized when any data byte from
F8 to FE is about to be transferred from the Dh to the DSR
in FM or by receipt of F5 in MFM. An F7 pattern will
generate two CRC characters in FM or MFM. As a con-
sequence, the patterns F5 thru FE must not appear in the
gaps, data fields, or ID fields. Also, CRC's must be
generated by an F7 pattern.
Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to ter-
minate a multiple sector read or write command or to in-
page D.197
FD1791/3 INTERPRETATION
IN MFM (D~E = 0)
Write 00 thru F4, in MFM
Write A1' in MFM, Preset CRC
Write C2" in MFM
Generate 2 CRC bytes
Write FB thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
"Missing clock transition between bits 3 & 4
sure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
the command will be terminated and the busy status bit
reset.
The lower four bits of the command determine the con-
ditional interrupt as follows:
IO = Not-Ready to Ready Transition
I1 = Ready to Not.Ready Transition
I2 = Every index Pulse
(3 = Immediate Interrupt
The conditional interrupt is e nabled when th e c o r-
responding bit positions of the command ((3- IO) are set to
a 1. Then, when the condition for interrupt is met, the IN-
TRQ line will go high signifying that the condition specified
has occurred. If )3 - IO are all set to zero (HEX DO), no in-
terrupt will occur but any command presently under
execution will be immediately terminated. When using the
immediate interrupt condition (I3 = 1) an interrupt will be
immediately generated and the current command ter-
minated. Reading the status or writing to the command
register will not automatically clear the interrupt. The HEX
DO is the only command that will enable the immediate
interrupt (HEX D8) to clear on a subsequent load command
register or read status register operation. Follow a HEX D8
with DO command.
Wait 8 micro sec (double density) or 16 micro sec (single
density before issuing a new command after issuing a
forced interrupt (times double when clock = 1 M H z).
Loading a new command sooner than this will nullify the
forced interrupt.
Forced interrupt stops any command at the end of an in-
ternal micro-instruction and generates INTRQ when the
specified condition is met. Forced interrupt will wait until
ALU operations i n p r o gress ar e c o mplete (CRC
calculations, compares, etc.).
More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (I1 = 1)
and the Every Index Pulse (I2 = 1 ) are both set, the
resultantcommand would be HEX "DA". The "OR" func-
tion is performed so that either a READY TO NOT- READY
or the next Index Pulse will cause an interrupt condition.
 READ TRACK
ENTER SEOVENCE

SET BUSY
RESET STATUS
BITS 2. 4. 5

NO INDEX
PULSE
4

NO
INTRO YES
READY
RESET BUSY

YES
SHIFT ONE BIT
INTO DSR

COPY S FLAG
TO SSO LINE
(1795'7 ONLY)

YES SET INTRO

INDEX
PULSE RESET BUSY

SET HLD
NO

ADDRESS YES
MARK DETECTEC
'1
NO
E- I

NO

YES

NO HAVE 8
BITS BEEN
ASSEMBLED
DELAY 15MS 4

YES

HLT I IS DR NO SET LOST

4 EMPTY DATA BIT

YES YES

TG43
UPDATE
TRANSFER
DSR TO DR

READ NO
TRACK
SET
DRQ

YES READ
ADDRESS

TYPE III COMMAND

'll TEST= ). NO DELAY

11 TEST = I and CLK= I MHZ 30 MS DELAY

Read Track/Address
 page 0.199

STATUS REGISTER

READ ADDRESS
Upon receipt of any command, except the Force Interrupt
SEQUENCE command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged. If the
HAVE 6 YES RESET BUSY
Force Interrupt command is received when there is not a
INDEX HOLES SET INTRO current command under execution, the Busy Status bit is
PASSED SET RNF
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.
NO
The user has the option of reading the status register
through program control or using the DRQ line with DMA or
interrupt methods. When the Data register is read the DRQ
NO HAS
IDAM BEEN
bit in the status register and the DRQ line are automatically
DETECTED reset. A write to the Data register also causes both DRQ's
to reset.
YES The busy bit in the status may be monitored with a user
program to determine when a command is complete, in
lieu of using the INTRQ line. When using the INTRQ, a busy
status check is not recommended because a read of the
SHIFT I BYTE
INTO DSR status register Io determine the condition of busy will reset
the INTRQ line.

The format of the Status Register is shown below:

TRANSFER
BYTE TO DR

BITS
7 6 5 4 3 2 1 0
S7 S6 S5 S4 S3 S2 S1 SO
SET DRO

Status varies according to the type of command executed

as shown in Table 4.
Because of internal sync cycles, certain time delays must
HAVE 6
BYTES BEEN
be observed when operating under programmed I/O.They
READ are: (times double when clock = 1 MHz)

YES

Delay Req'd.
'
TRANSFER TRACK Operation Nex t Operation FM MFM
NUMBER TO SECTOR
REGISTOR Write to Read Busy Bit 12 Ixs 6MS
Command Reg. (Status Bit 0)
Write to Read Status 28/xs 14 FIS
Command Reg. Bits 1-7
CRC YES SET CRC Write Any Read From Diff.
ERROR ERROR BIT Register Register

NO

IBM 3740 FORMAT — 128 BYTES/SECTOR

SET INTRO
RESET BUSY Shown below is the IBM single-density format with 128
bytes/sector. In order to format a diskette, the user must
TYPE III COMMAND issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
Read Track/Address is one Data Request.
page 0.200

issue the Write Track command and load the data register
NUMBER HEX VALUE OF with the following values. For every byte to be written, there
OF BYTES BYTE WRITTEN is one data request.
40 FF (or 00)'
6 00 NUMBER HEX VALUE OF
1 FC (Index Mark) OF BYTES BYTE WRITTEN
26 FF (or 00)' 80 4E
6 00 12 00
1 FE (ID Address Mark) 3 F6 (Writes C2)
1 Track Number 1 FC (Index Mark)
1 Side Number (00 or 01) 50 4E
1 Sector Number (1 thru 1A) 12 00
1 00 (Sector Length) 3 F5 (Writes A1)
1 F7 (2 CRC's written) 1 FE (ID Address Mark)
11 FF (or 00)' 1 Track Number (0 thru 4C)
6 00 1 Side Number(0 or1)
1 FB (Data Address Mark) 1 Sector Number (1 thru 1A)
128 Data(IBM uses E5) 1 01 (Sector Length)
1 F7 (2 CRC's written) 1 F7 (2 CRCs written)
27 FF (or 00)' 22 4E
247" FF (or 00)' 12 00
3 F5 (Writes A1)
"Write bracketed field 26 times 1 FB (Data Address Mark)
**
Continue writing until FD179X interrupts out. 256 DATA
Approx. 247 bytes. 1 F7 (2 CRCs written)
1-Optional '00' on 1795/7 only. 54 4E
598" 4E
IBM SYSTEM 34 FORMAT-
256 BYTES/SECTOR Write bracketed field 26 times
Shown below is the IBM dual-density format with 256 '*
Continue writing until FD179X interrupts out.
bytes/sector. In order to format a diskette the user must Approx. 598 bytes.

H,t
(I CC I )

I G G G

G If

*' I'
I I ' t t' C C C
I G

IN IIFN ONLY IRAN ANO RATA AN

ARE FREGEOEG SY T»REE SYTES OF
A HT C L O C K THANG G NSET)TEE•
STS AN G EL S A N G

Hf' it

,„ I "H .
f
I. ~
H 't '
* ' I

I G C G

IBM TRACK FORMA T

 page D.201

1. NON-IBM FORMATS
Variations in the IBM formats are possible to a limited
extent if the following requirements are met:
YDRR

1) Sector size must be 128, 256, 512 of 1024 bytes.

2) Gap 2 cannot be varied from the IBM format.
3) 3 bytes of A1 must be used in MFM. T RR

In addition, the Index Address Mark is not required for ISERY,CE

operation by the FD179X. Gap 1, 3, and 4 lengths can be as

short as 2 bytes for FD179X operation, however PLL lock up
time, motor speed variation, write. splice area, etc. will add
more bytes to each gap to achieve proper operation. It is 0
recommended that the IBM format be used for highest
system reliability.

FM MFM
'SET

Gap I 16 bytes FF 32 bytes 4E TDACF 4-

DATA
(DA YA D
Gap II 11 bytes FF 22 bytes 4E
6 bytes 00 12 bytes 00
3 bytes A1
NOTE US I A AF Bf Pf RMANENTLY T ED LOW DES RED
T IAE DOUBIES WHfN CLOCK M
Gap Ill * ' 10 bytes FF 24 bytes 4E
4 bytes 00 8 bytes 00 I SERYICE TWORLI CAS E,
'FLI
' OF\ I
FI \ 3
IS 3
3 bytes A1 DRO R H G E DGE N D ICATES T A' I E D A T A A E S T E R A S A SSEMBLED
DATA
Gap IV 16 bytes FF 16 bytes 4E DTTO FALLING EDGE INDICATES THAT THE DATA REGISTER W*S RfAD
INTRO RISING EDI t O CCURS AT END DF COAIMAND
INTRO FALLING LDI'E IN DIC*TES T»AT THF STATUS REGISTER WAS READ

' Byte counts must be exact.

*Byte counts are minimum, except exactly 3 bytes of A1 READ ENABLE TIMING
must be written.

TIMING CHARACTERISTICS
TA = 0 C to 70 C, Vco = + 12V . . 6 V , Vss = OV, Vcc =+5V + .25V

READ ENABLE TIMING (See Note 6, Page 21)

SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS

TSET Setup ADDR & CS to RE 50 nsec
THLD Hold ADDR & CS from RE 10 nsec
TRE RE Pulse Width 400 nsec CE = 50.pf
TDRR DRQ Reset from RE 400 500 nsec
TIRR INTRQ Reset from RE 500 3000 nsec See Note 5
TDACC Data Access from RE nsec CE = 50 pf
TDOH Data Hold From RE 50 150 nsec CE = 50 pf

WRITE ENABLE TIMING (See Note 6, Page 21)

SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS
TSET Setup ADDR & CS to WE 50 nsec
THLD Hold ADDR & CS from WE 10 nsec
TWE WE Pulse Width 350 nsec
TDRR DRQ Reset from WE 400 500 nsec
TIRR INTRQ Reset from WE 500 3000 nsec See Note 5
TDS Data Setup to WE 250 nsec
TDH Data Hold from WE 70 nsec
Page D.202

I RR'

TRY I I

DATA MUST
BE VALID NOMINAL

DISKETTE MODE DDEN CLK Tc

8" MFM 2 MHz 1 yes 1 EIs 2 As
8" FM 2 MHz 2 As 28s 4 yes
I,OTE I CS MAY BE PERMAI,ENTL Y TIED EOW IF DESIRED
2 WHEN WRITING DATA NTO SECTOR TRACK OR DATA
5" MFM 1 MHz 2 yAS 2AS 4„s
REGISTER USER CANNOT READ THIS RE PATER UNT L
AT LEAST • SEC INMFM AFTER T E e „" EDGE OF WE 5" FM 1 MHz 4 os 4 As 8 As
YHEN WRITING iNTO THE COLIMAND Ct , . T E R STATUS
S KOT VALID UNTIL SOME 2B SEC K U A SEC N V F V
LATER THESE TIMES ARE DOUBLED WHEN CLK 'AH
' TIME DOUBLES WHEN CLOCK IMH INPUT DATA TIMING
DAD RISING EDGE. INDICATES T AT THE DATA REGISTER IS EMPTY
DRO FALLIHG EDGE IND CATES THAT THE DATA REGISTER IS LOADED
NTRO RISING EDGE IND CATE THE END OF A COMMAND
NITRO FALLING EDGE IN D I CATES THAT T HE C O MMAND REG STER
IS WRITTEN TO

WRITE ENABLE TIMING

INPUT DATA TIMING:

SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS
Tpw Raw Read Pulse Width 100 200 nsec See Note 1
tbc Tieawead Cycle Time nsec 1800 ns @ 70'C
Tc RCLK Cycle Time nsec 1800 ns @ 70'C
Txy RCLK hold to Raw Read 40 nsec See Note 1
Txz Raw Read hold to RCLK 40 nsec See Note 1

WRITE DATA TIMING: (ALL TIMES DOUBLE WHEN CLK = 1 MHz ) (See Note6, Page21)
SYMBOL CHARACTERISTICS MIN, TYP. MAX. UNITS CONDITIONS

Twp Write Data Pulse Width 450 500 550 nsec FM

150 200 250 nsec MFM
Twg Write Gate to Write Data 2 Izsec FM
1 fzsec MFM
Tbc Write data cycle Time 2,3, or4 psec CLK Error
Ts Early (Late) to Write Data 125 n'sec MFM
Th Early (Late) From 125 nsec MFM
Write Data
Twf Write Gate off from WD @sec FM
fzsec MFM
Twdl WD Valid to Clk 100 nsec CLK = 1 MHZ
50 nsec CLK = 2 MHZ
Twd2 WD Valid after CLK 100 nsec CLK = 1 MHZ
30 nsec CLK = 2 MHZ
 Page 0.203

CLK
( IMHZ)

WD
Twdi Twd2

125 125
CLK
) 2MHZ)

WD

Twdl ~ [ ~ Twd2

WD M UST HAVE RISING EDGE IN FIRST SHADED AREA AND TRAILING

EDGE IN SECOND SHADED AREA.

WRITE DATA/CLOCK RELATIONSHIP

IDDEN — 0)

WRITE DATA TIMING

MISCELLANEOUS TIMING: (Times Double When Clock = 1 MHZ} (See Note 6, Page 21)

SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS

TCDI Clock Duty (low) 230 250 20000 nsec

TCD2 Clock Duty (high) 200 250 20000 nsec
TSTP Step Pulse Output 2or4 Izsec See Note 5
TDIR Dir Setup to Step 12 p.sec ~ CLK ERROR
TMR Master Reset Pulse Width 50 ILsec
TIP Index Pulse Width 10 y.sec
See Note 5
TWF Write Fault Pulse Width 10 Izsec
Page 0.204

NOTES:
1. Pulse width on RAW READ (Pin 27) is normally
100-300 ns. However, pulse may be any width if
pulse is entirely within window. If pulse occurs inboth
windows, then pulse width must be less than 300 ns
for MFM at CLK = 2 MHz and 600 ns forFM at 2
MHz. Times double for 1 MHz.
2 A PPL Data Separator is recommended for 8" MFM.
3 tbc should be 2 FES, naminal in MFM and 4 F S nOminal
in FM. Times double when CLK = 1 MHz
4. RCLK may be high or low during RAW READ (Polarity
is unimportant).
5. Times doublewhen clock = 1 MHz.
6. Output timing readingsareat VoL = 0.8vandvoR =
Zi-, 2.0v.

STEP A
YO
OAO
YO A T AP'

OA
TTAQ TSTP
J~ TSTP
I I I i
SP

STEP
YOL

MISCELLANEOUS TIMING
'FROM STEP RATE TABLE

Table 4.STATUS REGISTER SUMMARY

ALL TYPE I READ READ READ WRITE WRITE

BIT COMMANDS ADDRESS SECTOR TRACK SECTOR TRACK
S7 NOT READY NOT READY NOT READY NOT READY NOT READY NOT READY
S6 WRITE 0 0 0 WRITE WRITE
PROTECT PROTECT PROTECT
S5 HEAD LOADED 0 RECORD TYPE WRITE FAULT WRITE FAULT
S4 SEEK ERROR RNF RNF 0 RNF 0
S3 CRC ERROR CRC ERROR CRC ERROR CRC ERROR 0
S2 TRACK 0 LOST DATA LOST DATA LOST DATA LOST DATA LOST DATA
S1 INDEX PULSE DRQ DRQ DRQ DRQ DRQ
SO BUSY BUSY BUSY BUSY BUSY BUSY

STATUS FOR TYPE I COMMANDS

BIT NAME MEANING
S7 NOT READY This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.
S6 PROTECTED When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
S5 HEAD LOADED When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.
S4 SEEK ERROR When set, the desired track was not verified. This bit is reset to 0 when updated.
S3 CRC ERROR CRC encountered in ID field.
S2 TRACK 00 When set, indicates Read/Write head is positioned to Track 0. This bit is an inverted
copy of the TROD input.
S1 INDEX When set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.
SO BUSY When set command is in progress. When reset no command is in progress.
 Page 0.205

STATUS FOR TYPE 11 AND 111 COMMANDS

BIT NAME MEANING
S7 NOT READY This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
S6 WRITE PROTEC On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
S5 RECORD TYPE/ On Read Record: It indicates the record-type code from data field address mark.
WR IT E FA ULT 1 = Deleted Data Mark. 0 = Data Mark. On any Write: It indicates a Write Fault. This bit
is reset when updated.
S4 RECORD NOT When set, it indicates that the desired track, sector, or side were not found. This bit is
FOUND (RNF) reset when updated.
S3 CRC ERROR If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in
data field. This bit is reset when updated.
S2 LOST DATA When set, it indicates the computer did not respond to DRQ in one byte time. This bit is
reset to zero when updated.
S1 DATA REQUEST This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when up-
dated.
SO BUSY When set, command is under execution. When reset, no command is under execution.

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Dissipation = 0.6W
Voowithrepect to Vss(ground): +15to -0.3V CIN & CouT = 15 pF max with all pins grounded except
Voltage to any input with respect to V~ = + 15 to — 0.3V one under test.
Icc = 60 MA (35 MA nominal) Operating temperature = O'C to 70'C
loo = 15 MA (10 MA nominal) Storage temperature = — 55'C to + 125'C

OPERATING CHARACTERISTICS (DC)

TA = O'Cto70'C, Voo = + 12V + .6V, Vss = OV, Vcc = + 5V + .25V

SYMBOL CHARACTERISTIC MIN. MAX. UNITS CONDITIONS

IIL Input Leakage 10 uA VIN = V o o *
loL Output Leakage 10 pA VooT = Voo
Vnr Input High Voltage 2.6 V
Vit Input Low Voltage 0.8
VoH Output High Voltage 2.8 V lo = — 100pA
VoL Output Low Voltage 0.45 l o = 16 m A
Po Power Dissipation 0.6 W

*1792 and 1794 10 = 1.0 mA

"Leakage conditions are for input pins without internal pull-up resistors.
Page 0.206

610
MAX
IN01 x
INDE 4 00 1
001 200
2 060
MAX
2 025 MAX

015
MIN
060
;10
J
055
0 55 ~ i 014 125
575
620
040
MIN
060
110
J 055 0, 125
660
021 MIN

FD179XA42 CERAMIC PACKAGE FD179XB-02 PLASTIC PACKAGE

Infprmation furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is
assumed by Western Digital Corporation for its use; nor any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital
Corporation. Western Digital Corporation reserves the right to change said circuitry at anytime without notice.

WF S T F R i V D I G 'I T A L i 2445 McCABE WAY

I I R V I NE, CA 92714 (7 1 4 )5 5 7-3550, TWX 910-595-1139
 Page 0.207

SPIES'i& A 'Af ZP I N I 7 A f5
C 0 /7 P 0 R' xf / / 0 N

WD1691 FLOPPY SUPPORT LOGIC (F.S.L.)

oi

FEATURES GENERAL DESCRIPTlON

The WD1691 F.S.L. has been designed to minimize the
• Direct interface to the FD179X external logic required to interface the 179X Family of Floppy oo
Disk Controilers to a drive. With the use of an external VCO,
• Eliminates external FDC Logic the WD 1691 will generate the RCLK signal for the WD179X,
while providing ~n.t~d'u m~nt pulse (PLIMP) to control the
• Data Separation/RCLK GENERATION VCO frequency. VFOE/WF de-multipiexing is also accom-
plished and Write Precompensation signals have been in-
• Write Precompensation Signals cluded to interface directly with the WD2143 Clock Generator.
• VFOE/WF Demultiplexing The WD1691 is implemented in N-MOS silicon gate
technology and is available in a plastic or ceramic 20 pin
• Programmable Density dual-in-line package.
• 6" or 5.25" Drive Compatible

• All inputs and outputs TTL Compatible

e Single +5V Supply

+N
PHASE
COMPARE

PO
WDIN 20 VCC

19
RGO
18 LATE

EARLY
TG43
16 VCO tii
WD1691 VFOE
VFOE
WDOUT 16 DDEN IWP GEMUX PRECOMP T2
LOGIC
ti3
WG 14 PD
+4
VFOE/WF 13 PU

TG43 12 RCLK EARLY

LATCH WO IN
10 OECODE
VSS RDD

BLOCK DIAGRAM
page D.208

PIN NAME SYMBOL FUNCTION

WRITE DATA WDIN Ties directly to the FD179X WD pin.

INPUT

2, 3, 4, 19 P HASE 4 Phase inputs to generate a desired Write Precompensation

2, 3, 1, 4 delay. These signals tie directly to the WD2143 Clock
Generator.

STROBE STB Strobe output from the 1691. Strobe will latch at a high level
on the leading edge of WDIN and reset to a low level on the
leading edge of 04.

WRITE DATA WDOUT Serial, pre-compensated Write data stream to be sent to the
OUTPUT disk drive's WD line.

WRITE GATE WG Ties directly to the FD179X WG pin.

VFO ENABLE/ VFOE/WF Ties directly to the FD179X VFOE/WF pin.

WRITE FAULT

TRACK 43 TG43 Ties directly to the FD179X TG43 pin, If Write Precompen-
sation is required on TRACKS 44-76.

10 V„ Ground

READ DATA RDD Composite clock and data stream input from the drive.

READ CLOCK RCLK RCLK signal generated by the WD1691, to be tied to the
FD179X RCLK pin.

13 PUMP UP PU Tri-state output that will be forced high when the WD1691
requires an increase in VCO frequency.

14 PUMP DOWN PD Tri-state output that will be forced low when the WD1691 re-
quired a decrease in VCO frequency.

15 Double Density DDEN Double Density Select input. When Inactive (High), the VCO
Enable frequency is internally divided by two.

16 Voltage VCO A nominal 4.0MHz (8" drive) or 2.0MHz (5.25 drive) master
Controlled clock input.
Oscillator

17, 18 EARLY EARLY EARLY and LATE signals from the FD179X, used to deter-
LATE LATE mine Write Precompensation.

20 V„ V„ + SV 1 0 % power supply

DEVICE DESCRIPTION
The WD1691 is divided into two sections:
1) Data Recovery Circuit
2) Write precompensation Circuit
The Data ~Se arator or Recovery Circuit has four inputs:
DDEN, VCO, RDD, andVFOE/WF; and three outputs: PU,
PD and RCLK. The VVF/WF input is used in conjunction
with the Write Gate signal to enable the Data recovery circuit.
When Write Gate is high, a write operation is taking place,
and the data recovery circuits are disabled, regardless of the
state on any other inputs.
WG VFOE/WF
X
1 HI-Z
00
The Write Precompensation circuit has been designed
to be used with the WD2143-01 clock generator, When the
WD1691 is operated in a "single density only" mode, wnte
precompensation as well as the WD2143-01 is not needed.
In thiscase, p1, Q2, p3, p4, and STB should be tied together,
DDEN left open, and TG43 tied to ground.
ln the double-density mode (DDEN= 0), the sitLnals Early
and Late are used to select a phase input (pt - $4) on the
leading edge of WDIN. The STB line is latched high when
this occurs causing the WD2143-01 to start its pulse gen-
eration. P2 is used as the write data pulse on nominal
(Early=Late =i t), 42 is used for early, and f3is used for late.
The leading edge ofP4 resets the STB line i n'' i tion of
the next wnte data pulse. When TG43 =0 or DDEN =1, Pre-
compensation is disabled and any transitions on the WDIN
line will appear on the WDout line. If wnte precompensation
is desired on all tracks, leave TG43 open (an internal pull-up
will force a Logic I) while DDEN =O.
The signals,
DUES TG43, andTTDD have internal pull-
up resistors and may.be left open if a logic ( is desired on
any of these lines.
Page 0.209
When VFOE/WF and WRITE GATE are low,the data
recovery circuit is enabled. When the RDD iine goes Active
Low, the PU or PD signals will become active. If the RDD
line has made its transition in the beginning of the RCLK
window, PU will go from a Hl-Z state to a Logic I, requesting
anincrease in VCO frequency. It the RDD line has made its
transition at the end of the RCLK window, PU will remain in
a Hl-Z state while PD will go to a logic zero, requestincCa
decrease in VCO frequency. When the leading edge of RDD
occurs in the center of the RCLK window, both PU and PD
will remain tri-stated, indicating that no adjustment of the
VCO treruencyisneeded. The RC~ a i is a divid
e-by-
16 (DDEN =1 ) or a divide-by-8 (DDEN =O) of the VCO
frequency.
RDD PU+PD
X HI-Z
X
1
HI-Z
0 Enable
The minimum Voh level on PU is specified at 2.4V,
sourcing 200ua. During PUMP UP lime, this output will "drift"
from a tri-state to .4V minimum. By tying PU and PD together,
a PUMP signal is created that will be forced low for a de-
crease in VCO frequency and forced high for an increase in
VCO frequency. To speed up rise times and stabilize the
output voltage, a resistor divider can be used to set the tri-
state level to approximately 1.4V, This yields a worst case
swing of I Y ; acceptable for most VCO chips with a linear
voltage-to-frequencv charactenstic.
Both PU and PD signals are affected by the width of the
RAW READ (RDD) pulse. The wider the RAW READ pulse,
the longer the PU or PD signal (depending upon the phase
relationship to RCLK) will remain active. If the RAW READ
pulse exceeds ~ (VCO = 4MHz, DDEN = 0) or 500ns.
(VCO = 4MHz, DDEN = 1), then both a PU and PD will occur
in the same window. This is undesirable and reduces the
accuracy of the external integrator or low-pass filter to con-
vert the PUMP signals into a slow moving D.C. correction
voltage.
Eventually, the PUMP signals will have corrected the
VCO input to exactly the same frequency multiple as the
RAW READ signal.The leading edge of the RAW READ
pulse will then occur in the exact center of the RCLK window,
and ideal condition for the FD179X internal recovery circuits.
Page 0.210

AB L U TE MAXIM M R IN
Ambient Temperature under Bias .
Voltage on any pin with respect
to Ground (vss)
Power Dissipation .
R C R TERI
T, = II t o 70'C; V c = 5.0V 1 0%; V = O V
SPECIRCATIONS
-25 to 70'C Storage Temp.— Ceramic — 65'C to +150 C
Plastic — 55'C to +125'C
. -0.2 to +7V
. 1W
NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not
CS intended and should be limited to those conditions specified
in the DC Electrical characteristics.

SYMBOL PARAMETER MIN MAX TEST CONDITIONS

Vi, Input Low Voltage -0.2 +0.8 V

Vw Input High Voltage 2.0 V
Vc. Output Low Voltage 0.45 Ice= 3.2MA

Vc» High Level Output Voltage 2.4 V Ic„ = -200y.a

Vcc Supply Voltage 4.5 5.0 5.5 V

lcc Supply Current 100 MA All outputs open

AC ELECTRICAL CHARACTERISTC
T, = 0' to 70 C; V„ = S V = 10%; Vss = OV

SYMBOL PAR A M ETER TEST CONDITIONS

FIN VCO Input Frequency MHz DDEN=O
MHz DDEN = 1
RDD Pulse Width 100 ns.
W» EARLY (LATE) to WDIN 100 ns.
PUMP UP/DN Time ns.
W„ WDIN to WDOUT 80 ns. DDEN = 1
I„„ Internal Pull-up Resistor 4.0 6.5 10 KQ

I I
te - FIN - » I
I
Vcc
VCO

PINS
8, 9, 11, 15
ROO
only
I
Rpw

RCLK
INTERNAL PULL-UP RESISTOR ~ Vco -: 16 — ~
 Page 0.211

Wel ~ I i~ Wpw
I
WDIN I

EARLY

LATE

WDOUT
NOM EARLY NOM

TG43
DDEN ~ "0" WRITE DATA TIMING (MFM)

Wpw

WDIN

WDOUT
'I
Wpi
"0"
II
TG43
DDEN "1"
WRITE DATA TIMING (FM)
page 0.212

TyPICAL APPLICATIONS

Figure 1 illustrates the 1691 to FD177141 floppy disk con-
troller. The RCLK signal is used to gate the RAW data pulses
which are inverted by the 74LS04 inverter. Since RCLK will
be high during data and low during clock a 74LS08 is used
to switch the proper clock or data pulse to the FD1771.
Shown in Figure 2 is a Phase-Lock Loop data separator
and the support logic for a single and double-density 8" drive.
The raw data (Both clock and data bits) are fed to ~th
WD1691 and FD179X. The WD1691 outputs its PU or PD
signal, which is integrated by the .33uf capacitor and 33ohm
resistor to form a control voltage for the 74S124 VCO device.
The 4.0MHZ nominal output of the VCO then feeds back to
the WD1691 completing the loop. The WD2143-01 is also
used, providing write precompensation when in double-den-
sity, from tracks 44-77. The DDEN line can either be con-
trolled by a toggle switch or a logic level from the host
system.
To adjust write precampensation, issue a command to
the FD179X so that write data pulses are present. This can
be done with a 'WRITE TRACK' command and the IP line
open, or a continuous 'WRITE SECTOR' operation. With a
scope on pin 4 of the WD1691, adjust the precomp pot for
the desired value. This will range from 100 to 300 ns typically.
The pulse width set on pin 4 (O1) will be the desired precomp
delay from nominal.
The data separator must be adjusted with the RDD or
VFOE/WF line at a Logic I. Adjust the bias voltage poten-
tiometer for 1.4V on pin 2 of the 74S124. Then adjust the
range control to yield 4.0MHZ on pin 7 of the 74S124.

RAW
1771-01
DATA

74LS04
XTDS
1691
ADD
74LS08
12
RCLK 27
FDDATA

26
FDCLOCK

DDEN N.C.

FIG. 1
W01691 to FD1771<1 INTERFACE

SUBSTITUTING VCO's

There are other VCO circuits available that may be sub-

stituted for the 74S124. The specifications required are:
1) The VCO must tree run at 4.0MHz with a 1.4V control
signal. The WD1691 will force this voltage 1 Volt in
either direction (i.e, 4V = decrease frequency, 2.4V
= increase frequency). It a ~ 15% capture range is
desired, then a I Volt change on the VCO input should
change the frequency by 15%. Capture range should
be limited to about 25 % , to prevent the VCO from
breaking into oscillation and/or losing lock because of
noise spikes (causing abnormally quick adjustments of
the VCO frequency). Jitter in the VCO output frequency
may further be reduced by increasing the integration
capacitor/resistor, but this will also decrease the final
capture range and lock-up time.
2) The sink output current of the WD1691 is 3.2ma mini-
mum. The source output current is -200ua. Therefore,
source current is the limiting factor. Insure that the input
circuitry of the VCO does not require source current in
excess of -200ua.
Another alternative is io use a v oltage follower/level
shifter circuit to match the input requirements of the VCO
chosen. A more complex tilter can be used to convert the
PUMP UP/PUMP DOWN pulses to the varying DC voltage
signal required by the VCO, achieving an optimum condition
between lock-up time and high frequency rejection.
 Page D.2l3

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Page D.214

1691U CERAMIC PACKAGE 1691V PLASTIC PACKAGE

The is a preiiminary specdlcation wrrh tentabve device parameters and may be subfect to change atter final product charactenzalion is comore(ed.
Intonnabon furnished by Western Digilai Corporation is beievsd to be accurate and reliable. However. no responsibility is assumed by Western Digitai Corporation
for its use: nor any infringements of patents or other nghts of third partes whch may result from its use. No license is granted by imolicatcn or ctt:ervnse under
any patent or patent nghts ot Western Digrtat Corporation. Western Digital Corporation reserves the ngnt to change said circuitry st any time without noses.

3128 REDHILL AVEfNUE, BOX 2180

NEWPORT BEACH C A 92663 ( 1 4 j 5 5 7-3550 TWX 9'0 - 595-1 l39
 page D.215

N fES TE APN B / 8 / 7A l
C CJ F7 P 0 Itr' A 7 / 0 N

WD2143-D3 Four Phase Clock Generator

FEATURES GENERAL DESCRIPTION

• IMPROVED VERSION OF WD2143-01 The WD2143-03 Four-Phase Clock Generator is a MOB/
• TRUE AND INVERTED OUTPUTS LSI device capable of generating four phase clocks. The out-
• SINGLE 5 VOLT SUPPLY put pulse widths are controlled by tying an external resistor
• TTL COMPATABLE to the proper control inputs. All pulse widths may be set to
• ON CHIP OSCILLATOR the same width by tying the 4PW line through an external re-
• TTL CLOCK INPUTS sistor. Each pulse width can also be individually pro-
• TTL CLOCK OUTPUT grammed by tying a resistor through the appropriate 41PW-
• PROGRAMMABLE PULSE WIDTHS 44PW control inputs.
• PROGRAMMABLE PHASE'WIDTHS
• NO EXTERNAL CAPACITOR

yl PW

STB IN Q

osc
18 vcc
QPW
osc
$3 16 4I4 Pw OUT T Q
4i3 15 tb3 Pw
4I2 14 Q2 PW
4I2 13 $1 PW
12 OSC OUT
T Q
STB IN
GND 10 sTB DUT

PIN CONNECTIONS T Q

Figure 1 WD2143-03 PIN CONNECTIONS AND BLOCK DIAGRAM

DEVICE OPERATION

Each of the phase outputs can be controlled individually by
typing an external resistor from d>t PW-<b4PW to a +5V sup-
ply. When it is desired to have bt through d 4 outputs the
same width, the bt PW- h4PW inputs should be lett open and
an external resistor tied from the 4PW (Pin 17) input !o
+12V.
STROBE IN (pin 11) is driven by a TTL square wave with
STROBE OUT (pin 10) left open. Each of the four phase
outputs provide both true and inverted signals, capable of
driving 1 TTL load each.
page 0.216

PIN NUMBER SYMBOL DESCRIPTION

1 ,3,5, 7 Four phase clock outputs. These outputs are inverted (active low).

2, 4, 6, 8 41-g4 Four Phase clock outputs. These outputs are true (active high).

GND Ground

to STB OUT This pin is left unconnected,

STB IN Input signal to initiate four. phase clock outputs.

12 N.C. No connection

13-16 $ I PW-$4PW External resistor inputs to control the individual pulse widths of each output.
These pins can be left open if 4 PW is used.

17 $PW External resistor input to control all phase outputs to the same pulse widths.

18 Vcc +5V ~ 5/o power supply input

Table 1 PIN DESCRIPTIONS

TYPICAL APPLICATIONS

7400 STB IN

WD1891 WD214303
WD2143KI3
STB IN
10
NC STB OUT
+ 12

Figure 2 WRITE PRECOMP OPERATION WITH F.S.L Figure 3 TTL SQUARE WAVE OPERATION
WD1691

5
— 12

13
b1
2K
WD2143-03
14 6
412PW 42
17
10K dPW WD2143-03
15 4
83PW b3 b3

2
44 44
10K

Figure 4 EQUAL PULSE WIDTH OUTPUTS Figure 5 INDIVIDUAL PULSE WIDTH OUTPUTS
 Page D.217

0
0 I

n 0
lO C
CCN I Kfu<

'0 'V

Figure 6 WRITE PRECOMP FOR FLOPPY DISK

Figure 7 WD2143-03 TIMING DIAGRAM

SPECIFICATIONS

Absolute Maximum Ratings Note: Maximum ratings indicate limits beyond which perma-
nent damage may occur. Continuous operation at these limits
Operating Temperature 0' to + 70' C is not intended and should be limited to the DC electrical char-
acteristics specified.
Voltage on any pin with — 0.5 to +7V
respect to Ground 'Pin 17 = — 0.5V to +12V. Increasing voltage on Pin 17 will
decrease Tpw.
Power Dissipation 1 Watt

Storage Temperature plastic — 55 to +125' C

ceramic — 65 to +150'C

DC ELECTRICAL CHARACTERISTICS

V c = 5 V ~ 5 % , G N D = OV, TA 0 to 7 0 ' C .

SYMBOL PARAMETER MIN. MAX. UNITS CONDITIONS

Voi TTL low level output 0.4 = 1.6 ma.

Voh TTL high level output 2.4 ioh = — 100 ua.

Vii STB in low voltage 08

Vih STB in high voltage 2.4

icc Supply Current 80 ma All outputs open

Table 2 DC ELECTRICAL CHARACTERISTICS

PBgB D.21 8

SWITCHING CHARACTERISTICS

Vcc = 5V — 5' . G ND = OV TA =0 t o 70' C

SYMBOL PARAMETER MIN. MAX. UNITS CONDITIONS

Tcd STB IN to OSC out (t) 70 NS

Tpd STB OUT to d/1 70 NS

Tpw Pulse Width (any output) NS CL = 30pf

Tpr Rise Time (any output) 30 NS CL = 30pf

Tpf Fall Time (any output) 25 NS CL = 30pf

TFR STROBE Frequency MHz combined Tpw = 400 NS.

Tdpw Pulse Width Differential 10 /I /

/0 100-300 NS.

Table 3 SWITCHING CHARACTERISTICS

NOTE: TO
M moaov/od ot5055 voff potoi; voL = O.sv, voN = 2.0v

0 500
I Mxx

0 I50
MAX.

t
gg 0055 0 /25
~0205
$ 0 Ill •
Q+
0 021g
I
Q ~o
0 I25
0 055 MIN M IN
0 085

WD2143L-03 CERAMIC PACKAGE WD2143M-03 PLASTIC PACKAGE

This is a preliminary specification with tentative device parameters and may be sublect to change after final product characterization is
completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Western Digital Corporation for its use, nor any infnngements of patents or other rights of third parties which may result from its use No
license is granted by implication or otherwise under any patent or patent rights of Western Dig~tel Corporation Western Digital Corpora-
tion reserves the right to change said circuitry at any time without notice

N 'F S T F A FIffI D I G I TA L , ) 2445 McCABE WAY, POST OFFICE BOX 2180

IRVINE, CALIFORNIA 92714 (714) 557-3550, TWX 910-595-1139
 Page 0.219

M O T O R O LA MCM6633

32,76B-BITDYNAMIC RAM

The MCM6633 isa 32,768 bit,high-speed, dynamic Random-Access IVlOS

Memory. Organized as 32,768 one-bit words and fabricated using (N-CHANNEL, SILICON-GATE)
HMOS high-performance N-channel silicon-gate technology. This new
breed of 5-volt only dynamic RAM combines high performance with low 32,768-BIT
cost and improved reliabilny DYNAMIC RANDOM ACCESS
By multiplexing row- and column-address inputs, the MCM6633 re-
quires only eight address hnes and permits packaging in standard 16-pin
MEMORY
dual-in-line packages. Complete address decoding is done on chip with
address latches incorporated. Data out is controlled by CAS allowing
for greater system flexibilny
All inputs and outputs, including clocks, are fully TTL compatible
The MCM6633 incorporates a one-transistor cell design and dynamic
storage techniques.
• Organized as 32,768 Words of I Bit
• Single + 5 V Operation
• Fast 150 ns Operation
L SUFFIX
• Low Power Dissipation CERAMIC PACKAGE
275 mW Maximum (Active) CASE 690
30 mW Maximum (Standby)
• Th ree-State Data Output
• In ternal Latches for Address and Data Input
• Early-Wnte Output Capability PIN ASSIGNMENT
• 16K Compatible 128-Cycle, 2 ms Refresh
• RAS-only Refresh Mode N/C I• 16 vss
• CAS Controlled Output 2 15 CAS
• Up ward Pin Compatible from the 16K RAM (MCM4116, MCM4516, 3 14
MCM4517) 4 13 A6
• One Halt of the 64K RAM MCM6665
AO 5 12 A3
• Th e Operating Half of the MCM6633 is Indicated by Dewce Marking
A2 11 A4
MCM66330 Tie A7 CAS IA15) Low "0"
MCM66331 Tie A7 CAS (A15) High "I" Al 7 10 A5

Vcc 9 9 A7

BLOCK DIAGRAM For maximum compatibikty with MCM6632 and

MCM6664, a VCC trace should go to pin tt
~ VCC
~vss
rec/sarg
Sense Ampkiier Sense Ampl tier PIN NAMES
Clack '00 0
AO-A7 Address Input
AO CI D Data In
0
Q Data Out
Ai 4v 15 394 Bii Memory 16, 3B4-Bu Memory 0
Read/Wrne Input
aa Array
0S
rv Array W
~A
R R0W Address Strobe
A2 CAS Column Address Strobe
Vcc Power (+ 5 Vl
A3 s w ie w Vss Ground
0 I/2 Il o i 25SI 0
I/2 Ceii I/2 it 0 / 25EI
0
IJ Column Decoder Lagrc Column Decoder
A4 Data In, D
0

c/
A5 ia ss output This device contains circuitry to protect
ie 334-Bii Memory 8 16,394. Bii Memory E
0 Data. O
/0 the inputs against damage due to high
AE Array Array static voltages or electnc fields; however,
'0 0
cr
d it is advised that normal precautions be
A/ taken to avoid appkcauon of any voltage
higher than maximum rated voltages to
0
recisarg this high-impedance circuit.
Sense Amoirtier Sense Ampkler
Clock

DS9825/9-80
page D.220

MCM6633

ABSOLUTE MAXIMUM RATINGS (See Norel FIGURE I — OUTPUT LOAD

Rating Symbol Value Unk 5V
Voltage on Any Pin Relative to VSS (Except VCC) Vn Vout — 210+7
970 0
Voltageon VCC Supply Relauve to VSS — I to+7
0 to +70 O
Operating Temperature Range TA C
Storage Temperature Range Tst — 65 to +150 oc
Power Dissipation PD W
Data Out Current lout mA 100 pF' 12 kn
NOTE Permanent detnce damage may occur if ABSOLUTE MAXIMUM RATINGS are ex-
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT-
ING CONDITIONS Exposure to higher than recommended voltages for extended
pencds of lime could affect detnce reliabilny
Includes Jig Capacitance

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted )

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit Notes
Supply Voltage M C M6633L15/ M C M6633L20 VCC 4.5 5.0 5.5
M C M6633L15-5/ M C M6633L20-5 VCC 4 75 5.0 5 25
VSS 0 0 0
Logic I Voltage, All Inputs 7.0 Vdc
Logic 0 Voltage .— 2.0 0.8 Vdc

DC CHARACTERISTICS
Characteristic Symbol Min Max Units Notes
VCC Power Supply Current (tRC min ) iCCI mA
Standby VCC Power Supply Currenr iCC2 mA
VCC Power Supply Current Dunng l(7ES Only Refresh Cycles iCC3 mA
Input Leakage Current (any input! (0< V no 5 5) IExcept Pin 1) Il(L) 10
OutPut Leakage Current (OS Vou($5.5) ICAS at Logic 1) (OIL) 10 )rA
O utput Logic I Voltage I I i i « -- — 4 mA VOH 24
Output Logic 0 Voltage Sir lo„t = 4 mA VOL 04

AC OPERATING CONDITIONS AND CHARACTERISTICS

(See Notes 2, 3, 6, and Figure I)
(Read, Wnte, and Read-Modify-Wnte Cycles)
(Full Operating Voltage and Temperature Range Unless Otherwise Noted)

Parameter Symbol MCM6633-15 MCM6633-20 Units Notes

Min Max Min Mex
Random Reed or WnteCycle Time IRC ns 8,9
Read Write Cycle Time IR WC ns 8,9
Access Time from Row Address Strobe IRAC ns 10, 12
Access Time from Column Address Strobe ICAC 75 110 ns 11, 12
Output Buffer and Turn-011 Delay IOFF ns 17
Row Address Strobe Precharge Time IRP ns
Row Address Strooe Pulse Width IR AS ns
Column Address Strobe Pulse Widtii ICAS 75 110 ns
Row to Column Strobe Lead Time IRCD 75 ns 13
Row Address Setup Time IASR ns
Row Address Hold Time IRAH 25 ns
Column Address Setup Time IASC ns
Column Address Hold Time IC AH 45 its
Column Address Hold Time Referenced Io RAK IAR 120 155 ns
Transition Time IRise and Falll ns
 page D.22 1

M C M6633

AC OPERATING CONDITIONS AND CHARACTERISTICS

(See Notes 2, 3, 6, and Figure I )
(Read, Wnte, and Read Modify-Wnte Cycles)
(Full Operating Voltage and Temperature Range Unless Otherwise Noted)

MCM6633- I 5 M C M6633-20 Units Notes

Parameter Symbol
Min Mex Min Max
Read Command Setup Time (RCS ns
Read Command Hold time IRCH 10 10 ns 14
Read Commend Hold Time Referenced to )TAAr' tRRH ns 14
Wi te Command Hold T me (WCH 45 ns
Wr te Command Hold Time Referencea to RAS 'WCR ' 20 155 ns
Write Command Pulse Width 'WP 45 ns
Wnte Command to Row Strobe Lead Time (RWL 45 ns
Wn;e Command to Column Strobe Lead Time (CWL 45 ns
Data in Selup Time (DS ns 15
Data in Hold Time (DH 45 ns 15
Data in Hold Time Referenced to ~A (DHR 120 ns
Column to Row Strobe Precharge Time (CRp — 10 — 10 ns
Hold Time (RSH 75 110 ns
Refresh Penod tRFSH 2.0 20 ms
Command Setup Time (W — 10 — 10 Ii s 16
CAS to WWIWEDelEay (CWD 45 ns 16
R7ES' to ÃKIIE Delay (RWD I 25 ns 16
CAB Hold Time )CS H ns

CAPACITANCE (f = I 0 MHz, TA= 2 5 'C, VCC=5 V P enodically Sampled Rather Than )00r)(r Tested)
Parameter Symbol Typ Max Units Notes
Input Caparxtance (AO-A7), D C)1 pF
Input Capacitance R7(9. CTF(r', )70RITE Ci2 )0 pF
Output Capacitar ce (Q) (CAS = V)H to disable output) Ca pF

NOTES
I All voltages referenced to V 8 9
2 V (H min and V(L max are reference levels far measunng timing of input signals Transition times are measured between V(H and
VIL
3 A n initial pause of 100 xs is required atter power-up followed by ariy 8 RAS cycles before proper dewce operation guaranteed
4 C u rrent is a function of cycle rate and output loading, maximum current is measured at the fastest cycle rate with the output
open
Output is disabled (open-circuit) and RAS and CAS are both at a logic I
6 T h e transition time specification applies for all input signals In addition to meeting the transnion rate specification, all input sig-
nals must transmit between V(H and V(L lar between V(L and V(H) in a monotonic manner
7 C apacitance measured with a Boonton Meter or effective capacitance calculated fram the equation C = ~
AV
8 T h e specifications for tp c lmin), and tRw c lmin) are used only ta indicate cycle time at which proper operation over the full tem-
perature range (O'C s TA s 70'C) is assured
9 A C measurements assume t T= 5 0 ns
10 Assumes that tRCp S tRCP (maxi
11 Assumes that (RCpatRCO lmax)
12 Measured with a current load eqtavalent to 2 TTL loads I + 200 rrA, — 4 mA) and 100 PF (VOH = 2.0 V, VOL = — 0.8 V)
13 Operation wi;hin the tR cp (max) hm:I ensures that tRAc (max) can be met tR cp (maxi is spetx fied as a reference point only, if
tRcp is greater than the specified tRcp (maxi hmn, then access time is controlled excluswely by ) cAc.
14 Either tRRH or (RCH must be satisfied for a read cycle
15 These parameters are referenced to CA(x leading edge in random wnte cycles and to WRITE leading edge in delayed wnte or read.
modify-write cycleS
16 tW CS, (CWD, and tRWD are not restrictive operat ng parameterS They are included in the data sheet as electnCal charactern
s ties only if ; wcs 2 (wc s (min), the cycle ~s an early wnte cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle, if tCWp a )CWO (min) and (Ryyp a (Ryyp (min), the cycle is a read wnte cycle and the data out will
contain data read from the selected cell, if neither af the above sets of conditions is sausfied, the condition of the data aut (at
access time) is rndeterminate
17, toff (maX) de(inca the time at WhiCh the OutPut aChieVeS the OPen CirCuit COnditiOn and ia nO( referenCed tO OutPut VOltage leVelS
page 0.222

MCM6633

PIN ASSIGNMENT COMPARISON

M C M4516 MCM4517 MCM6632

I• 16 VSS N/C I• 16 VSS R EEl I• 16 VSS
15 CAS 15 15
14 II7 14 14
13 A6 RAS 13 A6 13 A6
AO 12 A3 AO 12 A3 AO 12 A3
A2 A4 A2 A4 A2 A4
AI 10 A5 AI 10 A5 AI 10 A5
VCC N/C VCC N/C A7
VCC

MCM6633 M C M5664 VICM6665

N/C I• 16 VSS I• 16 VcS N/C I• 16 VSS
15 15 CXS 15 CAS
ld 14 14

RAS 13 A6 13 A6 RAS 13 A6
AO 12 A3 AO 12 A3 AO 12 A3
A2 A4 A2 A4 A2 A4
AI 10 A5 AI 10 A5 AI 10 A5

VCC A7 VCC A" VCC

PIN VARIATIONS

Pin Number MCM4116 MC M4516 MCM4617 MCM6632 MCM6663 MCM6664 MCM6666

VS I — 5VI REFRESH REFRESH N/C REFRESH
Vpp(+ 12 Vt VCC VCC VCC VCC VCC VCC
VCCI + 5 Vi N/C N/C A7 A/ A7

ORDERING INSTRUCTIONS
PART NUMBER DESCRIPTION SPEED MARKING
M C M6633L 15 66330L15/66331L15
M C M 66330L15 32K RAM 66330L15
M C M66331L 15 Sidebraze 66331L15
MCM6633L20 Package 66330L20/66331 L20
"L"
MCM66330L20
MCM66331L20 56331L20
'MCM66330L20 = Tie A7 C~A (A15) Low "0"
MCM66331L20 = T i e A7 CAS (A151 High "I"
 page 0.223

MCM6633

READ CYCLE TIMING

Pi - -

IRAS

VIH
RAS
VII
'CSH IRP

IRSH ICRP
IRCD
VIH iCAS
CAS
VIL

IRAH
IASR IASC
MICAH
Add ass~~ Row Column
VIL Address Address
RRH
IRCS IRCH

ICAC

IRAC IOFF
VOH Va.'id
Q lData Outl High Z
VOL Data

WRITE CYCLE TIMING

IRC
IRAS
VIH
RAS
V IL
IRSH IRP
ICSH
IRC ICAS 'CRP
VIH
CAS
V IL

IRAH
IASP IASC ICAH
VIH
Row Column
Addresses
Address Address

ICWL

VIH
IWCS
+ WCH

I IRWL

D (Data lnl Valrd

Oata

IDHR

VOH
Q (Data Out) High 1
VOL
page 0.224

MCM6633

RAS ORLY REFRESH CYCLE

IData-in and Arne are Don t Care, CAS is HIGH)

IRC

IRP
V IH
If? AS
C'C

VIL

IRAH IR

IASR

Addresses,
Row Address
AO-A6

READ. WRITE/READ-MODIFY-WRITE CYCLE

\RWC
IRAS
VIH

VIL
IRSH IRP
tCSH
IRCD ICAS ICR~
VIH'

IRAH

VIH
IASR tASC Q(CAH
ow olumn
Addresses
A Address
ViL
IRWD ICWL
IRCS ICWD 'RWL
VIH
W
VIL
'WP (OFF
ICAC
VOH
0 (Data Out) Valid
High Z
Data
VOL
I(IAC 'DH
'DS
ViH
Valid
D (Data In)
Data
VIL
 page 0.225

MCM6633

MCMIRNI SIT ADDRESS MAP

Row Address A7 A6 A5 A4 A3 A2 Al AO
Column Address A7 A6A5 A4 A3 A2 Al AO Column Addresses
Her D sc A7 A B A 3 A4 A6 A2 AO A I
FE 264 I I I I I I I 0
FF 255 I I I I I I I I
FC 252 I I I I I I 0 0
FD 253 I I I I I 0 I
FA 250 I I I I I 0 I 0
FB 251 I I I I I 0 I I
FB 248 I I I 0 0 0
F9 249 I I I I I 0 0 I

82 130 I 0 0 0 0 0 I 0
83 131 I 0 0 0 0 0 I
BD 12 8 I 0 0 0 0 0 0 0
81 129 I 0 0 0 0 0 0 I
7F 127 0 I I I I I I I
C 7E 126 0 I I I I I I 0
7D 125 0 I I I I I 0 I
Q

-= O8
O O O o o o

4 0 0 0 0 0 I 0 0
03 3 0 0 0 0 0 0 I I
02 2 0 0 0 0 0 0 I 0
88 01 I 0 0 0 0 0 0 0 I
CO 0 0 0 0 0 0 0 0 0
88 o 8 8 OB Q8

• • • • • mo r o e c o - o

Oo Oo —0

o oa ao

O o o o o

O o o o o o a o

Q Q Q Q O O Q O Q

Oo o o o o o o o

Q a o o o o o o o

C O a a a o o o a o

Data Stored= Dm e AOX • A I y

Cotumn Row Date

Address Address
Stored
AI AO
Inverted
True
True
Inverted
page D.226