ECEXXX DSP Architectures L T P C

3 0 0 3
Version No. 1.00
Prerequisite: Familiarity with digital filters, matrix algebra, and random signal analysis.
Objectives:
This course on digital signal processing architectures which focuses on the implementation and
design of families of DSP architectures with in-depth analysis of the relevant algorithms. Students
learn the essential advanced topics in digital signal processing, Internal DSP architectural
requirements for a DSP device, system level hardware design of DSP Architectures and interfacing
peripherals to programmable DSPs.
Unit I Architectures for Programmable DSP Devices:
Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory,
Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution,
Speed Issues, Features for External interfacing.
Unit II Execution Control & Pipelining:
Hardware looping, Interrupts, Stacks, Relative Branch support, Pipelining and Performance, Pipeline
Depth, Interlocking, Branching effects, Interrupt effects, Pipeline Programming models.
Unit III ADSP Architectures and Synthesis:
Top Down approach to DSP LSI, Circuit Synthesis, High Performance Data conversion Techniques,
LSI Algorithms and Architectures, Hierarchical Design of Processor Arrays, Systolic Arrays, Stack
Filters, Wave-front Array Processors, Floating Point DSP processors, Systolic Processors for Image
Processing; Standard digital signal processors, Application Specific IC‟s for DSP, ADSP system
architectures, Standard DSP architecture, Ideal DSP architectures, Equalizers, Adaptive Equalizers,
Multiprocessors and multi-computers, Systolic and Wave front arrays, Shared memory architectures.
Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared
memory architecture with Bit – serial PEs.
Unit IV Interfacing Memory & I/O Peripherals to Programmable DSP Devices:
Memory space organization, External bus interfacing signals, Memory interface, Parallel I/O
interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA). A Multichannel
buffered serial port (McBSP), McBSP Programming, a CODEC interface circuit, CODEC
programming, A CODEC-DSP interface example.

Textbooks:
1. Avtar Singh and S. Srinivasan , “Digital Signal Processing”, Thomson Publications, 2004.
2. Lars Wanhammer, “DSP Integrated Circuits”, Academic press, New York 1999.
3. Lapsley et al., “DSP Processor Fundamentals, Architectures & Features, S. Chand & Co, 2000.
Reference Books :
1. B. VenkataRamani and M. Bhaskar, “Digital Signal Processors, Architecture, Programming and
Applications”, TMH, 2004.
2. Jonatham Stein, “Digital Signal Processing”, John Wiley, 2005.
3. Bayoumi, MA, VLSI Design Methodology for DSP Architectures, Klumer, 1994.
4. Sung-Yuan Kung, Robert E. Owen, J. Gerg Nash, “VLSI Signal Processing” Vol.1, Vol. II
IEEE Press. 1986.
Mode of Evaluation: CAT- I & II, Assignments/ Quiz, Term End Examination.

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