REAL TIME DIGITAL SIGNAL PROCESSING

by

LUIS EDUARDO LONDONO, B.S.

A THESIS

IN

ELECTRICAL ENGINEERING

Submitted to the Graduate Faculty

of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of

MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING

Approved

Accepted

May, 1982
 / *-
/ •

ACKNOWLEDGMENTS

I wish to express my gratitude to Dr. Donald Gustafson for his

assistance in the statement and solution of the problems presented in
this thesis and his guidance in the preparation of the manuscript.
I wish to thank the Learning Center of Texas Instruments Incorporated
for having initiated the Master Degree program under which I pursued
the graduate studies at Texas Tech University.

11
 CONTENTS

ACKNOWLEDGMENTS ii
LIST OF FIGURES v
LIST OF TABLES vii
I. INTRODUCTION 1
1.1 S t a t e m e n t o f t h e Problem 1
1.2 S i g n a l Sampling 1
1.3 Z-Transform 3
1.4 D i s c r e t e - T i m e Systems 4
1.5 Overview 4
II. DIGITAL SIGNAL PROCESSING HARDWARE 6
2.1 Introduction 6
2.2 Block Diagram 6
2.3 Address Decoder 9
2.4 Sampler and A/D Converter 10
2.5 Multiplier Data Interface 10
2.6 Multiplier 11
2.7 Accumulator 12
2.8 Digital to ikialog Converter 13
2.9 Echo Cancellation 14
2.10 Summary 14
III. DIGITAL FILTERS 25
3.1 Introduction 25
3.2 B i l i n e a r Transformation 26
3.3 Frequency T r a n s f o r m a t i o n 27
3.4 P r o t o t y p e Low-Pass F i l t e r 28
3.5 T r a n s f o r m a t i o n of a P r o t o t y p e F i l t e r 35
into other Digital Filters
3.6 Low-Pass t o Low-Pass T r a n s f o r m a t i o n 35
3.7 Low-Pass t o H i g h - P a s s T r a n s f o r m a t i o n 38
3.8 Low-Pass t o B a n d - P a s s T r a n s f o r m a t i o n 43
3.9 Low-Pass t o Band-Stop T r a n s f o r m a t i o n 50
3 . 1 0 Summary 53
iii
 IV. ECHO CANCELLATION 56
4.1 Introduction 56
4.2 Echo Synthesis 57
4.3 Echo Cancellation 59
V. CONCLUSIONS 63
LIST OF REFERENCES 65
APPENDIX 66

IV
 LIST OF FIGURES

1.1 S i g n a l sampler 2
2.1 Block diagram of hardware 8
2.2 Address decoder 15
2.3 Sampler and A/D c o n v e r t e r 16
2.4 Multiplier data interface 17
2.5 Multiplier 18
2.6 Subproduct adder 19
2.7 Product complementer 20
2.8 Accumulator 21
2.9 Accumulator clock 22
2.10 D i g i t a l to analog c o n v e r t e r 23
2.11 Echo sampling and delay c i r c u i t 24
3.1 Digital f i l t e r 25
3.2 Flow diagram of f i r s t order low-pass d i g i t a l f i l t e r 29
3.3 Response of f i r s t order low-pass d i g i t a l f i l t e r 30
3.4 Flow diagram of t h i r d order low-pass d i g i t a l f i l t e r 33
3.5 Response of t h i r d order low-pass d i g i t a l f i l t e r 34
3.6 Transformation from low-pass t o low-pass f i l t e r 36
3.7 Flow diagram of transformed f i r s t order low-pass f i l t e r . . . . 37
3.8 Low-pass t o h i g h - p a s s t r a n s f o r m a t i o n 39
3.9 Response of f i r s t order h i g h - p a s s d i g i t a l f i l t e r 41
3.10 Response of t h i r d order h i g h - p a s s d i g i t a l f i l t e r 42
3.11 Low-pass t o band-pass t r a n s f o r m a t i o n 43
3.12 Flow diagram of f i r s t order band-pass d i g i t a l f i l t e r 45
3.13 Response of f i r s t order band-pass d i g i t a l f i l t e r 46
3.14 Flow diagram of t h i r d order band-pass d i g i t a l f i l t e r 48
3.15 Response of t h i r d order band-pass d i g i t a l f i l t e r 49
3.16 Low-pass t o band-stop t r a n s f o r m a t i o n 50
3.17 Response of f i r s t order band-stop d i g i t a l f i l t e r 52
3.18 Response of t h i r d order band-stop d i g i t a l f i l t e r 54

v
4.1 Typical long distance telephone circuit 56
4.2 Typical impulse response 58
4.3 Block diagram of echo cancellation 59
4.4 Flow diagram of echo cancellation 61
4.5 Results of echo cancellation 62

VI
 LIST OF TABLES

2.1 Summary of addresses 9

2.2 Data interface addresses 10
2.3 Subproducts of multiplier 11
2.4 Weights of the multiplier 12
2.5 Accumulator control signals 13
3.1 Indexed address for third order filters 32
4.1 Indexed address for echo cancellation 60

Vll
 CHAPTER I

INTRODUCTION

1.1 Statement of the Problem

Digital signal processing is used in applications that include

spectrum analysis, pattern recognition, electrocardiogram processing,
noise elimination, modification of frequency spectrum, echo cancella-
tion, seismic wave analysis, etc.
Our objective is to demonstrate the realization of digital signal
processing in real time. We will design digital filters and perform
echo cancellation. Special hardware will be required which includes a
microprocessor, random access memory (RAM), a sampler and fast processing
circuits. The analog input will be sampled, digitized and loaded into
the microprocessor. Digital signals are processed according to algo-
rithms that require multiplication of variables by given constants.
Digital signal processing can be achieved in real time if the multipli-
cation time is short compared to the required processing period. We
will use a fast 8 bit by 8 bit TTL multiplier. We will also incorporate
an external accumulator for addition and subtraction of the products.
The input and output data will be stored in a 4 K RAM using relative
indexed addressing. The digital output of the accumulator will be
converted to analog at the end of each processing cycle. The micro-
processor programs will be entered in machine language which allows
fast execution speed. The response of the digital filters and the
echo cancellation will be shown in graph form.

1.2 Signal Sampling

Digital signal processing usually requires t h a t a sample of an
analog signal be taken at uniformly spaced time i n s t a n t s . This
sequence of samples i s called the discrete-time s i g n a l . An ideal
sampler i s considered to have a modulator signal that c o n s i s t s of a
sequence of impulse functions expressed by Eq. (1.1). A sampler can
be designed in practice utilizing a sample and hold amplifier followed
by an analog to digital converter

g(t) = Z 6(t-nT) (1.1)

n=-oo

where T is the sampling interval.

f(t) f*(t)

g(t) J
Figure 1.1 Signal sampler

The output of the sampler f*(t) is given by Eq. (1.2) and consists of
a series of impulses with area f(t).

f*(t) = Z f(t)6(t-nT) (1.2)

n=-oo

The discrete-time signal f*(t) is sent to the processing circuits to

be transformed according to an algorithm that depends on the function
to be performed. A practical application of digital signal processing
is in digital filters. We will also find an application in echo can-
cellation in telephone systems. The sampling pulse train g(t) can be
expressed in terms of Fourier series

g(t) = E ieJ^'^st (1.3)

n=-«> i

where Wg is the sampling frequency. The sampled signal f*(t) is the

product of the input signal f(t) and the modulating train g(t)

f*(t) = f(t)g(t) (1.4)

Replacing Eq. (1.3) into Eq. (1.4), we obtain

f*(t) = Z k(t)eJ'''^st (1.5)

n=-oo ^
Taking the Fourier transform of Eq. (1.5) and applying the shifting
theorem, we obtain

F*(a)) = -^ Z F((D-na)_) (1.6)

Eq. (1.6) indicates that the Fourier transform of a sampled signal

consists of frequency bands spaced according to the sampling frequency
(jOg. The sampling process introduces new spectral components that are
frequency translations of the fundamental band F((JO) ; the highest
frequency of F(a)) must be less than or equal to ^i Wg in order to
prevent overlapping of the bands.
There is another approach to the Fourier transform calculation
of a sampled signal. It consists of considering the input signal as
a constant during the sampling interval.

f(t)| = f(nT) (1.7)

I t=nT

Replacing Eq. ( 1 . 7 ) i n t o Eq. ( 1 . 2 ) , we o b t a i n

f*(t) =
Z f(nT)6(t-nT) (1.8)
n=-a>
The Fourier transform of Eq. (1.8) is
F*(o.) = 1 f(nT)e-^"'"T (^•'>
n=_oo

1.3 Z-Transform

The Laplace t r a n s f o r m of a sampled s i g n a l can be obtained from

the e x p r e s s i o n given by Eq. (1.9) with t h e s u b s t i t u t i o n of jto by s .

F*(s) = Z f(nT)e"'^^^ (1.10)

n=_oo

If we make t h e s u b s t i t u t i o n z = e^^, we o b t a i n t h e Z-transform F*(z).

F*(z) = Z f(nT)z-^ (1.11)

n=-oo
The Z-transform i s used i n t h e c a l c u l a t i o n of d i g i t a l f i l t e r s . It is
a mathematical t o o l t o o b t a i n t h e a l g o r i t h m expressed as a d i f f e r e n c e
equation.
The Z-transform of a delayed s i g n a l i s very important in t h e
conversion of Z-transform e x p r e s s i o n s i n t o d i f f e r e n c e e q u a t i o n s . It
can be demonstrated t o be [ l ]

Z{f(t-kT)} = F ( z ) z " ^ (1.12)

where kT i s t h e delay of t h e s i g n a l .

1.4 Discrete-Time Systems

A c a u s a l , l i n e a r , t i m e - i n v a r i a n t system with input f(nT) and

output y(nT) can be r e p r e s e n t e d by a d i f f e r e n c e equation of t h e form
M N
y(nT) = Z ai,f(nT-kT) - Z buy(nT-kT) (1.13)
k=0 k=l ^
where M and N are integers or could be infinite. If b^ = 0 for k = 1,
...., N, then the system is nonrecursive and it is called a transversal
filter with M + 1 taps. If N > 1 and h-^ is not zero, then the system
is called an Nth order recursive filter. Taking the Z-transform on
both sides of Eq. (1.13)
J^ -k N -k
Y(z) = F(z) Z a^z - Y(z) Z bi,z ^ (1.14)
k=0 ^ k=l ^
we can now derive the pulse transfer function

M -k
L aj^z

1 + Z bvz
k=l ^
A Z-transform e x p r e s s i o n such as t h a t given by Eq. (1.15) can be
transformed i n t o a d i f f e r e n c e equation given by Eq. ( 1 . 1 3 ) . I t i s an
a l g o r i t h m t h a t can be processed by a d i g i t a l computer or microprocessor.

1. 5 Overview
In t h i s chapter we have covered t h e g e n e r a l sampling t h e o r y , the
Z-transform and d i s c r e t e - t i m e systems. We examined the transformation
of Z-transform expressions into difference equations. Chapter I I i s
dedicated to the hardware we used for d i g i t a l signal processing. First
we present a block diagram of the system. The microprocessor i s used
b a s i c a l l y for data handling. A sampler i s used to take samples of the
analog input at constant i n t e r v a l s . The samples are d i g i t i z e d and
loaded into the microprocessor. The f a s t m u l t i p l i e r generates the
product of a v a r i a b l e by a decimal f a c t o r . The external accumulator
i s used to add or subtract the f i n a l products. Finally, the d i g i t a l
output of the accumulator i s converted to analog in order to obtain
the desired response.
D i g i t a l f i l t e r s are analyzed in Chapter I I I . We will examine the
general theory of d i g i t a l f i l t e r s . The b i l i n e a r transformation w i l l
be presented which we w i l l use to design low-pass d i g i t a l f i l t e r s . We
w i l l discuss the transformation of a prototype low-pass f i l t e r into
high-pass, band-pass, band-stop, and other low-pass f i l t e r s . We w i l l
present the flow diagrams that we used to implement the d i g i t a l f i l t e r s .
The experiment of echo cancellation in telephone systems w i l l be
examined in Chapter IV. The echo w i l l be sjmthesized u t i l i z i n g a
d i s c r e t e - t i m e convolution process. The synthetic echo w i l l then be
subtracted from the actual echo in order to cancel i t .
In Chapter V we w i l l present the conclusions of the experiments
performed with d i g i t a l f i l t e r s and echo cancellation. The micro-
processor programs u t i l i z e d in the experiments are included in the
Appendix.
 CHAPTER II

DIGITAL SIGNAL PROCESSING HARDWARE

2.1 Introduction

The first step in digital signal processing is to take a sample of

the analog input. We perform the sampling utilizing a sample and hold
amplifier. The sample is then converted to digital. This digital
sample is loaded into a microprocessor and stored in memory. A fast
multiplier is used in order to have a high sampling frequency; otherwise,
the microprocessor would take a long time to multiply by itself. The
product from the fast multiplier is added to or subtracted from an
external accumulator which is provided to save microprocessor time.
The output of this accumulator can be sent directly to a digital to
analog converter from which the desired response is obtained.

2.2 Block Diagram

The digital signal processing in real time was achieved utilizing

a processing circuit interfaced with a Heathkit ET-3400 microprocessor
trainer with memory and input/output accessory ETA-3400. Fig. 2.1
shows the block diagram. The MC68B00 microprocessor is utilized in
the trainer with a 2 MHz clock that provides the two phases, <j)l and (})2,
required by the microprocessor. The clock frequency is controlled by
an 8 MHz crystal. The original operating frequency of the microprocessor
trainer was increased to 2 MHz to allow a higher sampling frequency.
The microprocessor interfaces with the 4K RAM in the accessory and the
processing circuit through address and data buffers.
The 4 K R A M is composed of TMS2114 devices, each of which has
lKx4 bits; therefore, eight devices are required to have a 4K RAM
with eight bits at each memory location. Partial address decoding of
the RAM is provided by a ROM in the ETA-3400 accessory which assigns
addresses 0000 - OFFF to the RAM.
 The first step that must be taken in digital signal processing is
to sample the analog input utilizing a sample and hold amplifier which
is controlled by the DR signal from the A/D converter. The sampled
signal is converted to digital by means of a 2'S complement analog to
digital converter. It interfaces with the data bus and the micro-
processor by means of the ADC buffer which is controlled by the address
decoder. The 8 bit by 8 bit multiplier receives the multiplicand and
multiplier from the peripheral interface adapter (PIA). The multipli-
cand is sent from the microprocessor with address 4C00. It is a 2'S
complement digital signal. If the multiplicand is negative, it is
complemented before the multiplication is performed and the product
recomplemented after the multiplication. The multiplier is just a
decimal factor where bit 7 determines the sign. A "1" indicates a
negative multiplier. A "0" means it is positive. The multiplier is
sent to the PIA with address 4C02. The multiplier output has 16 bits
but we take only the eight most significant bits. The product goes to
an accumulator which also has an arithmetic logic unit for addition and
subtraction. It has control signals to determine the operation to be
performed. The accumulator performs a subtraction when the multiplier
sign is negative or when the multiplicand is sent to the PIA with
address 4C20 or 4C30. A "1" on bit 5 sets the accumulator to subtract.
A "1" on bit 4 generates a clock pulse to accumulate the product
internally and it sets the accumulator ready to accept another product.
The last multiplicand in a given cycle should be sent with a "0" on
bit 4 of the PIA address in order to prevent a double addition or
subtraction before the result in the accumulator is output. The
accumulator interfaces with the data bus and the microprocessor through
a buffer enabled with address 5000. This address also starts the
digital to analog converter (DAC) . It takes the digital data from the
accumulator and generates an analog output. The DAC can also take data
from the microprocessor when enabled with address 8000. The DAC
operates on 2'S complement signals and generates an offset output of
0 to 10 volts. A circuit with two operational amplifiers eliminates
the offset and gives an output with correct polarity.
 8

Address
Buffer C Microprocessor
<=c> Data
Buffer

f(t)
EJ
I Clock

2'S Complement ADC

Sampler A/D Converter O Buffer : = >

J
Address 1
Decoder
Accumulator t> Ace.
Buffer = ^

1 Peripheral
Multiplier Interface
C Adapter

J
2 ' S Complement
D/A C o n v e r t e r
Echo

I i
Sampler
Output Subtracter and Delay
Circuit

RAM Memory
(RAM) ^
Decoder

V
Address Data
Bus Bus
Figure 2.1 Block diagram of hardware
 A delay circuit was incorporated for echo cancellation. The
input is applied to a sampler. The sampled signal goes to an analog
to digital converter. The signal is converted back to analog after a
delay determined by the microprocessor program. The output of the DAC
has an offset which is corrected using an operational amplifier. This
signal is then subtracted from the synthetic echo generated by the
processing circuits.

2.3 Address Decoder

Device U301 (74LS42) on Fig. 2.2 is used for decoding addresses

A12 through A15. When an address is decoded, the corresponding output
on U301 goes low. The microprocessor trainer output VMA02 is buffered
with device U303B. It provides an enable signal (ENA) that is used
with all the decoded addresses in order to ensure that they go low only
when the address is valid and the clock is on phase 2.

Table 2.1 Summary of addresses

Signal
Address Name Gate Function
3000 PR UlUA Read product or result from accumulator
4000 CS2 U302A Enable peripheral interface adapter
5000 ACR U302B Read accumulator and start DAC
6000 ADC U302C Start ADC
7000 ADR U302D Read digital signal from ADC
8000 DAC U306C Convert digital signal to analog
9000 CLAl UlllB Clear accumulator
6800 CLA2 U306D Clear accumulator and start ADC

Table 2.1 indicates the name and function of each address and also the
gate used in Fig. 2.2. Signal RE enables the microprocessor to read
signals from the processing circuit. It goes low when one of the
signals PR, ACR, or ADR is low and R/W is high. Gates U303D, U304A,
and U304B are used to generate RE. A diode is provided in order to
 10

isolate RE from a similar signal in the ETA-3400 accessory. The

signals CLA and CLA are used to clear the accumulator when either CLAl
or CLA2 is low as determined by the addresses specified in Table 2.1.
Gate U303A generates signal CLA which is inverted by gate U206E.

2.4 Sampler and A/D Converter

The sampler and A/D converter are shown in Fig. 2.3. The analog
input is sampled once per processing cycle utilizing device U312 (AD582)
which is a sample/hold integrated circuit. The output signal of U312
is held at a constant value during the analog to digital conversion by
the DR (Data Ready) signal from ADC device U U O (AD570) .
The A/D conversion starts when address 6000 or 6800 is decoded. A
negative going pulse is applied to latch U304C - U304D which makes the
B/C (Blank/Convert) input of the ADC go high. The DR (Data Ready)
output goes high 1.5 ys later and resets the latch. The B/C input
goes back to low to start a new conversion. At the end of the conver-
sion which takes about 25 ys, the data is presented at the output of
the ADC in offset binary code. It is converted to 2'S complement code
by inverting bit 7 using inverter U305C. The 2'S complement digital
signal is presented to buffer U109 (74LS244). Its output is enabled
when address 7000 is decoded. The data is sent to the microprocessor
via the data bus.

2.5 Multiplier Data Interface

The interface circuit is shown in Fig. 2.4. The multiplicand and

multiplier are stored in the peripheral interface adapter U500
(MC68B21) when the respective address is decoded according to
Table 2.2.

Table 2.2 Data interface addresses

Address Function
4C00 Load multiplicand into side A of PIA
4C02 Load multiplier into side B of PIA
 11
The multiplicand i s a 2'S complement binary number where a " 1 " on b i t 7
means that i t i s negative. In t h i s case the multiplicand is complemented
u t i l i z i n g quad EX-OR devices U201 and U202 (74LS86). The eight b i t
binary multiplicand i s inverted and then a " 1 " i s added to b i t 0 using
devices U203 and U204 (74LS83). Positive multiplicands go through the
complementer without any change. The m u l t i p l i e r i s stored on side B
of PIA. Bit 7 of the m u l t i p l i e r i s the sign b i t . A "0" means i t is
p o s i t i v e and a " 1 " means i t i s negative. Bit 7 i s not used in the
multiplication per se but i t i s considered l a t e r to add or subtract the
product in the accumulator.

2 . 6 Multiplier

The 8 b i t by 8 b i t multiplication is performed u t i l i z i n g read

only memory integrated c i r c u i t s 74S274, each of which multiplies 4 b i t s
by 4 b i t s to generate a subproduct. The multiplier i s shown on
Figs. 2 . 5 , 2.6 and 2 . 7 . We divide the multiplicand into two sections
XL and Xjj. We physically shift the multiplier to the l e f t and place a
"0" on b i t 0. We also divide the multiplier into two sections YLandY^.
The 4 b i t sections are then applied to the four m u l t i p l i e r s UlOl, U102,
U103 and U104 (74S274). Four subproducts are obtained from these
m u l t i p l i e r s according to Table 2 . 3 .

Table 2.3 Subproducts of multiplier

Input A Input B Subproduct
2^ _ 2l5
XH %
24 . 2ll
% YL
24 _ 2ll
H %
20 _ 27
H ^L

The multiplier in this particular design is a decimal factor with

weights specified in Table 2.4.
 12
Table 2.4 Weights of the m u l t i p l i e r
Bit Weight
B7 -1.0
B6 0.5
B5 0.25
B4 0.125
B3 0.0625
B2 0.03125
Bl 0.015625
BO 0.0078125

The subproducts w i t h t h e same exponent a r e added using devices U207,

U208, U209 and U210 (74LS183) as shown in Fig. 2 . 6 . The Z and Cn + 1
o u t p u t s of t h e s e adders are again added u t i l i z i n g d e v i c e s U307 and
U308 (74LS83). The 2 C ^ ^ ^ c a r r y of U210 i s added to the 2^2 gubproduct,
The C4 c a r r y of U308 i s added to the 213, 2^^ and 2^^ subproducts
u t i l i z i n g d e v i c e U309 (74LS83). A 16 b i t product Z0-Z15 i s generated
a f t e r a l l t h e s e a d d i t i o n s , but we take only t h e e i g h t most s i g n i f i c a n t
b i t s Z8-Z15. If t h e o r i g i n a l m u l t i p l i c a n d was a 2'S complement nega-
t i v e number, the product i s recomplemented u t i l i z i n g t h e c i r c u i t shown
in Fig. 2.7 in order to o b t a i n the f i n a l product P0-P7.

2.7 Accumulator

The external accumulator was designed as shown in Fig. 2.8 in

order to speed up the data processing. Devices U105 and U107 (74S281)
are the accumulators which add or subtract the product from the multi-
plier. The control signals ASO, ASl, M and Cn are set by the flip-
flops U211A and U211B (74LS74) according to the functions listed in
Table 2.5.
 13

Table 2.5 Accumulator control signals

A^l ASO M Cn Accumulator function

H H L L Add
L H L H Subtract
L L H X Clear

The accumulator is set to add when the multiplier is positive and the
multiplicand is output by the microprocessor with address 4C00 or 4C10.
It is set to subtract when the multiplier is negative or the multipli-
cand is output with address 4C10 or 4C30. The accumulator is cleared
when the signal CLA goes low and it occurs when address 6800 is
decoded. The output of the accumulator is stored into its internal
register when it receives a clock pulse. The circuits shown in Fig. 2.9
were used to generate the clock pulse. The first "one shot" flip-flop
U310A (74LS221) generates a 2 us delay. The second "one shot" U310B
generates the actual clock pulse.

2.8 Digital to Analog Converter

The digital signal from the accumulator or the microprocessor can

be converted to analog utilizing the circuit shown in Fig. 2.10.
Bit 7 of the digital input is inverted in order to convert the signal
to offset binary code. The D/A conversion is performed on the positive
going edge applied to the CS input when addresses 5000 or 8000 are
decoded. The analog output of device U311 (AD558) is from 0 V to 10 V.
It is converted to bipolar (-5V to 5V) by offsetting it with the
operational amplifier U412A. The offset is determined by resistor R4
and potentiometer PI. The output of U412A is bipolar but inverted.
It is brought back to the correct polarity with operational amplifier
U412B.
 14

2.9 Echo Cancellation

The experiment of echo cancellation treated in Chapter IV requires

that the echo be subtracted from the output of the processing circuit.
Fig. 2.11 shows the circuits utilized for the sampling and digital
conversion of the echo. This digital signal is converted back to
analog after a delay determined by the processing circuit. The delay
is necessary to have the synthetic echo, generated by the microprocessor
and associated circuits, in phase with the actual echo.

2.10 Summary

In this chapter we covered the circuits we utilized in digital

signal processing. The microprocessor controls the timing of all the
operations performed. The address decoder receives the digital input
from the microprocessor. Each circuit is activated when it receives
the corresponding signal from the address decoder. The sampler and
A/D converter sample the analog signal and convert it to digital.
This digital signal is loaded into the microprocessor to be stored in
memory. A fast TTL multiplier was incorporated in order to have a
short processing period. The multiplier receives the data inputs from
the data interface circuit composed of a peripheral interface adapter
and a negative signal complementer. The output of the multiplier is
sent to an external accumulator where it is added to or subtracted
from its contents. The output of the external accumulator is sent to
a digital to analog converter from which we take the desired response.
Finally, the experiment of echo cancellation requires that the actual
echo be sampled and delayed in order to be subtracted from the synthetic
echo. The delay is achieved by converting the actual echo to digital
and then converting it back to analog in synchronism with the synthetic
echo.
 15

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 CHAPTER I I I

DIGITAL FILTERS

3.1 Introduction

A digital filter i s a d e v i c e t h a t modifies t h e frequency spectrum

of a s i g n a l u s i n g a d i g i t a l s y s t e m . The c h a r a c t e r i s t i c s of a d i g i t a l
filter can be changed v e r y e a s i l y w i t h a s o f t w a r e c h a n g e . Another
i m p o r t a n t a d v a n t a g e of d i g i t a l f i l t e r s i s t h e h i g h a c c u r a c y and r e l i -
a b i l i t y s i n c e t h e component t o l e r a n c e s a r e n o t c r i t i c a l . Filters are
u s e d f o r many p u r p o s e s . These i n c l u d e e l i m i n a t i o n of n o i s e , separation
of s i g n a l s which were mixed f o r t r a n s m i s s i o n , d e m o d u l a t i o n of signals
and m o d i f i c a t i o n of t h e f r e q u e n c y s p e c t r u m of a s i g n a l .
In t h i s c h a p t e r we w i l l c o n s i d e r d i g i t a l f i l t e r s in g e n e r a l . We
w i l l examine t h e b i l i n e a r t r a n s f o r m a t i o n which i s used t o d e s i g n
d i g i t a l f i l t e r s b a s e d on a n a l o g f i l t e r s . Then we w i l l d e r i v e t h e
f r e q u e n c y t r a n s f o r m a t i o n which r e s u l t s from t h e b i l i n e a r transformation
F i r s t and t h i r d o r d e r p r o t o t y p e l o w - p a s s f i l t e r s w i l l be d e s i g n e d . We
w i l l transform t h e s e low-pass f i l t e r s into high-pass, band-pass, band-
s t o p , and o t h e r l o w - p a s s f i l t e r s . The flow diagram and r e s p o n s e of
first and t h i r d o r d e r f i l t e r s w i l l be p r e s e n t e d . The m i c r o p r o c e s s o r
p r o g r a m s t h a t we u s e d a r e shown i n t h e Appendix. A digital filter
can be r e p r e s e n t e d a s shown i n F i g . 3 . 1 .

F(a)) ^ F*(a)) Y*(a))

f(t) T f(nT) y(nT)

Figure 3.1 Digital filter

25
 26

The signal Y*(iu) is given by the following expression

Y*(a)) = F*(a))G*(u)) (3.1)

where G*(aj) is the sinusoidal steady state response of the system. It

can be demonstrated [l] that

Y(a)) = F(a))G*(a)) for |a)|< 0)3/2 (3.2)

Eq. (3.2) i n d i c a t e s t h a t t h e spectrum F(u)) of a band-limited s i g n a l can

be modified u s i n g a d i g i t a l f i l t e r with s i n u s o i d a l steady s t a t e
response G*(a)) .

3.2 B i l i n e a r Transformation

The b i l i n e a r transformation

1 + s (3.3)
z = -.
1 - s

i s used t o map t h e s - p l a n e i n t o the z - p l a n e , where s = a + jo) and

oz b=t a ire"'
n . Replacing t h e s e e x p r e s s i o n s of s and z i n t o Eq. ( 3 . 3 ) , we
^^j9 ^ l + g + j o ) (3.4)
1 - a- jco

The magnitude | r | is
(1+5)2+0)2 h (3.5)
r = (1-a)^ +0)^

From Eq. (3.5), we can see that

r >1 for a > 0 (3.6)
r = 1 for 0 = 0
r <1 for a < 0
 27

The bilinear transformation maps:

a) t h e r i g h t half of t h e s - p l a n e onto t h e region o u t s i d e the u n i t
circle | z | = 1 of the z - p l a n e ,
b) t h e j a x i s of t h e s - p l a n e onto t h e u n i t c i r c l e | z | = 1 , and
c) t h e l e f t h a l f of the s-plane onto the i n t e r i o r of the u n i t
circle | z | = 1.
We w i l l use t h e b i l i n e a r t r a n s f o r m a t i o n to design d i g i t a l f i l t e r s based
on d e s i g n s of analog f i l t e r s .

3.3 Frequency Transformation

The b i p o l a r t r a n s f o r m a t i o n r e s u l t s in a d i f f e r e n t frequency
range of t h e d i g i t a l f i l t e r with r e s p e c t to t h e analog f i l t e r . Let
Q and o) r e p r e s e n t t h e frequency in t h e analog f i l t e r and d i g i t a l
f i l t e r respectively. From the b i l i n e a r transformation

z - 1 (3.7)
z+1
• rn

If a = 0, s = jfi, and z = e'^ , then

j"^"^-! (3.8)
jfi = - ^
e-^ +1

•n ' . ^T (3.9)
jn = jtan—
and ™
Q = tan^ (3.10)

We can e s t a b l i s h t h e frequency mapping ranges

0 <ui < a)g/4 -^ 0 <fi < 1 (3.11)

a)g/4 < 0) < oag/2 -> 1 < f2 < o°

An i n f i n i t e range of frequencies fi in t h e analog f i l t e r a r e compressed

i n t o a narrow range in the d i g i t a l f i l t e r . This e f f e c t i s c a l l e d
frequency warping. The c r i t i c a l frequencies such as cutoff, band-pass,
and band-stop must be prewarped according to Eq. ( 3 . 1 0 ) .
 28

3.4 Prototype Low-Pass Filter

The Butterworth low-pass filter is usually used as a prototype.

The squared amplitude response of an Nth order filter is

^^"^^ = ~ 9? (3.12)
1 + (a)/f2c)
The Butterworth filter has the property that A(n^) = if or -3dB
for all N. The squared amplitude A(a)) is given in terms of G(ja)) as

A(a)) = G(ja))^ = G(jcL))G(-ja)) (3.13)

Letting o) = s/j, we can find A(s).

A(s) = G(s)G(-s) = I (3.14)

G(s) can be expressed as a product.

G(s) = 1 ^ = 5k (3.15)

where sj^ are the poles of G(s).

First Order Low-Pass Filter

The Butterworth first order low-pass filter can be expressed on
the s-plane as

G(s) = - ^ (3.16)
s +1
The expression (3.16) can be transformed into the z-plane utilizing
the bilinear transformation, and we obtain

;(z) = ii+i^z ^ (3.17)

 1 29

Initialize Send y(nT)

PIA to DAC

I I
Store 1/2 Transfer ace.A
as multiplier t o a c e . B. Keep
f (nT - T) i n a c e . B

I I
Load f(nT)
from ADC Wait 10 ysec.
into ace.A

I
Clear external
accumulator and
start ADC

I
Add product
(l/2)f(nT)

I
Wait 2 ysec.

I
Add product
(l/2)f(nT-T)

Figure 3.2 Flow diagram of first order low-pass digital filter

 30
G*

0.2

f(KHz)
6 8 10 12 14
(a) Amplitude response

f(KHz)

A Experimental d a t a

-180'
(b) Phase response

Figure 3.3 Response of f i r s t order low-pass d i g i t a l filter

 31

and it can be realized by the difference equation

y(nT) = iif(nT) + iif(nT-T) (3.18)

The flow diagram of the filter is shown in Fig. 3.2. It is executed

with the microprocessor program 1 listed in the Appendix. The sampling
frequency found was 38.46 KHz and the cutoff frequency measured was
9.6 KHz. Fig. 3.3 shows the frequency response and phase angle of the
filter output.

Third Order Low-Pass Filter

The third order Butterworth low-pass filter is given by the
expression

G(s) = ^ ».19)
s^ +2s +2s + 1

Eq. (3.19) can be converted to t h e z-transform with the b i l i n e a r

t r a n s f o r m a t i o n and we o b t a i n

G(z) = 1 ^ ^ 3 z - ^ ^ 3 z - +Z-3

1+|.

The inputs and outputs of the filter are stored in memory with a rela-
tive address with respect to the index register as shown in Table 3.1.
The microprocessor program for the third order filter is more complex
than that used for the first order filter. The longer processing time
results in lower sampling frequencies.
 32

Table 3,1 Indexed address for third order filters

Relative Indexed
Variable Address
y(nT-T) 01
f(nT-T) 02
y(nT-2T) 03
f(nT-2T) 04
y(nT-3T) 05
f(nT-3T) 06
y(nT-4T) 07
f(nT-4T) 08
y(nT-5T) 09
f(nT-5T) OA
y(nT-6T) OB
f(nT-6T) OC

The inputs and outputs are also stored in the stack in order to have
the data readily available when the index register jumps back to the
upper end of the allowed memory. This jump of the index register is
achieved by transferring the stack pointer to the index register. The
memory area from 09FF to OFFF is assigned to the stack pointer and
the area from 03FF to 09FF is for the index register. We start the
program execution at the high end of the memory allowed for the index
register and stack pointer.
The cutoff frequency w^ can be calculated utilizing Eq. (3.10)
with T = 27r/a)g. We obtain w^ = Wg/4, where Wg is the sampling
frequency. The filter can be realized with the difference equation

(3.21)

y(nT) = |f (nT) +-|-f(nT-T) + |f(nT-2T) +-|f (nT-3T) - ^(nT-2T)

The filter was actually executed following the flow diagram shown in
Fig. 3.4. The sampling frequency found was 16.12 KHz and the cutoff
frequency measured was 4.04 KHz. The microprocessor program is shown in
the Appendix.
 33

1 1
Initialize PIA Send y(nT)
and index regis- Add
t o DAC and
ter (//09FF) (l/2)f(nT-2T)
load i t i n t o ace. A

I I I
Load #0FFF Load f(nT- -T)
into Push f(nT)
i n t o a c e . A,
stack pointer X = 02 into stack

I I I
Clear external
accumulator and Add Push y(nT)
start ADC (l/2)f(nT-T) into stack

I i I
S t o r e 1/3 a s Store 1/6 as
Store f(nT) a t
multiplier multiplier
X = 00 and decrement
index r e g i s t e r

I I I
Load y ( n T - 2 T ) Load f ( n T - 3 T ) Store y(nT)
i n t o ace. A, X = 03 i n t o ace. A, X=06 a t X= 00

I I
Subtract Add
(l/3)y(nT-2T) (l/6)f(nT-3T)

I I
Load f(nT) Transfer
S t o r e 1/2 as from ADC i n t o stack pointer
multiplier ace. A to index r e g i s t e r

I I
Decrement
Load f ( n T - 2 T ) Add
index r e g i s t e r
i n t o a c e . A, X = 04 (l/6)f(nT)
and wait 8 cycles

Figure 3.4 Flow diagram of t h i r d order low-pass d i g i t a l filter

 34
G*|

1.0

0.8 •

0.6 ••

0.4 -

0.2 ••

0.0 f(KHz)
3 4 5 6 8
(a) Amplitude response

f(KHz)

A Experimental d a t a

- 1 8 0 ••

(b) Phase response

Figure 3.5 Response of t h i r d order low-pass d i g i t a l filter

 35

3*5 Transformation of a Prototype F i l t e r

into other D i g i t a l F i l t e r s

A prototype low-pass f i l t e r with a cutoff frequency a)g/4 can be

transformed into another low-pass f i l t e r or into a high-pass, band-
pass, or band-stop f i l t e r by making a s u b s t i t u t i o n for z that maps the
u n i t c i r c l e into i t s e l f . The transformation was f i r s t proposed by
Constantinides [ 2 ] . We w i l l use the variables Z and fJ as the argument
and r e a l frequency v a r i a b l e of the prototype low-pass f i l t e r , and we
w i l l use the v a r i a b l e s z and w for the transformed f i l t e r . The t r a n s -
formation required to map the unit c i r c l e on the Z-plane onto the unit
c i r c l e in the z-plane i s of the form

A ^A -1^ ^ -N -N^/ - U (3.22)

Z = f (z) = ± = ±
l+diZ-^ + +dNz"^ D(z)

where D(z) is a polynomial with real coefficients and all its roots are
inside the unit circle. The roots of D(z~l) are the reciprocal of the
roots of D(z) and must lie outside the unit circle. D(z) has constant
coefficients and the conjugate of any of its complex roots must also
be a root.
Let p.,...,p be the roots of D(z) and let us factor expression
(3.22)
_^ N z-1 -p^* (3.23)
Z = ± n
k=l 1 -p, z

3.6 Low-Pass t o Low-Pass Transformation

A prototype low-pass f i l t e r can be transformed into another low-
pass f i l t e r of different cutoff frequency u t i l i z i n g the transformation
formula
7-1 _ z-^ - p (3.24)
1 -pz-1
 36

The point Z 1 with f2 = 0 is mapped to the point z = 1 with o) = 0.

The point Z -1 with fi = ± a)g /2 is mapped to the point z = -1 with
0) = a)g/2.

Let Z = e -^ and z = e "^

Then -jJ^T
e J =
e ^'^^-p^
(3.25)
1 - pe jwT

The cutoff frequenciesfi^,and W Q can be used to calculate p using

Eq. (3.25) and we obtain

sin[(J^^ -a)c)T/2] (3.26)

^ " sin[(J^p +a)p)T/2]

Z-plane z-plane

Prototype low-pass f i l t e r Low-pass f i l t e r

Figure 3.6 Transformation from low-pass to low-pass f i l t e r

 37
i
Initialize Store ace. A
PIA as f (nT - T)

Load f(nT)
1
from ADC into Store p
ace. A as multiplier

i i
Clear external
accumulator Load y(nT - T)
and start ADC into ace. B

* i
Store 1/2 (1 - p) Add
as multiplier pf(nT-T)

i ^

Add Send y(nT)

(l/2)(l-p)f(nT) to DAC and
load it into ace. B

i i
Wait 2 ysec. Store B as
y(nT-T)

i
Load f (nT-T)
into ace. B

Add
1/2) (1 -p)f(nT-T)

Figure 3.7 Flow diagram of transformed f i r s t order low-pass d i g i t a l filter

 38

A f i r s t order low-pass f i l t e r can be designed from the p r o t o t y p e using

t h e t r a n s f o r m a t i o n given by Eq. (3.24)

-1 (3.27)
G(z) = 1
(l-p)+(l-p)z
, 2 -1
1-pz
Eq. (3.27) can be transformed i n t o t h e d i f f e r e n c e equation

y(nT) = y d - p ) f ( n T ) +|-(1 - p ) f ( n T - T ) + p y ( n T - T ) (3.28)

If a)^, = a)g/8, we find t h a t p = 0.412 according to Eq. (3.26) and t h e

d i f f e r e n c e e q u a t i o n becomes

y(nT) = 0.293f(nT) + 0.293f (nT - T) + 0.414y(nT - T) (3.29)

The low-pass f i l t e r with a)j, = a)g/8 was executed according t o t h e flow

diagram shown in F i g . 3.7 and Program 3 in t h e Appendix. The sampling
frequency found was 31.74 KHz and the cutoff frequency measured was
3.96 KHz. The shape of the amplitude and phase response i s s i m i l a r
t o t h a t shown in F i g . 3.5 but with a lower cutoff frequency.

3.7 Low-Pass t o High-Pass Transformation

The t r a n s f o r m a t i o n from a low-pass f i l t e r to a high-pass filter

can be achieved by r o t a t i n g t h e u n i t c i r c l e 180°, so t h a t Z= 1 maps
t o z = - 1 and Z = - l maps t o z = 1. This t r a n s f o r m a t i o n can be performed
using t h e g e n e r a l formula (3.23) with N= 1 and i t can be v i s u a l i z e d
as shown on Fig. 3 . 8 .

-1 (3.30)
7-1 _ z -p
1-pz
 39

Z-plane z-plane

Low-pass filter High-pass f i l t e r

Figure 3.8 Low-pass t o h i g h - p a s s transformation

If t h e cutoff frequency of t h e low-pass p r o t o t y p e i s Q^ and the

d e s i r e d cutoff frequency of the h i g h - p a s s f i l t e r i s a)^,, i t i s r e q u i r e d
t h a t -fij. transforms t o w^, so t h a t
- -J^T _ ^ „_ Ja)T
-•iOT
Z= e and z = e'
Replacing Z and z i n t o Eq. (3.30) a t cutoff frequencies

(3.31)
pJ^cT = e -^ c - p
1 - pe -^ c

p can be calculated from Eq. (3.31) and we obtain

cos(f^c +a)c)T/2 (3.32)

P = cos(J^_ -a)„)T/2
C "'C'
 40

F i r s t Order High-Pass F i l t e r
The prototype f i r s t order low-pass f i l t e r can be transformed into
a high-pass f i l t e r u t i l i z i n g Eq. (3.30) and Eq. (3.32). If the cutoff
frequency of the high-pass f i l t e r i s chosen to be a)-/4, then p = 0 and
the transformation i s

Z ^ = -z ^ (3.33)

Replacing Eq. (3.33) into the f i r s t order low-pass prototype, we

obtain the f i r s t order high-pass f i l t e r .

G(z) = I - 1^"^ (3.34)

The filter expressed by Eq. (3.34) can be realized by the difference

equation

y(nT) = |-f(nT) - |f(nT-T) (3.35)

The high-pass f i l t e r was executed by the microprocessor following a

flow diagram similar to that shown in Fig. 3.2 and a program similar
to Program 1. The response of the f i r s t order high-pass d i g i t a l f i l t e r
i s shown in Fig. 3.9. The sampling frequency found was 38.46 KHz. We
measured a cutoff frequency of 9.6 KHz. The phase of the output s t a r t s
at 90 and drops l i n e a r l y to 0 at Wg/2.

Third Order High-Pass F i l t e r

The t h i r d order high-pass f i l t e r can be calculated from the third
order low-pass prototype u t i l i z i n g the transformation given by
Eq. ( 3 . 3 0 ) . If the cutoff frequency i s a)g/4, then p = 0 and the

transformation i s z" = -z and G(z) becomes

1 1 -3 - 1 . 1 . - 5 -2 -3 (3.36)
^. . 1 1 - 3z + 3z - z
^(^> = 6 , ^ 1 -2
I+3Z
The filter expressed by Eq. (3.36) can be realized by the difference
equation /o -^'j)
y(nT) =|-f(nT) -yf(nT-T) +yf(nT-2T) -•|f(nT-3T) -pr(nT-2T)
 41

f(KHz)
0 6 8 10 12 14
(a) Amplitude response

f(KHz)

A Experimental data

-180 •
(b) Phase response

Figure 3.9 Response of f i r s t order high-pass d i g i t a l filter

 42
|G*

1.0 •

0.8"

0.6--

0.4--

0.2--

0.0
f(KHz)
0 3 4 5 6 8
(a) Amplitude response

f(KHz)

^ Experimental data
•135-

(b) Phase response

Figure 3.10 Response of third order high-pass digital filter

 43

The t h i r d order high-pass f i l t e r was realized with a flow diagram

similar to t h a t shown in Fig. 3.4 and Program 2 but with different
signs on the third and fourth terms of the difference equation. The
response of t h i s f i l t e r i s shown in Fig. 3.10. The sampling frequency
found was 16.12 KHz. We measured a cutoff frequency of 4.04 KHz. The
phase angle of the output s t a r t s at -90 , changes clockwise with
frequency through three quadrants and ends at 0 when a) = a)g/2.

3.8 Low-Pass to Band-Pass Transformation

A low-pass d i g i t a l f i l t e r can be transformed into a band-pass

f i l t e r u t i l i z i n g the mapping technique. The pass band of the low-pass
f i l t e r in the Z-plane i s mapped into the z-plane according to the cutoff
frequencies of the band-pass f i l t e r .

Z-plane z-plane

Low-pass f i l t e r Band-pass f i l t e r

Figure 3.11 Low-pass to band-pass transformation

 44

The mapping of a low-pass i n t o a band-pass f i l t e r can be v i s u a l i z e d as

shown i n F i g . 3 . 1 1 . The t r a n s f o r m a t i o n r e q u i r e s t h a t e*^ in t h e

* ryi

Z-plane t r a c e t h e u n i t c i r c l e twice for each r e v o l u t i o n of e"^ in the

z-plane. The p o i n t Z = - l i s mapped i n t o z = ± l , t h e r e f o r e t h e t r a n s f o r -
mation must be q u a d r a t i c and i t can be shown t o be [2]
A ^A -1.L -2 (3.38)
_. d2 +dj^z +z
Z = -1 -2
1 + di z + d2Z

We replace Z and z by e^^ and e^ respectively.

e I.J -JwT , , -j2a)T

1 +dj^e -^ +d2e -^

After some m a n i p u l a t i o n of Eq. ( 3 . 3 9 ) , we can find the coefficients

di and d2«

d^ = -2ai^/(k + l) (3.40)

d2 = ( k - l ) / ( k + l ) (3.41)

k = cot[a)2 -a)i)T/2]tan(ficT/2) (3.42)

and a = cos[(a)2 + Wi)T/2]/cos[(a)2 - a)i)T/2] = COSCDQT (3.43)

where cog i s t h e c e n t e r frequency.

F i r s t Order Band-Pass F i l t e r
The f i r s t order band-pass f i l t e r can be designed u t i l i z i n g the
t r a n s f o r m a t i o n given by Eq. ( 3 . 3 8 ) , and the f i r s t order low-pass
prototype. We w i l l design a f i l t e r with cutoff frequencies w^ = a)g/8
and u)2 = 3a)s/8. According to Eq. (3.42) and Eq. ( 3 . 4 3 ) , k = l and a = 0 ;
t h e r e f o r e di =d2 = 0 and we o b t a i n t h e transformation

Z"^ = - z " ^ (3-A4)

 45

i
Initialize Subtract
PIA (1/2) f(nT-2T)

i i
Store 1/2 Load f(nT-T)
as multiplier into ace. B

i i
Load f(nT) Store ace. B
from ADC into as f(nT-2T)
ace. A

1 i
Clear Store ace. A
ext. accumulator as f(nT-T)
and start ADC

i 1
Add Send y(nT)
(l/2)f(nT) to DAC

i *

Load f(nT-2T) Wait 10 ysec.

into ace. B

i
Wait 1 ysec.

3ass digit
Figu]re 3 .12 FlovJ diagram of fii-St oreler band-]
 46

f(KHz)
6 8 10 12
(a) Amplitude response

f(KHz)

A Experimental data

- 1 8 0 ••

(b) Phase response

Figure 3.13 Response of first order band-pass digital filter

 47

With this transformation G(z) becomes

G(z) = 1-1.-2 (3.45)

The f i l t e r was implemented w i t h a microprocessor following t h e flow

diagram of F i g . 3.12 and with microprocessor Program 4 according t o
the difference equation

y(nT) = ^f(nT) - ^ f ( n T - 2 T ) (^"^^^

The sampling frequency found was 38.46 KHz and t h e cutoff frequencies
measured 4 . 8 KHz and 14.42 KHz. The response of the f i l t e r i s shown
i n Fig. 3 . 1 3 . The phase angle of t h e output s t a r t s a t 90 and changes
l i n e a r l y w i t h frequency. It is 0 a t the peak of the amplitude
response.

Third Order Band-Pass F i l t e r

A t h i r d o r d e r band-pass f i l t e r can be designed u t i l i z i n g t h e
t r a n s f o r m a t i o n s given by Eq. (3.38) and t h e t h i r d order low-pass
prototype. We w i l l design a f i l t e r with cutoff frequencies W(,i = a)g/8
and (0^,2 = 3a)g/8 which have t h e transformation

-1 -2 (3.47)
Z = -z
therefore

11 -, -^M-x -^ .-6 (3.48)

^, . 1 1 - 3z +3z - z
^(^) = 6 TTT^A
1+ Y
The filter can be realized by the difference equation
(3.49)
y(nT) = -^f(nT) -|f (nT - 2T) +^(nT - 4T) --^f (nT - 6T) - ^ ( n T - 4T)

The band-pass filter was implemented following the flow diagram shown
in Fig. 3.14 and Program 5 in the Appendix. The sampling frequency
found was 16.12 KHz and the cutoff frequencies measured were 2.01 KHz
 «

Initialize PIA
1 1
Send y(nT)
and Add
(1/2) f(nT-4T) t o DAC and
index register load i t into a c e . A

I
Load //OFFF
I I
into Load f(nT-2T) Push f(nT)
stack pointer into ace. A, X = 04 into stack

I
Clear external
I I
accumulator and Subtract Push y(nT)
start ADC (1/2) f(nT-2T) into stack

I I I
Store f (nT) atX=00
Store 1/3 as Store 1/6 as
and decrement
multiplier multiplier
index r e g i s t e r

I I I
Load y(nT-4T) Load f ( n T - 6 T ) S t o r e y(nT)
into ace. A, X = 07 i n t o ace. A, X= OC a t X= 00

I I
Subtract Subtract
(l/3)y(nT-4T) (l/6)f(nT-6T)

I I
Load f(nT) Transfer
Store 1/2 as from ADC stack pointer
multiplier i n t o ace.A t o index r e g i s t e r

i i
Decrement
Load f(nT-4T)
into ace. A, X = 08
Add
(l/6)f(nT)
index r e g i s t e r
and wait 8 c y c l e s
J

Figure 3.14 Flow diagram of third order band-pass digital filter

 49

f(KHz)
3 4 5 6 7 8
(a) Amplitude response

f(KHz)

A Experimental data

-180-•

(b) Phase response

Figure 3.15 Response of third order band-pass digital filter

 50

and 6.04 KHz. The response of the f i l t e r i s shown in Fig. 3.15. The
phase angle of the output s t a r t s at -90°, I t changes with frequency
and i s 0 a t the center frequency CJQ.

3.9 Low-Pass to Band-Stop Transformation

Z-plane z-plane

Low-pass f i l t e r Band-stop f i l t e r

Figure 3.16 Low-pass to band-stop transformation

The form of the mapping for low-pass t o band-stop transformation i s

iQT
shown in Fig. 3.16. e*^ in the Z-plane must t r a c e the unit c i r c l e

twice for each revolution of e'''^ in the z-plane; therefore, the t r a n s -

formation must be quadratic (N=2) and i t can be shown to be [2]

A ^A
(3.50)
_ d2 +d]^z - 1 . L+ z -2

' ^ ^1 ^
1 +d]^z +d2Z
 51

where dj^ and d2 a r e r e a l c o n s t a n t s . We r e p l a c e Z and z by e-^"^ and

jioT
e r e s p e c t i v e l y and o b t a i n

d i + d i e - J ^ T + e-J2^^ (3-51)
.-jfiT _
11 +
^Adj^e^-J^T , , -j2a)T
"^ +d2e "^

After some manipulation of Eq. (3,51), we obtain

di = -.2a/(l+k) (3.52)

d2 = (l-k)/(l+k) (3.53)

k = tan[(a)2-a)i)T/2]tan(fi^T/2) (3.54)

a = cos[(a)2+-a)i)T/2]/cos[(a)2-a)i)T/2] = coswot (3.55)

where CJQ i s t h e c e n t e r frequency.

F i r s t Order Band-Stop F i l t e r
The f i r s t order band-stop f i l t e r can be designed u t i l i z i n g t h e
t r a n s f o r m a t i o n given by Eq. ( 3 . 5 0 ) . We w i l l o b t a i n a f i l t e r with
0)^,]^ = a)g/8 and 0)^.2-3a)g/8. According to Eq. (3.54) and Eq. ( 3 . 5 5 ) ,
k = l and a = 0 . The t r a n s f o r m a t i o n from low-pass to band-stop i s

Z"^ = z"^ (3.56)

therefore
G(z) = j + | z " ^ (3.57)

The band-stop filter can be realized with the difference equation

y(nT) = ^(nT) + ^ ( n T - 2 T ) (3.58)

The first order band-stop filter was implemented with a flow diagram
similar to that shown in Fig. 3.12 and Program 4 but with positive sign
 52
G*

1.0 •^...jk

S ^

0.8 k
N. 4

0.6 • \ i i

0.4 •

0.2 -

0.0 — — I 1 f(KHz)
0 6 8 10 12 18
(a) Amplitude response

f(KHz)

A. Experimental d a t a

-180 •
(b) Phase response

F i g u r e 3.17 Response of f i r s t order band-stop d i g i t a l filter

 53

on the second term. The sampling frequency found was 38,46 KHz and the
cutoff frequencies were 4.80 KHz and 14.42 KHz. The response of the
filter is shown in Fig. 3.17. The phase angle of the output is 0° at
a)=0 and w = 0)3/2 where the amplitude response is 1.0.

Third Order Band-Stop Filter

The third order band-stop filter can be designed utilizing the
transformation given by Eq. (3.50) and the third order low-pass proto-
type. We will design a band-stop filter with cutoff frequencies
'^cl = '*>s/^ ^ ^ ^c2 = 30)3/8. The substitution required is

-1 -2
Z ^= z ^ (3.59)
therefore

^, , 1 l+3z-2+3z-* + E-6 <3.60)

6 1^1-4
I+3Z

The filter can be realized with the difference equation

(3.61)
y(nT) = •|-f(nT) +yf (nT - 2T) +^f(nT-4T) +-|-f(nT-6T) -pr(nT-4T)

The filter was implemented following a flow diagram similar to that

shown in Fig. 3.14. The sampling frequency found was 16.12 KHz and
the cutoff frequencies were 2.02 KHz and 6.04 KHz. The phase angle is
0° at 0) = 0 and o)=o)g/2 where the amplitude response is one. There is
an abrupt transition of the phase angle from 90° to -90° at the center
frequency.

3.10 Summary

This chapter was dedicated to the design and implementation of

d i g i t a l f i l t e r s u t i l i z i n g the hardware covered in Chapter I I . First
we designed f i r s t and t h i r d order prototype low-pass f i l t e r s using the
b i l i n e a r transformation. The f i r s t order low-pass f i l t e r was programmed
 54
|G*|

f(KHz)
0 3 4 5 6 7
(a) Amplitude response

f(KHz)

A Experimental data

-180"
(b) Phase response

Figure 3.18 Response of third order band-stop digital filter

 55

with a cutoff frequency of 9.61 KHz and an allowed frequency range of

19.23 KHz. The t h i r d order low-pass f i l t e r required longer processing
time and therefore i t had a narrower frequency range of 8.06 KHz.
The cutoff frequency of t h i s f i l t e r was 4.03 KHz. We used the
Constantinides transformations to transform the prototype low-pass
f i l t e r s into high-pass, band-pass, band-stop and other low-pass
filters. The amplitude and phase response of each f i l t e r are presented
in t h i s chapter. The solid curves correspond to the t h e o r e t i c a l
response. We u t i l i z e d a sine wave generator with v a r i a b l e frequency
to provide the input s i g n a l . The amplitude and phase difference of
the input and output signals were measured u t i l i z i n g an oscilloscope.
The measured values are indicated on the curves by a t r i a n g l e .
 CHAPTER IV

ECHO CANCELLATION

4.1 Introduction

T r a n s m i s s i o n and r e c e p t i o n of l o c a l t e l e p h o n e conversations
u t i l i z e two-wire c i r c u i t s . They a r e s e t up by c o n n e c t i n g t h e two
customers' telephone c i r c u i t s at the central office. For a d i s t a n c e
l o n g e r t h a n 35 m i l e s , a m p l i f i c a t i o n of t h e s i g n a l s i s o f t e n required.
S i n c e a m p l i f i e r s a r e one-way d e v i c e s , t h e two d i r e c t i o n s of transmission
must be s e p a r a t e d t o form a f o u r - w i r e s y s t e m . T r a n s m i s s i o n of m u l t i -
c h a n n e l s y s t e m s a l s o r e q u i r e s s e p a r a t i o n of s i g n a l s i n two d i r e c t i o n s
and t r a n s m i s s i o n over a f o u r - w i r e s y s t e m . The f o u r - w i r e system must
be c o n n e c t e d t o t h e l o c a l t w o - w i r e system by means of a d e v i c e called
a h y b r i d which i s b a s i c a l l y a d i f f e r e n t i a l transformer. Fig. 4.1
shows a t y p i c a l l o n g d i s t a n c e t e l e p h o n e circuit.

Ik Echo of B ' s s p e e c h

Talker A Talker B

Echo of A ' s s p e e c h ^

Figure 4.1 Typical long distance telephone circuit

56
 57

If the hybrid is not perfectly balanced, the "in" signal is coupled to

the "out" signal which is sent back to the talker that originated the
signal and it will be heard as an echo. Under ideal conditions a
signal on the "in" side of the hybrid is coupled to the two-line system
and produces no effect on the "out" side; however, the conditions are
not always ideal and there is often a mismatch. Extensive research has
been done on the subject of echo cancellation and articles have been
published in the proceedings of the IEEE [6], [7] which describe the
nature of the problem and different solutions to it.

4.2 Echo Synthesis

One solution to the problem of echo cancellation is to synthesize

a replica of the echo and subtract it from the actual echo. The syn-
thesis of the echo involves the use of a discrete-time convolution.
The input function f(t) is divided into a series of impulses with an
area equal to the magnitude of f(t) at the sampling instant and
uniformly spaced in time by the sampling period T, so that f(t) can
be expressed as shown in Eq. (4.1).

f(t) = Tf(0)6(t) +Tf(T)6(t-T) +Tf(2T)6(t-2T) + (4.1)

Eq. (4.1) represents a train of impulses and each of these impulses

produces an impulse response h(t) modified in amplitude by the area of
the related impulse and shifted in time to begin at the instant this
impulse reaches the circuit. The output function y(t) depends on the
contribution of each impulse, so that

y(t) = Tf(0)h(t) +Tf(T)h(t-T) +Tf(2T)h(t-2T) + (4.2)

= Z Tf(nT)h(t-nT)
n=0
 58

A property of the convolution allows the interchange of the input and

the impulse response and we obtain

y(t) = E Th(nT)f(t-nT) (4.3)

n=0
The impulse response of a hybrid circuit used in telephone networks
can be obtained by applying an impulse at point a of Fig. 4.1 and
obtaining the response at point b. It typically has a form shown in
Fig. 4.2. The pulse response is considered a constant for each particu-
lar circuit and the values of h(nT) are obtained by measuring the ampli-
tude of the pulse response at intervals nT.

h(t)

Figure 4.2 Typical impulse response

 59

4 . 3 Echo C a n c e l l a t i o n

A/D
1
Conversion

I
Echo
Sjmthesis

D/A
I Echo ^
Conversion

OH D/A
Conversion
A/D
Conversion

Figure 4.3 Block diagram of echo c a n c e l l a t i o n

The echo c a n c e l l a t i o n was performed with a c i r c u i t b u i l t according

to Fig. 4 . 3 . The " i n " s i g n a l i s sampled with a constant time i n t e r v a l
T and converted t o d i g i t a l . The sampling and echo s y n t h e s i s i s p e r -
formed by a microprocessor and a s s o c i a t e d processing c i r c u i t s d e s c r i b e d
i n Chapter I I . The echo s y n t h e s i s i s achieved with an algorithm
according t o Eq. ( 4 . 3 ) .
We l i m i t e d t h e number of terms to ten which allowed us to p r o c e s s
impulse r e s p o n s e s up to a l e n g t h of 1.15 ms. A faster microprocessor
i s r e q u i r e d for a longer p u l s e r e s p o n s e . Some period of time i s
r e q u i r e d t o s y n t h e s i z e the echo. This f a c t causes the s y n t h e t i c echo
t o be delayed with r e s p e c t t o the a c t u a l echo. This processing delay
 60

requires that the actual echo be sampled and converted to digital and
then back to analog. The delayed echo will then be in phase with the
synthetic echo. Finally, the synthetic echo is subtracted from the
actual echo utilizing an operational amplifier. The echo cancellation
was executed following the flow diagram shown in Fig. 4.4 and the
results are presented in Fig. 4.5 for a frequency range of 0 to 3600 Hz.
The microprocessor program is presented in the Appendix. The input
f(t) is stored in memory using indexed addressing. The previous inputs
are loaded from memory with relative indexed addresses according to
Table 4.1.

Table 4.1 Indexed address for echo cancellation

Relative Indexed
Input Address

f(t-T) 01
f(t -2T) 02
f(t-3T) 03
f(t-4T) 04
f(t-5T) 05
f(t-6T) 06
f(t-7T) 07
f(t-8T) 08
f(t -9T) 09
 61
1
Initialize Add product
PIA h(nT)f(t -nT)

I
Initialize
index register Decrement X
and stack pointer

I I
Clear external
accumulator and
start ADC
n = n +1 Wait
four cycles i
I
Load f(t) Transfer
n =1 from ADC stack pointer to
into ace. A index register

I
Load h(nT)
I
Push ace. A
I
into ace. B into stack and Decrement X
store it at X= 00

I I
Store h(0) as
I
Store h(nT) Load //OFFF
multiplier and
as multiplier
add h(0)f(t) into stack pointer

I I
Load f (t -nT) Send synthetic
into ace. A echo to DAC

Figure 4.4 Flow diagram of echo cancellation

 62

a (dB)

20--

4 •-

2 --

-I 1- -I 1- f(KHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5

Figure 4.5 R e s u l t s of echo c a n c e l l a t i o n

 CHAPTER V

CONCLUSIONS

Samples of analog signals were taken, digitized, and loaded into

a microprocessor. Digital signal processing requires fast processing
circuits in order to obtain the desired sampling frequency. We used
TTL fast multipliers which generate subproducts that have to be added
to obtain the final product. We designed the multiplier to handle 2'S
complement numbers by complementing negative multiplicands. In this
case we recomplement the final product. The multipliers that we used
are decimal factors with bit 7 as the sign bit. The TTL fast multi-
plier was interfaced with the microprocessor via a peripheral inter-
face adapter (PIA). An external accumulator was incorporated to add
or subtract the final products. The output of the accumulator was
connected to the data bus through a buffer. The digital to analog
converter can access the accumulator output.
The hardware allowed us to perform filtering of digital signals.
We programmed first order low-pass, high-pass, band-pass, and band-stop
filters with a sampling frequency of 38.46 KHz. This frequency range
was limited by the speed of the analog to digital converter. We also
programmed third order filters with a sampling frequency of 16.12 KHz.
The response of each is presented in graph form in Chapter III. We
used indexed addressing to store and load data in the third order
filters. We also used the microprocessor stack as a second phase for
data storage. When the index register is decremented and reaches the
lower end in memory, we transfer the stack pointer to the index register .
The data that had been stored in the stack can now be loaded with indexed
addressing. The experimental data correlates with the theoretical curves.
We performed the experiment of echo cancellation in telephone
systems. The echo is synthesized using discrete time convolution. The
actual echo is delayed according to the processing time, then it is
subtracted from the synthetic echo to obtain cancellation.

63
 64

The frequency range of d i g i t a l f i l t e r s can be increased with

f a s t e r m i c r o p r o c e s s o r s and analog to d i g i t a l c o n v e r t e r s . The u s e of
TTL f a s t m u l t i p l i e r s provided a speed about ten times f a s t e r than t h a t
of a s t a n d - a l o n e microprocessor system. Large computers a r e p r e s e n t l y
being used for d i g i t a l s i g n a l p r o c e s s i n g . The s i z e and cost of t h e
computer system can be decreased u t i l i z i n g microprocessors coupled to
f a s t m u l t i p l i e r s as we have done in t h i s work.
 65

REFERENCES

1. Steven A. T r e t t e r , I n t r o d u c t i o n t o Discrete-Time Signal P r o c e s s i n g ,

Wiley, New York, 1976
2. A. G. C o n s t a n t i n i d e s , S p e c t r a l Transformations for D i g i t a l F i l t e r s ,
P r o c . IEEE, Vol. 117, PP 1585-1590, August 1970
3. Andreas Antoniou, D i g i t a l F i l t e r s : Analysis and Design, McGraw-Hill,
New York, 1979
4. Gene Cavanaugh, Fast M u l t i p l i e r s u s i n g TTL Read Only Memories,
Texas I n s t r u m e n t s Application Report, Dallas
5. C D . Wallace, A Suggestion for a Fast M u l t i p l i e r , IEEE Transactions
on E l e c t r o n i c Computers, Vol. 13, No. 1, PP 14-17, February 1964
6. Man Mohan Sondhi and David A. Berkley, Silencing Echoes on the
Telephone Network, Proc. IEEE, Vol. 68, PP 948-963, August 1980
7. Nicholas Demytko and Kevin S. English, Echo Cancellation on Time
V a r i a n t C i r c u i t s , Proc. IEEE, Vol. 65, PP 444-453, March 1977
APPENDIX

66
 67

Program 1 F i r s t order low-pass filter

Address Hex Code Mnemonics Comment

0000 86 FF LDAA //FF Load //FF i n t o A

0002 B7 4C 00 STAA 4COO S e t p o r t A of PIA as o u t p u t
0005 B7 4C 02 STAA 4C02 S e t p o r t B of PIA a s o u t p u t
0008 86 04 LDAA //04 Load //04 i n t o A
OOOA B7 4C 01 STAA 4C01 E n a b l e o u t p u t r e g . of p o r t A
OOOD B7 4C 03 STAA 4C03 E n a b l e o u t p u t r e g . of p o r t B
0010 C6 40 LDAB //40 Load //40 i n t o B
0012 F7 4C 02 STAB 4C02 S t o r e 1/2 a s m u l t i p l i e r
0015 B6 70 00 LDAA 7000 Get f(nT) from ADC
0018 B7 68 00 STAA 6800 C l e a r e x t . a c e . and s t a r t ADC
OOIB B7 4C 10 STAA 4C10 Add product l/2'f(nT)
OOIE 01 01 NOP,NOP Wait 2 ysec.
0020 F7 4C 00 STAB 4COO Add product l/2-f(nT-T)
0023 F6 50 00 LDAB 5000 Load y(nT) into A and DAC
0026 16 TAB Keep y(nT) in B
0027 01 01 01 NOP,NOP,NOP Wait 3 ysec.
002A 01 01 01 NOP,NOP,NOP Wait 3 ysec.
002D 01 01 01 NOP,NOP,NOP Wait 3 ysec.
0030 01 NOP Wait 1 ysec.
0031 7E 00 15 JMP 0015 Jump to 0015
 68

Program 2 Third order low-pass filter

Address Hex Code Mnemonics Comment

0000 86 FF LDAA //FF Load //FF i n t o A

0002 B7 4C 00 STAA 4COO Set p o r t A of PIA as output
0005 B7 4C 02 STAA 4C02 Set p o r t B of PIA as output
0008 86 04 LDAA //04 Load //04 i n t o A
OOOA B7 4C 01 STAA 4C01 Enable output r e g i s t e r A
OOOD B7 4C 03 STAA 4C03 Enable output r e g i s t e r B
0010 CE 09 FF LDX 09FF Load //09FF i n t o index r e g .
0013 8E OF FF LDS OFFF Load //OFFF i n t o s t a c k p o i n t e r
0016 B7 68 00 STAA 6800 Clear e x t . ace. and s t a r t ADC
0019 C6 2B LDAB //2B Load //2B i n t o B
OOIB F7 4C 02 STAB 4C02 Store 1/3 as m u l t i p l i e r
OOIE A6 03 LDAA, X03 Load y ( n T - 2 T ) i n t o A
0020 B7 4C 30 STAA 4C30 Subtract l / 3 - y ( n T - 2 T )
0023 C6 40 LDAB //40 Load //40 i n t o B
0025 F7 4C 02 STAB 4C02 S t o r e 1/2 as m u l t i p l i e r
0028 A6 04 LDAA, X04 Load f ( n T - 2 T ) i n t o A
002 A B7 4C 10 STAA 4C10 Add l / 2 - f ( n T - 2 T )
002 D A6 02 LDAA, X02 Load f ( n T - T) i n t o A
002 F B7 4C 10 STAA 4C10 Add l / 2 - f ( n T - T )
0032 C6 15 LDAB //15 Load #15 i n t o B
0034 F7 4C 02 STAB 4C02 Store 1/6 as m u l t i p l i e r
0037 A6 06 LDAA, X06 Load f ( n T - 3 T ) into A
0039 B7 4C 10 STAA 4C10 Add l / 6 - f ( n T - 3 T )
003 C B6 70 00 LDAA 7000 Get f(nT) from ADC
003F B7 4C 00 STAA 4COO Add l / 6 - f ( n T )
0042 F6 50 00 LDAB 5000 Load y(nT) i n t o B and DAC
0045 36 PUSHA Push f(nT) i n t o s t a c k
0046 37 PUSHB Push y(nT) i n t o s t a c k
0047 A7 00 STAA, XOO Save f ( n T ) , X=00
0049 09 DEX Decrement index reg.
 69

Address Hex Co de Mnemonics Comment

004 A E7 00 STAB, XOO Save y(nT), X= 00

004 C 8C 04 00 CPX //0400 Compare index reg. to //0400
004F 2F 08 BLE 08 If less or equal go to 0059
0051 09 DEX Decrement index register
0052 01 NOP Wait 2 cycles
0053 01 NOP Wait 2 cycles
0054 01 NOP Wait 2 cycles
0055 01 NOP Wait 2 cycles
0056 7E 00 16 JMP 0016 Jump to 0016
0059 30 TSX Transfer stack to index
005A 09 DEX Decrement index register
005B 20 B6 BRA B6 Branch to 0013
 70

Program 3 Transformed l o w - p a s s filter

Address Hex Code Mnemonics Comment

0000 86 FF LDAA //FF Load //FF i n t o A
0002 B7 4C 00 STAA 4C00 Set p o r t A of PIA a s o u t p u t
0005 B7 4C 02 STAA 4C02 S e t p o r t B of PIA a s o u t p u t
0008 86 04 LDAA //04 Load //04 i n t o A
OOOA B7 4C 01 STAA 4C01 Enable o u t p u t r e g . of p o r t A
OOOD B7 4C 03 STAA 4C03 E n a b l e o u t p u t r e g . of p o r t B
0010 B6 70 00 LDAA 7000 Get f(nT) i n t o A
0013 B7 68 00 STAA 6800 C l e a r e x t . a c e . and s t a r t ADC
0016 C6 26 LDAB //26 Load //26 i n t o B
0018 F7 4C 02 STAB 4C02 S t o r e 0.293 as m u l t i p l i e r
OOIB B7 4C 10 STAA 4C10 Add p r o d u c t .0293f(nT)
OOIE 01 01 NOP,NOP Wait 2 y s e c .
0020 D6 CI LDAB CI Load f ( n T - T ) into B
0022 F7 4C 10 STAB 4C10 Add p r o d u c t .02 9 3 f ( n T - T )
0025 97 CI STAA CI S t o r e A as f ( n T - T)
0027 C6 35 LDAB //35 Load //35 i n t o B
0029 F7 4C 02 STAB 4C02 S t o r e 0.414 as m u l t i p l i e r
002 C D6 02 LDAB C2 Load y ( n T - T ) into B
002E F7 4C 00 STAB 4COO Add p r o d u c t 0 . 4 l 4 y ( n T - T )
0031 F6 50 00 LDAA 5000 Load y(nT) i n t o B and DAC
0034 D7 C2 STAB C2 S t o r e B a s y ( n T - T)
0036 7E 00 10 JMP 0010 Go t o 0010
 71

Program 4 F i r s t order band-pass filter

Address Hex Code Mnemonics Comment

0000 86 FF LDA //FF Load //FF i n t o A

0002 B7 4C 00 STAA 4 COO Define p o r t A as output
0005 B7 4C 02 STAA 4C02 Define p o r t B as output
0008 86 04 LDAA //04 Load //04 i n t o A
OOOA B7 4C 01 STAA 4C01 Enable output r e g i s t e r A
OOOD B7 4C 03 STAA 4C03 Enable output r e g i s t e r B
0010 C6 40 LDAB //40 Load //40 i n t o B
0012 F7 4C 02 STAA 4C02 S t o r e 1/2 as m u l t i p l i e r
0015 B6 70 00 LDAA 7000 Get f(nT) i n t o A
0018 B7 68 00 STAA 6800 Clear ext. ace, and start ADC
OOIB B7 4C 10 STAA 4C10 Add l/2-f(nT)
OOIE D6 C2 LDAB 40C2 Load f(nT-2T) into B
0020 01 NOP Wait 1 ysec.
0021 F7 4C 20 STAB 4C20 Subtract l/2-f(nT-2T)
0024 DC CI LDAB OOCl Load f(nT - T) into B
0026 D7 C2 STAB C2 Store B as f(nT-2T)
0028 97 CI STAA CI Store A as f(nT-T)

002 A F6 50 00 LDAB 5000 Output y(nT)

002 D 01 01 01 NOP, NOP,NOP Wait 3 ysec.

0030 01 01 NOP, NOP Wait 2 ysec.

0032 7E 00 15 JMP 0015 Jump to 0015

 72

Program 5 Third o r d e r b a n d - p a s s filter

Address Hex Code Mciemonics Comment

0000 86 FF LDAA //FF Load #FF i n t o A

0002 B7 4C 00 STAA 4COO Set port A of PIA as output
0005 B7 4C 02 STAA 4C02 Set port B of PIA as output
0008 86 04 LDAA //04 Load #04 into A
OOOA B7 4C 01 STAA 4C01 Enable output register A
OOOD B7 4C 03 STAA 4C03 Enable output register B
0010 CE 09 FF LDX 09FF Load //09FF into index register
0013 8E OF FF LDS OFFF Load #0FFF into stack pointer
0016 B7 68 00 STAA 6800 Clear ext. ace. and start ADC
0019 C6 2B LDAB //2B Load //2B into B
OOIB F7 4C 02 STAA 4C02 Store 1/3 as multiplier
OOIE A6 07 LDAA, X07 Load y(nT-4T) into A
0020 B7 4C 30 STAA 4C30 Subtract l/3-y(nT-4T)
0023 C6 40 LDAB //40 Load #40 into A
0025 F7 4C 02 STAB 4C02 Store 1/2 as multiplier
0028 A6 08 LDAA, X08 Load f (nT -4T) into A
002 A B7 4C 10 STAA 4C10 Add l/2-f(nT-4T)
002D A6 04 LDAA, X04 Load f(nT-2T) into A
002 F B7 4C 30 STAA 4C30 Subtract l/2-f(nT-2T)
0032 C6 15 LDAB #15 Load #15 into B
0034 F7 4C 02 STAB 4C02 Store 1/6 as multiplier
0037 A6 OC LDAA, XOC Load f(nT-6T) into A
0039 B7 4C 30 STAA 4C30 Subtract l/6-f(nT-6T)

003 C B6 70 00 LDAA 7000 Get f(nT) from ADC

003F B7 4C 00 STAA 4COO Add l/6-f(nT)
0042 F6 50 00 LDAB 5000 Load y(nT) into B and DAC
0045 36 PUSHA Push f(nT) into stack
0046 37 PUSHB Push y(nT) into stack
0047 A7 00 STAA, XOO Save f(nT), X= 00
0049 09 DEX Decrement index r e g i s t e r
 73

Address Hex Co>de Mnemonics Comment

004 A E7 00 STAB, XOO Save y(nT), X= 00

004 C 8C 04 00 CPX #0400 Compare index reg. to #0400
004F 2F 08 BLE 08 If less or equal go to 0059
0051 09 DEX Decrement index register
0052 01 NOP Wait 2 cycles
0053 01 NOP Wait 2 cycles
0054 01 NOP Wait 2 cycles
0055 01 NOP Wait 2 cycles
0056 7E 00 16 JMP 0016 Jump to 0016
0059 30 TSX Transfer stack to index
005A 09 DEX Decrement index register
005B 20 B6 BRA B6 Branch to 0013
 74

Program 6 Echo cancellation

Address Hex Code Mnemonics Comment
0000 86 FF LDA #FF Load //FF i n t o A
0002 B7 4C 00 STAA 4C00 Set p o r t A of PIA a s o u t p u t
0005 B7 4C 02 STAA 4C02 Set p o r t B of PIA a s o u t p u t
0008 86 04 LDAA #04 Load #04 i n t o A
OOOA B7 4C 01 STAA 4C01 Enable output register A
OOOD B7 4C 03 STAA 4C03 Enable output register B
0010 CE 09 FF LDX 09FF Load //09FF into index register
0013 8E OF FF LDS OFFF Load #0FFF into stack pointer
0016 B7 68 00 STAA 6800 Clear ext. ace. and start ADC
0019 D6 Bl LDAB Bl Load h(T) into B
OOIB F7 4C 02 STAB 4C02 Store h(T) as multiplier
OOIE A6 01 LDAA, XOl Load f (t -T) into A
0020 B7 4C 10 STAA 4C10 Add product h(T)f(t-T)
0023 D6 B2 LDAB B2 Load h(2T) into B
0025 F7 4C 02 STAB 4C02 Store h(2T) as multiplier
0028 A6 02 LDAA, X02 Load f(t - 2T) into A
002 A B7 4C 10 STAA 4C10 Add product h(2T)f(t-2T)
002 D D6 B3 LDAB B3 Load h(3T) into B
002 F F7 4C 02 STAB 4C02 Store h(3T) as multiplier
0032 A6 03 LDAA, X03 Load f (t -3T) into A
0034 B7 4C 10 STAA 4C10 Add product h(3T)f(t-3T)
0037 D6 B4 LDAB B4 Load h(4T) into B
0039 F7 4C 02 STAB 4C02 Store h(4T) as multiplier
003 C A6 04 LDAA, X04 Load f (t -4T) into A
003E B7 4C 10 STAA 4C10 Add product h(4T)f(t-4T)
0041 D6 B5 LDAB B5 Load h(5T) into B
0043 F7 4C 02 STAB 4C02 Store h(5T) as multiplier
0046 A6 05 LDAA, X05 Load f(t -5T) into A
0048 B7 4C 10 STAA 4C10 Add product h(5T)f(t-5T)
004B D6 B6 LDAB B6 Load h(6T) into B
004D F7 4C 02 STAB 4C02 Store h(6T) as multiplier
0050 A6 06 LDAA, X06 Load f(t - 6T) into A
 75
Address Hex Code Mciemonics Comment
0052 B7 4C 10 STAA 4C10 Add product h(6T)f(t-6T)
0055 D6 B7 LDAB B7 Load h(7T) into B
0057 F7 4C 02 STAB 4C02 Store h(7T) as multiplier
005A A6 07 LDAA, X07 Load f (t -7T) into A
005 C B7 4C 10 STAA 4C10 Add product h(7T)f(t-7T)
005F D6 B8 LDAB B8 Load h(8T) into B
0061 F7 4C 02 STAB 4C02 Store h(8T) as multiplier
0064 A6 08 LDAA, X08 Load f (t -8T) into A
0066 B7 4C 10 STAA 4C10 Add product h(8T)f(t-8T)
0069 D6 B9 LDAB B9 Load h(9T) into B
006B F7 4C 02 STAB 4C02 Store h(9T) as multiplier
006E A6 09 LDAA, X09 Load f(t -9T) into A
0070 B7 4C 10 STAA 4C10 Add product h(9T)f(t-9T)
0073 B6 70 00 LDAA 7000 Load f(t) into A
0076 36 PUSHA Push f(t) into stack
0077 A7 00 STAA, XOO Store f(t) in memory
0079 D6 BO LDAB BO Load h(0) into B
007 B F7 4C 02 STAB 4C02 Store h(0) as multiplier
007E B7 4C 00 STAA 4COO Add product h(0)f(t)
0081 8C 04 00 CPX #0400 Compare index to #0400
0084 2F 06 BLE 06 If less or equal go to 008C
0086 09 DEX Decrement index register
0087 01 NOP Wait 2 cycles
0088 01 NOP Wait 2 cycles
0089 7E 0091 JMP 0091 Jump to 0091
008 C 30 TSX Transfer stack to index
008D 09 DEX Decrement index register
008 E 8E OF FF LDS #0FFF Load #0FFF into stack pointer
0091 F6 50 00 LDAB 5000 Load y(nT) into DAC
0094 7E 00 16 JMP 0016 Jump to 0016