Fiche VN Control (US) 2005 31/05/05 17:39 Page 1

PRODUCT OVERVIEW
VN-CONTROL
TEST AUTOMATION FOR BUS-BASED SYSTEM-LEVEL VERIFICATION

BENEFITS
• Quickly verifies interfaces and module
hdl code interaction of bus-based designs
• Automatically generates “real-world” system-level
tests to detect corner case bugs
configuration verification
information ip
• Integrates easily into existing verification
environment
vn-control
• Ready-to-use without the need to learn new
languages
• Leverages models and monitors from TransEDA,
test third-party, or user created
results
• Works with all leading simulators

Overview Increase Productivity

The time to develop a high-end FPGA, ASIC, or SoC
device is becoming longer than the life cycle of the
device primarily due to the amount of time it takes to
verify the functionality of the device. Today, verifying
high-end designs typically consumes 70% or more of
the total development time and resources. Using
VN-Control on designs interfacing with buses in
conjunction with bus functional models and monitors
can minimize the time required to generate high
quality tests.
Key Features
Ready to use
Connect to the verification environments, define the
system topology, then generate comprehensive tests.
Automatic test generation
Generate self-checking tests from user specified
parameters and constraints.
Automatic response checking
Automatically verify system response during simulation
by checking data consistency.
Built-in synchronization capabilities
Ideal for handling constrained-random test
generation for multiple, independent traffic streams.
VN-Control significantly increases verification
productivity through automatic test generation and
dynamic, or “run-time“, response checking. During
simulation, VN-Control actively operates verification IP
to generate "real world" stimuli and verify data at the
interfaces of the design under test (DUT). As a result,
VN-Control significantly reduces your verification time
and effort.
Easily Handle
Complexity
VN-Control easily verifies architectures consisting of
multiple processors, multiple I/O agents, multiple bus
standards, and even handles high concurrency. To
achieve high coverage system-level testing,
VN-Control generates tests containing multiple,
independent traffic streams at the various ports or
interfaces of a DUT. VN-Control also supports systems
generating multiple simultaneous transactions that may
be deferred, re-tried, terminated, or completed out of
order.
Fiche VN Control (US) 2005 31/05/05 17:39 Page 2
Create Dynamic,
Reactive Tests
VN-Control generates tests and performs checks
dynamically during simulation. As a result, users can
create sophisticated, reactive tests which can pause
or stop the simulation based on the results from the
models or monitors, then generate alternative test
sequences. Dynamic, reactive tests lets the testbench
quickly detect problems and automatically respond
immediately which saves time compared to
simulations which run for many hours and produce no
useful result because of an error that occurred in the
first few seconds.
Automatically Perform
Response Checking
During simulation, VN-Control automatically checks
that data correctly arrive to their intended
destinations. Challenges with this type of data
integrity checking include tracking the location of the
data and dealing with varying formats on different
busses. To illustrate these issues, consider the
following system-level data flow example: data is
read from system memory into a cache, read from the
cache, written into another memory location, and
finally read from memory into an I/O agent. Each
movement across a different interface complicates the
checking since the data packet may be reformatted
on each interface.
VN-Control automatically keeps track of the data
and ensures that it is uncorrupted by the DUT.
Ready-to-Use Solution
VN-Control is ready to use and works "out-of-the-box"
with TransEDA’s verification IP. Simply attach
VN-Control to the IP and design, and then provide
the configuration information to start test generation.
VN-Control easily integrates into existing verification
environment without requiring any modifications or
methodology changes. In addition to TransEDA’s
verification IP, VN-Control works with third-party and
user-developed bus functional models.
u.s.a.
16795 Lark Avenue
Suite 102
Los Gatos, CA 95032
Tel: 408.335.1300
Fax: 408.335.1319
www.transeda.com • email:info@transeda.com
No New Languages
to Learn
VN-Control provides test automation for bus-based
SoC designs using easy-to-use templates rather than
requiring users to learn a new verification language.
Simply define the topology of the system based on
the devices that are connected to the DUT – such as
processors and I/O agents – and specify the
transaction constraints. Without a single line of
verification code, VN-Control automatically generates
sophisticated tests that handle multiple, independent,
concurrent traffic streams and checks that data is correct.
Verification IP
TransEDA's verification IP are well-tested, and verified
against the latest specifications, and compatible with
VN-Control. Simply plug these powerful models,
monitors, and arbiters into your system under test and
you are ready to start.
Every TransEDA model and monitor is subjected to
hundreds of directed and pseudo-random
configurations to thoroughly test them under a wide
range of situations. In addition, the IP is continually
enhanced based on feedback from customers using
them in a wide variety of applications.
Platform Support
VN-Control supports the following simulators:
• Cadence Verilog-XL, NC-Sim, NC-Verilog and
Incisive
• Synopsys VCS
• Mentor ModelSim
• IEEE 1364 compliant with PLI 1.0 support.
VN-Control supports the following compute platforms
and operating systems:
• Red Hat Linux 7.X, 8.0
• SUN Solaris 7, 8 and 9.
u.k. © 2005 TransEDA. TransEDA, the TransEDA logo, Verification From Concept to
4th floor, black horse house Reality and Verification Navigator are registered trademarks of TransEDA. Foundation
Leigh road, Eastleigh Models, VN-Control, VN-Cover, VN-Optimize, VN-Property and VN-Check
Hampshire,so50 9fh are trademarks of TransEDA. imPROVE-HDL, imPROVE-HPK and imPROVE-TLL
Tel:+44 (0)23 8068.3500 are registered trademarks of Valiosys S.A. All other trade marks are the property of their
Fax:+44 (0)23 8065.0805 respective owners.