IRF510

Data Sheet January 2002

5.6A, 100V, 0.540 Ohm, N-Channel Power Features

MOSFET • 5.6A, 100V
This N-Channel enhancement mode silicon gate power field
• rDS(ON) = 0.540Ω
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of • Single Pulse Avalanche Energy Rated
energy in the breakdown avalanche mode of operation. All of • SOA is Power Dissipation Limited
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers, • Nanosecond Switching Speeds
relay drivers, and drivers for high power bipolar switching • Linear Transfer Characteristics
transistors requiring high speed and low gate drive power.
• High Input Impedance
These types can be operated directly from integrated
circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA17441.
Components to PC Boards”

Ordering Information Symbol

PART NUMBER PACKAGE BRAND D

IRF510 TO-220AB IRF510

NOTE: When ordering, include the entire part number.

G

Packaging
JEDEC TO-220AB

SOURCE
DRAIN
GATE

DRAIN (FLANGE)

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

 IRF510

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

IRF510 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 5.6 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 4 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 20 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD 43 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 19 mJ
Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA, (Figure 10) 100 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero-Gate Voltage Drain Current IDSS VDS = 95V, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) 5.6 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) VGS = 10V, ID = 3.4A (Figures 8, 9) - 0.4 0.54 Ω
Forward Transconductance (Note 2) gfs VGS = 50V, ID = 3.4A (Figure 12) 1.3 2.0 - S
Turn-On Delay Time td(ON) ID ≈ 5.6A, RGS = 24Ω , VDD = 50V, RL = 9Ω , - 8 12 ns
Rise Time tr VDD = 50V, VGS = 10V - 25 63 ns
MOSFET switching times are essentially independent
Turn-Off Delay Time td(OFF) of operating temperature - 15 7 ns
Fall Time tf - 12 59 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 5.6A, VDS = 0.8 x Rated BVDSS, - 5.0 30 nC
(Gate to Source + Gate to Drain) IG(REF) = 1.5mA (Figure 14)
Gate to Source Charge Qgs Gate charge is essentially independent of operating - 2.0 - nC
temperature.
Gate to Drain “Miller” Charge Qgd - 3.0 - nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 135 - pF
Output Capacitance COSS - 80 - pF
Reverse-Transfer Capacitance CRSS - 20 - pF
Internal Drain Inductance LD Measured From the Modified MOSFET - 3.5 - nH
Contact Screw On Tab To Symbol Showing the
Center of Die Internal Devices
Measured From the Drain Inductances - 4.5 - nH
Lead, 6mm (0.25in) From D
Package to Center of Die LD
Internal Source Inductance LS Measured From The G - 7.5 - nH
Source Lead, 6mm
LS
(0.25in) From Header to
Source Bonding Pad S

Junction to Case RθJC - - 3.5 oC/W

Junction to Ambient RθJA Free air operation - - 80 oC/W

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

 IRF510

Source to Drain Diode Specifications

PARAMETER SYMBOL Test Conditions MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET D - - 5.6 A

Symbol Showing the
Pulse Source to Drain Current ISDM - - 20 A
Integral Reverse
(Note 3) P-N Junction Diode G

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 5.6A, VGS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time trr TJ = 25oC, ISD = 5.6A, dISD/dt = 100A/µs 4.6 96 200 ns

Reverse Recovered Charge QRR TJ = 25oC, ISD = 5.6A, dISD/dt = 100A/µs 0.17 0.4 0.83 µC

NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, start TJ = 25oC, L = 910µH, RG = 25Ω, peak IAS = 5.6A.

Typical Performance Curves Unless Otherwise Specified

1.2 10
POWER DISSIPATION MULTIPLIER

1.0
8
ID, DRAIN CURRENT (A)

0.8
6

0.6
4
0.4

2
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

10
THERMAL IMPEDANCE (oC/W)

0.5
ZθJC, TRANSIENT

1
0.2
0.1 PDM
0.05
0.02
0.1 0.01 t1
SINGLE PULSE t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
0.01
10-5 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (S)

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

 IRF510

Typical Performance Curves Unless Otherwise Specified (Continued)

100 10
OPERATION IN THIS VGS = 10V
REGION IS LIMITED
BY rDS(ON) PULSE DURATION = 80µs
10µs 8 DUTY CYCLE = 0.5% MAX

ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

10 VGS = 8V
100µs
6

1ms VGS = 7V
4
1
VGS = 6V
TC = 25oC 2
VGS = 5V
TJ = 175oC
SINGLE PULSE VGS = 4V
0.1 0
1 10 102 103 0 10 20 30 40 50
VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

10 10
VDS ≥ 50V

ID(ON), ON-STATE DRAIN CURRENT (A)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
8
ID, DRAIN CURRENT (A)

VGS = 8V 1
6
TJ = 25oC
TJ = 175oC
VGS = 7V
4
0.1
VGS = 6V
2
VGS = 5V
VGS = 4V
0 10-2
0 2 4 6 8 10 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

5 3.0
PULSE DURATION = 80µs ID = 3.4A, VGS = 10V
DUTY CYCLE = 0.5% MAX PULSE DURATION = 80µs
NORMALIZED ON RESISTANCE

DUTY CYCLE = 0.5% MAX

rDS(ON), DRAIN TO SOURCE

4 2.4
ON RESISTANCE (Ω)

3 1.8

2 1.2
VGS = 10V
VGS = 20V
1 0.6

0 0
0 4 8 12 16 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

 IRF510

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 500
ID = 250µA VGS = 0V, f = 1MHz
NORMALIZED DRAIN TO SOURCE

CISS = CGS + CGD

1.15 400 CRSS = CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
COSS ≈ CDS + CGD

1.05 300

0.95 200 CISS

COSS
0.85 100

CRSS
0.75 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180 1 2 5 10 2 5 102
TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

2.5 100
PULSE DURATION = 80µs PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDS ≥ 50V
gfs, TRANSCONDUCTANCE (S)

2.0
TJ = 25oC
10
1.5

TJ = 175oC
1.0 TJ = 175oC
1

0.5
TJ = 25oC

0 0.1
0 2 4 6 8 10 0 0.4 0.8 1.2 1.6 2.0
ID, DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 3.4A
VGS, GATE TO SOURCE VOLTAGE (V)

VDS = 80V
16 VDS = 50V
VDS = 20V

12

0
0 2 4 6 8 10
Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

 IRF510

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL VDS
90% 90%

+
VDD 10% 10%
RG
- 0

DUT 90%

VGS 50% 50%

PULSE WIDTH
VGS 10%
0

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD

SAME TYPE Qg(TOT)

AS DUT VGS
12V
0.2µF 50kΩ Qgd
BATTERY
0.3µF
Qgs

D
VDS

G DUT
0

IG(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM

©2002 Fairchild Semiconductor Corporation IRF510 Rev. B

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FAST  OPTOLOGIC™ SMART START™ VCX™
Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
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DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench  SuperSOT™-8
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EnSignaTM MicroFET™ QT Optoelectronics™ TruTranslation™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SILENT SWITCHER  UltraFET 
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Definition of Terms

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Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4