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IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES ISSN NO: 2394-8442

A novel design methodology of 1-bit hybrid full adder using SVL Technique
Vipin Kumar Shrivas#1, Shyam Akashe*2,
1ResearchScholar, ITM University Gwalior
2Associate
Professor, ITM University Gwalior
1er.vipinshrivas@gmail.com, 2 shyam.akashe@yahoo.com

Abstract—In this paper, we are presenting a hybrid 1-bit full adder. Hiring to each one like transmission gate logic and
complementary metal-oxide-semiconductor (CMOS) logic. We are operating the purposed circuit with the help of cadence
virtuoso tool in 45-nm technology of software. The performance parameter of the circuit such as power and delay are
compared with the 16t full adder design for 1.8-V supply at 180nm and for 1.2-V supply at 90-nm technology. For 0.7-V
supply at45-nm technology, the average power consumption (0.07689µW) was found to be exceptionally low with average
low delay (0.00136PS) ensuing from the intentional incorporation of extremely weak COM. The propose was
supplementary extensive for implementing 32- bit full adder moreover, the power at 180-nm technology for the 1.8-v
power supply voltage and 2.45-ns delay and 53.36µW power at 90-nm technology for 1.2-v power supply voltage. If we
meet our result with any other old method, then we get a lot of difference in our today's outcome, whether it is speed or
power and delay.

Keyword logic: Hbrid full adder, low power, high speed.

1. INTRODUCTION
The rising significance of transportable gadget and require to restricted power use on has prompt expedient and
contemporary investigations and advancement in low vitality VLSI outline over the span of current years. The pouring
powers at the accompanying improvements are advantageous device applications requiring low power spending and
exceptionally raised throughput. The necessity of low-control devise is additionally complimenting a most vital worry in
high show advanced frameworks, for example, microchip, computerized flag processor (DSP) and other more
applications.

In the present period rising the difficulties battery worked transportable gadgets as phone brilliant, tablet's, note pad and
PC [8] requests vitality efficient devise. The equipment which is utilized as a part of these sorts of devises needs to
transport most worthwhile show with exceptionally frail power utilization as the aggregate of battery deplete has briefest
impact on devise execution. In Very Large Scale Integration (VLSI) innovation it's diminishing the extent of the circuit and
furthermore lessens the quantities of transistor on the circuit.

Expansive circuit densities enhance the show at the outpouring of more power utilization. Snake is inescapable in all
registering gadgets together with a Digital Signal Processor, ALU (Arithmetic Logic Unit), Microprocessor. [3]. adder has
grave effect on the presence of each computerized figuring equipment. Essential wedge used to outline adder is full adder
Efficient sorted out course of action of the snake can be gotten by improving full adder. The show of the full snake has
specifically contact on all sort of number juggling circuit of the framework.

Along these lines the full adder which is composed as vitality proficient is basic to achieve the most ideal course of action
in the outline of PC equipment. Snake is a champion among the most fundamental parts of the processor [2] and [1]. This
way, we clearly, extending the carrying out of snake cell will improve whole structure implementation. In this paper, the
aftereffects of the proposed 14t (Hybrid Full Adder) have been contrasted and the introduced 16t viper at 180-nm and 90-
nm with untrustworthy supply voltages, input voltages, temperatures and frequencies.

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IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES ISSN NO: 2394-8442

The consequence of the proposed full adder is start to be efficient with little region of settled cost. Full Adder is one of
the gadgets which worked in the few fields of the rationale style. There are two sorts of rationale style family. Which is
static rationale family and dynamic rationale family? In the Static rationale plans [5] are strong, unswerving, and it's expend
low power yet it's require an expansive chip territory. In the opposite side Dynamic rationale plans expend more power
[13] yet its needs less chip region.

The static outline scent the better general execution as looked at than the dynamic good judgment style .There are bunches
of static plan are accessible which are, Pass-Transistor-Logic, Transmission gate(TG), Complimentary-Pass-Logic(CPL).
For the plan of ordinary Full Adder we require 28transistorsCMOS transistor [2].

If we will embracing this outline can build the heartiness, dependability execution of the circuit and we can enhanced
voltage swing [9] yet in this traditional outline of the adder the additional transistors are required more energy to draw out
the usefulness [11]. This rationale [4] configuration are strong, dependable, great to drive capacity, more modest number
transistors and to a great degree vitality proficient when contrasted with the offered full adder plans.

Self-controllable voltage level hybrid full adder

To reduce the power of the supply voltage U-SVL technique is used at the upper side of the proposed circuit. And raise
the ground potential L-SVL technique is used at the lower side of the proposed circuit. So, a self controlled voltage level
technique (SVL) can be working as control circuit. By the implementation of this technique we can achieve reduction of
the power dissipation and other ration of the results

Purposed full adder

In the proposed 1-bit hybrid full adder devise. The full adder is come from the varied circuit of the carry producer unit
and the sum generation module. The Hybrid logic proposed is a mixture of conventional CMOS logic (SUM) and
Transmission gate logic (CARRY) with fixed transistor resizing.Transistors MN1, MP1, MN2, MP2, MN3 and MP3
perform XNOR [11] operation and its control with the input signal. Transistor MP6, MP7, MN6, MN7 are used to
implement the SUM module and transistors MP4, MP5, MN4 MN5, are used to generate the carry module. We are
presenting the purposed full adder design on cadence virtuoso tool at 45-nm technology at 0.07v power supply.

The result of this full adder is compared to the other design of full adder with special importance on the hybrid designing
method. We are neglecting the bericateand improving the level graph of the power, delay and PDP (power and delay
product) of the present circuit. By the use of this method of designing the full adder we reduced up to 20% of power and
delay of the circuit and also We are using transistor sizing (W/L), and critical path delay technique to reducing the power
and delay of the full adder circuit also We are changed the transistor size to reduce the power consumption of the circuit
and get better result to other design of full adder.

The SVL technique comprise of an upper U-SVL circuit and L-S-SVL circuit. The implementation of the hybrid full adder
using SVL. The wide channel pull up PMOS and a pull down NMOS are used in U-SVL design. So superior supply
voltage and decrease ground level voltage is presented by both U-SVL and L-SVL design. A supply voltage of
Vdd=Vn<Vdd and ground level voltage of vs=vp>0v is equally given to both U-SVL and L-SVL circuit.where, total
voltages go down to all L-SVL and U-SVL circuit is represented by vn and vp

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IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES ISSN NO: 2394-8442

MN7
MP5

Sleep

MN6

MP2 MN4 MP4


Cin

MN1 A
Sum

B
MN2
Carry

MP1 MN3
MP3 MN5

MN9
MP6

Sleep

MN10

FIGURE:-1 BIT HYBRID FULL ADDER USING SVL TECHNIQUE

Design
Average
Sr. no. technology(n Delay (pf) PDP (fj) Transistor count
power(µw)
m)

1 180-nm 4.1563 µw 224 pf 0.931 fj 16


2 90-nm 1.17664 µw 0.0913 pf 0.107427 fj 16

3 45-nm 0.07698 µw 0.00136 pf 9.94E-O5 fj 15

Table 1. Result of SVL techniques of the hybrid full adder

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IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES ISSN NO: 2394-8442

4.5
4
3.5
3
2.5 180-nm
2 90-nm
1.5 45-nm
1
0.5
0
Average Delay (pf) PDP (fj)
power(µw)

Figure 2. Comparison of proposed circuits with various full adder circuits for 45nm technology

Parameter analysis:-

Power consumption: - the power consumption of the circuit is the average power which is consumed by the circuit is
known as power consumption of the circuit. With development in technology skill the supply voltage has been reduce in
trying to reduce the power conservation in the circuit. The graph of the power consumption is shown in the fig..
Maximum power takes place during the transitions of signal.
Energy consumed by the circuit is given by
=∫ ( )×( ( )) ………………… (1)
( )= = ∫ ( ×( ( )) ………… (2)

Leakage power: -The reserve power of any gadget is given by leakage power. The Leakage current can arise from
substrate injection property and sub-threshold voltage. Leakage power is wastage of power supply and leakage power of
full adder is given by as

Power (total) = Static Power + Dynamic Power……………… (3)


( ) =∝ ( ) …………… (4)
( )= ( ) × ………………(5)

When electrical energy converted in to the field that is called the rate of the electrical power, such as motion, heat, or
an electromagnetic field. The P is the common symbol of the power by the help of P we are describe the power in the
circuit. Watt is the stand red unt of the power, which is symbolized by W. Static power is a type of power when the circuit
is not active and power is consuming. Dynamic power is type of power when the power is consumed and the inputs are
active. When inputs have ac action mode, capacitances are charging mode and discharging mode and the power raise as a
result. The dynamic power includes both the ac component as well as the static component.

2. CONCLUSIONS
In the designing of a 1 bit low power hybrid full adder has been purposed on cadence virtuoso tool on 45nm technology.
The reproduction outcome rising successfully that the proposed adder presented better PDP as compared with the
previous reports. The leakage power, leakage current and also a leakage voltage are reduced as compared to conventional
circuit.

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IAETSD JOURNAL FOR ADVANCED RESEARCH IN APPLIED SCIENCES ISSN NO: 2394-8442

The Average power of the purposed circuit on 45nm at 0.7v is 0.07689µw, power delay product (PDP) is 9.94E-05FJ and
also reduced the delay of the purposed circuit is 0.0812ns. We have improved the figure of merit of the purpose full adder
by 20% (approx). The performance of the circuit is improved in terms of power, delay and leakage current and noise. The
circuit has been used for design of low power

ACKNOWLEDGEMENT
The author would like to present gratitude to ITM University Gwalior and Cadence Virtuoso Design tool, Bangalore for
providing the platform to work in 45-nm technology.

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