Microwave -2 WLAN project report

Submitted to
Olof Bengtsson
University of Gavle

Submitted by
Md.Moklesur Rahman
821008-P157
Master’ program in Electronics/Telecommunication

1
Table of Contents
Table of Contents ...................................................................................................................2
Introduction: ...........................................................................................................................3
Chapter 1:...............................................................................................................................4
(1) Design for LNA (Low Noise Amplifier): ..........................................................................4
(1.1) Introduction: ...............................................................................................................4
(1.2) Calculation for LNA:..................................................................................................5
(1.2.1) Stability Check: ...................................................................................................5
(1.2.2) Unilateral Figure of Merit: ...................................................................................6
(1.3) Simulation by ADS: ...................................................................................................7
(1.3.1) Noise circle, Gain circle and stability circle: ........................................................7
(1.4) Matching circuit network:......................................................................................... 11
(1.4.2) Matching Circuit diagram: ................................................................................. 12
(1.4.2) DC biasing for low noise amplifier: ................................................................... 14
(1.4.3) Circuit simulation for LNA with 50 ohm design ................................................ 19
(1.4.4) Conversion matching network from 50 to 80 ohm .............................................. 20
(1.4.5) circuit simulation for 80 ohm matching with biasing .......................................... 22
(1.4.6) simulation results: .............................................................................................. 26
Chapter 2 .............................................................................................................................. 30
(2) Maximum Gain Amplifier: .............................................................................................. 30
(2.1) Introduction .............................................................................................................. 30
(2.2) Specification: ........................................................................................................... 30
(2.2.1) schematic diagram for biasing voltage for MGA ............................................... 31
(2.2.2) Biasing point for MGA ..................................................................................... 32
(2.3)MATCHING NETWORK: ........................................................................................ 35
(2.3.1) Schematic diagram for 50Ω MGA with bias voltage without biasing Circuit ...... 36
(2.4) Biasing Circuit for MGA: ......................................................................................... 38
Chapter 3 .............................................................................................................................. 43
3.1 Introduction: ............................................................................................................... 43
3. 1.2 Theory: ............................................................................................................... 43
3.2 Specification: .............................................................................................................. 43
3.3.1 Dielectric oscillator measurement using by VNA ................................................. 43
3.3.1 Resonating frequency for Oscillator ..................................................................... 44
3.3.3 Equivalent Dielectric resonant oscillator circuit in ADS ....................................... 45
3.3.5 Selecting S-parameter .......................................................................................... 49
3.3.4 Stability checking ................................................................................................. 51
3.3.5 Oscillating condition: ........................................................................................... 52
3.3.6 Matching network ................................................................................................ 53
3.3.7 Final diagram and results...................................................................................... 55
Reference ............................................................................................................................. 57
Appendix : Smith Chart ........................................................................................................ 58

2
 Wireless LAN design

Introduction:
The main objective of this project is to get the theoretical and experimental
knowledge of microwave (low noise amplifier, maximum gain amplifier) and oscillator
design. I have design Wireless LAN at 5.2 GHz, the European Standard for 23, 5 Mb/s radio –
link. The whole work is done an insight to system in software environment that is given a
deeper knowledge of microwave measurement technology regarding noise, power and
intermediations

Fig: Transmitter and Receiver section

3
Technical Information: In our design we used a modern GaAs PHEMT(Normally-ON-
mode pseudomorphic high-electron mobility transistor) from Agilent,ATF-35143 or a BJT
(Bipolar Junction Transistor).the data sheets for the transistors could be found on Agilent’s
www.agilent.com

Our all designs have to be made on Teflon. Minimum Line width and line spacing is 2.2mm.
The following parameters are important that are given for substrate:

Εr=2.54
TanD=.003
Height=0.8

For suitable biasing circuit we used some passive SMT components and Murata capacitor
from murata libaray. For active bias we will use SMT PNP transistor (BC858c).

Chapter 1:

(1) Design for LNA (Low Noise Amplifier):

(1.1) Introduction:
A low noise amplifier is an electronics device used to filter out the noise
of input signal received at front end of communication system. Low noise amplifier is used in
wide variety of application such as RF communication system including computer networks
and mobile phone. The main function of LNA is to amplify extremely low power signal
without noise.

The specifications of LNA are given below:

Frequency: 5.1 to 5.3 GHz.
Bias: Minimum Power Consumption
NF: 0.8 but .5dB flatness within band.

4
(1.2) Calculation for LNA:
We have selected DC biasing that is given by the data sheet the for LNA design. As we need
minimum power consumption we choose the s-parameter from data sheet for the biasing point
Vds= 2V and 5mA. We have taken following S parameters value actually at 5 GHz but our all
design done at 5.2 GHz

S11=0.66  -156.09, S21=3.09  53.63

S12=0.150  -9.83, S22=0.45  -102.71

F=0.8 dB,  opt=0.52  44.4

Rn/50=0.09, Fmin=0.64 dB

(1.2.1) Stability Check:

Δ−Ktest will provide us the stability checking of the circuit.

By this stability checking it can be shown that a device will be unconditionally

Stable or conditionally stable. So we used the Rollet’s condition, defined as

  S11S22  S12S21 <1

1  S 211  S 2 22  2
And K= 1
2 S12S 21

I have gotten the value of K=0.557  1 and  =0.3933. We can say our system is conditionally
stable.
So we need to draw the stability circles.

Stability Circle:
For source side:

CS 
S11  S 22  =2.358  171.463
 

S11  
2 2

5
 S12S 21
RS  2
=1.650

2
S11

For load side:

CL 
S 22  S11
 
 =10.2866  134.303
S 22  
2 2

S12S 21
RL  2
=9.696

2
S 22

(1.2.2) Unilateral Figure of Merit:

To compute the figure of merit for unilateral or bilateral we have to use the following equation.

1 GT 1
 
1  U  2
GTU 1  U 2

Where U is the unilateral figure of merit

S12S21S11S22
U
1  S 2  1  S 2


11 

22  
U=0.3057

1
 0.586 Or -2.32 dB
 1U 2
1
 2.0726 Or +3.16 dB
 1U 2

It’s a more than  .2 dB. So we can say that our design is bilateral conditionally stable.

6
(1.3) Simulation by ADS:
(1.3.1) Noise circle, Gain circle and stability circle :
Noise figure is given by teacher that is 0.8 dB. So now we have to compute the centre and radius
for noise figure circle

S  OPT
2
F  FMIN
N  1  OPT
2

1  S
2
4 RN / Z 0

F=-0.8 dB=1.20 and

At 5 GHz we have got the following value from the data sheet.

 Opt=0.52  44.4 and Rn/50=0.09, Fmin=0.64 dB

N=0.1010

OPT
CF  =0.472  114.4
N 1

RF 

N N  1  OPT
2
 =0.2630
N 1

The noise circle is given by the following figure

7
 NsCircle1

cir_pts (0.000 to 51.000)

Available Gain: we have to calculate available Gain

We have to decide which value is the better for optimum goal .we are going to get based on
the following criteria:
Which point we will take that’s should be close to centre of the smith chart to get a better
bandwidth and maximum gain in the 0.8 dB noise Circle. Beside we have to check that

8
weather is in stable region or in unstable region. So we choose the gain value 13 dB. But our
maximum gain was 13.13 that are given by data sheet.

Calculation for available Gain:

Ga=13 dB=19.95

GA  S 21 g A
2

gA= 19.952 =2.089

3.09



g A S11  S 22 
CA 

1  g A S11  
2 2
 =0.8720  171.46
1  2 g A S11S 21 K  g A2 S12S 21
2

rA 
 
=0.5840
1  g A S11  
2 2

Here K=0.557 is the same ass before

I have drown Source Stability Circle, Load Stability Circle, NF Circle and available gain circle in
Smith Chart

I have gotten the following value:

s =0.34  147

9
 S12 S 21s
out = S 22 + =0.555  -122.58
1  S11s


L = out =0.555  122.58

Second step, we have found s and L by using ADS

m1
indep(m1)= 7
GaCircle1=0.381 / 151.032 m2
gain=13.000000 indep(m2)= 7
impedance = Z0 * (0.472 + j0.204) GaCircle1=0.275 / 140.226
gain=12.000000
impedance = Z0 * (0.617 + j0.235)

m1m2m3
S_StabCircle1

L_StabCircle1
NsCircle1
GaCircle1

Eqn gama_s=polar(0.275,140.226)

Eqn gama_out=(S(2,2)+((S(1,2)*S(2,1)*gama_s)/(1-S(1,1)*gama_s)))

Eqn gama_L=conj(gama_out)

cir_pts (0.000 to 200.000)

m3 indep(L_StabCircle1) (0.000 to 51.000)
cir_pts (0.000 to 51.000)
indep(m3)= 10 indep(S_StabCircle1) (0.000 to 51.000) freq S freq gama_out gama_L gama_s
GaCircle1=0.244 / 111.783
gain=11.000000 S(1,1) 5.200 GHz 0.482 / -124.... 0.482 / 124.... 0.275 / 140....
5.200 GHz 0.652 / -161....
impedance = Z0 * (0.758 + j0.365)
S(1,2)
5.200 GHz 0.151 / -13.2...
S(2,1)
5.200 GHz 3.032 / 49.8...

S(2,2)
5.200 GHz 0.436 / -106....

Figure: Another color is source stability circle; Blue color is load stability circle; pink color is
noise circle and Red color is gain Circle.

10
I have taken the value of s =0.27  140.22and L =0.482  -124

Above values are almost close to our manual calculation by smith chart. Some difference might be
given the S parameters value for 5 GHz from the datasheet. We used almost our design at 5.2 GHz
in ADS

(1.4) Matching circuit network:

For matching network We can choose any solution whatever we
like lumped design, Single stub, balanced stub and4/λ. Lumped elements isn’t ever reasonable
design for high frequency and for large range frequencies. For micro strip or strip line
transmission line, open circuited stubs are so easy to fabricate. For transmission lines like coax or
waveguide, however, short circuited subs are usually preferred.
For LNA, we consider the open circuited stub solution

Source side: Length of the distribution line is .152λ

And length of the Stub Length is .08λ
Load Side: Length of the distribution length is .155λ
And Length of the stub length is .1309λ
For 50 Line, W=2.203050 mm
L=39.6184 mm.
Therefore
Source side: Length of the distribution line is 6.0219968mm
And length of the stub length is 3.327945mm
Load Side: Length of the distribution length is 6.16066mm
And length of the stub length is 5.190010mm.

Above all stubs distance and all lengths for 50 ohm

11
(1.4.2) Matching Circuit diagram:

Using the above value, the following schematic diagram is designed without bias.

Figure: matching network for low noise amplifier with out biasing

12
 m2
freq= 5.200GHz
dB(S(2,1))=11.901

14
m2
12

10
dB(S(2,1))

8
nf(2)

2 m1
0
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

freq, GHz
m1
freq=5.200GHz
nf(2)=0.799

Figure: output of above circuit for 50 ohm without biasing

We have got the output of the gain is 11.901 and noise figure is 0.799

13
(1.4.2) DC biasing for low noise amplifier:
For dc biasing we consider the low power consumption with Vds =2 volt and I ds =5 mA from
datasheet.

14
Figure: schemetric diagram finding the VGS

DC.VDS DC.VGS
VGS=-1.000 -1.000
0.250 -0.800
0.350 -0.600
0.450 -0.400
0.550 -0.200
0.650 0.000
0.750
0.850
0.950
1.050
1.150
1.250
1.350
1.450
1.550
1.650
1.750
1.850
1.950
2.050
6 2.150
2.250
2.350
4 2.450
2.550
DC.VGS
DC.VDS

2.650
2 2.750
2.850
2.950
0 3.050

-2
0 5 10 15 20 25 30 35 40 45 50

Minimum Noise Figure v ersus VGS and VDS dB(S21) v ersus VGS and VDS Maximum Av ailable Gain v ersus VGS and VDS
1.6 15 m1
VGS=0.000 20 VGS=0.000
VGS=-200.m
VGS=-400.m VGS=-200.m
m2 VGS=-800.m
VGS=-600.m
VGS=-1.00 VGS=-400.m
VGS=-600.m
10 VGS=-800.m
VGS=-1.00
1.4 VDS=3.650 15
NFmin[0]=1.182 5
NFmin, dB

dB(S21)

MAG, dB

VGS=-0.600000
m2
VGS=-600.m
VGS=-800.m
VGS=-400.m 0
1.2 VGS=-200.m
VGS=-1.00
VGS=0.000 10
-5 m1
1.0 VDS=4.550 5
-10 dB(S21[0])=12.59
VGS=-0.200000
0.8 -15 0
0.0
0.5
1.0

1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0

VDS VDS VDS

Associated Power Gain (input matched for
NFmin, output then conjugately matched)
versus VGS and VDS dB(S11) and dB(S22) v ersus VGS and VDS dB(S12) v ersus VGS and VDS
0 -21
20
VG S=0. 000

VG S=- 200. m
-22
15
VG S=- 400. m
VG S=- 600. m -2 VGS=0.000
VGS=-200.m
VGS=-400.m
VGS=-600.m
VGS=-800.m
VGS=-1.00 VGS=-1.00
VG S=- 800.
1. 00m
-23 VGS=-800.m
Pgain_assoc

VGS=-600.m
-4
dB(S22[0])
dB(S11[0])

-24 VGS=-400.m
dB(S12)

10 VGS=-200.m
-6 -25 VGS=0.000
5 VGS=0.000 -26
m4
m4 VDS=250.0m -8
-27
0 Pgain_assoc=-897.6m VGS=-200.m
VGS=0.000000 -10 VGS=-400.m -28
VGS=-1.00
VGS=-600.m
-5 VGS=-800.m -29
-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDS VDS
VDS

See "Matching at 1 Bias Point" page See "Circles_Ga_Gp_NF_Stability" page

for optimal source and load impedances for available gain, power gain, noise, and
to match for gain or noise figure. stability circles, as well as optimal source
Equations are on the "Equations" page. and load impedances for gain and noise.
Equations are on the "Equations2" page.

Figure: characteristic I-V curve for ATF-35143 transistor for finding VGS

15
The biasing circuit is designed by the following value

Vds =2 volt, I ds =5 mA and VGS =-0.75 and VDD =5 volt

Figure: biasing circuit

16
 IB=.1 mA
VG=-0.75

VDD  VDS 52

R1= = =588.23 ohm
I DS  I B 5  .1  103

R2=
VDS  VGS 5   0.75 =27500 ohm
=
I BB 0.1  10 3
V  VDD  0.75   5
R3= GS = =42500 ohm
I BB .1  10 3

Substituting the all resister and capacitor value into the following circuit

Figure: circuit diagram for low noise amplifier for 50 ohm design

17
 15 m1
m1
freq=5.200GHz
dB(S(2,1))=13.659
10
dB(S(2,1))
nf(2)

m2
freq= 5.200GHz
5
nf(2)=0.863
m2
0
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

freq, GHz

Figure: the output of the LNA with bias voltage and biasing circuit

18
(1.4.3) Circuit simulation for LNA with 50 ohm design

Figure: Circuit diagram for low noise amplifier for 50 ohm design after optimization

19
 m1
freq= 5.200GHz
dB(S(2,1))=11.903
optIter=0
20
m1
10
m2
dB(S(2,1))

0
nf(2)

-10

-20

-30
1 2 3 4 5 6 7 8 9 10

freq, GHz
m2
freq= 5.200GHz
nf(2)=0.800
optIter=0

Figure: the output of the LNA with bias voltage and biasing circuit after optimization

(1.4.4) Conversion matching network from 50 to 80 ohm

Conversion for matching network from 50 ohm to 80 ohm.

We have s =0.27  140.22and L =0.482  -124 .with respect to that value we got the
impedance for source side and load side that are giving:

20
Z S 50 =0.617+j0.235 ohm

Z L 50 =0.432+j0.448 ohm

After conversion into 80 ohm from 50 ohm for matching circuit, we got the following value

Z S 80 =0.385+j0.146 ohm and Z L 80 =0.27+j0.28 ohm

From smith chart we got the following value for 80 ohm matching circuit with open circuited
stub

Source side: Length of the distribution line is .08λ

And length of the Stub Length is .0135λ
Load Side: Length of the distribution length is .095λ
And Length of the stub length is .1699λ
For 80 Line, W=0.961509 mm
L=40.791200 mm.
Therefore
Source side: Length of the distribution line is 3.2632mm
And length of the stub length is 5.5068 mm
Load Side: Length of the distribution length is 3.9159 mm
And length of the stub length is 6.9345 mm

Above all stubs distance and all lengths for 80 ohm

21
(1.4.5) circuit simulation for 80 ohm matching with biasing

The following circuit diagram for 80 ohm matching with biasing:

Figure: circuit diagram for low noise amplifier for 80 ohm design

22
 m1
freq= 5.200GHz
dB(S(2,1))=12.936
60

40

20
m1
dB(S(2,1))

m2
nf(2)

-20

-40

-60
3 4 5 6 7 8 9 10

freq, GHz
m2
freq= 5.200GHz
nf(2)=0.827

Figure: the output of the LNA with bias voltage and biasing circuit

23
Figure: circuit diagram for low noise amplifier for 80 ohm design with optimization

24
 m1
freq=5.200GHz
dB(S(2,1))=11.904
optIter=0

60

40

20
m1
dB(S(2,1))

m2
nf(2)

-20

-40

-60
1 2 3 4 5 6 7 8 9 10

freq, GHz

m2
freq=5.200GHz
nf(2)=0.797
optIter=0

Figure: the output of the LNA with bias voltage and biasing circuit

25
(1.4.6) simulation results:
We got gain and noise figure of low noise amplifier 11.904 dB and 0.797 dB

m3 m1 m4
freq=4.800GHz freq=5.200GHz freq=5.400GHz
dB(S(2,1))=11.927 dB(S(2,1))=11.904 dB(S(2,1))=11.518
optIter=0 optIter=0 optIter=0

14
m3 m1 m4
12

10
dB(S(2,1))

8
nf(2)

2m6 m2 m5
0
4.8 4.9 5.0 5.1 5.2 5.3 5.4

freq, GHz

m6 m2
freq=4.800GHz freq=5.200GHz m5
nf(2)=0.908 nf(2)=0.797 freq=5.400GHz
optIter=0 optIter=0 nf(2)=0.773
optIter=0

Figure: the output of the LNA with bias voltage and biasing circuit with flatness.

26
Lay out: Lay out can be generated automatically using ADS.we had to opatain some
substitute in our schematic circuit as 50 ohm termination and power supply was supplanted by
the port.The lumped component was supplanted by the corresponding model in the ADS
which named R-pad and CPad.we gotten an concept about the dimenson of the lumped
component while soldering the actual components in these dimension which was measured
for the capacitor and resistors.In that’s way the transistor also was supplanted by the
component name which was availabe in the libery of ADS .the fooling is showing for
schemetic layout circuit diagram.

Fig: Layout circuit design for LNA

27
 Fig: Final Layout diagram

Manufacturing: the layout design was printed on the particular film which let the UV light
through it. The copper layer was abided on the printed circuit board. The printed circuit
board was put in to sodium hydroxide for a while. The printed circuit board was put into tank
through warm liquid in order to remove the bare copper. After removing excess copper we
got the actual printed circuit board which made it up for soldering easily.

28
Result and discussion:

20
m3 m3
freq= 5.2GHz
0
dB(finalresult1..S(2,1))=4.625
dB(finalresult1..S(2,1))

-20

-40

-60

-80
0 1 2 3 4 5 6

freq, GHz

Fig: Final measurement result (Transmission Coefficient S21)

The final gain 4.62dB from my measurement at specified frequency, which differs from my
design specification gain. The measurement gain is low as compare simulation gain and
design specifications. It can be happened due to few reason .First all we made PCB board
manually and we have done soldering by hand .moreover, Capacitor and resistor should be
close to accurate value.

29
Chapter 2

(2) Maximum Gain Amplifier:

(2.1) Introduction
A 5.2 GHz maximum gain amplifier is to be design using open circuit stub and ATF 35143 GaAs
FET in a common source configuration. Data sheets for the transistor are available on Agilent web
pages www.agilent.com. First, we have to determine the source and load terminations. Moreover,
we have to conjugate match both input (Source side with input of transistor) and output (output of
the transistor with Load) or we can say in mathematically

S =   in and  L =   OUT

(2.2) Specification:
An MGA with maximum output will be designed with the following specifications:
Frequency: 5.1-5.3 GHz
Gain Flatness: 0.1 dB over bandwidth.
Gain: Maximum (taken flatness into consideration)
Return Loss: Min 15dB
Also analyze it regarding output power, compression, spectral response and noise.

Calculation:

Since we used ATF-35143 with higher power, we can’t use directly values for the S-parameters
from the datasheet. In nonlinear simulation, we need to get more than one bias point. We have to
download the suitable model of the PHEMT from the Agilent Homepage and make a schematic
form to get the S-parameters

30
(2.2.1) schematic diagram for biasing voltage for MGA

Schematic diagram for biasing voltage for MGA:

31
(2.2.2) Biasing point for MGA
Using the above schematic I have taken the point biasing point V =4.550V and V =-.2V which is
shown in following plot. For this biasing point the maximum gain amplifier will be designed with
gain 14.47 dB

m1
VDS=4.550
dB(S21[0])=14.47
VGS=-0.200000

Minimum Noise Figure v ersus VGS and VDS dB(S21) v ersus VGS and VDS
m1 Maximum Av ailable Gain v ersus VGS and VDS
5 15 VGS=-200.m
VGS=0.000
VGS=-400.m 20
VGS=-600.m
m2 VGS=-1.00 10 VGS=-800.m VGS=0.000
VGS=-200.m
VGS=-400.m
4 VDS=3.650 15 VGS=-600.m
NFmin[0]=451.9m 5
NFmin, dB

VGS=-800.m
dB(S21)

MAG, dB
3 VGS=-0.600000 10
0
2 5
-5
1 m2 -10 0
VGS=-800.m VGS=-1.00 VGS=-1.00
VGS=0.000
VGS=-600.m
VGS=-200.m
VGS=-400.m
0 -15 -5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 VDS VGS=-1.00
VDS VGS=-800.m VDS
VGS=-600.m
VGS=0.000
VGS=-200.m
VGS=-400.m
Associated Power Gain (input matched for VGS=-1.00
-5
NFmin, output then conjugately matched) dB(S11) and dB(S22) v ersus VGS and VDS dB(S12) v ersus VGS and VDS
dB(S22[0])
dB(S11[0])

VGS=-800.m
versus VGS and VDS -12 VGS=-1.00
20 -10 VGS=-600.m
VGS=-400.m
VG
VG S=0.
S=-
S=- 200.
400.
000m
600. m

VG S=- 800. m
VGS=-200.m
VGS=0.000
-14 VGS=-800.m
10 m4
-16
Pgain_assoc

-15 VGS=-600.m

dB(S12)
0 -18 VGS=-400.m
VGS=-200.m
-10 -20 -20 VGS=0.000
m4
VDS=250.0m 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -22
-20 Pgain_assoc=4.713 VDS
VGS=0.000000 VG S=- 1. 00 -24
-30 -26
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDS VDS

See "Matching at 1 Bias Point" page See "Circles_Ga_Gp_NF_Stability" page

for optimal source and load impedances for available gain, power gain, noise, and
to match for gain or noise figure. stability circles, as well as optimal source
Equations are on the "Equations" page. and load impedances for gain and noise.
Equations are on the "Equations2" page.

DC1.DC.IDS.i
VDS VGS=-1.000 VGS=-0.800 VGS=-0.600 VGS=-0.400 VGS=-0.200 VGS=0.000
0.250 0.0000 A 1.717 mA 8.015 mA 17.14 mA 27.83 mA 39.27 mA
0.350 0.0000 A 2.088 mA 9.783 mA 21.05 mA 34.45 mA 49.03 mA
0.450 0.0000 A 2.325 mA 10.92 mA 23.64 mA 38.94 mA 55.82 mA
0.550 0.01292E-24A 2.458 mA 11.58 mA 25.16 mA 41.66 mA 60.09 mA
0.650 0.01292E-24A 2.522 mA 11.90 mA 25.92 mA 43.07 mA 62.39 mA
0.750 0.01292E-24A 2.550 mA 12.04 mA 26.24 mA 43.68 mA 63.42 mA
0.850 0.01292E-24A 2.571 mA 12.14 mA 26.46 mA 44.05 mA 63.96 mA
0.950 0.01292E-24A 2.592 mA 12.24 mA 26.68 mA 44.41 mA 64.48 mA
1.050 0.01292E-24A 2.613 mA 12.34 mA 26.89 mA 44.76 mA 65.00 mA
1.150 -0.01292E-24A 2.635 mA 12.44 mA 27.11 mA 45.12 mA 65.52 mA
1.250 -0.03877E-24A 2.656 mA 12.54 mA 27.32 mA 45.48 mA 66.04 mA
1.350 -0.03877E-24A 2.677 mA 12.63 mA 27.54 mA 45.84 mA 66.56 mA
1.450 -0.03877E-24A 2.699 mA 12.73 mA 27.76 mA 46.20 mA 67.07 mA
1.550 -0.03877E-24A 2.720 mA 12.83 mA 27.97 mA 46.55 mA 67.59 mA
1.650 -0.03877E-24A 2.741 mA 12.93 mA 28.19 mA 46.91 mA 68.11 mA
1.750 -0.03877E-24A 2.762 mA 13.03 mA 28.40 mA 47.27 mA 68.62 mA
1.850 -0.03877E-24A 2.784 mA 13.13 mA 28.62 mA 47.62 mA 69.14 mA
1.950 -0.03877E-24A 2.805 mA 13.23 mA 28.83 mA 47.98 mA 69.66 mA
2.050 -0.01292E-24A 2.826 mA 13.33 mA 29.05 mA 48.34 mA 70.17 mA
2.150 -0.01292E-24A 2.847 mA 13.43 mA 29.26 mA 48.69 mA 70.69 mA
2.250 -0.01292E-24A 2.869 mA 13.53 mA 29.48 mA 49.05 mA 71.20 mA
2.350 -0.01292E-24A 2.890 mA 13.63 mA 29.69 mA 49.41 mA 71.72 mA
2.450 -0.01292E-24A 2.911 mA 13.73 mA 29.91 mA 49.76 mA 72.23 mA
2.550 -0.01292E-24A 2.932 mA 13.83 mA 30.12 mA 50.12 mA 72.75 mA
2.650 -0.01292E-24A 2.954 mA 13.93 mA 30.34 mA 50.47 mA 73.26 mA
2.750 -0.01292E-24A 2.975 mA 14.03 mA 30.55 mA 50.83 mA 73.78 mA
2.850 -0.01292E-24A 2.996 mA 14.12 mA 30.77 mA 51.18 mA 74.29 mA
2.950 -0.01292E-24A 3.017 mA 14.22 mA 30.98 mA 51.54 mA 74.81 mA
3.050 -0.01292E-24A 3.039 mA 14.32 mA 31.20 mA 51.89 mA 75.32 mA
3.150 -0.01292E-24A 3.060 mA 14.42 mA 31.41 mA 52.25 mA 75.83 mA
3.250 -0.01292E-24A 3.081 mA 14.52 mA 31.62 mA 52.60 mA 76.35 mA
3.350 -0.01292E-24A 3.102 mA 14.62 mA 31.84 mA 52.96 mA 76.86 mA
3.450 -0.01292E-24A 3.123 mA 14.72 mA 32.05 mA 53.31 mA 77.37 mA
3.550 -0.01292E-24A 3.145 mA 14.82 mA 32.27 mA 53.67 mA 77.88 mA
3.650 -0.01292E-24A 3.166 mA 14.92 mA 32.48 mA 54.02 mA 78.40 mA
3.750 -0.01292E-24A 3.187 mA 15.02 mA 32.69 mA 54.38 mA 78.91 mA
3.850 -0.01292E-24A 3.208 mA 15.11 mA 32.91 mA 54.73 mA 79.42 mA
3.950 -0.01292E-24A 3.229 mA 15.21 mA 33.12 mA 55.08 mA 79.93 mA
4.050 -0.01292E-24A 3.251 mA 15.31 mA 33.34 mA 55.44 mA 80.44 mA
4.150 -0.01292E-24A 3.272 mA 15.41 mA 33.55 mA 55.79 mA 80.95 mA
4.250 -0.01292E-24A 3.293 mA 15.51 mA 33.76 mA 56.14 mA 81.46 mA
4.350 -0.01292E-24A 3.314 mA 15.61 mA 33.98 mA 56.50 mA 81.97 mA
4.450 -0.01292E-24A 3.335 mA 15.71 mA 34.19 mA 56.85 mA 82.48 mA
4.550 -0.01292E-24A 3.357 mA 15.81 mA 34.40 mA 57.20 mA 82.99 mA
4.650 -0.01292E-24A 3.378 mA 15.90 mA 34.62 mA 57.55 mA 83.50 mA
4.750 -0.01292E-24A 3.399 mA 16.00 mA 34.83 mA 57.91 mA 84.01 mA
4.850 -0.01292E-24A 3.420 mA 16.10 mA 35.04 mA 58.26 mA 84.52 mA
4.950 -0.01292E-24A 3.441 mA 16.20 mA 35.25 mA 58.61 mA 85.03 mA
5.000 0.03877E-24A 3.452 mA 16.25 mA 35.36 mA 58.79 mA 85.28 mA

32
We have found out the S from the following circuit diagram.

Output for the biasing point for MGA:

33
 We have to choose such a point on the gain circle as if the point should
be close to the center of the shirt chart. So we have taken the S =0.034  168.919 with 15.0
dB gain.

m3
indep(m3)= 191
GaCircle1=0.160 / -178.138
gain=16.000000 m2
impedance = Z0 * (0.724 - j0.008) indep(m2)= 193
GaCircle1=0.034 / 168.919
gain=15.000000
impedance = Z0 * (0.936 + j0.012)

m1
S_StabCircle1
L_StabCircle1

indep(m1)= 194
GaCircle1

m3m2
m1
GaCircle1=0.038 / 18.021
gain=14.470000
impedance = Z0 * (1.075 + j0.025)

indep(L_StabCircle1) (0.000 to 51.000)

indep(S_StabCircle1) (0.000 to 51.000)
cir_pts (0.000 to 200.000)

Eqn g1=S(2,2)+(S(1,2)*S(2,1)*polar(0.034,168.919))/(1-S(1,1)*polar(0.034,168.919))

Eqn g2=conj(g1)

f req S f req g1 g2
S(1,1) 5.200 GHz 0.294 / -155.102 0.294 / 155.102
5.200 GHz 0.762 / -173.324

S(1,2)
5.200 GHz 0.112 / -2.175

S(2,1)
5.200 GHz 5.241 / 64.147

S(2,2)
5.200 GHz 0.276 / -156.952

Fig: Maximum gain for fix bias point for MGA

34
Now we are going to calculate the L by the following equation.
S S 
out = S 22 + 12 21 s =0.294  -155.102
1  S11s


L = out

L =0.294  155.102

(2.3)MATCHING NETWORK:
For matching network we chosen open circuited stub solution for 80
ohm .so we have gotten the transmission stub length and stub distance from the smith chart .

Already we got the S =0.034  168.919 with impedance Zo  (0.936+j0.025) and we done
conversion from 50 to 8o ohm and then we got the impedance (0.585+j0.0075)

We have plotted the above value for S and L on the smith chart and then we found out
the following stub length and distance

For source side

l1=0.053  , d1=0.036 

And l2=0.446  , d1=0.472 

For load side ( L )

l1=0.083  , d1=0.076 

And l1=0.425  , d1=0.492 

Therefore we got the following value after line cal.

W=.961509 mm and L=40.791200 mm for 80 ohm matching circuit

35
(2.3.1) Schematic diagram for 50Ω MGA with bias voltage without biasing
Circuit

We putted above value into the following circuit

Fig: Schematic diagram for 50Ω MGA with bias voltage without biasing Circuit

36
Above circuit we got the maximum gain 14.171 dB at 5.2 GHz for MGA and flatness is .241

m4 m1
freq= 5.200GHz m3
freq= 5.200GHz freq= 5.300GHz
dB(S(2,1))=14.171 dB(S(2,1))=14.171
dB(S(2,1))=13.930
m1
m4 m3
15

10
dB(S(1,1))
dB(S(2,1))

0
m2

-5
5.20 5.22 5.24 5.26 5.28 5.30

freq, GHz

Eqn flatness=m3-m4
m2
freq= 5.200GHz
dB(S(1,1))=-1.356

freq flatness freq m4 freq m3

<inva... -0.241 5.200... 14.171 5.300... 13.930

Fig: gain output with biasing voltage with out biasing for 80 ohm.

37
(2.4) Biasing Circuit for MGA:
To design the maximum gain amplifier we used active circuit. But for LNA design we used the
passive bias. So, the circuit design will be different. We will use BJT-model initially to design the
bias circuit. The transistor itself has a noise. We have to look for maximum gain in this design.
Hence, we can consider active bias for MGA.

Figure: biasing circuit

VGS=-0.2 volt, VDS=4.55 volt, IDS=57.2 mA

IREF=15 mA IBB=5 mA , Vcc=5

VDS  VBE  VDD 5  .7  (5)

R4= = =590 ohm
I RFE 15  10 3

R5=
VCC  VDS 5   5 =76.66 ohm
=
I RFE 15  10 3
V  VDS 5   5
R6= CC = =7.234 ohm
I BB  I DS (5  57.2)  10 3

VGS  VDS  0.2   5

R7= = =960 ohm
I BB 5  10 3

Now we need to substitute the above value into the following circuit diagram.

38
Fig: schematics circuit diagram for 80 ohm with active biasing of MGA

39
 m7 m9
freq=5.100GHz freq=5.300GHz
dB(S(2,1))=14.102 dB(S(2,1))=13.864
m8
freq=5.200GHz
dB(S(2,1))=13.984

m7 m8 m9
15

10
dB(S(1,1))
dB(S(2,1))

0
m12 m11 m10

-5
5.10 5.12 5.14 5.16 5.18 5.20 5.22 5.24 5.26 5.28 5.30

freq, GHz

m10
m12 m11 freq=5.300GHz
freq=5.100GHz freq=5.200GHz dB(S(1,1))=-1.416
dB(S(1,1))=-1.484 dB(S(1,1))=-1.454

Fig: output diagram with active biasing of MGA for 80 ohm matching circuit

From the above plot we got the maximum gain 13.984 dB and flatness 0.236.

40
Fig: schematics circuit diagram for 80 ohm with active biasing of MGA after optimization

41
 m3
m1 freq=5.200GHz
freq=5.100GHz dB(S(2,1))=15.442
dB(S(2,1))=15.553 optIter=25 m2
optIter=25 freq=5.300GHz
dB(S(2,1))=15.243 Eqn flatness=m3-m4
optIter=25

20 m1 m3 m2

10
dB(S(1,1))
dB(S(2,1))

-10 m6 m4
m5
-20
5.10 5.12 5.14 5.16 5.18 5.20 5.22 5.24 5.26 5.28 5.30

freq, GHz
m4
freq=5.300GHz
m6 dB(S(1,1))=-14.948
freq=5.100GHz m5 optIter=25
dB(S(1,1))=-14.953 freq=5.200GHz
optIter=25 dB(S(1,1))=-16.527
optIter=25

Fig: output diagram with active biasing of MGA for 80 ohm matching circuit after
optimization

We have gotten 15.442 dB gain and flatness 0.31dB after optimization. We got some
difference with compare previous value.

42
Chapter 3
3.1 Introduction:
An oscillator is a non-linear circuit that converts DC power to an AC waveform. RF oscillators
provide sinusoidal outputs, which minimizes the undesired harmonics as well as noise sidebands.
A 5.6 GHz oscillator is to be designed using open circuit stub with BJT AT42086.for the design is
a dielectric puck with a resonance frequency close to the design frequency

3. 1.2 Theory:

Dielectric resonators Oscillator (DRO) are largely used nowadays in application of

Communication system, electronics warfare, missile and radar application [1].As compared
with others oscillator device like micros tip oscillator, crystal oscillator and cavity oscillator,
and they have more advantages feature with small size, low cost and ease of integration.

3.2 Specification:
An oscillator with maximum output power has to be designed. The oscillation frequency will be
5.135GHz. We used open circuit stubs and BJTAT42086. To make it as narrow band as possible
and to analyze it regarding output power, spectral purity and phase noise.

3.3.1 Dielectric oscillator measurement using by VNA

We measured the dielectric response which coupled to the micros tip line found in the radio
frequency lab for simulation the equivalent circuit for ADS. We found the quality factor and
resistance value of the puck. The quality factor can be measured by measuring S11.the following
figure is showing the measuring results. We measured the dielectric puck response using Network
analyzer (VNA). We got the following Output

m1
freq=5.620GHz
m2 dB(S(1,1))=-3.141
freq= 5.585GHz
dB(S(1,1))=-3.293
0
m2m1

-5
dB(S(1,1))

-10

-15

-20

-25
5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

freq, GHz

43
m1=5.620 GHz and m2=5.585 GHz
Q= 5.6/ (m1-m2)
=160

3.3.1 Resonating frequency for Oscillator

A parallel RLC circuit can be used to model DR in ADS. The component is called ‘cResP’.
Using this circuit, we have to find out the Q value and equivalent resistance. We got Q value 160
and =40Ω.The following graph is showing the resonece frequency of the oscillator

-2

-4

-6

-8
dB(S(1,1))

-10

-12

-14

-16

-18

-20
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

freq, GHz

Fig: resonance frequency for oscillator

44
And the following figure is represented as the RLC resonator circuit

Fig: RLC circuit in ADS for resonator

3.3.3 Equivalent Dielectric resonant oscillator circuit in ADS

45
If we compare both outputs with above figure, the central frequency of dielectric resonator is not
exactly same what we designed using ADS. Because the oscillation frequency can be differed due
to present of different kinds of metal without changing the value of R and Q value.

We used the above circuit for comparing the output of the ADS and VNA

46
 0

-2

-4

-6
dB(data_flo..S(1,1))

-8
dB(S(1,1))

-10

-12

-14

-16

-18

-20

-22
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

freq, GHz

Fig: Compare the DR circuit for ADS and VNA

We used the following circuit to compare the results for ADS and VNA with optimization

47
After optimization we got the diagram .we think resonate frequency is close to what we got
from VNA

-2

-4

-6
dB(data_flo..S(1,1))

-8
dB(S(1,1))

-10

-12

-14

-16

-18

-20

-22
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

freq, GHz

Fig: Compare the DR circuit for ADS and VNA with optimization

48
3.3.5 Selecting S-parameter
We will select the bias point on the S parameters. In oscillators case we will make instability
unlike amplifiers. We have to find bias point such that we reach at some values of VEB and
VCB where selecting points of S11 is greater than one. Under this case the whole smith chart
is exist in unstable region except a small region. So we can choose L so that correspondingly
we have a larger OUT .

Fig: schematic diagram for calculating the S-parameter

49
 ICEvsVCE
VCE=4.400
ICmrkr=0.013

0.0131332

0.0131332
ICvsVCE

0.0131332
ICmrkr

ICEvsVCE

0.0131332

0.0131332

0.0131332
4.4000000

4.4000000

4.4000000

4.4000000

4.4000000

4.4000000
VCE

13.1m

freq S
13.1m
ICvsIB

ICEvsIBE
VBE=-0.800, VCE=4.400, S(1,1)
5.600 GHz 1.258 / 26.206 13.1m
VBE=-0.800, VCE=4.400, S(1,2)
5.600 GHz 0.942 / 21.587 13.1m
VBE=-0.800, VCE=4.400, S(2,1)
5.600 GHz 1.032 / 119.760 13.1m
-800.m

-800.m

-800.m

-800.m

-800.m
VBE=-0.800, VCE=4.400, S(2,2)
5.600 GHz 0.407 / 162.826
ICEvsIBE
VBE=-0.800
ICvsIB=0.013 VBE

The following is the biasing point corresponding to the S-parameter

50
3.3.4 Stability checking
We used the model BJT AT42086 to find out the S-parameter which would be downloaded from
Agilent Homepage [1]. So we got this value by the following circuit in AD

51
 The operating point at which S-parameters are calculated can be selected from
DC plots below. The red marker chooses the value of Vce, the blue one the value of Ib.

m1
indep(m1)=23
S_StabCircle1=0.367 / -3.549
VBE=-0.800000, VCE=4.400000, freq=5.600000GHz
impedance = Z0 * (2.154 - j0.113)

freq S
VBE=-0.800, VCE=4.400, S(1,1)
L_StabCircle1
S_StabCircle1

5.600 GHz 1.258 / 26.206

m1
VBE=-0.800, VCE=4.400, S(1,2)
5.600 GHz 0.942 / 21.587

VBE=-0.800, VCE=4.400, S(2,1)

5.600 GHz 1.032 / 119.760

VBE=-0.800, VCE=4.400, S(2,2)

5.600 GHz 0.407 / 162.826
indep(S_StabCircle1) (0.000 to 51.000)
indep(L_StabCircle1) (0.000 to 51.000)

Above smith chart we can see that the whole smith is in instable region without above blue
line

3.3.5 Oscillating condition:

Since we saw on the above figure that we can choose the value of L as feel free. So we have
to take such a value of L as if the value of OUT will be larger. At the denominator part of
the following equation we will select the value of L such like that the value of s11* L wil
be equal to 1.

S12 S 21L
OUT  S 22 
1  S11L

52
Hence we will choose the value of L =0.79/-26.206 which corresponding to the value we can
get OUT =18.2/55.37
1  OUT
Z OUT =Z o =53.82/174.787
1  OUT
=-53.60+j4.89

To apply the following condition

ZT= (-R OUT /3)-jX OUT
= 17.866-j4.89

(Z T ) 50
=0.35732-j0.097

3.3.6 Matching network

Here we will design the matching network on the termination side with help of open shunt
stub and maintain the harmonic balance .we will design the whole matching network for 50
ohm.

Distance of stub (d 1 ) =0.067 λ

Length of stub (l 1 ) =0.137 λ
Distance of stub (d 2 ) =0.401 λ
Length of stub (l 2 ) =0.365 λ

Where λ= 36.7711 mm

Now we will select a larger value for the same reason as compare in LNA.for load side it need
to match the value of L to the resonator network. So the equivalent impedance of the
resonator network will be seen through the micro strip line is such like a real in the resonance

frequency. So the phase of L be zero or 180 degree at new point L .the reflection
coefficient will me achieved by the transferring through the l x .the real part of the reflection
coefficient will be unchanged but only phase will be changed. It can be written as the
following way


L = L *e jB1 =0.73/180

l x =0.286* λ
= 0.286*36.7711
= 10.5165

53
Fig: schematic diagram for matching circuit

54
3.3.7 Final diagram and results

Fig: schematic diagram with passive biasing.

55
The following graph showing the final response of the oscillator

1.0

50
ts(HB.out), V

0.5
0

dBm(HB.out)
0.0
-50

-0.5 -100

-1.0 -150

0 20 40 60 80 100 120 140 160 180 200

-200
time, psec 0 1 2 3 4 5 6 7 8

harmindex

freq harmindex
0.0000 Hz 0
10.57 GHz 1
21.14 GHz 2
31.70 GHz 3
42.27 GHz 4
52.84 GHz 5
63.41 GHz 6
73.97 GHz 7
84.54 GHz 8

With passive biasing and real filtering components .we got the final response of the oscillator
which is closed to sinusoidal wave. It’s less affected by the Intermediation products .and other
graph showing the harmonic which are interfering with the signal.

56
Reference
1) www.agilent.com
2) David M. Pozar, Microwave Engineering, Jhon Wiley and Sons Inc.
3) Semiconductor Device, physics and Technology, Second Edition S.M.Sze, Jhon Wiley and
Sons
4) Design of 5.305 GHz DRO with Simulation and optimaization

57
Appendix : Smith Chart

58
59
60
61
62
63
64