VLSI DESIGN FLOW

LOGICAL DESIGN

• Specifications comes first, they describe abstractly the functionality, interface, and the
architecture of the digital IC circuit to be designed.
• Behavioral description is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications.
• RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.
• RTL description is then converted to a gate-level netlist using logic synthesis tools.
• A gate-level netlist is a description of the circuit in terms of gates and connections
between them, which are made in such a way that they meet the timing, power and area
specifications.
PHYSICAL DESIGN

• System partitioning: Divide a large system into small pieces (modules).

• Pre layout simulation: Check to see if the design functions correctly.
• Floor planning: Arrange the blocks of the netlist on the chip.
• Placement: Decide the locations of cells in a block.
• Routing: Make the connections between cells and blocks.
• Extraction: Determine the resistance and capacitance of the inter connect.
• Post layout simulation: Check to see the design still works with the added loads of the
interconnect.
• Finally a physical layout is made, which will be verified and then sent to fabrication.
STEPS IN DESIGN
Designer Tasks Tools

Define Overall Chip

Text Editor
Architect C/RTL Model C Compiler
Initial Floorplan

Behavioral Simulation RTL Simulator

Logic Logic Simulation Synthesis Tools
Designer Timing Analyzer
Synthesis
Datapath Schematics Power Estimator

Cell Libraries
Circuit Circuit Schematics Schematic Editor
Designer Circuit Simulation Circuit Simulator
Router
Megacell Blocks

Layout and Floorplan

Physical Place and Route Place/Route Tools
Designer Physical Design
Parasitics Extraction and Evaluation
DRC/LVS/ERC Tools

INTRODUCTION TO Xilinx ISE 9.1i TOOL

Synthesis and simulation procedure:

APPARATUS REQUIRED

System with P4 processor, ISE web pack 9.1i.

PROCEDURE

a) FOR SYNTHESIS
1. Open the software Xilinx ISE
2. File New Project
a. New project wizard appears
b. Type project name and location. Enter next
c. In the next window, set the device properties(or leave of with default)
d. Create new source window, press next
e. Add existing source, press next
f. Click finish.
 3. A new project is created
4. In the source window, right click on project name and press create new source
a. In the new source wizard – select verilog module and type file name. Press next.
b. Enter input, output ports and set their directions accordingly in the define module
window.
c. Enter finish.
5. Filename.v window appears. Type in the program and save it.
6. Go to process window and double click synthesis XST.
7. After synthesis view the ‘RTL schematic’.

b) FOR SIMULATION

a. In the source window select “synthesis/implementation”.

b. Right click on the “project” and select “new source”.
c. Select source type as “test bench waveform” and give a filename (filename should not
be the same as the project name).
d. Enter next and click finish.
e. Timing and clock wizard window appears and select the clock information as
“combinational” and click finish.
f. Set the input waveform according to the truth table of the required digital circuit and
save it.
g. In the process window, choose Xilinx ISE simulator and in that select “.tbw” file.
h. Simulate behavioral model.
i. Verify the truth table of the required digital circuit in Simulation window that appears.

Note: The following snapshots appear according to above procedure.

Select Devices. Use the pull-down arrow to the value for each Property Name. Click in the field
to access the pull-down list.

Creating a new Verilog Module file: Click New Source

Then Next, Assign Inputs & Outputs

Next Finish. Then Next . . .

 EXPT.NO. SYNTHESIS AND SIMULATION OF HALF DATE
1a ADDER, FULL ADDER, RIPPLE CARRY
ADDER

AIM:

(i) To synthesize simulate half adder and full adder using Xilinx ISE 9.1i.
(ii) To synthesize and simulate Ripple carry adder using Xilinx ISE 9.1i.

APPARATUS REQUIRED:

System with P4 processor, Xilinx ISE web pack 9.1i.

PROCEDURE:

Follow the synthesis and simulation procedure given in introduction to Xilinx ISE 9.1i.

HALF ADDER

LOGIC DIAGRAM OF HALF ADDER:

A 1
3
Sum
B 2

1
3
2
Carry

TRUTH TABLE OF HALF ADDER:

OUTPUTS
INPUTS

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

PROGRAM:
 DATA FLOW STRUCTURAL BEHAVIOURAL

module ha(a, b, s, c); module ha(a, b,s,c); module ha(a, b, s, c);

input a; input b; input a; input b; input a; input b;

output s; output c; output c; output s; output c;

assign s=a^b; output s; reg s,c;

assign c=a&b; xor(s,a,b); always@(a or b)

endmodule and(c,a,b); begin

endmodule s=a^b; c=a&b;

end

endmodule

SIMULATED OUTPUT OF HALF ADDER:

RTL – SCHEMATIC OF HALF ADDER:

FULL ADDER

LOGIC DIAGRAM OF :
TRUTH TABLE:

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

PROGRAM:
 Structural Data-Flow Behavioral

module fabe(a, b,c, sum, module fabe(a, b, c, sum, module fabe(a, b, c, sum,
carry); carry); carry);

input a; input b; input c; input a; input b; input c; input a; input b; input c;

output sum; output carry; output sum; output carry; output sum; output carry;

wire w1,w2,w3; wire w1,w2,w3; reg sum, carry, w1,w2,w3;

xor(w1,a,b); assign sum=(a^b)^c; always @(a or b or c)

and(w2,a,b); assign w1=a^b; begin

xor(sum,w1,c); assign w2=a&b; sum=(a^b)^c;

and (w3,w1,c); assign w3=w1&c; w1=a^b;

or(carry,w3,w2); assign carry=w2|w3; w2=a&b;

endmodule endmodule w3=w1&c;

carry=w2|w3;

end

endmodule

RTL- SCHEMATIC

SIMULATED OUTPUT:
RIPPLE ADDER

BLOCK DIAGRAM OF 4 BIT RIPPLE CARRY ADDER:

LOGIC DIAGRAM OF FULL ADDER MODULE:

1
A 3
W1 1
2 3
Sum
B 2
Cin

1
3
W2
2
1
3
2

1
3
W3
2

1
3
Carry
2
1
3
W4
2

TRUTH TABLE:
 A B Cin Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

PROGRAM:

DATA FLOW STRUCTURAL BEHAVIORAL

module rrd(a, b, cin, module RIP(a, b, cin, cout, sum); module rrd(a, b, cin,
sum, cout); sum, cout);
input [3:0] a;
input [3:0] a; input [3:0] a;
input [3:0] b;
input [3:0] b; input [3:0] b;
input cin;
input cin; input cin;
output cout;
output [3:0] sum; output [3:0] sum;
output [3:0] sum;
output cout; output cout;
wire c1,c2,c3;
assign reg [3:0]sum;
{cout,sum}=a+b+cin; faas n1(a[0],b[0],cin,sum[0],c1);
reg cout;
endmodule faas n2(a[1],b[1],c1,sum[1],c2);
reg [4:0]temp;
faas n3(a[2],b[2],c2,sum[2],c3);
always@(a or b or cin)
faasn4(a[3],b[3],c3,sum[3],cout);
begin
endmodule
temp=a+b+cin;
module faas(x,y,z, sum, carry);
sum=temp[3:0];
 input x; input y; cout=temp[4];

input z; end

output sum; endmodule

output carry;

wire w1,w2,w3;

xor(w1,x,y);

xor(sum,w1,z);

and(w2,x,y);

and(w3,w1,z);

or(carry,w3,w2);

endmodule

RTL - SCHEMATIC:

SIMULATED OUTPUT:
RESULT:

Thus half adder, full adder and Ripple adder were synthesized and simulated using Xilinx
ISE 9.1i.

EXPT. NO. SYNTHESIS AND SIMULATION OF D,T FLIP FLOPS DATE

1b AND 4-BIT RIPPLE COUNTER
AIM

(i) To synthesize and simulate D and T FF using Xilinx ISE 9.1i.

(ii) To synthesize and simulate 4- Bit Ripple Counter using Xilinx ISE 9.1i.

APPARATUS REQUIRED

System with P4 processor, Xilinx ISE web pack 9.1i

PROCEDURE:

Follow the synthesis and simulation procedure given in introduction to Xilinx ISE 9.1i.

(i) FLIP-FLOPS
LOGIC DIAGRAM of D-FLIP FLOP:

TRUTH TABLE:

Q(t) D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

PROGRAM:

module dff (d, clk, q, qbar);

input d; input clk;

 output q;

output qbar;

reg q,qbar;

initial q=0;

always @(posedge clk)

begin

q=d;

qbar=~d;

end

endmodule

RTL - SCHEMATIC:

SIMULATED OUTPUT:

LOGIC DIAGRAM of T-FLIP FLOP :

TRUTH TABLE:

Q(t) T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

PROGRAM:

module TFF(q, clk, t);

output q;

input clk;

input t;

reg q;

initial q=0;

always@(posedge clk) begin

q=q^t;

end

endmodule

RTL - SCHEMATIC:
SIMULATED OUTPUT:

(ii) RIPPLE COUNTER:

LOGIC DIAGRAM:

TRUTH TABLE:

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0
 13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0

PROGRAM:

module ripple(q, clock, data);

output [3:0] q;

input clock; input data;

tff a(q[0],clock, data);

tff b(q[1],q[0],data);

tff c(q[2],q[1],data);

tff d(q[3],q[2],data);

endmodule

module tff(q, clk, t);

output q;

reg q;

input clk;

input t;

initial q=0;

always @ (negedge clk) begin

q=(q^(t));

end

endmodule
RTL - SCHEMATIC:

SIMULATED OUTPUT:

RESULT:

Thus Flip-Flops and ripple counter were synthesized simulated using Xilinx ISE 9.1i.
 EXPT. DATE
SYNTHESIS AND SIMULATION OF A 4 BIT BOOTH’S
1c MULTIPLIER AND SHIFT AND ADD MULTIPLIER

AIM

(i) To synthesize and simulate 4 bit Booth’s multiplier using Xilinx ISE 9.1i.

(ii) To synthesize and simulate 4- Bit Shift and add multiplier using Xilinx ISE 9.1i.

APPARATUS REQUIRED

System with P4 processor, Xilinx ISE web pack 9.1i

PROCEDURE:

Follow the synthesis and simulation procedure given in introduction to Xilinx ISE 9.1i.

BOOTHS MULTIPLIER

PROGRAM:

module bm(xa,ya,za);

input [3:0]xa; input [3:0]ya; output [7:0]za;

integer i; reg[9:0]temp; reg[1:0]a; reg[5:0]y; reg[5:0]x; reg[9:0]z; reg[7:0]za;

always@ (xa or ya)

begin

y[5:0]=6'b000000;

y[5:1]=ya[3:0]; x[4:0]=xa[3:0];

z=9'b000000000;

temp=10'b0000000000;

for(i=0;i<=4;i=i+1)
 begin

a[0]=y[i]; a[1]=y[i+1];

case(a)

2'b01:temp[4:0]=x[4:0];

2'b10:temp[4:0]=(~x[4:0])+5'b0001;

2'b11:temp[4:0]=5'b00000;

2'b00:temp[4:0]=5'b00000;

endcase

if(temp[4]==0)

temp[9:5]=5'b00000;

else

temp[9:5]=5'b11111;

temp=temp<<i;

z=z+temp;

end

za=z;

end

endmodule

RTL- SCHEMATIC:
SIMULATED OUTPUT:

SHIFT AND ADD MULTIPLIER

PROGRAM:
module smul(x,y, reset,z);

input [3:0]x; input [3:0]y; input reset;

output [7:0]z; wire co,ci;

reg[7:0]t; reg[7:0]z; integer i,j;

always@(x or y or reset)

begin

if(reset)

z=8'b0; j=0;

for(i=0;i<4;i=i+1)

begin

t=8'b0;

if(y[i])
 begin

t[i]=x[0];

t[i+1]=x[1];

t[i+2]=x[2];

t[i+3]=x[3];

end

z=z+t;

end

end

endmodule

RTL-SCHEMATIC:

SIMULATED OUTPUT:
RESULT:

Thus 4 bit shift and add multiplier and Booth’s multiplier is synthesized, simulated and output is
verified with truth table
 EXPT. NO. DATE
2 ANALYSIS AND SIMULATION OF STATE MACHINES

AIM

To analyze, synthesize and simulate state machines using Xilinx ISE 9.1i.

APPARATUS REQUIRED

System with P4 processor, ISE Xilinx 9.1i

PROCEDURE:

1. Analyze the given sequential logic circuit and derive State and Output equations, State
Table and State diagram.
2. Write the Verilog code for the state diagram of the given sequential logic circuit.
3. Follow the synthesis and simulation procedure given in introduction to Xilinx ISE 9.1i.

THEORY:

MEALY MODEL:

Analysis describes what a given circuit will do under certain operating conditions. The
behavior of a clocked sequential circuit is determined from the inputs, the outputs, and the state
of its flip-flops. The outputs and the next state are both a function of the inputs and the present
state. The analysis of a sequential circuit consists of obtaining a table or a diagram for the time
sequence of inputs, outputs, and internal states. It is also possible to write Boolean expressions
that describe the behavior of the sequential circuit.

These expressions must include the necessary time sequence, either directly or indirectly.
A logic diagram is recognized as a clocked sequential circuit if it includes flip-flops with clock
inputs. The flip-flops may be of any type, and the logic diagram may or may not include
combinational logic gates.

State Equations:

The behavior of a clocked sequential circuit can be described algebraically by means of

state equations. A state equation (also called a transition equation) specifies the next state as a
function of the present state and inputs. Consider the sequential circuit shown in Fig. 1. It acts as
a 0-detector by asserting its output when a 0 is detected in a stream of 1s.
 A(t + 1) = A(t)x(t) + B(t)x(t)

B(t + 1) = A’(t)x(t)

y(t) = [A(t) + B(t)]x’(t)

A state equation is an algebraic expression that specifies the condition for a flip-flop state
transition. The left side of the equation, with (t + 1), denotes the next state of the flip-flop one
clock edge later. The right side of the equation is a Boolean expression that specifies the present
state and input conditions that make the next state equal to 1. Since all the variables in the
Boolean expressions are a function of the present state, we can omit the designation ( t ) after
each variable for convenience and can express the state equations in the more compact form

A(t + 1) =Ax + Bx ; B(t + 1) =A’x ; y = Ax’+ Bx’

LOGIC DIAGRAM:

STATE TABLE:

The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table (sometimes called a transition table). The table consists of four sections labeled present
state, input, next state, and output. The present-state section shows the states of flip-flops A and
B at any given time t. The input section gives a value of x for each possible present state. The
next-state section shows the states of the flip-flops one clock cycle later, at time t + 1. The output
section gives the value of y at time t for each present state and input condition.
STATE TABLE FOR THE CIRCUIT OF FIG. 1:

Present Input Next State Output

State

A B x A B y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 1 1 0

1 0 0 0 0 1

1 0 1 1 0 0

1 1 0 0 0 1

1 1 1 1 0 0

STATE DIAGRAM:

The information available in a state table can be represented graphically in the form of a
state diagram. In this type of diagram, a state is represented by a circle, and the (clock-triggered)
transitions between states are indicated by directed lines connecting the circles. The state
diagram provides the same information as the state table and is obtained directly from Table. The
binary number inside each circle identifies the state of the flip-flops.

The directed lines are labeled with two binary numbers separated by a slash. The input
value during the present state is labeled first, and the number after the slash gives the output
during the present state with the given input. A directed line connecting a circle with itself
indicates that no change of state occurs.

MOORE MODEL:
LOGIC DIAGRAM:

STATE EQUATIONS:

A(t+1) = JA’ + K’A

B(t+1) = JB’ + K’B

A(t+1) = BA’ + (Bx’)’A = A’B+AB’+Ax

B(t+1) = x’B’ + (A x)’B = B’x’ + ABx + A’Bx’

STATE TABLE:

Present Input Next State

Flip- Flop Inputs
State

A B x A B JA KA JB KB

0 0 0 0 1 0 0 1 0

0 0 1 0 0 0 0 0 1

0 1 0 1 1 1 1 1 0

0 1 1 1 0 1 0 0 1

1 0 0 1 1 0 0 1 1

1 0 1 1 0 0 0 0 0

1 1 0 0 0 1 1 1 1

1 1 1 1 1 1 0 0 0

STATE DIAGRAM:
PROGRAM:

MEALY MODEL:

module Mealy_Zero_Detector ( output reg y_out, input x_in, clock, reset );

reg [1: 0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ ( posedge clock, negedge reset)
if (reset == 0) state <= S0;
else state <= next_state;
always @ (state, x_in) // Form the next state
case (state)
S0: if (x_in) next_state = S1; else next_state = S0;
S1: if (x_in) next_state = S3; else next_state = S0;
S2: if (~x_in) next_state = S0; else next_state = S2;
S3: if (x_in) next_state = S2; else next_state = S0;
endcase
always @ (state, x_in) // Form the Mealy output
case (state)
S0: y_out = 0;
S1, S2, S3: y_out = ~x_in;
endcase
endmodule

MOORE MODEL:
module Moore_Model ( output [1: 0] y_out, input x_in, clock, reset );

reg [1: 0] state;

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

always @ ( posedge clock, negedge reset)

if (reset == 0) state <= S0; // Initialize to state S0

else case (state)

S0: if (~x_in) state <= S1; else state <= S0;

S1: if (x_in) state <= S2; else state <= S3;

S2: if (~x_in) state <= S3; else state <= S2;

S3: if (~x_in) state <= S0; else state <= S3;

endcase

assign y_out = state; // Output of fl ip-fl ops

endmodule

MEALY MODEL:

RTL-SCHEMATIC:

SIMULATED OUPUT:

MOORE MODEL:
RTL-SCHEMATIC:

SIMULATED OUPUT:

RESULT:

Thus the given sequential logic circuit is analyzed and the verilog code for state diagram
of the logic circuit is synthesized and simulated and output is verified with state table.

EXPT. DATE
 3a

AIM:

To Study Field Programmable Gate Array (FPGA) board and to test the on-board LEDs
and Switches using ISE 9.1Simulator.

APPARATUS REQUIRED:

System with P4 Processor, Xilinx SPARTAN 3 FPGA kit, JTAG cable, Xilinx ISE 9.1i
Simulator, Switch Mode Power Supply (SMPS).

THEORY:

DIP SWITCHES:

When in the UP or ON position, a switch connects the FPGA pin to V cc, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic low.
The switches typically exhibit about 2ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board.

KEY SWITCHES:

The key switches can provide pulse input to the FPGA. The switches connect to an
associated FPGA pin. Pressing a key generates logic High on the associated FPGA pin. There is
no active debouncing circuitry on the key switches.

LEDS:

Test LEDs are provided for mapping output of FPGA or tracking particular stage in the
design. A series current limiting resistor of 270 ohm is associated with every LED. To turn on
an individual LED, drive the associated FPGA control signal High.

PROCEDURE:

1. Create a new project & create a new Verilog file.

2. Type the program for testing LEDs and Switches and Save it
3. Synthesize the program and view the RTL Model.
4. Create test bench waveform and simulate it.
5. Download the program using the procedure given below into the FPGA.
6. Now test the physical working of the switches and the LED’s on – board.

DOWNLOADING PROCEDURE:
 1. Select “Synthesis/Implementation” in the source window.
2. Select the created module (*.v file) in the source window.
3. Select “user constraint” in the process window, double click “edit constraint” to create
user constraint file (*.UCF).
4. Type the net list to define the I/O pins and save it.
5. Double click “implement design” in the process window.
6. Double click “Generate programming “file and select the respective created bit file
(*.bit)
7. Double click “ configure device (iMPACT) ”. In the impact window that appears, select
‘configure device using boundary scan’. Click finish
8. Right click on the created Xilinx model & select ‘program’, give OK on the displayed
window.

PROGRAM:

module leds(a, b);

input [0:15]a;

output [0:15]b;

reg b;

always@(a)begin

b=~a;

end

endmodule

RTL- SCHEMATIC:

USER CONSTRAINT FILE (UCF):

net a[0] loc = p48; net a[6] loc = p40; net a[12] loc = net b[2] loc = net b[9] loc =
p97; p71; p57;
net a[1] loc = p46; net a[7] loc = p39;
net a[13] loc = net b[3] loc = net b[10] loc =
net a[2] loc = p45; net a[8] loc = p50; p100; p72; p58;
net a[3] loc = p44; net a[9] loc = p51; net a[14] loc = net b[4] loc = net b[11] loc =
net a[4] loc = p43; net a[10] loc = p101; p74; p61;
p95; net a[15] loc = net b[5] loc = net b[12] loc =
net a[5] loc = p42;
net a[11] loc = p102; p76; p62;
p96; net b[0] loc = p67; net b[6] loc = net b[13] loc =
p77; p63;
net b[1] loc = p68;
net b[7] loc = net b[14] loc =
p78; p64;

net b[8] loc = net b[15] loc =

p52; p65;
SIMULATED OUTPUT:

RESULT:

Thus the FPGA board is studied and tested.

EXPT. NO. DATE

 3b

AIM:

To implement Adder and Multiplier in FPGA and verify the truth table

APPARATUS REQUIRED:

System with P4 Processor, Xilinx SPARTAN3 FPGA kit, JTAG, Xilinx ISE9.1i
Simulator, Switch Mode Power Supply.

PROCEDURE

Follow the down loading procedure given in Expt. 3(a) to configure the FPGA device for
adder and multiplier circuits and verify their working.
RESULT:

Thus adder and multiplier circuits are implemented in FPGA and their output is verified
with truth table.
 EXPT. SYNTHESIS, P&R AND POST P&R SIMULATION OF DATE
4 COUNTER CIRCUITS AND CRITICAL
PATH/STATIC TIMING ANALYSIS

AIM:
To perform Synthesis, P&R and post P&R simulation of counter circuits and Critical
paths/static timing
analysis.

APPARATUS REQUIRED:
System with P4 Processor and Xilinx ISE9.1i Simulator.

PROCEDURE:
Refer the program for 4 bit ripple counter given in ext. 1(c) and follow the procedure given
below:

SYNTHESIS, P&R AND POST P&R SIMULATION OF COUNTER:

Place and route:

Post place and route:

PERFORMING POST-PLACE & ROUTE SIMULATION

We can simulate the placed and routed design on the chip, also known as timing
simulation. This process uses the post-place and route simulation model (a structural SIMPRIM-
based VHDL or Verilog file) and a standard delay format (SDF) file generated by NetGen. The
SDF file contains true timing delay information of the design.

Post-Place & Route simulation can be performed on a simulation netlist or a source file available
in the Post-Route Simulation view, which may include any of the following:

 HDL test benches

 Test bench waveform files
 Simulation-only HDL source files, such as IP simulation models or external simulation
models
 Structural HDL simulation netlists generated after the design is implemented

This process is recommended prior to generating a programming file.

1. Run the Implement Design process.

2. In the Sources tab, select Post-Route Simulation from the drop-down list.
3. Select a test bench file, a test bench waveform file or an HDL source file to simulate.
Note If you select a test bench to simulate, the necessary netlist will be generated for the top
module of the design.

4. To simulate a lower-level module of your design, you can set the Generate Multiple
Hierarchical Netlist option in the Simulation Model Properties dialog box for
the Generate Post-Plce & Route Simulation Model process. After the simulation model
netlist is generated, the netlist appears in the hierarchy under the test bench that
instantiates it. Select this test bench to simulate.

TO PERFORM PLACE & ROUTE SIMULATION

1. In the Processes tab, expand Xilinx® ISE® Simulator or ModelSim Simulator.

2. Right-click Simulate Post-Place & Route Model, and select Properties.
3. Set the property values according to the desired results.
o For the ISim, you can set the ISim Properties and the Simulation Model
Properties in the Process Properties dialog box.
o For the ModelSim Simulator, you can set the Simulation Properties, the Display
Properties and the Simulation Model Properties in the Process Properties dialog
box.
4. Double-click Simulate Post-Place & Route Model.

The files that are passed to your simulator include:

o The test bench or test bench waveform file.

 o The post-place and route simulation model (a VHDL or Verilog file).
o The standard delay format (SDF) file which contains true delay information for
your design.
Simulation is performed and the results are found in your simulator.

If no stimulus is available, the design is simply compiled and loaded in the simulator.
You must then create a stimulus file and perform a simulation on the design in your
simulator.

o For more information about using ModelSim, see the ModelSim Simulator
documentation.
o For more information about using ISim, see the ISim Help.
You can perform any of the following:

Analyze the results of the simulation process in your simulator.

Rerun the Implement Design process.

If the results are correct, generate a programming file.

RESULT:

Synthesis, P&R and post P&R simulation of counter circuits and Critical paths/static timing
analysis was done successfully.
 EXPT. FPGA IMPLEMENTATION OF COUNTER AND TESTING DATE
5 USING CHIP SCOPE PRO

AIM:
To implement a 4 bit ripple counter using FPGA and test it using Chip Scope Pro feature.

APPARATUS REQUIRED:
System with P4 Processor, Xilinx SPARTAN3 FPGA kit, JTAG, Xilinx ISE9.1i
Simulator, Switch Mode Power Supply

PROCEDURE:
Follow the down loading procedure given in Expt. 3(a) to configure the FPGA device for
the 4 bit ripple counter given in Expt. 1(c) and verify its working using Chip Scope Pro feature.
The procedure for verification using Chip Scope Pro is outlined below:

CHIP SCOPE PRO:

Xilinx provides Chip Scope Pro software to view hardware simulation (to view the
current status of the hardware signals in a FPGA board). We can run the Chip Scope Pro for
current project and also configure the FPGA through Chip Scope Pro. An FPGA may get inputs
from the outside environment like switches or binary signals from external hardware and the
Project output is changed depending on the input. When we change the input in hardware we get
the output changes in hardware which is also updated in Chip Scope Pro simulation window.
Thus we can view the real time changes of hardware signals in software. Refer Xilinx website to
know more details about Chip Scope Pro.
Working procedure of Chip Scope Pro is given in the following section. Counter function
is taken as an example to view the hardware simulation. Create a new project file and give the
Verilog Coding, UCF file. Save the files and select New Source from Project menu. New Source
Wizard window will open, here select Chip Scope Definition and Connection File. Give the file
name and file location to store the file then click ‘Next’ and ‘Finish.

CONFIGURING THE LOGIC ANALYZER CORE

In order to test the counter design we have to configure and insert the logic analyzer core in
our design. Follow these steps:
 1. In the ‘Sources” view right click on the top module (counter.v) and select ‘New Source’

2. In the ‘New Source Wizard’ window, select ‘Chipscope Definition and Connection File’ and
specify the filename as ‘counter_db’. Click ‘Next’ and then click ‘Finish’.
3. Note that ‘counter_debug.cdc’ file has been added to your ‘Sources’ list and is listed
below the selected top module (counter).

4. Double click on ‘debug.cdc’ to launch the ChipScope Pro Core Inserter application. This
application will integrate the logic analyzer core into our counter design. Do not alter any
settings on the first screen. Click ‘Next’.

5. To observe any signal, we have to specify the trigger. Logic analyzer core will start capturing
the desired signal upon activation of trigger signal. In this example we want to monitor the
counter’s counting action as soon as ‘rst’ signal is deactivated. So we will create two trigger
ports. One port will be ‘rst’ signal and another port will be counter’s eight least significant
bits.
Set ‘Number of trigger ports’ to 2.
In ‘TRIG0’ frame set ‘Trigger Width’ as 1 (since ‘rst’ is one bit signal).
In ‘TRIG1’ frame set ‘Trigger Width’ as 8 (as we want to observe counter’s 8 least significant
 bits).
Click Next.

6. Now in this window we will specify capture parameters. We want to use our trigger ports
as data ports which will be recorded by logic analyzer. We also want to sample data on rising
clock edge.
In ‘Sample On’ list select ‘Rising’.
Set Number of samples to be recorded by changing ‘Data Depth’ to 1024 samples. This will
record 1024 samples from the trigger event. You can at the most record 16K samples.
Select both check boxes in ‘Trigger Ports Used As Data’ frame.
Click Next.
7. Now we will specify which signal(s) to be used as Clock and Trigger. Click on ‘Modify
Connections’.

8. Select the ‘Clock signals’ Pane, then select ‘clk_BUFG’ signal from the left hand side list and
then click on ‘Make Connection’. This will add ‘clk’ signal as the clock signal for logic
analyzer.
9. Now select ‘Trigger/Data signals’ pane. Select ‘TP0’ and connect ‘rst_IBUF’ signal to CH0
channel.

10. Similarly click on ‘TP1’ pane and add connect counter’s lower eight bits to eight channels.
Click ‘OK’ once you finish making connections.
11.Now in the main window click on ‘Return to Project Navigator’. It will ask for saving the
project, click ‘Yes’. Now we are ready to compile the entire counter design along with the
logic analyzer core.

12. In the ISE, select top level module ‘counter’ and in the ‘Processes’ pane double click on
‘Analyze Design Using ChipScope’. This will start the process to synthesize combined unit
consisting of design under test (in this case counter) and the chipscope cores.
DEBUGGING THE DESIGN USING CHIPSCOPE ANALYZER TOOL:

Once the synthesis gets over, ISE will launch the Analyzer tool. Make sure that FPGA board is
connected to PC.

1. Once the analyzer tool is running, click on ‘Initialize JTAG Chain’ icon located at the top right
corner of the window. This will initialize the JTAG chain and identify the devices found in the
chain. A dialog box will appear showing the devices discovered. Click ‘OK’.

2. Now select the FPGA device from the JTAG chain, right click and then select ‘Configure’ to
specify the configuration bit stream file.

3. Select the bit stream file ‘cntr.bit’ from the bit stream folder. Then click ‘OK’.

IMPORTANT:

4. After clicking ‘OK’, tool will load the bit stream file into FPGA and check the availability of
debugging cores. If debugging core is found tool will show ‘INFO: Found 1 Core Unit in the
JTAG device Chain.’ Message in status window.

If you see ‘Found 0 Core …’ message instead, then either you have selected wrong bit stream
file or something has gone wrong in one of the previous steps and debugging core has not
been inserted properly into the design.
If everything is fine then you will see options for Logic Analyzer core inserted in our design.
Now double click on the ‘Trigger Setup’ element to launch trigger setup window. And for
trigger port 0 (i.e. ‘rst’ signal) specify the trigger Value 0.
5. This will make logic analyzer to trigger as soon as ‘rst’ become zero and record 1024 samples
on successive clock edges. Note that trigger signals are sampled on rising clock edge. Double
click on ‘Waveform’ element to see the waveform. 5. Now everything is ready. To apply the
settings and ARM the trigger click on button. After that press the ‘Down’ button on the
development board to release the ‘rst’ signal. This will trigger the logic analyzer. Once 1024
samples are recorded, this data will be transferred to PC and will be displayed in the
waveform window.

NOTE: To see the names of the trigger ports, you can import the ‘debug.cdc’ file in analyzer tool.
Click on File>Import and then select ‘counter_debug.cdc’
RESULT:

4 bit ripple counter was implemented on the FPGA and tested successfully using Chip
Scope Pro.
 INTRODUCTION TO TANNER EDA TOOL

On the desk top click on S – Edit v 15.0 icon, Then Go to ‘File’ in the main menu select ‘New’
and ‘New Design’.

Type the design name and locate it in a folder and click OK as shown below.

Add Libraries from Library Toolbar – For this the Folder is located at:
My Computer\your login name\Tanner EDA\Tanner Tools v15.0 v15.0\Process\ . . . . Click OK.
(Refer snap shot given below.)
Go to Cell, click on ‘New View’ then press OK. A new schematic entry window as shown below
appears.

(Scroll mouse for Zoom in and Zoom out.) On the left side click on ‘Generic_250nm_Devices’
for the design of CMOS Inverter. Select PMOS_2_5V and Click on ‘Instance’. The device will
now be attached to the mouse, Place it on the schematic screen by a single right click of the
mouse. Similarly we can select & paste all required components. Properties of devices can be
changed from properties toolbar, they are customizable.

Select Wire tool, Then Click on open node of device and connect the wires to the nodes as
per circuit diagram
Now connect input, output port accordingly and ‘Print voltage’ is available in ‘SPICE
Commands’ from Library.
Then Go To Spice Simulation, ‘Transient/Fourier Analysis’ as presented below . Set the
above shown Parameters.

Then select ‘General’, include Library File, Set path as Z:/../../My Documents/Tanner
EDA/Tanner Tools v15.0/Process/Generic_250nm/Generic_250nm_Tech/Generic_250nm.lib TT.

Then Click OK Button. Finally Click Start Simulation. The OUTPUT is obtained in W-Edit.

EXPT. NO. DATE

 6

AIM:
To perform synthesis and standard cell based design of counter circuit and power and
delay analysis using TANNER EDA TOOL

APPARATUS REQUIRED:

System with P4 Processor, TANNER EDA tool.

PROCEDURE:

In continuation of the 7th experiment, in schematic editor, click on “Cell” tab and select
“Generate Symbols” option and click on “Modify”. Then the below shown symbol would be
noticed.

Save this symbol and create a new cell and use the cell0 as the component in the new design.
Then rig up the circuit as shown below. For placing PadIn&PadOut use the library
“Generic_250nm_IO_Pads” from the Library Navigator.

Now click on File -> Export -> Export TPR…. This will generate the TPR file of the design that
was generated in S-Edit.
Then browse to the path where the TPR file has to be saved.
Now, invoke L-Edit, from the desktop.

Do the layer setups by following the below given steps. Click on File -> and select “Replace
Setup…”

Click on the “Browse” button and browse to the path as “C:\Users\Documents\Tanner

EDA\Tanner Tools v15.0\Designs\Lights\lights.tdb” and click OK. Again click OK.

Then click on “Tools -> SPR -> Place and Route…” In “Standard Cell Place and Route”
window, click on “Setup” button as shown in figure.
Click on the “Browse” button under Standard Cell Library File, and browse to the path as
“C:\Users\Bharani\Documents\Tanner EDA\Tanner Tools v15.0\Designs\Lights\lights.tdb” and
click on “Browse” button under “Netlist File” and browse to the path of the TPR file that was
generated in S-Edit. As per this example, the path would be
“E:\ec2357\nco_10bit\nco_10bit.tpr”.
Then click on “Initialize Setup”, “Padframe Setup…” and Pad Route Setup…” buttons
respectively and observe the status as below.

Initialize Setup
Padframe Setup…

Pad Route Setup… Change the Pad Via Layer as Via under the Layers tab. And click OK.
Then click on OK in the SPR Setup window

Then click on Run button. Then find the design imported summary as below.
Once the automatic placing and routing of the design is completed, run the DRC check & and
then extract the spice netlist by using the “lights.ext” file as reference. The extracted spice netlist
would look like the one as shown in the below figure.
Keep only the MOSFET components and comment the lines with * for others components, if
extracted.

Then at the bottom of the netlist, include the spice commands as shown in the upcoming
steps.To insert the spice commands, click on the “Insert Command” button on the tool bar. Then
the Command Wizard opens up.

Then expand the functions as desired to insert as commands. As per this design, we need to insert
Analysis type, path to the model file, analysis results, Power Supply and the required input
sources. To insert the analysis type, follow the instructions as shown.

Now, we need to insert the path to the model file, by using the following steps.
Next is to print the waveforms of the desired signal.

Then the power supply for the design has to be connected.

Finally after inserting all the commands, the file would look like as follows.

The simulated output can be observed in the waveform editor, i.e. W-Edit.
 To get better view of the waveform, zoom the waveform editor by pressing ‘+’ key from
the keyboard. To measure the frequency of the waveform, select “Measures” from the Waveform
calculator, then select “Frequency” from the Add Measure window, and then select the signal
name from the Traces navigator, click “Trace Nav” in the waveform calculator and then press
“Measure” button in the waveform calculator.

The measured frequency of the signal can be observed in the command window of W-Edit.
COUNTER CIRCUIT:
SETTING FOR Voltage Source V2 & V3
SIMULATION SETTING
SIMULATION OUTPUT:

RESULT:

Synthesis and standard cell based design of counter circuit has been completed using
TANNER EDA and power and delay analysis has been performed.
EXPT. NO. P&R, POWER AND CLOCK ROUTING AND POST P&R DATE
7 SIMULATION OF COUNTER AND STATIC TIMING
ANALYSIS USING TANNER EDA TOOL

AIM:
To perform place and route, power and clock routing, post place and route simulation and
static timing analysis of counter using TANNER EDA TOOL.

APPARATUS REQUIRED:
System with P4 Processor, TANNER EDA tool.

THEORY:

STATIC TIMING ANALYSIS (STA):

The STA is static the analysis of the design is carried out statically and does not depend
upon the data values being applied at the input pins. This is in contrast to simulation based
timing analysis where a stimulus is applied on input signals, resulting behavior is observed and
verified, then time is advanced with new input stimulus applied, and the new behavior is
observed and verified and so on. a design along with a set of clock definitions and the definition
of the external environment of the design, the purpose of static timing analysis is to validate if
the design can operate at the rated speed. That is, the design can operate safely at the specified
frequency of the clocks without any timing violations. Some examples of timing checks are setup
and hold checks. A setup check ensures that the data can arrive at a flip-flop within the given
clock period. A hold check ensures that the data is held for at least a minimum time so that there
is no unexpected pass-through of data through a flip-flop: that is, it ensures that a flip-flop
captures the intended data correctly. These checks ensure that the proper data is ready and
available for capture and latched in for the new state

CLOCK TREE SYNTHESIZES:

CTS are the process of insertion of buffers or inverters along the clock paths of ASIC
design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to
minimize skew and insertion delay. Apart from these, useful skew is also added in the design by
means of buffers and inverters. Clock is propagated after placement because the exact physical
location of cells and modules are needed for the clock’s propagation which in turn impacts in
dealing with accurate delay and operating frequency and clock is propagated before routing
because when compared to logical routes, clock routs are given more priority. This is because,
clock is the only signal switches frequently which in acts as source for dynamic power
dissipation.

Though wide range of clock routing algorithm is available, EDA tool chooses the
optimized algorithm automatically and it only shows the critical paths after propagating the tree.
If a design results in negative slack, increasing the clock timing is an easy way but changing the
clock period changes the operating frequency. Solving the negative slack without changing the
clock period is possible by up-sizing or down-sizing the cell in critical paths.

PROCEDURE:

Follow the P&R procedure given in Expt. 6 to place the counter block in FPGA and route
the blocks and verify their working using POST P&R simulation.

RESULT:

Place and route, power and clock routing, post place and route simulation and static timing
analysis of counter was performed successfully using TANNER EDA Tool.
 EXPT. NO. DATE
8a CMOS INVERTER

AIM:

To perform schematic entry of a CMOS Inverter and verify its functionality using
transient analysis.

APPARATUS REQUIRED:

System with P4 Processor, Tanner EDA Tool.

THEORY:

CMOS Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input. When the
input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON. The output is
pulled-up to VDD. When the input A = 1, nMOS transistor is ON and pMOS transistor is OFF.
The Output is Pulled-down to GND.

PROCEDURE

Draw the schematic of CMOS Inverter using S-Edit.

Perform Transient Analysis of the CMOS Inverter.
Go to ‘setup’, in that select ‘spice simulation’. Choose Transient Analysis and set the
parameters as explained in the instructions above.
 Obtain the output waveform from W-Edit.
 Obtain the spice code using T-Edit.
SCHEMATIC DIAGRAM:
OUTPUT WAVEFORM:

RESULT:
Thus a CMOS Inverter was constructed and its functionality was verified using transient
analysis.

EXPT. NO. DATE

DIFFERENTIAL AMPLIFIER
AIM:

To verify the functionality of CMOS Differential Amplifier and determine its gain,
bandwidth and CMRR through schematic entry.

APPARATUS REQUIRED:

System with P4 Processor & Tanner EDA Tool.

THEORY:

A differential amplifier is a type of electronic amplifier that multiplies the difference

between two inputs by some constant factor (the differential gain). Many electronic devices use
differential amplifiers internally. The output of an ideal differential amplifier is given by:

Vout = Ad(Vin1 – Vin2), where Vin1 and Vin2 are the input voltages and Ad is the differential
gain. In practice, however, the gain is not quite equal, for the two inputs. This means that if V in1
and Vin2 are equal, the output will not be zero, as it would be in the ideal case. A more realistic
expression for the output of a differential amplifier thus includes a second term.

Vout = (Ad(Vin1 – Vin2) + Ac(Vin1 + Vin2))/2

Ac is called the common-mode gain of the amplifier. As differential amplifiers are often
used when it is desired to null out noise or bias-voltages that appear at both inputs, a low
common-mode gain is usually considered good. The common-mode rejection ratio, usually
defined as the ratio between differential-mode gain and common-mode gain, indicates the ability
of the amplifier to accurately cancel voltages that are common to both inputs. Common-mode
rejection ratio (CMRR): CMRR= Ad / Ac

The input common-mode range (ICMR) is the range of common-mode voltages over
which the differential amplifier continues to sense and amplify the difference signal with the
same gain.

Typically, ICMR is defined by the common-mode voltage range over which all
MOSFETS remain in the saturation region.
SCHEMATIC DIAGRAM:

PROCEDURE

 Enter the schematic of differential amplifier using S-Edit.

 Perform AC Analysis of the differential amplifier.
 Go to ‘setup’ in that select ‘spice simulation’. Choose ‘ac analysis’ and give the following
values.
 Set ‘Start frequency =10’,’ Stop frequency=10meg’, ‘No. of frequency=25’, ‘Sweep type
= dec’. Click on ‘general’ type and give path to Generic_250nm.lib.Then Click OK.
 RUN Simulation to get output.
 Obtain the frequency response from W-Edit.
 Obtain the spice code using T-Edit.
COMMON MODE OUTPUT:

MEASUREMENT RESULT SUMMARY

AC_Measure_Gain_1 = At

AC_Measure_GainBandwidthProduct_1 =

DIFFERENTIAL MODE OUTPUT:

MEASUREMENT RESULT SUMMARY

AC_Measure_Gain_1= At

AC_Measure_GainBandwidthProduct_1 =

CMRR= Ad / Ac =

RESULT:

The functionality of CMOS Differential Amplifier was verified and its gain, CMRR and
ICMR were determined through schematic entry.
EXPT. NO. LAYOUT GENERATION, PARASITIC EXTRACTION AND DATE
POST LAYOUT SIMULATION OF DIFFERENTIAL
9
AMPLIFIER CIRCUIT USING TANNER EDA TOOL

AIM:

To generate layout of CMOS differential amplifier and to extract required parameters using
Tanner EDA tool.

APPARATUS REQUIRED:

System with P4 Processor & Tanner EDA Tool.

PROCEDURE:

 Open the Differential amplifier’s spice net list from T-Edit(extracted from schematic)
 Change NMOS25 to NMOS and PMOS25 to PMOS
 Go to SDL Navigator
 SDL Navigator Window pops up. Click on folder icon to load net list.
 Browse to location where Differential amplifier’s net list is available and load it.
 We will get a message “Number of warnings and Number of instances added”. Now go to
main menu and choose cell0.
 Now all the ports will get listed in SDL navigator window. Choose a port and click on blue
line button to make connections.
 Follow the fly-lines and complete the connections.
 Routed layout will be as below
 Extract the required parameters
 Resimulate and verify the design
CMOS DIFFERENTIAL AMPLIFIER LAYOUT

RESULT:
Thus layout for Differential amplifier is generated using Tanner EDA tool.