Clock Period

Dr DC Hendry

April 23, 2006

1 Setup and Hold Periods

Setup and Hold Periods of Storage Elements

All storage elements (that is, flip flops and latches) have a setup and a
hold period.
The setup period is that period of time before the active clock edge during
which the input data to the storage element must be static.
The hold period is that period of time after the active clock edge during
which the input data to the storage element must be static.
Should data change during this period then a setup violation or a hold
violation is said to have occurred.
Should such a violation occur, the data stored by the storage device is
unpredictable. There is also a small probability that the device enters a
metastable state.

Setup Period

1. The setup period is the minimum length of time the data input signal must
remain stable before the active edge of the clock to ensure predictable and
correct functioning of the cell.1
2. Correct functioning of the cell is defined to occur when the delay to a
stable output does not exceed the reference delay (measured with a large
setup time) by more than 10%.1
1 Paraphrase of TSMC databook
 Clock Period

3. Measured as the interval between the data signal crossing 50% of Vdd and
the clock signal crossing 50% of Vdd 1

Setup Period Waveforms

Input 50% Vdd

Clock 50% Vdd

setup
time

Hold Period Waveforms

The hold period is similarly defined to the setup period but refers to the period
of time after the active clock edge during which the input data must not change.

Input 50% Vdd

Clock 50% Vdd

hold
time

Setup and Hold Violations

A simple model of the input to any modern storage element is:

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 Clock Period

Clock

Input

Setup times are small and positive.

Hold times are small and positive, or zero, or small and negative.

VHDL Models

VHDL attributes are very useful here, in particular:

signalstable(T) where T is an expression of type TIME and is non-
negative. The result is true if the signal has not changed for T units of
time, false otherwise.
signallast event returns the time of the last event on the signal.
There are a number of other attributes which provide variations on the
above.

D Latch with Setup Check

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 Clock Period

library ieee;
use ieee.std logic 1164.all;

entity dlatch is

generic (
tclk2q : time := 0.3 nS;
tsetup : time := 0.25 nS;
thold : time := 0.2 nS);

port (
clk : in std logic;
d : in std logic;
q : out std logic;
q n : out std logic);

end dlatch;

dl: process (clk, d)

begin
if clk = 1 then
q <= d after tclk2q;
q n <= not d after tclk2q;
end if ;
if clkevent and clk = 0 then
Assume tsetup is +ve
if not dstable(tsetup) then
q <= X;
q n <= X;
report "Setup time violation" severity warning;
end if ;
end if ;
if devent then
...
end process dl;

VITAL Standard

1. The generics above could be used (with much effort) to represent real
delays.
2. Real designs have say one million logic gates.

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 Clock Period

3. Actual delays (especially clock to Q) depend on the output load of the

gate. Also applies to input to output delay of logic gates such as AND,
OR etc.
4. CAD tools must do calculation and add real delays for an accurate delay
simulation.
5. Representation of the delays of the gates are therefore standardised.

VITAL Standard ...

1. VHDL Initiative Towards Asic Libraries = VITAL

2. This standard from IEEE defines a large number of generic parameters
that logic gates should include.
3. Simulators include code to load values into these generics using data de-
rived from layout (either ASIC or FPGA).
4. Simulators usually include a number of options for the control of VITAL
models (such as switching off various checks ...).
5. Based on IEEE 1164 and existing delay calculation tools (particularly SDF
format).

2 Metastable States

Metastable States

1. The VAST majority of setup and hold violations do not cause a metastable
state.
2. A very small number of such violations however can cause the storage
element to display a very long clock to Q delay.
3. Essentially, the storage element is caught half way between logic 0 and
logic 1.
4. Circuit noise will eventually cause the device to go to either logic 0 or
logic 1.

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 Clock Period

Input Synchronisers

1. External inputs from the outside world have timing unrelated to the clock
signal.
2. Setup and hold violations with metastability simply reflect the uncertainty
on the timing of the input signal.
3. Metastable states are however a possible cause of problems.
4. Synchroniser circuits can be used to reduce the probability of such prob-
lems to an acceptable level.
5. Such circuits do however introduce a delay into the input signal - not
usually a problem.

Input Synchronisers ...

low very low very, very low

probability probability probability
of metastability of metastability of metastability

Input D Q D Q D Q "synchronised"
output

Q Q Q
Clock

3 Clock Period

Basic Minimum Clock Period

The minimum clock period for a register to register transfer must allow for:

1. The clock to Q delay of the register supplying data - tclk2Q .

2. The maximum propagation delay of the combinational logic - tmax .
3. The setup time of the receiving register - tsetup .

 -
 -
tclk2Q  -
tmax tsetup
4.

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 Clock Period

Clock Skew

1. Clock signals need to be distributed to a large number of storage elements.

2. It is not possible to ensure that each signal arrives at each element at
precisely the same time.
3. CAD tools can however reduce the variance in arrival time by insertion of
appropriate buffers.
4. Clock signals therefore arrive at storage elements with a range of arrival
times - that spread in arrival time is the clock skew - tskew .

Clock Period with Skew

1. The clock period must now allow for the clock to the register supplying
data being late with respect to the clock of the receiving register by tskew .
 -
 -
tskew  -
tclk2Q  -
tmax tsetup
2.
3. The minimum clock period is now:
tclock = tskew + tclk2Q + tmax + tsetup

Hold Violations

1. Can the input signals to the receiving register arrive too early and cause
a hold violation?
2. In the absence of clock skew this is unlikely as tclk2Q is usually much larger
than thold .
3. With clock skew however, this needs to be considered. If the minimum
combinational logic delay is tmin , we require:
tclk2Q + tmin > tskew + thold

- tclk2q + tmin
-


 - -

4. tskew + thold

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 Clock Period

4 Pipelining

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