VHDL Descriptions of FSMs

Dr DC Hendry

March 15, 2006

1 FSM Block Diagram

The block diagram of a Mealy FSM was:

Next
Inputs State Reg Output
Logic Logic

clock

The blocks of this design are:

State Register The state register has as input the clock signal, the next state
from the next state logic on the D lines and normally an active low reset
line. The output of the state register is the current state of the machine.

Next State Logic This combinational logic has as input the current state and
the control inputs, its output is the next state.
Output Logic Another combinational logic block whose inputs are the current
state (and only the current state for a Moore machine), and the control
inputs (for a Mealy machine). The output is the output of the machine.
 FSMs in VHDL

When described in VHDL, each of these components may be described by a

single process. A more elaborate design is possible in which each block above
is a design unit, this however simply obfuscates the overall design of the FSM.
For simpler state machines and the circuitry they control, it would be possible
to place that simple circuitry into the same design unit as the FSM, avoid this.
Synthesis tools are best able to apply effective FSM optimisation algorithms
only if the FSM is in a separate design unit to the data path circuitry (well
explain the terminology here in a later lecture).

2 VHDL Coding

The coding of state machines is one instance where VHDLs user defined types
can greatly improve the readability of a design, and make debugging so much
easier. Taking the example of the 1011 sequence detector from the last lec-
ture, and using the state names START, SEEN1 and so on (we cant use 10xx
and the like as VHDL names need to start with an alphabetic). The the follow-
ing declaration are useful in the declarations section of the architecture body:

type statename is (start, seen1, seen10, seen101, success);

signal current state, next state : statename;

With these declarations we get two signals, one for the next state of the ma-
chine called next state, and one for the current state of the machine called
current state. Each of these signals can only take on one of the values start,
seen1, seen10, seen101 or success. Of course the synthesis tool will later
decide (given the correct commands) to replace these with an optimised set of
binary codes. We do not need to know what these codes are.

2.1 The State Register

The state register should be edge triggered and should normally include a reset
line. In most cases the reset line is essential since it ensures that the state regis-
ter is placed into a known value. Note that given the above declaration of type
statename, the default value for current state is start, and so the simulation
will quite happily proceed even if no reset line is present! By convention, reset
lines are active low (that is, the machine is reset when the reset line is at logic 0
as opposed to logic 1). Again by convention, an active low signal is indicated
by appending n to its name. The reset signal will therefore be called rst n.

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2.2 Next State and Output Combinational Logic FSMs in VHDL

Adherence to such conventions greatly improves the readability of code.

Here is the code for the state register with an asynchronous active low reset
line, using a process with a sensitivity list:

state reg : process (clk, rst n)

begin
if rst n = 0 then
current state <= start;
else if clkevent and clk = 1 then
current state <= next state;
end if ;
end process state reg;

Note that the inputs to this circuitry are the clock signal clk, the reset line
rst n, and the next state signal next state. You should be able to understand
from previous work why this is a description with an asynchronous reset line.

2.2 Next State and Output Combinational Logic

The next state combinational logic and the output combinational logic may
be also be described with processes. Depending on the coding effort needed,
which is also very close to the readability of the code, it may advantageous to
use either one process for both blocks of combinational logic, or two separate
processes, one for each of the next state combinational logic and the output
logic.

Lets start by considering two separate processes for the next state and out-
put logic, then well look at a combined process. First, the next state logic.
This block of combinational logic has two inputs, the current state in the signal
current state, and the inputs to the machine, in this case the signal a. Well
use a process with a sensitivity list, and so both of the signals current state
and a are on that sensitivity list. Within the process well use case statements
as a highly readable mechanism for specifying the logic. The code is shown in
figure 1.

Note the use of the initial sequential assignment in this code of:

next state <= start;

This statement essentially ensures that the process, even in the presence of
slight errors in coding, is still combinational logic and not sequential.

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2.2 Next State and Output Combinational Logic FSMs in VHDL

next state logic: process (current state, a)

begin process next state logic

next state <= start;

case current state is

when start =>
if a = 0 then
next state <= start;
else
next state <= seen1;
end if ;

when seen1 =>

if a = 0 then
next state <= seen10;
else
next state <= seen1;
end if ;

when seen10 =>

if a = 0 then
next state <= start;
else
next state <= seen101;
end if ;

when seen101 =>

if a = 0 then
next state <= seen10;
else
next state <= success;
end if ;

when success =>

if a = 0 then
next state <= start;
else
next state <= seen1;
end if ;

when others => null;

end case;

end process next state logic;

Figure 1: Next State Logic Description

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 FSMs in VHDL

The output logic is given in figure 2.

output logic: process (current state)

begin process output logic
if current state = success then
x <= 1;
else
x <= 0;
end if ;
end process output logic;

Figure 2: Output Logic

The next figure shows the effect of simulating this design. Note how the sim-
ulator prints the state names on the simulation waveform, greatly easing de-
bugging.

Page 1 of 1
SimVision: Waveform 1

Cursor = 49,935,000,000fs
Baseline = 0
CursorBaseline = 49,935,000,000fs

Figure 3: Simulation of sequence detector design

3 Invoking Synthesis Tool Optimisations

Synthesis tools can provide a number of optimisations for the construction of

FSMs. These include:

1. State Reduction. For certain state diagrams some states may be redun-
dant. There are manual methods available to remove such
Printed at 15:46:57 on Mon, Mar 06, 2006
states, these
Printed by SimVision from Cadence Design Systems, Inc.

methods are time consuming however, and in fact simply implemented

in software.

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 FSMs in VHDL

2. State Assignment. State assignment, as has been indicated earlier, is a

difficult problem to solve precisely. Synthesis tools however do have al-
gorithms available for this problem.

Perhaps the most useful facet of using CAD tools for these problems, is that
once coded, the algorithms may be re-applied following a modification to the
design. The designer is not therefore dissuaded from further development of
the design by the need to re-apply time consuming manual techniques.

The approach taken by PKS, and by the majority of CAD tool vendors, is to use
VHDL attributes to indicate those signals that are state variables, and to choose
the optimisation algorithms to be applied.

Here is part of the code of the sequence detector design that I actually used:

library ambit;
use ambit.attributes.all;

architecture rtl of detector is

type state name is (start, seen1, seen10, seen101, success);

signal current state, next state : state name;
attribute STATE VECTOR of current state : signal is true ;
attribute ENCODING of current state : signal is "one_hot";

begin rtl

As you can see the basic type definition and signal declarations for the current
and next states are as above, this is followed however by two attribute state-
ments, each of which uses an attribute defined by the synthesis tool. These
attributes are defined in the library ambit in the package attributes.

The attribute ENCODING of the signal current state directs the synthesis tool
to use a certain algorithm for coding of the state code. Some of the supported
options are:

binary Use a sequential binary coding, 00, 01, 10, 11 etc.

one hot Use a one-hot encoding (discussed later).
area Use an encoding which minimises logic area (heuristic).

timing Use an encoding for least propagation delay (heuristic).

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 FSMs in VHDL

One-hot encoding has the following properties:

1. One-hot encoding uses one flip-flop per state of the machine, so more
flip-flops are required.
2. One one flip-flop has its Q set at a time (the hot flip-flop), all others are at
0.
3. Resultant state encoding:
State Code
start 10000
seen1 01000
seen10 00100
seen101 00010
success 00001

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