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Dr DC Hendry
This lecture begins with short investigation of counter circuits as a simple exam-
ple of a finite state machine. This is followed by general definitions of the two
classes of finite state machine, Moore machines and Mealy machines. In this
lecture we will concentrate upon manual design methods as a means of ensuring
understanding of the basic concepts. In the next lecture we will look at VHDL
descriptions of the same circuits.
1 Synchronous Counters
A synchronous circuit is one in which all flip-flops are clocked by the same
signal. This design approach ensures that combinational logic circuits driven by
these same flip-flops have predictable timing, that is, data is available at a given
point in time determined by the clock signal, and that data must be supplied
to flip-flops at a known point in time.
Next Reg-
State ister
Combin-
ational D Q
Logic Current
State
Next
State
Clk
The contents of the register, which is also the input to the combinational logic,
are referred to as the current state of the machine, while the output of the
combinational logic block, which is also the input to the register, is referred to
as the next state of the machine. On the arrival of the active edge of the clock
signal, the next state is copied to the current state.
Suppose the register contains the binary data for the number 5, that is, 101,
then the next state logic is designed so that for an input of 5, the output is
6. On the next active edge of the clock, the contents of the register would be
incremented from 5 to 6.
The combinational logic, the next state logic, needs to be designed to cater not
just for the input 5 with output 6, but all inputs and outputs needed. These
can be derived from a next state table. Next state tables come in two types, an
unassigned state table and an assigned state table. For the modulo 8 counter
the two tables are:
In this case the decision as to which binary code will represent each state is
trivial, it is simply the binary representation of the decimal number.
In this case, since there are only 8 states, we need only three bits to represent
all states. The register, or state register, will therefore consist of three flip-flops.
The schematic for the modulo 8 counter now becomes:
D2 D Q
Q2
Next
State Q
Logic
D1 D Q
Q1
D0 D Q
Q0
Clk
From the assigned state table we can construct three K-Maps, one for each of
the outputs of the next state logic, D0 , D1 and D2 . Assume that D2 is the most
significant bit, take the K-Map for D2 :
D2 Q2 Q1
00 01 11 10
0 0 0
1 1
Q0
1 0
1 0
1
D2 = Q2 Q0 + Q2 Q1 + Q2 Q1 Q0
In a similar manner Boolean equations may be derived for the signals D1 and
D0 , as follows:
D1 Q2 Q1
00 01 11 10
0 0
1 1 0
Q0
1 1 0 0
1
Giving:
D1 = Q1 Q0 + Q1 Q0
D0 Q2 Q1
00 01 11 10
0
1 1 1 1
Q0
1 0 0 0 0
Giving D0 = Q0 .
Although not particularly useful for a counter, the state diagram, or state bubble
view, is more useful for more complex designs. Here is the state diagram for the
modulo 8 counter:
7 1
6 2
5 3
4
For many counters, and for the majority of finite state machines, one or more
control inputs can affect the next state for a given current state. In the case of
counters such a control input could determine whether the counter counts up
or counts down on each clock edge.
Take the case of a modulo 4 counter with an up/down control line, the unas-
signed state table becomes:
Current up/down
State 0 1
0 3 1
1 0 2
2 1 3
3 2 0
Current up/down
State 0 1
Q1 Q0 D1 D0 D1 D0
00 11 01
01 00 10
10 01 11
11 10 00
The Boolean equations for the signals D1 and D0 are then calculated from the
assigned state table. The inputs to the combinational logic are now Q1 , Q0 and
up/down. Denoting the up/down signal by u, gives the K-Maps:
D1 Q1 Q0 D0 Q1 Q0
00 01 11 10 00 01 11 10
0
1 0
1 0 0 1 0 0 1
u u
1 0
1 0
1 1 1
0 0
1
D0 = Q0
D1 = Q1 Q0 u+Q1 Q0 u+Q1 Q0 u+Q1 Q0 u
3 Moore Machines
Inputs Next
State Reg Output
Logic Logic
clock
1. The next state logic and the register (Reg) play a similar role to the same
components in the counter.
2. Control inputs, in addition to the current state, determine the next state
of the machine.
3. The outputs of the machine are now obtained via a new block, the output
logic from the current state.
4 Mealy Machines
Next
Inputs State Reg Output
Logic Logic
clock
1. Very similar to the Moore machine, except that the control inputs are now
also input to the output logic.
2. Like the Moore machine, the next state depends upon the current state
and the control inputs.
3. Unlike the Moore machine the outputs now depend upon both the current
state and the control inputs.