COMPLEX INSTRUCTION SET COMPUTER (CISC)

The earliest processor designs used dedicated hardwired logic to decode and execute
each instruction. That was appropriate for simple designs with few registers, but made
architectures more complex and hard to build. Developers of computer systems took
another approach; they built simple logic to control the data paths between the various
elements of the processor, and used microcode instruction set to control the data path
logic. In those systems, the main processor has some built-in ROM, which contains
groups of microcode instructions, corresponding to each machine-language instruction
(a macrocode instruction). Because instructions could be retrieved much faster from a
local ROM than from main memory, designers put as many instructions as possible into
microcode. Microcode implementation allows using the same programming model
among different hardware configurations, beside the advantage of easily modifying the
instruction set. Some machines were optimized for scientific computing, others were
optimized for business computing; however, since they all shared the same instruction
set, programs could be moved from one machine to another without re-compilation (but
with a possible increase or decrease in performance depending on the underlying
hardware.) This kind of flexibility and power made microcoding the preferred way to
build new computers for some time. Assembly language programming and the low
memory size of the early days promoted the CISC style, leading to common features
including 2-operand format, register to memory and memory to register instructions,
multiple addressing modes for memory, variable length instructions and many clock
cycles per instruction. The hardware architectures had typically complex instruction-
decoding logic, small number of general-purpose registers and several special-purpose
registers
Reduced instruction set computer
A reduced instruction set computer, or RISC, is one whose instruction set
architecture (ISA) has a set of attributes that allows it to have a lower cycles per
instruction (CPI) than a complex instruction set computer (CISC). Various suggestions
have been made regarding a precise definition of RISC, but the general concept is that of
a computer that has a small set of simple and general instructions, rather than a large set
of complex and specialized instructions. Another common RISC trait is their load/store
architecture, where memory is only accessed through specific instructions, rather than as
a part of most instructions. Although a number of computers from the 1960s and 70s have
been identified as being forerunners of RISCs, the modern concept dates to the 1980s. In
particular, two projects at Stanford University and University of California, Berkeley are
most associated with the popularization of this concept. Stanford's MIPS would go on to
be commercialized as the successful MIPS architecture, while Berkeley's RISC gave its
name to the entire concept, commercialized as the SPARC. Another success from this era
were IBM's efforts that eventually led to the Power Architecture. As these projects matured,
a wide variety of similar designs flourished in the late 1980s and especially the early 1990s,
representing a major force in the Unix workstation market as well as embedded
processors in laser printers, routers and similar products. Most RISC architectures have
fixed-length instructions (commonly 32 bits) and a simple encoding, which simplifies fetch,
decode, and issue logic considerably. One drawback of 32-bit instructions is reduced code
density, which is more adverse a characteristic in embedded computing than it is in the
workstation and server markets RISC architectures were originally designed to serve. To
address this problem, several architectures, such as ARM, Power ISA, MIPS, RISC-V, and
the Adapteva Epiphany, have an optional short feature-reduced instruction format or
instruction compression feature. The SH5 also follows this pattern, albeit having evolved
in the opposite direction, having added longer media instructions to an original 16-bit
encoding.
 Booth's multiplication algorithm
Booth's multiplication algorithm is a multiplication algorithm that multiplies two
signed binary numbers in two's complement notation. The algorithm was invented
by Andrew Donald Booth in 1950 while doing research on crystallography at Birkbeck
College in Bloomsbury, London. Booth used desk calculators that were faster
at shifting than adding and created the algorithm to increase their speed. Booth's algorithm
is of interest in the study of computer architecture.
Booth's algorithm examines adjacent pairs of bits of the N-bit multiplier Y in signed two's
complement representation, including an implicit bit below the least significant bit, y1 = 0. For each
bit yi, for i running from 0 to N 1, the bits yi and yi1 are considered. Where these two bits are
equal, the product accumulator P is left unchanged. Where yi = 0 and yi1 = 1, the multiplicand
times 2i is added to P; and where yi = 1 and yi1 = 0, the multiplicand times 2i is subtracted from P.
The final value of P is the signed product.
The representations of the multiplicand and product are not specified; typically, these are both also
in two's complement representation, like the multiplier, but any number system that supports
addition and subtraction will work as well. As stated here, the order of the steps is not determined.
Typically, it proceeds from LSB to MSB, starting at i = 0; the multiplication by 2i is then typically
replaced by incremental shifting of the P accumulator to the right between steps; low bits can be
shifted out, and subsequent additions and subtractions can then be done just on the highest N bits
of P.[1] There are many variations and optimizations on these details.....
The algorithm is often described as converting strings of 1s in the multiplier to a high-order +1 and
a low-order 1 at the ends of the string. When a string runs through the MSB, there is no high-
order +1, and the net effect is interpretation as a negative of the appropriate value.
Booth's algorithm can be implemented by repeatedly adding (with ordinary unsigned binary
addition) one of two predetermined values Aand S to a product P, then performing a
rightward arithmetic shift on P. Let m and r be the multiplicand and multiplier, respectively; and
let x and y represent the number of bits in m and r.
Implementation-

1. Determine the values of A and S, and the initial value of P. All of these numbers should
have a length equal to (x + y + 1).
1. A: Fill the most significant (leftmost) bits with the value of m. Fill the remaining
(y + 1) bits with zeros.
2. S: Fill the most significant bits with the value of (m) in two's complement
notation. Fill the remaining (y + 1) bits with zeros.
3. P: Fill the most significant x bits with zeros. To the right of this, append the value
of r. Fill the least significant (rightmost) bit with a zero.
2. Determine the two least significant (rightmost) bits of P.
1. If they are 01, find the value of P + A. Ignore any overflow.
2. If they are 10, find the value of P + S. Ignore any overflow.
3. If they are 00, do nothing. Use P directly in the next step.
4. If they are 11, do nothing. Use P directly in the next step.
3. Arithmetically shift the value obtained in the 2nd step by a single place to the right.
Let P now equal this new value.
4. Repeat steps 2 and 3 until they have been done y times.
5. Drop the least significant (rightmost) bit from P. This is the product of m and r.
Example- Find 3 (4), with m = 3 and r = 4, and x = 4 and y = 4:

m = 0011, -m = 1101, r = 1100

A = 0011 0000 0
S = 1101 0000 0
P = 0000 1100 0
Perform the loop four times:
1. P = 0000 1100 0. The last two bits are 00.
P = 0000 0110 0. Arithmetic right shift.
2. P = 0000 0110 0. The last two bits are 00.
P = 0000 0011 0. Arithmetic right shift.
3. P = 0000 0011 0. The last two bits are 10.
P = 1101 0011 0. P = P + S.
P = 1110 1001 1. Arithmetic right shift.
4. P = 1110 1001 1. The last two bits are 11.
P = 1111 0100 1. Arithmetic right shift.
The product is 1111 0100, which is 12.
The above-mentioned technique is inadequate when the multiplicand is the most negative
number that can be represented (e.g. if the multiplicand has 4 bits then this value is 8). One
possible correction to this problem is to add one more bit to the left of A, S and P. This then
follows the implementation described above, with modifications in determining the bits of A and
S; e.g., the value of m, originally assigned to the first x bits of A, will be assigned to the first x+1
bits of A. Below, the improved technique is demonstrated by multiplying 8 by 2 using 4 bits for
the multiplicand and the multiplier:

A = 1 1000 0000 0
S = 0 1000 0000 0
P = 0 0000 0010 0
Perform the loop four times:
1. P = 0 0000 0010 0. The last two bits are 00.
P = 0 0000 0001 0. Right shift.
2. P = 0 0000 0001 0. The last two bits are 10.
P = 0 1000 0001 0. P = P + S.
P = 0 0100 0000 1. Right shift.
3. P = 0 0100 0000 1. The last two bits are 01.
P = 1 1100 0000 1. P = P + A.
P = 1 1110 0000 0. Right shift.
4. P = 1 1110 0000 0. The last two bits are 00.
P = 1 1111 0000 0. Right shift.
The product is 11110000 (after discarding the first and the last bit) which is 16.
 CACHE AND VIRTUAL MEMORY

Virtual or logical memory is a concept that, when implemented by a

computer and its operating system, allows programmers to use a very
large range of memory or storage addresses for stored data. The
computing system maps the programmers virtual addresses to real
hardware storage addresses. In addition to managing the mapping of
virtual storage addresses to real storage addresses, a computer
implementing virtual memory or storage also manages storage
swapping between active storage (RAM) and hard disk or other high
volume storage devices. Data is read in units called pages of sizes
ranging from a thousand bytes (actually 1,024 decimal bytes) up to
several megabyes in size.

Cache ram is very high-speed RAM chips which sit between the CPU
and main memory. It stores memory accesses by the CPU. Cache ram
helps to alleviate the gap between the speed of a CPUs megahertz
rating and the ability of RAM to respond and deliver data. It reduces the
frequency that the CPU must wait for data from the main memory.
 ADDRESSING MODE

1)Immediate Mode
The operand is an immediate value is stored explicitly in the instruction:
Example: SPIM (opcode Test, source)
2) Index Mode
The address of the operand is obtained by adding to the contents of the
general register (called index register) a constant value. The number of the
index register and the constant value are included in the instruction code.
Index Mode is used to access an array whose elements are in successive
memory locations. The content of the instruction code, represents the
starting address of the array and the value of the index register, and the
index value of the current element. By incrementing or decrementing index
register different element of the array can be accessed.
Example: SPIM/SAL - Accessing Arrays
3) Indirect Mode
The effective address of the operand is the contents of a register or main
memory location, location whose address appears in the instruction.
Indirection is noted by placing the name of the register or the memory
address given in the instruction in parentheses. The register or memory
location that contains the address of the operand is a pointer. When an
execution takes place in such mode, instruction may be told to go to a
specific address. Once it's there, instead of finding an operand, it finds an
address where the operand is located.
NOTE:Two memory accesses are required in order to obtain the value of
the operand (fetch operand address and fetch operand
value).Example: (textbook) ADD (A), R0

I/O Interface (Interrupt and DMA Mode)

The method that is used to transfer information between internal storage and external I/O
devices is known as I/O interface. The CPU is interfaced using special communication links by
the peripherals connected to any computer system. These communication links are used to
resolve the differences between CPU and peripheral. There exists special hardware
components between CPU and peripherals to supervise and synchronize all the input and
output transfers that are called interface units.

Mode of Transfer:
The binary information that is received from an external device is usually stored in the memory
unit. The information that is transferred from the CPU to the external device is originated from
the memory unit. CPU merely processes the information but the source and target is always
the memory unit. Data transfer between CPU and the I/O devices may be done in different
modes.
Data transfer to and from the peripherals may be done in any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now lets discuss each mode one by one.
 1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually the transfer
is from a CPU register and memory. In this case it requires constant monitoring by the CPU of
the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct access to
the memory unit. A transfer from I/O device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from device to the CPU
and store instruction to transfer the data from CPU to memory. In programmed I/O, the CPU stays
in the program loop until the I/O unit indicates that it is ready for data transfer. This is a time
consuming process since it needlessly keeps the CPU busy. This situation can be avoided by
using an interrupt facility. This is discussed below.
2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily.
This situation can very well be avoided by using an interrupt driven method for data transfer. By
using interrupt facility and special commands to inform the interface to issue an interrupt request
signal whenever data is available from any device. In the meantime the CPU can proceed for any
other program execution. The interface meanwhile keeps monitoring the device. Whenever it is
determined that the device is ready for data transfer it initiates an interrupt request signal to the
computer. Upon detection of an external interrupt signal the CPU stops momentarily the task that
it was already performing, branches to the service program to process the I/O transfer, and then
return to the task it was originally performing.
3. Direct Memory Access: The data transfer between a fast storage media such as magnetic
disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals
directly communicate with each other using the memory buses, removing the intervention of the
CPU. This type of data transfer technique is known as DMA or direct memory access. During
DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over
the buses to manage the transfer directly between the I/O devices and the memory unit.

Bus Request: It is used by the DMA controller to request the CPU to relinquish the control of the
buses.
Bus Grant: It is activated by the CPU to Inform the external DMA controller that the buses are in high
impedance state and the requesting DMA can take control of the buses. Once the DMA has taken the
control of the buses it transfers the data. This transfer can take place in many ways.
BusTransfer:
In which a block sequence consisting of memory words is transferred in a continuous burst where the
DMA controller is the master of the memory buses. This mode is needed for fast devices like magnetic
disks.
CyclicStealing:
In this DMA controller transfers one word at a time after which it must return the control of the buses to
the CPU. The CPU merely delays its operation for one memory cycle to allow the direct memory I/O
transfer to steal one memory cycle.
 SRAM (static random access memory)

SRAM (static RAM) is random access memory (RAM) that retains data
bits in its memory as long as power is being supplied. Unlike dynamic
RAM (DRAM), which stores bits in cells consisting of a capacitor and
a transistor, SRAM does not have to be periodically refreshed. Static
RAM provides faster access to data and is more expensive than DRAM.
SRAM is used for a computer's cache memory and as part of the random
access memory digital-to-analog converter on a video card.

DRAM (dynamic random access memory)

Dynamic random access memory (DRAM) is a type of memory that is
typically used for data or program code that a
computer processor needs to function. DRAM is a common type of
random access memory (RAM) used in personal computers (PCs),
workstations and servers. Random access allows the PC processor to
access any part of the memory directly rather than having to proceed
sequentially from a starting place. RAM is located close to a computers
processor and enables faster access to data than storage media such
as hard disk drives and solid-state drives.DRAM stores each bit of data
or program code in a storage cell consisting of a capacitorand
a transistor, and is typically organized in a rectangular configuration of
storage cells. A DRAM storage cell is dynamic in that it needs to be
refreshed or given a new electronic charge every few milliseconds to
compensate for charge leaks from the capacitor.DRAM is one option
of semiconductor memory that a system designer can use when
building a computer. Alternative memory choices include static RAM
(SRAM), electrically erasable programmable read-only memory
(EEPROM), NOR flash and NAND flash. Many systems use more than
one type of memory.
 DRAM vs. SRAM

DRAM is a successor to SRAM. Memory designers reduced the number

of elements per bit and eliminated differential bit lines to save chip area
to create DRAM. As a result, DRAM is less expensive to produce than
SRAM.

But SRAM retains some advantages over DRAM. SRAM does not need to
be refreshed because it operates on the principle of switching
the current flow in one of two directions rather than holding a charge in
place within a storage cell. SRAM is generally used for cache memory,
which can be accessed more quickly than DRAM.

SRAM is capable of byte-level reads and writes, and is faster at reads

and writes than DRAM. DRAM writes data at the byte-level and reads at
the multiple-byte page level.

Power differences vary based on whether the system is in active or

sleep mode. DRAM requires less power than SRAM in an active state,
but SRAM consumes considerably less power than DRAM does while in
sleep mode.

EPROM
EPROM (erasable programmable read-only memory) is programmable
read-only memory (programmable ROM) that can be erased and re-used.
Erasure is caused by shining an intense ultraviolet light through a
window that is designed into the memory chip. (Although ordinary room
lighting does not contain enough ultraviolet light to cause erasure,
bright sunlight can cause erasure. For this reason, the window is
usually covered with a label when not installed in the computer.)A
different approach to a modifiable ROM is electrically erasable
programmable read-only memory (EEPROM).