ABC DFT Flow 002

cad_dd_00502 (Note Id 1110) ISSUE 3 ABC AND MABC DESIGN FOR TESTABILITY METHODOLOGY
ABC and MABC Design for Testability

Methodology v002
cad_dd_00502
Note Id: 1110
Issue 3 May 17, 2007
2007
PMC-Sierra, Inc.
100 2700 Production Way
Burnaby BC Canada V5A 4X1
Phone 604.415.6000 FAX 604.415.6200
This document is CONFIDENTIAL and PROPRIETARY and is for the use of PMC-Sierra Inc. personnel only, except to the extent that permission is
expressly granted elsewhere.
In any event, no part of this document may be reproduced in any form without the express written consent of PMC-Sierra, Inc.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 1 of 86

DOC NO: cad_dd_00502 (Note Id 1110) ISSUE DATE:

FILE NAME: ISSUE NUMBER: 3
MARKETING NO: NA STATUS:
FILING PATH: ICDC (Top Level >> Digital_Design >> Procedures_and_Flows >> DFT_Flows >> ABC_DFT)
TITLE: ABC AND MABC DESIGN FOR TESTABILITY METHODOLOGY
ABSTRACT: This document provides the general guidelines and rules to design testable ABCs and MABCs.
KEY WORDS: DFT, Scan, JTAG, ATPG, ABC, MABC, ABC Design Rules, Analog Test Bus
INCLUSIONS:
AC JTAG Calculator
PREPARED BY: REVIEWED BY:
Bernard Guay
Karim Arabi Manager, Mixed Signal Development
Manager, Design for Test
Bill Lye
APPROVED BY
Leader, Mixed Signal Development
Graeme Boyd
Principal Engineer
Alan Nakamoto
Director, Design Services
Frank Barber
Technical Advisor
Brian Gerson
VP, Mixed Signal Development
Richard Steedman
Principal Engineer
Ken Ferguson
Manager, Test Technology Engineering
2007
PMC-Sierra, Inc.
Phone 604.415.6000 FAX 604.415.6200

REVISION HISTORY
Issue Date Originator Reviewer Details of Change

Issue 1 December Karim Arabi Alan Nakamoto, Brian Document Released as cad_dd_00501
2001 Gerson, Tad
Kwasniewski, Bill Lye,
Graeme Boyd, Frank
Barber, Richard
Steedman, Ken
Ferguson
Issue 2 July 2002 Karim Arabi Alan Nakamoto, Brian Document Released as cad_dd_00502
Gerson, Bernard Guay,
Some details added about
Bill Lye, Graeme Boyd,
List of mandatory and optional pins
Frank Barber, Richard
Relationship between IDDQ and SCANB
Steedman, Ken
Relationship between ENB and IDDQ
Ferguson
Guidelines about probing nets
Naming conventions
Issue 3 May 2007 Omid Chavoshi Karim Arabi, Ken Document updated to address issues and
Brough, Jurgen Hissen, questions raised in the following
Mathieu Gagnon, CAD_PREPs:
Gershom Birk, John 27232
Plasterer, Guillaume 27184
Fortin, Ken Ferguson 26601
16007
15247
14398
59127
43680
In addition two new sections were added:
1) AC JTAG [IEEE 1149.6 Std]
2) I/O control using UDRs
2007
PMC-Sierra, Inc.
Phone 604.415.6000 FAX 604.415.6200

CONTENTS
CONTENTS......................................................................................................4
LIST of FIGURES ...........................................................................................6
1 DEFINITIONS ...........................................................................................9
2 INTRODUCTION ....................................................................................10
2.1 Order of Precedence....................................................................10
3 ABC/MABC Overview ............................................................................. 11
3.1 General Block Diagram of an ABC ............................................... 11
3.2 Block Diagram of an MABC .........................................................13
3.3 ABC/MABC Test Related Signals.................................................16
3.4 ABC/MABC Test Arbitration Logic ................................................28
3.5 Related Application Notes ............................................................30
4 ABC/MABC Digital DFT and ATPG Flow.................................................31
4.1 ABC/MABC Test Insertion and ATPG Flow ..................................31
4.2 DFT Rules ....................................................................................34
4.3 Test Synthesis Procedure ............................................................46
4.3.1 Scan Insertion Strategy for ABCs ......................................46
4.3.2 Scan Insertion Strategy for MABCs ...................................46
4.3.3 Scan Insertion and ATPG Users manual ..........................47
5 ABC/MABC Analog DFT Flow.................................................................48
5.1 Main Analog DFT Goals ...............................................................48
5.1.1 Design Debugging .............................................................48
5.1.2 Test Coverage ...................................................................48

5.1.3 Test Time ...........................................................................48
5.1.4 ATE Adaptation..................................................................49
5.2 Mixed-Signal DFT Methodology ...................................................49
5.2.1 Analog Test Bus.................................................................49
5.2.2 Connecting the Analog Test Bus at the Top-Level .............56
5.2.3 Loopback...........................................................................58
5.2.4 Bypassing..........................................................................62
5.2.5 IEEE 1149.4 ......................................................................63
6 IEEE 1149.6 Standard [AC JTAG]...........................................................64
6.1 slim_ac I/O Logic Macro [IOLM] ...................................................66
6.2 AC JTAG Test Related Signals.....................................................68
6.3 Analog AC JTAG Receiver Implementation..................................72
6.3.1 Analog AC JTAG Receiver Parameters .............................73
6.3.2 Analog AC JTAG Receiver Parameter Calculator..............75
7 I/O control inputs During Test Mode........................................................76
8 APPENDIX A ..........................................................................................78
8.1 IEEE 1149.4 .................................................................................78
8.2 IEEE 1149.4 TBIC ........................................................................79
8.3 IEEE 1149.4 ABM.........................................................................80
8.4 IEEE 1149.4 Instruction Set .........................................................81
8.5 Component Measurement Using IEEE 1149.4.............................82
8.6 IEEE 1149.4 Used for On-Chip Testing ........................................84
9 Reference ...............................................................................................85

LIST OF FIGURES
Figure 1: Simplified block diagram of a testable ABC. Mandatory signals

are highlighted....................................................................................11
Figure 2: ABC and its interface to wrapper/shim................................................. 12
Figure 3: Simplified block diagram of an example of an MABC. ......................... 15
Figure 4: Example Test Mode Arbitration Truth Table ......................................... 28
Figure 6: Example Test Mode Select and Enable Arbitration Truth Tables.......... 29
Figure 7: Simplified view of the ABCs Digital Core............................................. 31
Figure 8: ABCs Digital Core test insertion flow. For simplicity only VHDL
file names are presented. .................................................................. 33
Figure 9: ABCs Digital Core scan vector generation and verification flow.......... 34
Figure 10: Handling internally generated clocks. SCANB is an active low

top-level scan test mode signal. The mux is often embedded
into PLLs and DLLs. .......................................................................... 37
Figure 11: Internally generated clock should not go through any

combinational logic before reaching the multiplexer.
TEST_CLK is a dedicated top-level test clock................................... 37
Figure 12: Clocks should not go through any combinational logic. ..................... 38
Figure 13: Handling gated clocks. ...................................................................... 39
Figure 14: Handling sequential controlled set and reset. .................................... 39
Figure 15: Lockup latch concept for functional cross-clock domain paths. ......... 41
Figure 16: Making Latches transparent in test mode.......................................... 41
Figure 17: Placement of boundary scan cells (BSCs) for ABCs. The mux
is normally inside the TX. .................................................................. 44
Figure 18: Schematic block diagram of the Analog Test Bus used to
observe internal signals of an ABC (a) and the schematic of
analog test switches (b)..................................................................... 50
Figure 19: Connection of ATB2s from different ABCs to top-level ATB2. ............ 51

Figure 20: A bad example for monitoring VDD and VSS values at different
points of the device............................................................................ 51
Figure 21: Measuring current level of internal nodes. P1 and N1 are part
of the analog circuit under test. I1 and I2 are measured
through ATB2..................................................................................... 53
Figure 22: Schematic block diagram of the Analog Test Bus applied to an
analog core as a stimulus bus (a) and the implementation of
multiplexer (b).................................................................................... 54
Figure 23: Connection of ATB1s from individual ABCs to top-level ATB1. .......... 54
Figure 24: Schematic block diagram of the Analog Test Bus concept
combining stimulus and output test buses......................................... 55
Figure 25: Schematic block diagram of the two-pin Analog Test Bus
concept used to measure and apply differential signals. ................... 55
Figure 26: Schematic block diagram of the Analog Test Bus concept and
its connection to the top-level ATAP (a) and the implementation
of analog test pad (b)......................................................................... 57
Figure 27: Schematic block diagram of the Analog Test Bus concept and
its connection to a single analog test pad at the top-level. ................ 57
Figure 28: Instantiating identical instances of an MABC as a reusable

hard-core with embedded pads. ........................................................ 58
Figure 29: Loopback DFT technique implemented with multiplexers.................. 59
Figure 30: Digital and analog loop back DFT technique for a data
communication device (T1/E1 Line Interface). .................................. 60
Figure 31: Loopback technique to test high-speed transmitter and receiver

pairs with embedded pattern generators and checkers. .................... 61
Figure 32: Loopback technique for a receiver/transmitter pair in a data

communication device. ...................................................................... 62
Figure 33: Bypassing DFT strategy implemented using multiplexers. To

test the analog block in the middle, switches should be set to
S1 = 0, S2 = 1, and S3 = 0. ............................................................... 63
Figure 34: Bypassing the Jitter Attenuator to measure CDR jitter

specifications and diagnose possible cause of an excessive
jitter.................................................................................................... 63

Figure 35: Problem with DC JTAG testing of differential and/or ac-coupled

signals ............................................................................................... 64
Figure 36: AC JTAG differential signal reception with Test Receiver .................. 65
Figure 37: slim_ac IOLM Block Diagram ............................................................ 67
Figure 38: Top-level example connections between one slim_ac IOLM and
one ABC receiver .............................................................................. 72
Figure 39 :Top-level example connections between one slim_ac IOLM and

one ABC transmitter .......................................................................... 72
Figure 40 : Typical AC JTAG Receiver................................................................ 73
Figure 41 : Block diagram of AC JTAG receiver circuit ....................................... 74
Figure 42: Test mode I/O control using a UDR ................................................... 77
Figure 43: IEEE 1149.4 chip architecture. .......................................................... 79
Figure 44: Schematic representation of IEEE 1149.4 TBIC. ............................... 80
Figure 45: An example of ABM implementation. SCD: Switch for Core

Disconnect......................................................................................... 81
Figure 46: Interconnect component measurement for components situated

between an IC and ground. IT is a current source and VT is a
voltage measurement unit. ................................................................ 82

between two mixed-signal ICs........................................................... 83
Figure 48: IEEE 1149.4 used to support Analog Test Bus (ATB) DFT
technique........................................................................................... 84

1 DEFINITIONS
A/MSC Analog or Mixed-Signal Core

ABC Analog Block Circuitry
ABM Analog Boundary Module
ASIC Application Specific Integrated Circuit
ASSP Application Specific Standard Product
ATAP Analog Test Access Port
ATE Automatic Test Equipment
ATPG Automatic Test Pattern Generation
BIST Built-In Self Test
CTA Concurrent Testing Approach
CUT Circuit Under Test
DBM Digital Boundary Module
DFT Design for Testability
DUT Device Under Test
ECBI Extended Common Bus Interface
IOLM IO Logic Macro
IP Intellectual Property
JTAG Joint Test Action Group (also called Boundary Scan latter adopted by
IEEE 1149.1 standard)
LSB Least Significant Bits
MABC Mega ABC
MPIF Microprocessor Interface
MSB Most Significant Bits
MTSB Mega TSB
PRBS Pseudo Random Binary Sequence
SOC System-On-a-Chip
TAP Test Access Port
TBIC Test Bus Interface Circuit
TDI Test Data In
TDO Test Data Out
TMS Test Mode Select
TSB Telecom System Block
UDR User-Defined Register [cad_dd_00694 on ICDC]
VHDL VHSIC Hardware Description language

2 INTRODUCTION
Testing, debugging and characterizing mixed signal ICs is known to be difficult

and time consuming. The problem is aggravated when high-performance analog
and mixed-signal cores are integrated as a part of a system-on-a-chip (SOC)
solution. SOC poses serious access problem and puts more pressure on test
time budget because the analog and mixed-signal circuit is now only a small part
of the whole chip. Consequently, to overcome testability obstacles, mixed-signal
design for test (DFT) techniques are joining the mainstream IC design practice.
This document provides the general methodology and rules to design testable
analog block circuitry (ABC) and Mega ABC (MABC). All new ABCs and MABCs
should be designed following the rules and guidelines provided in this document
to ensure their reusability and compatibility with the new digital DFT flow. For
more information about DFT flow for digital circuits, please refer to PM-2001526
and PM-2002148. Note that this document is focused on digital and analog DFT
techniques for ABCs and MABCs and does not cover any built-in self-test (BIST)
technique.
Throughout this document the standard ABC signal naming convention is

followed.
2.1 Order of Precedence
In case of conflict, the following documents rank in control in the order named:
ABC Design Procedure (PMC-1951249)

ABC Design Practice (PMC-1960106)
TSB Design for Testability Rules (PMC-2001526)
This document
Top-Level Design for Testability Methodologies (PMC-2002148)

3 ABC/MABC OVERVIEW
3.1 General Block Diagram of an ABC
Figure 1 illustrates a simplified block diagram of an ABC. It could be either

instantiated inside a Telecom System Block (TSB) or be a part of a Mega ABC
(MABC). An ABC includes an analog or mixed-signal core (A/MSC). It may also
include a Digital Core. As shown in Figure 2 the ABC is normally surrounded by
a wrapper or accompanied by a shim to interface it to configuration registers.
Configuration registers are either located in the ECBI block of a TSB or are
located at top-level. A detailed description of each block is followed:
ABC
ANALOG ANALOG
INPUTS Analog or Mixed-Signal Core OUTPUTS
ATB1 (A/MSC) ATB2
ATBN1 ATBN2
ABC Digital Core

DIGITAL DIGITAL
INPUTS Test Test Mode Functional OUTPUTS
Arbitrator Decoder Digital Circuitry
IDDQ
FLL_CLK
TEST_CLK
MODEx
ENB
SCAN_OUTy
SCAN_INy
SCAN_EN
SCANB
ATINy
ATMSB
DTINy
DTMSB
DTBOy
DTBIy
HDTBOy
HDTBIy
JTAG_ENB
TX_JTAG
RX_JTAG
Figure 1: Simplified block diagram of a testable ABC. Mandatory signals are

highlighted.

ABC ABC
ANALOG ANALOG
ANALOG Analog or Mixed-Signal Core OUTPUTS OUTPUTS
ANALOG Analog or Mixed-Signal Core
INPUTS (A/MSC) INPUTS (A/MSC)
ATB1 ATB2 ATB1 ATB2
ATBN1 ATBN2 ATBN1 ATBN2
DIGITAL DIGITAL
DIGITAL OUTPUTS OUTPUTS
ABC Digital Core DIGITAL
INPUTS ABC Digital Core
INPUTS
Shim Interface Logic

Wrapper
To MPIF To MPIF
Figure 2: ABC and its interface to wrapper/shim.
A/MSC may contain pure analog circuitry or a combination of analog circuitry

and non-synthesizable or non-scanned digital circuitry. The digital part of
A/MSC is normally operating at very high speeds and either cannot be
synthesized or cannot be scanned even if it is synthesized. It is tested at the
same time that the analog circuitry is tested using dedicated analog tests.
The A/MSC is a part of the ABC.
ABC Digital Core contains three main components: Functional Digital

Circuitry, Test Arbitrator and Test Mode Decoder. Functional Digital Circuitry
is normally synthesized and scanned digital circuitry such as finite state
machines (FSM) and digital signal processing (DSP) blocks. It is needed to
be integrated with the ABC either to achieve repeatable timing specifications
from chip to chip or to enable functional simulation and verification of the ABC
(i.e. can not be split as could not verify correct operation). Test Mode
Decoder contains all decoding circuitry for zATINy and zDTINy buses. Test
Arbitrator includes digital circuitry required to place the ABC in safe mode
during JTAG and scan test modes and establish priority between different test
modes. The ABC Digital Core is normally full-scanned to ensure that all
manufacturing defects are properly detected during production testing. The
ABC Digital Core is a part of the ABC and is archived with the ABC.
Wrapper/Shim contains ECBI block and other required glue logic.

Wrapper/Shim interfaces the ABC with the device level microprocessor
interface (MPIF). Configuration registers are normally located inside ECBI.
Content of configuration registers is decoded using decoding logic located
inside the wrapper/shim for zATMSBx and zDTMSBx buses and inside the
ABCs ABC Digital Core for zATINy and zDTINy buses. Shim resides outside

the ABC at the same level of hierarchy but wrapper creates a new level of
hierarchy and instantiates the ABC. The Wrapper/shim should be archived
independently if design reuse is required.
Mandatory signals are in bold color in Figure 1. Some of the mandatory signals
may be omitted with a justified reason described in the related ABC engineering
document. The following test control signals, if included in the ABC, should be
set to a specific logic value in order to setup the ABC in the normal operation
mode. For a detailed definition of these signals, please refer to Section 3.3.
ATMSB: Analog test mode selector signal should be set to logic 1

DTMSB: Digital test mode selector signal should be set to logic 1
IDDQ: Global IDDQ enable signal is set to logic 0
JTAG_ACTIVEB: Global JTAG enable signal is set to logic 1
JTAG_EXTESTB: Global JTAG EXTEST instruction signal is set to logic 1
SCANB: Global scan test mode signal is set to logic 1
SCAN_EN: Global scan enable signal should is set to logic 0
FLL_CLK: Global functional lockup latch clock is set to logic 1
3.2 Block Diagram of an MABC
An MABC is a collection of reusable ABCs to perform a specific function that

cannot be accomplished by a single existing ABC. Figure 3 illustrates an
example of an MABC constructed from three different ABCs. To simplify the
diagram only test related connections are shown.
The MABC A/MSC block represents the MABCs analog circuitry and non-
synthesizable or non-scanable logic. The MABC Digital Core contains Functional
Digital Circuitry, Test Arbitrator and Test Mode Decoder. Functional Digital
Circuitry represents all MABC-level glue logic and control circuitry. Test Mode
Decoder contains the required decoding circuitry to create MABC-level test
modes from zATINy and zDTINy buses. Test Arbitrator includes digital circuitry
required to place the MABC in safe mode during JTAG and scan test modes and
establish priority between different test modes. A given MABC may not contain
all of these blocks depending on its application and functionality. Inside the
MABC, these blocks are at the same level of hierarchy as the ABCs. An MABC
inherits the same mandatory test signals from its ABCs.

The decoding logic for MABC level test modes from zATINy and zDTINy buses is
located inside the MABC Test Mode Decoder block.
The MABC-level zDTMSBy and zATMSBy buses are not encoded. They are
simply a collection of individual ABC test mode selector signals and the MABC-
level ATMSB and DTMSB signals. They should provide the capability of putting
individual ABCs in test mode and also engaging multiple ABCs in MABC level
test modes such as loopback.
MABC is normally surrounded by a wrapper or accompanied by a shim to

interface to the top-level MPIF. Wrapper/Shim contains ECBI circuitry and other
glue logic for interfacing ABCs together and with the ECBI block. Configuration
registers are located inside the ECBI block. Configuration registers contain
encoded data to represent test modes. The required decoding should be done
using decoding logic located inside the wrapper/shim for zATMSBy and
zDTMSBy buses.
The following test control signals, if included in the MABC, should be set in order
to setup the MABC in the normal operation mode. For a detailed definition of
these signals, please refer to Section 3.3.
zATMSBy: Analog test mode selector bus should be set to logic 11 .. 1

zDTMSBy Digital test mode selector bus should be set to logic 11 .. 1
IDDQ: Global IDDQ enable signal is set to logic 0
JTAG_ACTIVEB: Global JTAG enable signal is set to logic 1
JTAG_EXTESTB: Global JTAG EXTEST instruction signal is set to logic 1
SCANB: Global scan test mode signal is set to logic 1
SCAN_EN: Global scan enable signal should is set to logic 0
FLL_CLK: Global functional lockup latch clock is set to logic 1

MAB
C ABC1 ABC2
Analog or Mixed- Analog or Mixed-
ATB Signal Core Signal Core ATB2
1
ATBN (A/MSC) (A/MSC) ATBN2
1
ABC Digital Core ABC Digital Core
MABC A/MSC
ABC3
MABC Digital Analog or Mixed-
Core
Test Mode
Signal Core
Decoder (A/MSC)
Test Arbitrator
ABC Digital Core
Functional Digital
Circuitry
TB
JTAG_EXTES
y
SCAN_IN
Ty
SCAN_OU
N
SCAN_E
SCANB
ATMSBy
ATINy
DTMSBy
DTINy
DTBOy
DTBIy
HDTBOy
HDTBIy
IDDQ
G
TX3_JTA
G
RX3_JTA
TX1_JTAG
RX1_JTAG
G
TX2_JTA
RX2_JTAG
ENB
EB
JTAG_ACTIV
FLL_CLK
K
TEST_CL
zMODEx
Figure 3: Simplified block diagram of an example of an MABC.

3.3 ABC/MABC Test Related Signals
This section gives a detailed description of signals related to test and validation.
Note that standard ABC naming convention rules are used to describe these
signals.
Table 1: Brief description of signals related to scan.
Name Type Description

SCANB Input from Mandatory.
a chip top-
Active-low scan test mode signal.
level pin
or from a This signal is controllable either from the top-level of
JTAG DFT the chip or from a JTAG DFT register bit, and is driven
register bit LOW during scan test mode, and driven HIGH during
normal chip operation. When this signal is active, the
ABC Digital Core is forced into the scan test mode,
and the remainder of the ABC is forced into a safe
mode, protecting it from random digital control inputs
from the remainder of the chip.
At the top-level of the chip, SCANB is normally
inverted to generate IDDQ, however some chips may
have independent IDDQ and SCANB signals.
Alternatively, two different bits of JTAG DFT register in
the padring might be used to generate SCANB and
IDDQ signals. When SCANB is asserted, the ABC is
also in an IDDQ state (ie. any digital scan flops in the
ABC should work, but the rest of the ABC must draw
no current from digital supplies, and ABC outputs to
core are static).
Inside the ABC/MABC, JTAG_EXTESTB has priority
over this signal.
If unused, this signal should be driven HIGH.


JTAG_ACTIVEB Input from Mandatory
JTAG
Active-low JTAG boundary scan test mode signal
Controller
generated by device JTAG controller.
The JTAG_ACTIVEB signal is driven HIGH when the
JTAG controller is in its Test-Logic-Reset state;
otherwise JTAG_ACTIVEB is driven LOW in all 15
other states to indicate a JTAG operation is occurring.
When JTAG_ACTIVEB signal is active, the device
could still be fully functional to be compliant with the
JTAG standard e.g. when BYPASS or SAMPLE
instructions are executed.
The main usage of this signal is to turn off JTAG
specific circuitries such as CMLtoCMOS converters
that drive receivers JTAG cells; such circuitries do not
need to be active in normal functional mode.
For ABCs that do not contain a JTAG cell, this signal
should act to put the blocks into reasonable known
conditions that will not interfere with boundary
scanning or cause excessive power dissipation. In
particular, if the ABC/MABC produces signals required
by I/O circuitry (for example a PECL transmitter
current reference) the block must provide sane
outputs that allow JTAG testing to proceed.
JTAG_EXTESTB Input from Mandatory
JTAG
Active-low JTAG boundary scan signal indicating the
Controller
standard JTAG EXTEST instruction is being executed.
The main usage of this signal is to determine whether
transmitters boundary scan test (JTAG) path or their
functional path is selected.
When JTAG_EXTESTB signal is active, the device is
not in full functional mode and the xJTAGy bus is used
to drive and monitor analog device I/Os. The ABC
should be in operation mode to ensure that the signal
path between the JTAG boundary scan cell and the
I/O pad is alive. When this signal is inactive, the
xJTAGy bus is ignored.


IDDQ Input from Mandatory
a chip top-
level pin Active-high IDDQ enable signal.
or from a The IDDQ signal is generated either from a top-level
JTAG DFT pin or from a JTAG DFT register bit and it ensures that
register bit the chip is IDDQ testable.
ABC/MABC output pins that drive digital circuitry, with
the exception of zSCAN_OUTy bus, should be gated
with IDDQ signal to ensure that they do not toggle
during the IDDQ test mode.
During an IDDQ test, an ABC must draw no current
from the power supply. In cases where certain parts of
the ABC must draw current during IDDQ, a separate
analog supply pin should be provided for these parts.
JTAG_EXTESTB and SCANB have higher priority
over this signal. At the very top-level of the device,
inverting SCANB normally generates IDDQ. However,
in some cases, IDDQ and SCANB could be
independent top-level signals or generated by different
bits of JTAG DFT register in the padring.
IDDQ should not be confused with ENB signal that is
generated by an ECBI register and is an ABC specific
signal. Inside the ABC, IDDQ and ENB functionality
may overlap, but IDDQ should have higher priority
over ENB.
If unused, this signal should be driven LOW.


ENB Input from Mandatory
wrapper
Active-low ABC enable signal.
This signal is controllable through a wrapper/shim
ECBI register and engages normal operating mode
when driven LOW.
When inactive, the ABC/MABC should be disabled and
its power dissipation reduced as much as possible.
Its used to minimize power dissipation if the ABC is
not required to operate. ENB is also used to measure
ABCs power dissipation by using it to enable and
disable the ABC and calculate the difference between
power dissipation in both cases.
This signal should not be confused with the IDDQ
signal. ENB has slightly different requirements than
IDDQ. ENB shuts down the whole ABC while IDDQ is
only required to shut down the part of the ABC that is
on the digital power rail. However, IDDQ is required to
guarantee static outputs from the ABC while ENB
could allow some activity. In practice, ENB and IDDQ
can have the same effect if their action satisfies both
sets of requirements. Otherwise, IDDQ must have
precedence over ENB.


z 1ATMSBy 2 Input from Mandatory
wrapper
Active-LOW analog test select signal (ABC) or analog
test select bus (MABC).
This signal is controllable through a wrapper/shim
ECBI register and engages analog test mode when
driven LOW.
For an ABC, this signal is used to enable analog test
mode. When analog test mode is active, the zATINy
bus determines which internal nodes are connected to
the analog test bus. When analog test is inactive
(zATMSBy all driven HIGH), the analog test bus is in a
high-impedance state.
For an MABC, this signal is a bus consisting of the
zATMSBy signals from the individual ABCs, together
with any MABC-specific analog test controls (like
loopback or bypass modes) that may engage testing in
more than one ABC.
In either situation, the ECBI register (contained within
the wrapper/shim) that controls this signal uses a
decoder to select which blocks are selected for analog
testing.
Inside the ABC/MABC, the signals JTAG_EXTESTB,
SCANB, and IDDQ all have priority over this signal.
1
The z at the beginning can be a prefix such as TXi_, RXi_, Ci_ where i is a number. This allows
for MABCs to contain many ABCs that have their own configuration bus without having naming
conflict.
2
The y at the end can only be either a bus ([n-1:0]) or nothing.


zATINy Input from Mandatory
wrapper
Analog test selector bus.
This signal drives a decoder internal to the ABC/MABC to
select one of possible functional analog test, debug and
characterization modes and determines the test procedure
to be performed. If zATMSBy is HIGH, this signal is
ignored and the analog test bus is in a high impedance
state
The register driving this bus contains encoded data that is
decoded using a decoder located inside the ABC. MABC-
level test modes are decoded inside the MABC, but outside
ABCs
Information about the mapping of this signal to test modes
is block dependent and found in the individual ABC/MABC
engineering document. The only standard defined test
mode is the null mode, set by driving this signal LOW,
providing a common null state for the analog test bus for
situations where zATINy is shared between multiple
ABC/MABCs. In the null mode, the analog test bus is in a
high impedance state.


ATB1 Analog I/O Mandatory
ATB2 Analog test bus.
ATB1 and ATB2 are generic bi-directional analog test buses
that may be used to apply analog signals to or observe
analog signals from internal circuit nodes. The actual
nodes to be forced or measured are determined by the
zATMSBy and zATINy signals.
ATB1 is the preferred analog stimulus bus, and ATB2 is the
preferred analog measurement bus, however both may be
used to apply or observe differential analog signals.
Alternatively, if a four-pin analog test port is permitted,
ATBN1 may be used in conjunction with ATB1 to apply
differential signals and ATBN2 may be used in conjunction
with ATB2 to measure differential signals.
If the analog test bus is inactive (zATMSBy is HIGH) or if
the analog test bus is in the null state (zATINy), these
signals are in a high impedance state. Under any other
condition, these signals are used for analog testing and
more information will be found in the individual ABC/MABC
engineering documents.
If unused, these signals should be left floating on-chip.
Pads driving the analog test bus will ground this bus when
the top-level ATMSB signal is driven HIGH. If desired, ATB
could be declared using a bus notation. eg. ATB[0] and
ATB[1]
ATBN1 Analog I/O Inverse analog test bus.
ATBN2 An ABC/MABC will have this signal only if a four-pin analog
test access port is permitted. In this situation, ATBN1 is
used with ATB1 to form a differential test stimulus bus,
while ATBN2 is used with ATB2 to form a differential test
measurement bus, again controlled by zATMSBy and
zATINy.
Like ATB1 and ATB2, these signals are essentially bi-
directional wires and may be used for both stimulus and
measurement, depending upon the test being performed.
If unused, these signals should be left floating on-chip.
Pads driving the analog test bus will ground this bus when
the top-level ATMSB signal is driven HIGH.


zDTMSBy Input from Active-low functional digital test select signal (ABC) or
wrapper functional digital test select bus (MABC).
An ABC/MABC will have this signal only if it has a digital
test bus (zDTBIy, zDTBOy, zHDTBIy, and zHDTBOy).
This signal is controllable through a wrapper/shim ECBI
register and engages functional digital test mode when
driven LOW.
For an ABC, this signal is used to enable functional digital
test mode. When analog test mode is active, the zATINy
bus determines which internal nodes are connected to the
digital test bus. When digital test is inactive (zDTMSBy all
driven HIGH), the digital test bus inputs (zDTBIy and
zHDTBIy) are ignored and the digital test bus outputs
(zDTBOy and zHDTBOy) are driven LOW.
For an MABC, this signal is a bus consisting of the
zDTMSBy signals from the individual ABCs, together with
any MABC-specific digital test controls (like loopback or
bypass modes) that may engage testing in more than one
ABC.
In either situation, the ECBI register (contained within the
wrapper/shim) that controls this signal uses a decoder to
select which blocks are selected for digital testing.
Inside the ABC/MABC, the signals JTAG_EXTESTB,
SCANB, and IDDQ all have priority over this signal. This
signal may be active at the same time as zATMSBy,
allowing mixed-signal testing.


zDTINy Input from Functional digital test selector bus.
wrapper
An ABC/MABC will have this signal only if it contains a
digital test bus.
This signal drives a decoder internal to the ABC/MABC to
select one of the possible functional analog test, debug and
characterization modes and determine the test procedure
to be performed.
If zDTMSBy is HIGH, this signal is ignored and the analog
test bus is in a high impedance state.
Information about the mapping of this signal to test modes
is block dependent and found in the individual ABC/MABC
engineering document. The only standard defined test
mode is the null mode, set by driving this signal LOW,
providing a common null state for the digital test bus for
situations where zDTINy is shared between multiple
ABC/MABCs. In the null mode, the digital test bus inputs
are ignored while the digital test bus outputs are driven
LOW.
zDTBIy Input from Low-speed digital test bus input.
wrapper
This signal mapped to a wrapper/shim ECBI register and is
used to apply low-speed digital test signals. It is used in
production test, debug or validation to force the state of
internal digital nodes, selected by zDTMSBy and zDTINy.
When zDTMSBy is HIGH this signal is ignored.
zDTBOy Output to Low-speed digital test bus output
wrapper
This signal mapped to a wrapper/shim ECBI register and is
used to read low-speed digital test signals. It is used in
production test, debug or validation to observe the state of
internal digital nodes, selected by zDTMSBy and zDTINy.
When zDTMSBy is HIGH, this signal is driven LOW.
If unused, this signal should be left floating on-chip.


zHDTBIy Input from High-speed digital input test bus output.
chip pins
This signal is mapped to external input pins of the IC and is
used to apply high-speed digital test signals that cannot be
applied using an ECBI register. It is used in production test,
debug or validation to force the state of internal digital
nodes, selected by zDTMSBy and zDTINy.
When zDTMSBy is HIGH, this signal is ignored.
zHDTBOy Output to High-speed digital output test bus input.
chip pins
This signal is mapped to external output pins of the IC and
is used to observe high-speed digital test signals that
cannot be observed using an ECBZI register. It is used in
production test, debug or validation to observe the state of
internal digital nodes selected by zDTMSBy and zDTINy.
When zDTMSBy is HIGH, this signal is driven LOW.
If unused, this signal should be left floating on-chip.
SCAN_EN Input from Active-high scan enable signal.
chip top-
This is a global signal, controllable from the top-level of the
level
chip, used for mux-DFF scan style and controls the input
mux of all scan flip-flops. It should be driven LOW in the
normal mode of operation.
An ABC/MABC will have this input pin only if it contains
scanable logic.
zSCAN_INy Input from Scan chain input ports of the ABCs Digital Core.
wrapper
The size of this bus should not exceed the ECBI bus width.
ABC/MABC will have this input bus only if it contains
scanable logic.
zSCAN_OUTy Output to Scan chain output ports of the ABCs Digital Core.
wrapper
The size of this bus should not exceed the ECBI bus width.
An ABC/MABC will have this output bus only if it contains
scanable logic. This bus is excluded from the list of
ABC/MABC digital outputs that are gated by the IDDQ
signal.


TEST_CLK Input from Scan test clock.
chip top-
This is a global signal multiplexed with internally generated
level
clocks to control flops that could not be controlled from top-
level. It should not be used for any other purposes.
An ABC/MABC will have this signal only if it contains
internally generated clocks that drive scanable logic inside
the chip.
FLL_CLK Input from Functional lockup latch clock.
chip top-
This is a global signal to clock functional lockup latches
level
used to prevent capture violation during scan test mode. It
should not be used for any other purposes. FLL_CLK
should be set to logic 1 in the normal operation mode.
An ABC/MABC will have this signal only if it contains
scanable logic in which functional lockup latches have been
inserted.
zJTAGy Input or JTAG input or output signal.
Output on
This signal is required if the ABC contains an I/O cell for
JTAG shift
which JTAG testing makes sense (for example an LVDS
register
transmitter or receiver).
This signal goes to a dedicated boundary scan cell and
should represent the input or output logic value when the
JTAG_ACTIVEB signal is active. The boundary scan cell is
a part of the JTAG boundary scan register.
The ABC designer is responsible to deliver a HDL model
that properly describes the JTAG behavior of the ABC.
If unused, these signals should be driven LOW (if they are
inputs) or left floating on-chip (if they are outputs).


OENB Input from Active-low output enable signal.
wrapper
An ABC/MABC will have this signal only if it has output
circuitry for which powering it down separately makes
sense (for example, an LVDS transmitter).
This signal is controllable through a wrapper/shim ECBI
register and engages normal operating mode when driven
LOW.
When inactive, the output circuitry should be disabled in a
manner that makes sense for the application.
Inside the ABC/MABC, the signals JTAG_EXTESTB and
ENB have priority over this signal, as may the SCANB and
IDDQ signals.
1
zMODEx Input from Configuration mode bus.
wrapper
This bus determines the functional operation mode of the
ABC/MABC. Its operation is block dependent and is
documented in the blocks engineering document.
1
The x at the end of the name can be nothing, a number, a number followed by a letter or a bus.

3.4 ABC/MABC Test Arbitration Logic
Because of the number of different DFT signals and their interactions with block
enables, each ABC/MABC will require test arbitration logic. This section
describes a generic test arbiter. Depending upon the application, the ABC/MABC
designer may need different test arbitration circuitry; however the arbiter
described in this section should cover the majority of the situations.
The test arbiter consists of three inter-related decoders. The first is the priority
decoder for the various test modes, the second uses the test modes to modify
the Analog and Digital Test Mode Select signals and the third uses the test
modes to modify the block enable signals. This arbiter accepts the
JTAG_EXTESTB, JTAG_ACTIVEB, SCANB, IDDQ, ATMSB, DTMSB, ENB, and
OENB signals, and produces modified versions of all of these (with the _OUT
suffix). The test mode arbitration truth table is shown in Figure 4 below, while the
test mode select and block enable arbitration are shown in Figure 6. This test
arbiter is a standard re-usable element [abc_dft_jtag_logic_v2] available in
lib90n_E library whose verilog RTL and gates netlists are located in:
[/tools/sync_mirror/4.1/PM20_25_13_E/artist/PM20_25_13_E/lib90n_E]
To obtain more information on usage of the test arbiter, you may refer to the
readme text file at:
[/tools/sync_mirror/4.1/PM20_25_13_E/artist/PM20_25_13_E/lib90n_E/abc_dft_jt
ag_logic_v2/readme/text.txt]
JTAG_EXTESTB JTAG_ACTIVEB SCANB IDDQ

JTAG_EXTESTB SCANB IDDQ JTAG_ACTIVEB Notes1
_OUT _OUT _OUT _OUT
0 X X 0 0 0 1 0 JTAG EXTEST Mode
0 X X 1 0 0 1 0 Invalid JTAG Mode
2
1 0 X X 1 1 0 1 SCAN Mode
3
1 1 1 X 1 1 1 1 IDDQ Mode
1 1 0 0 1 0 1 0 JTAG SAMPLE Mode
1 1 0 1 1 1 1 0 Normal Mode
1
: Modes appear in their order of precedence
2
: Including IDDQ mode based on scan vectors
3
: Based on functional vectors
Figure 4: Example Test Mode Arbitration Truth Table

Mode ATMSB DTMSB ATMSB_OUT DTMSB_OUT

JTAG EXTEST X X 1 1
JTAG Invalid X X 1 1
SCAN X X 1 1
IDDQ X X 1 1
JTAG SAMPLE A B A B
Normal A B A B
Mode ENB OENB ENB_JTAG_OUT OENB_OUT ENB_OUT

JTAG EXTEST X X 0 0 1
JTAG Invalid X X 0 0 1
SCAN X X 1 1 1
IDDQ X X 1 1 1
JTAG SAMPLE 1 X 1 1 1
JTAG SAMPLE 0 1 0 1 0
JTAG SAMPLE 0 0 0 0 0
Normal 1 X 1 1 1
Normal 0 1 0 1 0
Normal 0 0 0 0 0
Figure 6: Example Test Mode Select and Enable Arbitration Truth Tables
For further information, you may also refer to the ABC Control Priority Table in
Analog Block Circuitry (ABC) Engineering Document Template
[cad_icsa_00029]; the ABC Control Priority Table defines the test modes useful
for a top-level usage where more combinations are possible from the logic.

3.5 Related Application Notes
A brief description and location of all application notes and user guides required
to perform DFT and ATPG on an ABC Digital Core can be found in Table 2.
Table 2: Location of DFT and ATPG application notes.

General Block DFT and ATPG ICDC component [cad_dd_00446]
Application Note
Provides a step by step user manual for scan and test insertion, and production test
pattern generation and verification.
TSB Scan Insertion Application Note ICDC component [cad_dd_00796]
Provides details of scan insertion procedures at TSB level.
ABC DFT Home Page ICDC component [cad_dd_00444]
Provides links to the currently supported versions of the ABC DFT flow at PMC.

4 ABC/MABC DIGITAL DFT AND ATPG FLOW
This section provides details of automatic scan insertion and ATPG for the digital
part of ABCs.
4.1 ABC/MABC Test Insertion and ATPG Flow
As shown in Figure 7, the scanned ABC Digital Core contains a predetermined

number of scan chains and related scan pins. All scan pins should exist in the
RTL design of the ABC Digital Core. This includes a dedicated scan bus
(SCAN_IN[n-1:0] & SCAN_OUT[n-1:0]), SCAN_EN, SCANB, FLL_CLK, and
TEST_CLK reserved for scan insertion. These pins are left dangling in the RTL
description of the ABC Digital Core. SCANB may be used by test logic in the pre-
scan netlist. FLL_CLK is used if functional lockup latches are required to be
inserted in the post-scan netlist. TEST_CLK is used if the ABC Digital Core
contains internally generated clocks.
ABC Digital Core
Functional Outputs
Functional Inputs
...
...
...
...
SCAN_OUT[0]
SCAN_IN[0]
SCAN_OUT[1]
SCAN_IN[1]
SCAN_OUT[n-1]
SCAN_IN[n-1]
SCAN_EN
TEST_CLK
SCANB
FLL_CLK
Figure 7: Simplified view of the ABCs Digital Core.

Figure 8 depicts a simplified flow of scan insertion. The next step is to insert scan and
test logic in the gate-level netlist following the rules and procedures detailed in this
document.
After logic synthesis is finished the script head_tail_id.pt is run with pt_shell using
pmxx_xx_xx_core_scan_info.tcl to identify head and tail registers required to guard
band scan chains. At the same time, a preview of all scan chains and required test logic
is generated. Next, the insert_scan.dctcl script is run with dc_shell-t to insert scan
chains and all required test logic using DFTAdvisor following the rules detailed in this
document. The resulting netlist is called pmxx_xx_xx_core_prelockup.v.
After test synthesis is completed, a script called pmxx_xx_xx_core_lockup.pt is used

with pt_shell to create a report file (pt_timing_report.rpt) that contains information about
the existing timing paths between different functional clock domains. The script
insert_functional_ll.prl uses the generated timing report file and DFTAdvisor to
automatically insert lockup latches in the functional cross-clock domain paths. For more
details about lockup latch insertion procedure, please refer to the Functional Lockup
Latch Insertion Application Note. You can skip the lockup latch identification and insertion
step if you have already inserted lockup latches in your RTL design. The resulting
netlist is called pmxx_xx_xx_core_postscan.v.
The post-scan design is then optimized and checked for static timing violations. The
final static timing analysis should be done with back-annotated physical data to check
for hold time violation in scan and functional paths and setup time violations in functional
paths. Final gate level netlist of the Logic Core are called pmxx_xx_xx_gates.v and
pmxx_xx_xx_gates.vhd.
After finishing the test synthesis procedure, FastScan is used to automatically generate
scan test patterns for the final digital block. As shown in Figure 9 serial test patterns are
generated in WGL format and parallel test patterns are generated in Verilog format.
Parallel Verilog test patterns are generated only for test pattern verification and
mismatch analysis and are fully simulated. The run time of parallel Verilog test pattern
simulation is extremely short as it directly loads the scan memory elements with the
necessary test pattern values and reads their content in parallel rather than spending
simulation cycles with loading and unloading the scan chain. Also, it is very convenient
for ATPG mismatch debugging. Note that parallel vector simulation does not verify the
scan data load and result unload operations.

RTL Design of Digital Core

( pmxx_xx_xx.vhd )
Logic Synthesis pmxx_xx_xx_core.dc

DesignCompiler write_pmxx_xx_xx_core_prescan.dctcl
gate VHDL/ pmxx_xx_xx_core_prescan.v
Verlilog
Test Synthesis insert_scan.dctcl

DFTAdvisor, PrimeTime & head_tail_id.pt
DesignCompiler pmxx_xx_xx_core_scan_info.tcl
pmxx_xx_xx_core_prelockup.v
Lockup Latch
Identification & Insertion insert_functional_ll.prl
pmxx_xx_xx_core_lockup.pt
DFTAdvisor& PimeTime
pmxx_xx_xx_core_postscan.v
insert_functional_ll.log
Logic Reoptimization & reoptim_pmxx_xx_xx_core.dctcl

Static Timing Analysis pmxx_xx_xx_atpg_info.tcl
DesignCompiler & PrimeTime write_pmxx_xx_xx_atpg.dctcl
pmxx_xx_xx_core_gates.db
pmxx_xx_xx_atpg.dof
No Design Note: Static timing analysis is done

Specifications on the pre- and post-scan netlist
OK? considering setup time violations
for functional paths and hold time
Yes violations for functional and scan
paths
Post-Scan Design
Archived
pmxx_xx_xx_gates.v
pmxx_xx_xx_gates.vhd
Figure 8: ABCs Digital Core test insertion flow. For simplicity only VHDL file names are
presented.
The serial WGL file contains all test patterns required for scan testing in production. It is
recommended to fully simulate the WGL pattern file as well. WGL patterns should be
simulated with back-annotated physical data from layout. WGL patterns are simulated
by running the script do_gen_wgl2vhdl2vcd.prl that translates WGL patterns to
VHDL/Verilog using VTRAN and simulates them using NCSim. If there is no simulation
mismatch, the test vectors in WGL format are archived for production testing.

Logic Core Post-Scan Netlist

(pmxx_xx_xx_gates.v)
gate Verilog
ATPG
pmxx_xx_xx_atpg.dof
FastScan
pmxx_xx_xx_scan.wgl pmxx_xx_xx_scan.v
WGL to VHDL Complete Parallel

do_gen_wgl2vhdl2vcd.prl Conversion Vector Simulation
VTRAN NCSim
Full or Partial Serial

Vector Simulation
NCSim
Note: WGL patterns are

partially simulated if the
full WGL simulation run
time is prohibitive. WGL Vector No
Simulation
patterns are simulated OK?
using pre- and post-
layout netlists. Yes
WGL Test Patterns

Archived
pmxx_xx_xx_scan.wgl
Figure 9: ABCs Digital Core scan vector generation and verification flow.
If the serial WGL simulation run time is prohibitive, only a subset of the WGL
serial patterns could be simulated to ensure the integrity of scan chains and the
WGL file itself.
4.2 DFT Rules
Testability should be considered early in the design cycle and DFT rules should
be considered during RTL development. Any violation of the DFT rules will result
in the degradation of fault coverage. To avoid re-synthesis, the designer has to
assume that all flip-flops initially used are going to be scanned. Hence, the
timing, load, and area attributes have to be set to the appropriate values
corresponding to scan equivalent flip-flops. Such an approach will have
pessimistic constraints but in the end will ensure that the logic will meet required
timing constraints after scan insertion.

The following rules should be enforced to make sure that the ABC Digital Core
can be scanned and is complaint with PMC top-level and TSB level DFT strategy.
Most of commercial DFT tools can perform rule compliance checking at gate
level. Depending on the test tool used, some of these rule violations can be fixed
automatically. However, it is important that the designer be aware of the changes
occurring in his/her design.
It is strongly recommended that the designer ensure that his/her design is

testable by inserting all required test logic at RTL. Ideally, the DFT tool should
only chain flops together to create scan chains.
Rule 1: Random logic should be full-scanned
PMC has adopted full-scan test methodology. Therefore, Random logic is full-
scanned. The number of scan chains is equal to the width of the ECBI bus.
Rule 2: All clocks should be directly controllable at top-level and should not
drive combinational logic
Flip-flops controlled by internally generated clocks are not scanned and therefore
cannot be properly controlled by ATPG tools. These include frequency dividers,
PLLs, pulse generators, gated clocks and asynchronous logic. In some designs,
internally generated clocks cannot be avoided. In scan test mode, these flip-
flops should become directly controllable at top-level. Note that delayed clocks
are considered as being internally generated and should be made controllable
from the top-level.
As shown in Figure 10, we should multiplex the internally generated clock with a
dedicated test clock called TEST_CLK. TEST_CLK should be added as a
primary input to the ABC Digital Core. Designer must ensure that a suitable
balanced mux that does not introduce duty cycle distortion and is immune to
clock feed-through is inserted. The best location to insert the mux is right after
the clock is regenerated. This ensures that the inserted mux is always located at
the root of the clock tree dedicated to the logic driven by the generated clock.
Another advantage of multiplexing internally generated clocks at source is that
every destination block does not need to implement its own mux as the mux is
already implemented at source. Please note that, the bypass mechanism is often
embedded into PLLs and DLLs.
To insure that clock skew does not cause any hold-time violations during scan
testing, physical designer must use the TEST_CLK at the top-level of the ABC
Digital Core as the root of the clock tree during the final gated-clock tree
synthesis to ensure that all sub-clock trees are balanced. In the example
illustrated in Figure 11(a), the TEST_CLK should be used as the root of the clock
tree and therefore all flip-flops controlled by the TEST_CLK will be on the same

clock tree during scan test mode. The end goal is to ensure that there is hold
time violation between flip-flops driven by TEST_CLK.
Gated clock tree synthesis tool only fixes transition problems after the mux and
the path from the generated clock and the mux may remain susceptible to cross
talk depending on its transition time. As shown in Figure 11(a), it is important to
ensure that internally generated clocks do not go through any combinational logic
before reaching the mux. Figure 11(b) depicts a circuit violating this rule.
The mux should be inserted manually at the RTL. DFTAdvisor is set up not to fix
this problem. It is important to note that if the mux is not inserted manually,
DFTAdvisor will not scan flip-flops controlled by the generated clock.
Here is a summary of points to consider when dealing with internally generated

clocks:
Internally generated clocks should not go through any combinational logic

Internally generated clocks should be multiplexed with the TEST_CLK
available as an ABC Digital Core primary input
The mux should be inserted at RTL
The mux should be controlled with SCANB signal
The mux should be immune to clock feed-through and duty cycle distortion
The mux should be inserted at source where the clock is generated
The TEST_CLK must be used as the source of the clock tree during the final
gated clock tree synthesis process to eliminate hold time violations in
TEST_CLK domain in test mode
The TEST_CLK should not be used for any other purposes
In some cases such as clock sampling circuitry driving combinational circuits

using a clock is inevitable. As shown in Figure 12(b) to make this kind of circuits
testable a mux is used to drive the combinational circuit from a control point in
scan test mode. Therefore, the combinational logic becomes controllable and the
clock does not propagate through the combinational logic.

D Q
ref_clk Clock clk1
...
Generator
D Q
D Q
ref_clk Clock clk1
...
1
Generator 0
D Q
test_clk
scanb
Figure 10: Handling internally generated clocks. SCANB is an active low top-
level scan test mode signal. The mux is often embedded into PLLs and DLLs.
D Q
clk1
D Q 1
...
D Q
test_clk
scanb
(a)
D Q
clk1
D Q Logic 1
...
D Q
test_clk
scanb
(b)
Figure 11: Internally generated clock should not go through any combinational
logic before reaching the multiplexer. TEST_CLK is a dedicated top-level test
clock.

Combinational
Clk
Logic
D Q
(a)
Clk 1
0
Combinational
Logic
D Q
Control
Point scanb
(b)
Figure 12: Clocks should not go through any combinational logic.
Rule 3: Gated clocks should be directly controllable at top-level

Gated clocks are sometimes used for power reduction, or as a design style to
reduce logic. Similar to internally generated clocks, gated clocks can make it
impossible to perform a reliable scan testing. Whether possible its preferable to
avoid gating clocks. If a gated clock is used as a design style as shown in Figure
13(a), the alternative solution presented in Figure 13(b) must be used to make
the design testable. Note that the latch may or may not exist as a part of the
gated clock technique. Faults associated to enable signal may require
observation trees to increase the fault coverage.
In the case where a gated clock is not used to minimize power dissipation, the
technique illustrated in Figure 13(c) is recommended. This technique does not
require any modifications to make the design testable but consumes more power.

Obervation Tree
D Q D Q
en en
D Q
en
scanb D Q
en
sys_clk sys_clk
(a) (b)
D Q
0
D 1
(c)
en
sys_clk
Figure 13: Handling gated clocks.
Rule 4: All set/reset signals should be directly controllable at top-level

Sequential elements driven by uncontrollable set or reset signals are considered
as untestable. It includes software set/reset, synchronized set/rest, and
sequential controlled set/reset cases. This implies that certain pattern
combinations will not be able to be shifted in during scan or set/rest pins cannot
be tested during scan.
D Q
sys_clk
(b)
D Q 1
D Q 0
sys_clk
rstb scanb
D Q D Q
sys_clk
(a) (c)
D Q
scanb
Figure 14: Handling sequential controlled set and reset.
It is best to avoid this design style. However, in the cases where there are
controlled asynchronous set/reset signals, they can be disabled during test mode

as shown in Figure 14. The preferred solution is the technique illustrated in

Figure 14(b) where rstb is the designated top-level reset signal. Designer must
ensure that a suitable balanced mux that is immune to clock feed-through and
does not cause duty cycle distortion is inserted. Please note that internally
generated set/reset signals should not pass through any combinational circuitry.
DFTAdvisor automatically fixes this violation.
Rule 5: Multiple clock domains should be merged during scan
All clocks for a given ABC Digital Core will be pin equivalent and toggled
simultaneously during production scan testing. This rule makes design for test
reuse regardless of the device under test top-level clock strategy. Exceptions to
this rule are clocks that are always available as top-level primary I/Os such as
ecbi_wrb and MPIF clocks. ecbi_wrb is used as a scan test clock.
Rule 6: Lockup latches should be used to prevent race condition
Lockup latches should be inserted in scan chains and functional paths to prevent
race conditions during shift and capture cycles. DFTAdvisor automatically inserts
lockup latches while stitching scan chains to prevent race condition during scan
shift operation. However, no current commercial DFT tool inserts lockup latches
in functional cross-clock domain paths. Inserting lockup latches in functional
cross-clock domain paths provides the ability to simultaneously toggle all clock
domains without loosing any test coverage. pmxx_xx_xx_core_lockup.pt is used
with pt_shell to create a report file (pt_timing_report.rpt) that contains information
about the existing timing paths between different functional clock domains.
insert_functional_ll.prl script is then used to automatically insert lockup latches in
functional cross-clock domain paths.
A dedicated clock called FLL_CLK is used to clock lockup latches in functional
cross-clock domain paths. FLL_CLK is available as a Logic Core input pin and is
only used to control functional lockup latches. Figure 15 illustrate an example
where s_clck and d_clk are skewed due to different clock tree latencies, but the
lockup latch controlled by FLL_CLK prevents a race in the cross-clock domain
path. Therefore, s_clck and d_clk can be toggled at the same time if the lockup
latch is inserted. As shown in Figure 15, an additional capture cycle is added to
each pattern.

D Q D Q D Q
En
s_clk fll_clk d_clk
scan_en
s_clk
fll_clk
d_clk
shift capture shift
Figure 15: Lockup latch concept for functional cross-clock domain paths.
Rule 7: Latches should become transparent in scan mode

Latches cannot be scanned unless they are converted into flip-flops. This results
in an extremely large area overhead. If the latches are part of memory it might
be best to model all the latches together as a memory. However this would imply
that special manual patterns will be needed for the latches. Using a memory
model would reduce the difficulty in generating patterns for faults near the
latches. A more general solution is to make the latches transparent during test
mode (see Figure 16). This takes care of the problem of propagating fault effects
through the latches, but the enable faults on the latches may require observation
trees to increase the fault coverage. This fix may be applied automatically using
scan insertion tools.
D Q Obervation Tree
D Q
en En en
scanb En
Figure 16: Making Latches transparent in test mode.

Rule 8: Sub-chains should be guard banded
All sub-chains should start with a positive-edge flip-flop and end with a positive
edge flip-flop followed by an active low lockup latch. This will facilitate sub-chain
stitching during hierarchical scan insertion. Sub-chains are stitched together and
should not be mixed with individual scan cells in bottom-up hierarchical scan
insertion process. Scan insertion scripts provided as a part of the DFT flow
ensures scan chain guard banding. It will add additional positive edge flip-flops
to violating scan chains to make them compliant to this rule.
Rule 9: ABCs should be in a safe state during scan testing mode
The ECBI block controls ABCs functional configurations and analog test modes
using ECBI registers. These registers are scanned and therefore can have
random logic values during scan testing mode. All ABC digital input signals
should be in a safe state when the chip is in scan test mode. SCANB should be
used to force input digital signals to a safe state during scan test mode, if they do
have a safe state.
Rule 10: Make RAMs transparent during scan

Apart from the memory itself, logic preceding and following the memories should
be testable. The most efficient way to do this is to propagate values through the
memories during testing. Two different practical implementations are possible:
Bypass the memory using a mux to connect Din to Dout. XOR observation
trees are used to make memory address bus observable. This technique is
implemented in the PMC RAM BIST solution. The path from Din to Dout may
be broken using additional flip-flops to avoid the creation of false paths and
provide control and observe points.
Add a special test mode that would write to a known address and read from
the same address. This would make the memory appear as simple buffers to
the rest of the design in the scan mode.
Rule 11: Analog I/Os transporting a dynamic signal should have a JTAG cell
In many PMC chips high-speed differential I/Os constitute a significant portion of

the total I/Os and therefore cannot be omitted from the boundary scan register in
JTAG mode. Transmitter or receiver ABCs are typical examples that should have
a JTAG cell. As shown Figure 17, the JTAG cell is not directly placed in the
signal path so that the performance is not affected and is normally inserted in the
wrapper that is placed around the ABC. The JTAG cell is not differential and the

ABC should map the differential input to a single ended signal for the JTAG input
cell or map the single ended value of the JTAG output cell to a differential output
signal.
Note that analog I/Os that do not transport an active signal such as pads
connected to reference inputs, external passive components and transformers
are excluded from this rule and do not need to have a JTAG cell.
When the JTAG_EXTESTB signal is active, the ABC should be in the operation
mode so that the received input value by the receiver is transferred to RX_JTAG
and the TX_JTAG value is transferred through the transmitter. The
JTAG_EXTESTB signal has priority over IDDQ, zATMSBy, zDTMSBy and all
other digital and analog inputs.
When the device goes into JTAG mode, input pads could have arbitrary data. If
these pads control clock frequency of an oscillator or a CSU in an ABC that
drives digital circuitry, the clock frequency becomes uncontrollable. If during the
JTAG mode the clock frequency exceeds the nominal functional specification, we
may experience excessive power dissipation. The JTAG_EXTESTB signal should
be used to force susceptible ABC digital signals into a safe state in JTAG mode
to ensure that clock signals do not go wild in the JTAG mode. Note that most of
ABC digital input signals may not require a safe state and do not need to be
forced to a specific value by JTAG_EXTESTB.
In SerDes applications JTAG ports are used in conjunction with:
- Transmitter outputs: active when JTAG_EXTESTB=JTAG_ACTIVEB=0
- Receiver inputs: AC-JTAG active when JTAG_EXTESTB=X;JTAG_ACTIVEB=0
- refclk receiver input: DC-JTAG, active when

JTAG_EXTESTB=X;JTAG_ACTIVEB=0; used only by PE
Not that any circuitry that is disabled in JTAG_EXTESTB mode should be

confirmed to have no impact on the proper operation of the JTAG transmitter. For
example, the reference current sources for a transmitter could be outside the txrx
slice and the designer of that slice may not immediately think of the JTAG
implications of shutting down that reference current.
ABC designer is responsible to deliver a HDL model that properly describes the
JTAG behavior of the ABC.

S
off-chip
Functional
Digital Output
TX
...
BSC
Functional
RX
Digital Input
BSC
Figure 17: Placement of boundary scan cells (BSCs) for ABCs. The mux is
normally inside the TX.
Rule 12: Make sure IDDQ level is as small as the leakage current
IDDQ is the quiescent current on the digital power supply of a chip after the circuit
has stabilized. Bridging faults, stuck-at faults, and some stuck-open faults cause
a great increase in this current. Many of these faults would not be detected with
stuck-at test vectors. Therefore, measuring this current, and using a threshold to
determine defective chips, can greatly increase the quality of chips being shipped
to customers. There are certain restrictions on designs to make the use of IDDQ
possible. For IDDQ testing to be feasible, the normal value for IDDQ should be
much lower than the IDDQ of a circuit with a defect present. Typical IDDQ values
depend on the design, and can vary from a few nano-amps to few milli-amps.
Some of the issues and how they should be handled are listed below.
Floating Input Nodes: Floating input nodes are nodes that are not driven to
any value. Such nodes are likely to drift in voltage and cause other gates to
be turned at least partially on. This would cause the IDDQ current in the
normal circuit to be very high. Note that if all tri-state gates driving a net go to
their high-impedance state, then the net becomes a floating note.
Internal Bus Contention: If a bus is driven by two sources and each source
drives to a different value, then the IDDQ current would increase dramatically.
This situation should be avoided in the design by ensuring that only one
source drives the bus at any given time.
Pull-ups and Pull-downs: Resistance pull-ups and pull-downs may create a
permanent path from Vdd to Gnd through the resistor and result in a
considerable IDDQ current. They should be switched off when the chip-level
IDDQ enable signal (IDDQ) is active and the affected circuitry is required to be
IDDQ testable.

Analog Circuits Sharing Digital Power Rails: Analog circuits can have very
high currents, invalidating the use of IDDQ testing. All currents from the digital
rail of analog circuits should be switched-off when the chip-level IDDQ enable
signal (IDDQ) is active. The mechanism for shutting off must have a short
settling time (less than 1 ms). Also, the shut off mechanism must not
increase IDDQ inadvertently.
Analog Circuits with Dedicated Power Pads: Analog circuits that have
dedicated power rails and pads do not need to be switched-off during IDDQ
testing. ABC digital output pins driving internal digital circuitry should not
toggle in IDDQ mode.
PLLs and Embedded Memories: Turn off PLLs, oscillators, internal clock
generators and embedded memories if they share the same power rail with
the digital core. This is usually accomplished via the IDDQ signal. Turning off
a PLL can take hundreds of mil-seconds to restart, which can have a big
impact on the test time. For example, gating off the input to a PLL may still
allow it to "freewheel" for a very long time. The turn off mechanism should
have a short settling time.
I/O Buffers: Output buffers tend to have large current, which reduces the
sensitivity of IDDQ testing. By having separate VDD signals for the pads and the
Chip Core, lower IDDQ threshold levels can be used for the Chip Core,
increasing the number of faults detected. This may be difficult to do in a
FlipChip but can easily be done in a WireBond package. To make I/Os IDDQ
testable, all pull-up and pull-down resistors should be disconnected in IDDQ
mode.
Dynamic Logic: Dynamic logic is functionally equivalent to "floating nodes"
and is therefore problematic for IDDQ testing if they do not have dedicated
power rails and pins. They should be connected to an independent power rail
so as not to corrupt measurements on other digital rails.
JTAG: ABCs interfacing analog I/Os transporting a dynamic signal require to
support a special kind of boundary scan cell that requires the ABC to be in
functional mode to pass JTAG signal through the ABC. As a result,
JTAG_EXTESTB has priority over IDDQ enable (IDDQ), scan test mode
(SCANB) signals and all other input signals. Therefore, other signals should
not be capable of changing the ABC status when it is in JTAG mode.
Rule 13: All scanned logic should exceed 95% test coverage
Current PMC test coverage limit is set to 95% for stuck-at faults. This test
coverage target should be achieved with no more than 3 scan test cycle per gate.
A test cycle is one test clock cycle during scan test mode and should not be
confused with a test pattern that is a full scan load. The best in class goal is to
achieve 97% stuck-at fault coverage with one scan test vector per gate. Test

points are inserted only if ATPG did not achieve the target fault coverage after
generating a predetermined number of patterns set by the total test pattern count.
Test points could also be used if the ATPG run time is prohibitive.
4.3 Test Synthesis Procedure
Test synthesis includes scan and test logic insertion procedure. After
synthesizing the Logic Core, scan and test logic is inserted and the final post-
scan netlist is optimized.
4.3.1 Scan Insertion Strategy for ABCs
As mentioned before the RTL design of the ABC Digital Core should contain a
dedicated scan bus (SCAN_IN[n-1:0] & SCAN_OUT[n-1:0]), SCANB, SCAN_EN,
FLL_CLK, and TEST_CLK reserved for scan insertion. These pins are left
dangling in the RTL description of the ABC Digital Core.
Scan insertion is performed after the final Logic Core shown in Figure 1 is
designed and fully synthesized. The total number of scan chains should match
the ECBI width that is typically 16 bit wide. Scan insertion is done in one pass
using DFTAdvisor and test logic is inserted using DFTAdvisor and
DesignCompiler. Here is a summary of scan insertion strategy:
The number of scan chains should not exceed the ECBI bus width (16 bit)
Each scan chain may mix flip-flops with different clocks and different edges
Each scan chain starts with a positive edge flip-flop and ends with an active
low lockup latch
All clocks are toggled at the same time during scan testing. Exceptions to this
are clocks that will always be available at top-level regardless of the device
that encompass the ABC.
If the ABC is wrapped by a TSB, its scan chains are declared as sub-chains
inside the TSB and the TSB is scanned following the rules and guidelines
provided in the document PMC-2001526 entitled TSB Design for Testability
Rules
4.3.2 Scan Insertion Strategy for MABCs
An MABC is a collection of reusable ABCs to perform a specific function that

cannot be accomplished by a single existing ABC. To meet device test coverage

requirement, the digital section of MABCs should be full scanned. All scripts and
template referred to in this document are designed to be reused for MABCs.
Here are the steps to follow in order to scan an MABC:
Ensure that all ABCs are scanned following the guidelines and rules provided
in this document
Scan the MABC by declaring ABCs scan chains as sub-chains using the
scripts provided in this document
The total number of scan chains at MABC level is equal to or less than the
ECBI bus width
If the MABC is wrapped by a TSB at top-level, MABC scan chains are
declared as sub-chains inside the TSB and the TSB is scanned following the
rules and guidelines provided in the document PMC-2001526 entitled TSB
Design for Testability Rules.
4.3.3 Scan Insertion and ATPG Users manual
Users manual provides a detailed step by step guide for scan insertion and
production test pattern generation and verification. It also provides links to
scripts, application notes and templates required in order to apply the flow. The
General Block DFT and ATPG Application Note is found on the ICDC as a
component.

5 ABC/MABC ANALOG DFT FLOW
For digital circuits Boundary-Scan, Scan, Test Access Register (TAR) and mux
isolation are widely accepted and practiced. Unfortunately, there is not an
industry standard that defines mixed-signal DFT techniques. Recently, IEEE
1149.4 has been approved as an IEEE standard for analog test access at board
and chip level but has not been adopted by the industry yet. Having proven and
standard DFT techniques for mixed-signal circuits results in a greater design and
test efficiency.
5.1 Main Analog DFT Goals
Here are main motivations behind applying analog and mixed-signal DFT
techniques on chip.
5.1.1 Design Debugging
DFT techniques tend to simplify and shorten the validation and debugging
process by providing capabilities such as higher controllability and accessibility,
fault location and fault diagnosis. These capabilities will reduce time to market by
reducing the number of design revisions. DFT techniques can also minimize the
need for wafer probing by providing direct access to critical internal nodes.
5.1.2 Test Coverage
Each mixed-signal core should be able to achieve at least 95% fault coverage
using the stuck-at-0 and stuck-at-1 fault models for the digital part and short and
open fault model for the analog part. Currently, we do not have any tool that can
fault grade analog circuits. Therefore, adopted analog test and DFT techniques
should provide the ability to test key parameters of the mixed-signal core under
test. Its designer responsibility to identify key parameters that should be tested
in production.
5.1.3 Test Time
Test time should be reduced to a reasonable level by providing techniques such

as structural testing, parallel testing and correlation-based testing.

5.1.4 ATE Adaptation
DFT should be able to provide the ability to test high-performance mixed-signal

cores on existing ATEs that otherwise are not capable of testing such cores. This
includes problems associated with precision, accuracy, speed, number of analog
channels and digitizers, and pin-count. Some DFT techniques make it possible
to test a mixed-signal device on a digital tester.
5.2 Mixed-Signal DFT Methodology

In this section the most important DFT techniques that can be used at ABC and
MABC level to improve the testability of mixed-signal circuits are briefly covered.
The following sections give an example on how different analog DFT techniques
can be used to increase testability.
5.2.1 Analog Test Bus

Each ABC can have an Analog Test Stimulus Bus (ATB1) and Analog Test Output
Bus (ATB2). ATB1 is used to force voltages and currents to test-points inside that
particular ABC circuitry. ATB2 is used to measure or observe analog signals at
critical nets inside the ABC.
If differential signals need to be applied or measured, ATB1 and ATB2 can be
used as a differential bus to apply test signals to or observe test results from
internal differential nets. Alternatively, Inverse Analog Test Bus (ATBN1 &
ATBN2) can be used to simultaneously apply test signals to and observe test
results from differential nets.
Analog test selector bus (zATINy) determines which internal nets are connected
to ATB1 (ATBN1) and ATB2 (ATBN2). zATMSB signal acts as the ABCs top-level
analog test mode select signal. ATB1 (ATBN1) and ATB2 (ATBN2) from different
ABCs will be connected together and go to the devices Analog Test Access Port
(ATAP) which is composed of AT1 and AT2 in case of a two-port ATAP and AT1,
ATN1, AT2 and ATN2 in case of a four-port ATAP.
5.2.1.1 Analog Test Output Bus
Analog Test Output Bus is the most popular analog DFT technique. It is used as
an output bus to improve observability during test and debug. As shown in
Figure 18(a), it provides access to critical points to probe out internal signals.
ATB2 acts as a virtual probe to observe internal points and reduces the need for
wafer probing and problems associated with it. If the target net is differential,
ATB1 can be used in conjunction with ATB2 to observe differential signals.

Alternatively, if a four-port ATAP is permitted, ATBN2 can be used in conjunction

with ATB2 to observe differential signals.
ECBI normal registers provide the zATINy bus that is decoded inside the ABC to
provide control signals required for internal test switches. The Test Arbiter logic
block is that from Section 3.4.
Some internal nodes are buffered before being sampled. The buffer is necessary
if the internal probed node is not able to drive the test bus or if the parasitic
loading of the bus affects the performance of the CUT during the test mode.
Figure 18(b) represents the implementation of analog switches used to connect
or disconnect the ATB2. A T type analog switch is used to minimize the impact
of signal feed-through and charge injection. The leakage current of the switch
should be considered if you probe high-impedance nets.
ATMSB Test Arbitrator ABC

ATMSB_OUT
ATB2
ATINx Test Mode
...
Decoder
s s s
Analog Analog
... Analog
Buffer
BB #1 BB #2 BB #N
(a)
(b)
Figure 18: Schematic block diagram of the Analog Test Bus used to observe
internal signals of an ABC (a) and the schematic of analog test switches (b).
As shown in Figure 19, ATB2s from different ABCs are connected together to
form the top-level ATB2 bus.

Analog Test Output Bus (ATB2)
ABC #1 ABC #2 ... ABC #M
Figure 19: Connection of ATB2s from different ABCs to top-level ATB2.
(a)
Figure 20: A bad example for monitoring VDD and VSS values at different points
of the device.
Probing signals at the right layout location could be difficult to verify if special
considerations are not taken into account. Figure 20(a) illustrates a bad example
of monitoring AVS signal of block1. Since AVS is a global signal, LVS cannot be
used to verify the correct probing and the ABC designer has to visually inspect
the layout to ensure the correct connection of the probe point. Figure 20(b)
demonstrates a good practice for monitoring AVS at a desired location inside

block 2. A small metal resistor is used to create a unique net name

(AVS_SENSE) from the global net that should be probed. AVS_SENSE
becomes an output of the block2 and is probed using the analog test bus as
TESTPOINT3. In this case, LVS can successfully identify the AVS_SENSE net
name and make sure that it is probed using the analog test bus.
(b)
Figure 20: A good practice for monitoring VDD and VSS values at different points
of the device.
For simplicity, only voltage sampling is illustrated in previous figures. However, in

practice sampling internal current signals through a copy current mirror is very
popular. Figure 21 shows an example of observing current at internal nodes. P1
and N1 transistors are part of the analog circuit under test and P11 and N11 are
added to enhance testability. They provide the ability to measure the current
flowing through P1 and P2. I1 and I2 are copied from I1 and I2 using a current
mirror and measured through the ATB2 bus.

VDD
CUT
P1 P11
I1 I'1
s ATINy
Analog
Circuitry ATB2
s
I2 I'2
N1 N11
VSS
Figure 21: Measuring current level of internal nodes. P1 and N1 are part of the
analog circuit under test. I1 and I2 are measured through ATB2.
Note that transmission gates used for ATB purposes should be of a specific type
(e.g. lib90n_D analog_test category, which contains cells such as
atb_only_switch) so that Mixed-Signal Verification can automatically verify them.
5.2.1.2 Analog Test Stimulus Bus
Analog Test Stimulus Bus is a powerful analog DFT approach that provides the
ability to apply test signals to internal analog and mixed-signal blocks. If the
target input is differential, ATB2 can be used in conjunction with ATB1 to apply
differential signals. Alternatively, if a four-port ATAP is permitted, ATBN1 can be
used in conjunction with ATB1 to apply differential signals.
Related analog multiplexers are used to apply test signals to internal nodes.
They are controlled using the ECBI analog test registers through the zATINy bus.
In order to minimize the performance degradation, proper test points should be
selected to insert the multiplexers. Switched capacitor, switched current and
already multiplexed inputs are examples where ATB1 can be inserted without any
significant performance penalty.
For simplicity, only applying voltage stimulus is illustrated in Figure 22(a).

Current stimulus can also be injected in selected test points as a way to test or
debug analog and mixed-signal circuits. A practical implementation of
multiplexers used to apply test stimulus is shown in Figure 22(b). For all details
about the implementation of the Test Arbiter, refer to and Figure 6.
Figure 23 illustrates how ATB1s from different ABCs are connected together to
form the top-level ATB1 bus.

Analog BB #1 0
1
Analog
BB #2
0
1
Analog
BB #3
... 0
1
Analog
BB #N
s s s
Test Mode
ATINx
...
Decoder
ATMSB_OUT
Analog Test Bus
ATMSB Test Arbitrator
ABC
ATB1
(a)
Signal Input
0
Test Input 1
s
(b)
Figure 22: Schematic block diagram of the Analog Test Bus applied to an analog
core as a stimulus bus (a) and the implementation of multiplexer (b).
ABC #1 ABC #2 ... ABC #M
Analog Test Input Bus (ATB1)
Figure 23: Connection of ATB1s from individual ABCs to top-level ATB1.
5.2.1.3 Analog Test Bus (ATBx) Used as Stimulus and Output Bus
ATB1 and ATB2 can be used together to form an Analog Test Bus (ATBx) that is
used for observing and applying analog signals (Figure 24). All associated
switches and multiplexers are controlled using configuration registers located
inside ECBI through the zATINy bus. Switches and multiplexers implemented as
shown in Figure 18(b) and Figure 22(b) respectively.

As an example consider testing analog BB #3. To test this block, ATB1 is used to
apply a test input to this block through its multiplexer. ATB2 is used to observe
the test response through the switch. Other switches and multiplexers are
properly set in order to prevent conflicting with this test.
ATB2 ...
s s s
Analog
BB #1
0
1
Analog
BB #2
0
1
Analog
BB #3
... 0
1
Analog
BB #N
s s s
...
Test Mode
ATINy Decoder
ATMSB_OUT

ATB1 ABC
Figure 24: Schematic block diagram of the Analog Test Bus concept combining
stimulus and output test buses.
Figure 25 illustrates how a two-pin analog test bus can be used to measure and
apply differential signals. The decoding logic should activate each test
individually to ensure that bus contention does not occur.
ATB2
1
Analog Analog 0 Analog
VIN VOUT
BB #1 BB #2 0 BB #3
1
s0
Test Mode s1
ATINx Decoder s2
ATMSB_OUT

ATB1 ABC
Figure 25: Schematic block diagram of the two-pin Analog Test Bus concept used
to measure and apply differential signals.

5.2.2 Connecting the Analog Test Bus at the Top-Level

It is recommended to design ABCs to be compatible with the two-port Analog Test
Access Port (ATAP) that uses ATB1 and ATB2 as test bus. The device should
have two dedicated analog pins called AT1 and AT2. AT1 is a test input pin to
access ATB1 and AT2 is a test output pin to access ATB2. However, in some
devices it may be difficult to dedicate two pins to the ATAP. Therefore, to enable
the reuse of the ABC in different devices, the two-pin internal analog test bus
should also be able to interface with a one pin ATAP (AT1). To accomplish this
goal, the zATINy/zDTINy decoder located inside the ABC should also decode test
modes where the test output (ATB2) and test stimulus buses (ATB1) are used
individually. Therefore, if an ABC has some probability of being reused in
extremely low-pin count devices, it is safe to design its zATINy/zDTINy decoder
to enable using one-port and two-port ATAPs.
The four-port version (ATB1, ATBN1, ATB2, and ATBN2) should be used only if
both differential stimulus and signal measurement are required and measurement
and observation need to be performed simultaneously. Again, to enable the
reuse of the ABC in different devices, the four-port internal analog test bus
should also be able to interface with one-port and two-port ATAPs. To
accomplish this goal, the zATINy/zDTINy decoder located inside the ABC should
also decode all possible test modes where only one or two test buses are used.
As a result the ABC could be plugged to one-port, two-port or four-port ATAPs at
the top-level without having any bus contentions or loosing significant numbers of
test modes.
Figure 26 demonstrates the connection of ATB1 and ATB2 to top-level ATAP pins
(AT1 & AT2). Note that ATB1 and ATB2 are bidirectional buses and therefore if
ATN1 and ATN2 cannot be added due to pin count limitation, AT1 and AT2 can be
used for differential signal measurement or applying differential analog signals.
In case of extreme pin count limitation, only one pad can be used to access both
ATB1 and ATB2. ABCs address decoder should provision all possibilities to
make sure that the ABC can be properly tested using different ATAPs without
resulting in any bus contention or conflict.
As shown in Figure 27, AT1 is used for measuring analog signals or applying test
stimulus and measuring the test response of functional analog outputs.
Although, ABCs are expected to support one-port ATAP, but to be conservative a
switch is used to ensure that both ATB1 and ATB2 buses are not connected to
the top-level pin AT1 at the same time. ATB1/2 and ATMSB signal controlling the
pads driving ATB1/ATB2 and ATBN1/ATBN2 are normally generated from a top-
level register.

ATB2
ATB2
AT2 PAD
Device pin
ABC #1 ABC #2 ABC #M
AT1 PAD
ATB1
ATB1
ATMSB
(a)
PAD S
PAD
(b)
Figure 26: Schematic block diagram of the Analog Test Bus concept and its
connection to the top-level ATAP (a) and the implementation of analog test pad
(b).
ATB2
Device pin
ABC #1 ABC #2 ABC #M

ATB1
AT1 PAD
ATB1
ATMSB
ATB1/2
Figure 27: Schematic block diagram of the Analog Test Bus concept and its
connection to a single analog test pad at the top-level.

ABC/MABCs are sometimes designed and reused as hard-cores that may also
instantiate all pads inside the ABC/MABC (especially for Flip-Chip devices). A
device may instantiate several identical instances of the hard-core ABC/MABC
and due to routing constraints may not share identical pins such as ATAP that
could be normally shared. Therefore, a device may actually have several sets of
ATAPs each for a different hard-core ABC/MABC. An example is demonstrated
in Figure 28. ATAP of each MTSB is identified by a dedicated prefix.
ATB2 MABC1
Rx1_AT1 PAD
ATB2
ABC ABC ABC
#1 #2 #M
ATB1
Rx1_AT2 PAD
ATB1
ATMSB
ATB2 MABC2
Rx2_AT1 PAD
ATB2
ABC ABC ABC
#1 #2 #M
ATB1
Rx2_AT2 PAD
ATB1
ATMSB
Figure 28: Instantiating identical instances of an MABC as a reusable hard-core

with embedded pads.
5.2.3 Loopback
Loopback is a viable and common DFT technique that may prove very beneficial
for applications that include both receiver and transmitter on the same chip.
Practical examples are telecommunication, data communication, audio, and
industrial control products. Loopback DFT technique, also called loop-around,
may result in a fully digital test for a mixed-signal part yet keeping good test
coverage. Many networking and telecommunication ASSP implement loopback
as a device feature. Use loopback wherever you can justify its implementation.
Figure 29 illustrates a system that is designed to support digital loopback DFT

technique. In this example, three digital-in and digital-out signal paths may be
established to provide reasonable test coverage for all building blocks.

Path 1: S1=0, S2=X and S3=X establishes a digital path to test two digital
blocks. This is useful for debugging and validation.
Path 2: Digital blocks, ADC and DAC can be tested together by setting S1=1,
S2=0 and S3=X. Digital vectors should target the ADC-DAC pair because
digital blocks are already tested using the first path. Note that faults in the
DAC-ADC pair can self compensate errors in each other. The mux in front of
the ADC can greatly affect its performance.
Path 3: Setting S1=1, S2=1 and S3=0 creates a test path to test all building
blocks together. Test vectors should target analog building blocks as the rest
of the building blocks have already been tested using the first two test paths.
This test is the most useful in production testing.
Digital DAC Analog
0 0 0
Digital ADC Analog
1 1 1
S1 S2 S3
Figure 29: Loopback DFT technique implemented with multiplexers.
Note that it is also possible to establish analog or mixed-signal paths based on

the loopback technique. Digital loopback is the preferred technique as it makes it
possible to test a mixed-signal circuit on a digital tester. Analog loopback
provides additional flexibility in accessing and stressing all components of the
device.
Figure 30 shows a practical data communication product (T1/E1 Line Interface)
that contains both digital and analog loopback DFT techniques. This example
shows that the part can be tested using fully analog or fully digital tests. For
example, one fully analog test path is created by setting S5=1, S4=1, S1=0 and
S2=1.

S5=1, S4=1, S1=0, S2=1 S1=1, S2=1, S5=0, S4=1, S3=1

S1 S2
Encoder
1 Timing & 1
Driver
0 Control 0
Decoder
0 Data 0
Receiver
0
1 Recovery 1 1
S3 S4 S5
Figure 30: Digital and analog loop back DFT technique for a data communication
device (T1/E1 Line Interface).
Related switches are controlled using ECBI normal registers through the zATINy
and zDTINy buses. Loopback often happens for MABCs and therefore there
should be a dedicated ATMSB signal dedicated to MTSB level test modes.
5.2.3.1 Loopback for High-Speed Transmitter and Receiver Pairs
All high-speed transmitter and receiver pairs are tested using an external
loopback technique. All data links faster than 200 MHz should implement
loopback DFT technique following guidelines provided in this section. As
illustrated in Figure 31 the external loopback is established on the load-board and
a PRBS data is applied to the transmitter. The PRBS data goes through the
external loopback and is received via the receiver. The received data should
match the transmitted data. One major deficiency of this test is that a strong
transmitter can mask faults that result in a week receiver. To overcome this
problem, the amplitude level of the transmitter should be programmable in the
test mode so that the transmitter amplitude can be decreased to stress the
receiver sensitivity. Note that the external loopback introduces a fixed
attenuation in the path. The external fixed loopback attenuation should be
considered to determine the amount of required on-chip programmable
attenuation to properly stress the receiver. To ensure that the transmitter levels
are within specifications and have not been affected by the process variations or
defects, its output levels are measured at DC using the tester prior to starting the
at-speed test.

S
off-chip
Digital
Output
TX
...
PRBS Generator
& Checker BSC
Digital
RX
Input
BSC
Figure 31: Loopback technique to test high-speed transmitter and receiver pairs
with embedded pattern generators and checkers.
Here is a summary of test phases:
The transmitter output levels are tested at DC

The external loopback is established and the transmitter/receiver pair is
tested using internally generated PRBS data
Eye opening and jitter is tested by sweeping the location of the sampling point
and checking if the data recovered correctly
In the external loopback mode, the transmitter amplitude is reduced to
measure the receiver sensitivity or stress the receiver
A phase hit is introduced in the loop to stress the data and clock recovery
circuitry
The internal loopback from the receiver to the transmitter is established and
used to complete the test
Designer must also ensure that an internal loopback from the receiver to
transmitter (Figure 32) can be established. The internal loopback is very useful
for debugging, characterization and validation. Note that internal loopback
cannot be done in all cases as it impacts the performance of the receiver and
transmitter.

S1 Transmitter off-chip
1
0
Receiver
Figure 32: Loopback technique for a receiver/transmitter pair in a data

communication device.
Here are general rules that ABC designer should follow when designing
transmitters and receivers.
The transmitter amplitude should be externally programmable or controllable

in the test mode
Proper Pseudo Random Binary Sequence (PRBS) generator and checker
circuitry should be implemented on-chip
The data sampling point of the data recovery unit (DRU) should be
controllable in the test mode. This cannot be done for a clock recover unit
(CRU)
The possibility of injecting a phase hit should be provided if it cannot be
applied externally
An internal loopback should be provided to ensure that there is an inverting
path from the receiver to the transmitter
5.2.4 Bypassing
In some applications, bypassing intermediate blocks can be used to simplify the

test problem or provide a better diagnostic. The basic idea is to bypass blocks
that should not be involved in the specific testing. A typical example is bypassing
jitter attenuator block to be able to measure the jitter specification without it.
Loopback could be considered as special case of bypassing technique. In the
example shown in Figure 33, the first and the last blocks are bypassed in order to
test the middle block.

Use bypassing in cases where you need to remove from the test path a block
that has a redundant functionality.
Analog 1 Analog 1 Analog 1

Block #1 0 Block #2 0 Block #3 0
S1 S2 S3
Figure 33: Bypassing DFT strategy implemented using multiplexers. To test the
analog block in the middle, switches should be set to S1 = 0, S2 = 1, and S3 = 0.
Figure 34 shows an example where bypassing is used to eliminate the jitter

attenuator from the test path. Otherwise, it would be almost impossible to find
out whether an excessive jitter is due to a problem in the Clock & Data Recovery
block or in the Jitter Attenuator block.
N N
Clock & Data Jitter 1
Sampler
Recovery Attenuator 0
Figure 34: Bypassing the Jitter Attenuator to measure CDR jitter specifications
and diagnose possible cause of an excessive jitter.
5.2.5 IEEE 1149.4
IEEE 1149.4 is a new IEEE standard that aims at providing a complete solution
for testing analog and digital I/O pins and the interconnection between mixed-
signal integrated circuits. Its secondary objective is to provide access to internal
cores based on the test access bus concept. It includes IEEE 1149.1 boundary
scan Test Access Port (TAP) controller and therefore provides a support
infrastructure for BIST and test set-up. PMC has not adopted IEEE 1149.4 as a
test strategy mainly because it is more suitable for low-speed analog circuits.
Please refer to APPENDIX for a detailed description of this standard.

6 IEEE 1149.6 STANDARD [AC JTAG]
The IEEE Std 1149.6-2003 (AC JTAG) is build atop the IEEE Std 1149.1 (DC
JTAG) to improve the ability for testing differential and/or ac-coupled
interconnections between integrated circuits on circuit boards. As shown in
Figure 35 below, the problem with DC JTAG is that it cannot test for AC-coupled
connections as the coupling capacitor appears as an open circuit to the DC
JTAGs voltage levels. Moreover DC JTAG can only test for the single-ended
digital side of a differential signal.
Figure 35: Problem with DC JTAG testing of differential and/or ac-coupled signals
On the other hand, as shown in Figure 36 each leg of the differential signal path
has its own test receiver. The purpose of each test receiver is to independently
monitor the given leg of the signal path; In addition, AC-coupled connections can
also be tested since AC JTAG generates time-varying (AC) transitions, as
apposed to DC JTAG levels. These are features provided by AC JTAG which
results in adequate defect coverage and diagnosis capability.

Figure 36: AC JTAG differential signal reception with Test Receiver
To design receivers which are compliant with AC JTAG, you must refer to IEEE Standard
1149.6-2003 [AC JTAG]. Moreover, you may also refer to PMCs 90nm
PM50_00_18_A: Stork OC48/TFI receiver which has the AC JTAG capability. Note that
transmitters do not require any specific enhancements in order to be compliant with AC
JTAG. Instead, it is the responsibility of the digital logic to drive pulses out of the
transmitters; this is accomplished by means of slim_ac IOLM which is introduced next.

6.1 slim_ac I/O Logic Macro [IOLM]
At PMC, a slim_ac IOLM is instantiated in the digital padring and is coupled with
each of the transmitter and/or receivers, which are going to be used during AC
JTAG. For receivers, slim_ac IOLM is used to observe both the positive and
negative legs of a receiver that is compliant with AC JTAG i.e. it contains the
required Test Receiver logic as depicted in Figure 36. For transmitters, the
slim_ac IOLM would provide the necessary pluses or train of pulses during AC
JTAG test. Figure 37 on next page shows the block diagram of the slim_ac IOLM.
For more information about the 90nm slim_ac IOLM, you may refer to component
cad_dd_00655 on ICDC.

so D Q pad_tdo
padside_p data_in
BC4
capture_clk
* * GN
shift_dr
capture_en
si jtag_acinit_p
so jtag_acinit_n
padside_n data_in
BC4
capture_clk
*
shift_dr
capture_en
si
AC7 so
frompad pin_input
i output_data
jtag_ac jtag_ac
ac_test_signal ac_test_signal
update_clk scanb
tck * scan_in
capture_clk
* ic_input cin
shift_dr shift_dr
capture_dr capture_en
update_dr update_en data_out topad
mode
si
control_out
mode mode BC2 so

shift_dr All ports shown with an asterisk (*)
capture_en are being clocked by TCK
update_en
* update_clk
capture_clk
pad_tdi
* si
oenb 1 data_out oenpad
hiz data_in
0
scan_dir
scanb
pad_test
scan_en hiz
Figure 37: slim_ac IOLM Block Diagram

6.2 AC JTAG Test Related Signals

This section gives a detailed description of slim_ac IOLM pins related to AC JTAG.
Table 3: slim_ac IOLM AC JTAG pins

padside_p Input The P-side of the Rx input signal.
For slim_ac IOLMs associated with transmitters, the
padside_p port is tied to ground by the padring
generation tool.
For slim_ac IOLMs associated with receivers, the
padside_p port is routed to the device cores edge by
the padring generation tool; the corresponding core
port name would be named: rx_jtagp_<signal_name>
where signal_name is the given top-level signal name.
The P-side of the Rx input for a given differential
signal must be connected to its corresponding
rx_jtagp_<signal_name> port.
padside_n Input The N-side of the Rx input signal.

padside_n port is tied to ground by the padring
generation tool.
padside_n port is routed to the device cores edge by
the padring generation tool; the corresponding core
port name would be named: rx_jtagn_<signal_name>
where signal_name is the given top-level signal name.
The N-side of the Rx input for a given differential
signal must be connected to its corresponding
rx_jtagn_<signal_name> port.


frompad Input The single-ended side of the Rx input signal.
frompad port is tied to ground by the padring
generation tool.
frompad port is routed to the device cores edge by the
padring generation tool; the corresponding core port
name would be named: rx_jtag_<signal_name> where
signal_name is the given top-level signal name.
If the [M]ABC provides the single-ended version of a
differential signal, then it must be connected to
rx_jtag_<signal_name> port. Otherwise, you must tie
this port to ground in the core.
jtag_acinit_p Output Initializes the voltage hysteresis to for P-side of the Rx

input signal.
jtag_acinit_p port is assigned to OPEN by the
padring generation tool.
jtag_acinit_p port is routed to the device cores edge
by the padring generation tool; the corresponding core
port name would be named:
rx_jtag_acinit_p_<signal_name> where signal_name
is the given top-level signal name.
jtag_acinit_n Output Initializes the voltage hysteresis to for N-side of the Rx

input signal.
jtag_acinit_n port is assigned to OPEN by the
jtag_acinit_n port is routed to the device cores edge
by the padring generation tool; the corresponding core
port name would be named:
rx_jtag_acinit_n_<signal_name> where signal_name
is the given top-level signal name.


ac_test_signal Input Generated in the vicinity of the TAP controller and is
used to modulate static test data into a time-varying
signal that can pass through AC-coupling. A test
receiver and detector are used to recover the static
test data value from within the time-varying signal.
This is signal is routed to slim_ac IOLMs by the
ac_test_signal_o Output Feed-through buffered version of ac_test_signal signal

for downstream IOLMs to relieve routing congestion.
jtag_ac Input Active-high signal generated by TAP controller. If

either EXTEST_PULSE or EXTEST_TRAIN AC JTAG
instructions are executed, then jtag_ac is HIGH;
otherwise its value is a logic LOW.
padring generation tool. In addition, jtag_ac input port
is routed to the device cores edge by the padring
generation tool. The receivers must use jtag_ac to
distinguish between AC JTAG and DC JTAG modes.
The default value of jtag_ac is a logic LOW.
jtag_ac_o Output Feed-through buffered version of jtag_ac signal for
downstream IOLMs to relieve routing congestion.


oenpad Input For IOLMs associated with receivers, the oenpad port
is assigned to OPEN by the padring generation tool.
For IOLMs associated with transmitters that are tri-
statable, the oenpad port is routed to the device cores
edge by the padring generation tool; the
corresponding core port name would be named:
tx_jtag_oeb_<signal_name> where signal_name is the
given top-level signal name.
The tx_jtag_oeb_<signal_name> port must be
connected to the OENB input of the DFT block of the
given transmitter signal.
Note: For IOLMs associated with transmitters that are
not tri-statable, the oenpad port is is assigned to
OPEN by the padring generation tool.
jtag_acforce Input to Active-high signal that when pulsed high for a

the ABC minimum of 400 ps, it causes voltage hysteresis
comparators in the AC JTAG receiver to be pre-loaded
with either positive or negative voltage hysteresis
determined by values of JTAG_ACINIT_P and
JTAG_ACINIT_N.
The jtag_acforce signal is generated by the TAP
controller in the digital padring and is only routed to
the device cores edge by the padring generation tool.
Although jtag_acforce is not among the slim_ac ports,
but it appears in this table as it is related to AC JTAG.
The jtag_acforce must be connected to jtag_acforce
input of the ABC receiver.
The default value of jtag_acforce is a logic LOW.
The two diagrams below show examples of top-level connections between a slim_ac
IOLM and the core where the ABCs reside. Figure 38 shows the connections for a top-
level differential receiver signal, indiff_p/n, which might be declared as follows in a
device pad_ report file:
28 28 - indiff_p group8 JAID_AC no_pad

29 29 - indiff_n group8 JAID_AC no_pad

pmxxxx.vhd
pmxxxx_core.vhd pmxxxx_padring.vhd
pmxxxx_jtag.vhd pmxxxx_pads.vhd
rx_jtag_acinit_p_indiff
rx_jtag_acinit_n_indiff slim_ac iolm I/O pads
ABC
rx_jtagp_indiff padside_p jtag_acinit_p rx_jtag_acinit_p_indiff
indiff_p indiff_p
rx_jtag_indiff frompad
indiff_n indiff_n rx_jtagn_indiff padside_n jtag_acinit_n rx_jtag_acinit_n_indiff
Figure 38: Top-level example connections between one slim_ac IOLM and one
ABC receiver
Figure 39 shows the connections for a top-level differential transmitter signal, sig_p/n,
which might be declared as follows in a device pad_report file:
122 122 - sig_p group8 JAODT_AC no_pad

123 123 - sig_n group8 JAODT_AC no_pad
pmxxxx.vhd
pmxxxx_padring.vhd pmxxxx_core.vhd
pmxxxx_pads.vhd pmxxxx_jtag.vhd
slim_ac IOLM
topad tx_jtag_sig sig_n

ABC sig_p
oenpad tx_jtag_oeb_sig
Figure 39 :Top-level example connections between one slim_ac IOLM and one
ABC transmitter
6.3 Analog AC JTAG Receiver Implementation
Figure 40 below illustrates the block diagram of a typical AC JTAG receiver which
is presumed to receive signals form a driver in the same technology.

Receiver (Rx)
Back- plane
Channel
RXIP
RXOP
Main
Transmitter Signal
(Driver) Path RXON
RXIN
JTAGP
JTAGN
JTAGAC
JTAG_ACFORCE
JTAG_ACINIT_P
JTAG_ACINIT_N
VREF
ENABLE
JTAG Receiver
Figure 40 : Typical AC JTAG Receiver
A brief description of all JTAG signals shown in Figure 40 is given below:
JTAGAC: This signal controls the AC-mode and DC-mode of operation of the
JTAG receiver.
JTAG_ACFORCE: This signal forces JTAG_ACINIT_P on JTAGP and

JTAG_ACINIT_N on JTAGN. It is used to initialize the JTAG outputs as required
by the standard [1].
JTAG_ACINIT_P/N: the values on these inputs are used to initialize JTAGP/N

outputs.
VREF: the voltage level on this pin is used as the threshold of the DC comparator
in the DC-mode of operation of the JTAG receiver.
ENABLE: enables/disables the JTAG receiver.
6.3.1 Analog AC JTAG Receiver Parameters

Figure 41 shows a block diagram of the AC JTAG receiver circuit. The way the standard
is defined (see chapter 6 of reference [1]), one single ended AC JTAG receiver is
required for each leg of the differential path. Therefore, for differential receivers, two
identical single-ended AC JTAG receivers as shown in Figure 41 are used.

In the AC-mode of operation, the JTAG receiver compares the input signal to the low-
pass version of itself, while in its DC-mode of operation; the input is compared to a fixed
threshold (VREF).
VHYST_ LEVEL
RXIP
VHYST_EDGE
JTAGAC
LPF (TLP)
THYST 0 JTAGP
VREF
1
JTAG_ ACINIT_P
JTAG_ ACFORCE
Positive feedback
(behaves as a latch , level triggered by JTAG _ACFORCE)
Figure 41 : Block diagram of AC JTAG receiver circuit
The AC JTAG receiver parameters are defined below:
Vhyst_Level: Minimum input signal level (on RXIP & RXIN) recognized as a valid
level by the JTAG receiver in its DC-mode of operation. This parameter
immunizes the JTAG receiver against small amplitude noise happening around
VREF, and accordingly eliminates false responses on JTAGP/N.
Vhyst_Edge: Minimum signal transition (on RXIN & RXIP) recognized as a valid
transition by the JTAG receiver in its AC-mode of operation. This parameter
immunizes the JTAG receiver against small signal transitions due to noise or
crosstalk, and accordingly eliminates false responses on JTAGP/N.
Thyst: This parameter is the minimum pulse duration recognized as a valid signal.
This parameter should be set such that it eliminates the detection of short
duration, large amplitude pulses as a valid signal (The JTAG receiver only
responds to input signals with a transition larger than Vhyst_Edge and lasting longer
than Thyst).
TLP: Time constant of the low-pass filter used for AC-JTAG.
THP: High-pass time constant associated with AC-coupling capacitor (in the case
of AC-coupled receivers).

Ttest: Minimum time between signal transitions caused by boundary scan test.
This parameter puts an upper bound on the clock frequency (TCK).
Vmin: Minimum signal amplitude received by the JTAG receiver in a given

standard (assuming a driver in the same technology).
Vmax: Maximum signal amplitude received by the JTAG receiver in a given

standard (assuming a driver in the same technology).
Ttrans: Slowest rise/fall time recognized as valid (dictated by the standard of

interest).
6.3.2 Analog AC JTAG Receiver Parameter Calculator

The values of AC JTAG receiver parameters, as listed above, depend on the standard
for which the AC JTAG receiver is being designed (PCI-X, SONET, TFI-5, SAS, ). An
Excel spread sheet calculator is designed to simplify the extraction of AC JTAG receiver
parameters for any standard. The JTAG calculator Excel spreadsheet is inserted in the
INCLUSIONS: field on page 2.
To calculate JTAG receiver specifications for a given standard using the above
calculator, one first need to fill out the required technology parameters table (green
column) located on the right of the spread sheet. The corresponding AC JTAG receiver
parameters will then be automatically calculated in the table on the left of the spread
sheet (purple column).
One way to implement the AC JTAG receiver architecture shown in Figure 41 can be
found in the SONET OC-48/12/3/TFI-5 receiver circuit [PM50_00_18_A]. The AC JTAG
receiver circuit is instantiated by the name of jtagACDetect.

7 I/O CONTROL INPUTS DURING TEST MODE
For I/O pads that are instantiated in the digital padring of a device, there are
provisions in place to ensure that I/O pads which have control inputs are placed
in a known/safe state during test modes such as internal scan or boundary scan.
For example, in 90nm devices there exists a pads_ctrl_reg user-defined register,
which is automatically inserted in the digital padring by the padring generation
flow to provide control via JTAG for I/O pads that have control inputs such as
schmitt-enable, pull-up or pull-down enable, drive strength, etc. The
pads_ctrl_reg is compatible with PMC JTAG TAP controller and hence could
easily be accessed via the JTAG TAP controller and allow testing of I/O pads by
setting different control values.
For I/O pads that exist in ABCs, however, the padrings pads_ctrl_reg register
can not automatically implement the same degree of control because the
interface of the ABCs is unknown to the padring generation flow. Besides, the
padring generation flow, as the name suggests, it only generates the padring; it
also generates an empty core which will subsequently be pulled in by Product
Development.
Figure 42 below suggests a method, similar to that of digital padring, which could
be implemented in a wrapper generated by top-level designers to provide
controlling of ABCs I/O control inputs via JTAG logic. In Figure 42, for example it
has been determined that ctrl1 and ctrl3 inputs to the ABC must preset to a logic
1 upon jtag reset, whereas ctrl2, ctrtl4 and ctrl5 must clear to a logic 0. Hence
the user-defined registers bits are chosen accordingly. When internal scan or
jtag EXTEST instruction is being executed the user-defined register takes over
and over-rides the values that are normally provided by the functional logic.
Moreover, since the user-defined register is simply accessible via JTAG, then
Product Engineering, for example, could easily access this register and capture
different values to perform various tests for debug and diagnosis on the ABC
I/Os.
The information as to which control inputs of a given ABC must be controlled by a

user-defined register and what are the default power-on reset or default capture
values for each bit must be provided by MSDG in the ABCs Eng. doc.

Device Core
jtag_extestb
dll_scanb
1
ctrl1
0
1
Functional Logic
ctrl2
0
1
ctrl3 ABC
0
1
ctrl4
0
1
ctrl5
0
TDI 1 0 1 0 0 TDO
user-defined register
Upon applying reset , these are the

default values being output by
individual register bits
Figure 42: Test mode I/O control using a UDR

8 APPENDIX A
8.1 IEEE 1149.4
IEEE 1149.4 is a new IEEE standard that aims at providing a complete solution
for testing analog and digital I/O pins and the interconnection between mixed-
signal ICs. Its secondary objective is to provide access to internal cores based
on the Test Access Bus concept. It includes IEEE 1149.1 boundary scan Test
Access Port (TAP) controller and therefore provides a support infrastructure for
BIST and test set-up.
Figure 43 shows the IEEE 1149.4 architecture that includes the following
elements:
Test Access Port (TAP) comprising a set of four dedicated test pins: Test Data
In (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCLK),
and one optional test pin: Test Reset (TRSTn).
Analog Test Access Port (ATAP) comprising two dedicated pins: Analog Test
Stimulus (AT1) and Analog Test Output (AT2), and two optional pins: Inverse
AT1 (AT1n) and Inverse AT2 (AT2n) for differential signals.
Test Bus Interface Circuit (TBIC).
An Analog Boundary Module (ABM) on each analog I/O.
A Digital Boundary module (DBM) on each digital I/O.
A standard TAP Controller and its associated registers.

ABM ABM
AMB ABM
Analog Core
DMB DBM
DBM DBM
DBM Digital Core DBM
DBM DBM
AB1 AB2
AT1 TBIC AT2
TDI
TCK TAP Controller
TDO
TMS and Registers
TRSTn
Figure 43: IEEE 1149.4 chip architecture.
For complete details about this DFT technique please refer to the standard
reference manual published by IEEE.
8.2 IEEE 1149.4 TBIC
Test Bus Interface Circuit shown in Figure 44 controls connections between the
ATAP and internal test buses and shall be able to:
Disconnect test bus lines from the ATAP during normal mode and connect it to
an internal source (e.g. Vclamp).
Connect AB1 to AT1 whether or not AB2 is connected to AT2.
Connect AB2 to AT2 whether or not AB1 is connected to AT1.
Apply VH or VL to the external test bus via the ATAP while they are
disconnected from their internal test buses.

Digitize ATAP voltages by comparing VAT1 and VAT2 to V + VL VH VL

VTH = H
2 4
Deliver current or voltage stimuli to pin through AT1 pin and AB1 bus
and support bidirectional transmission.
AB1 AB2 for Interconnect

testing
Bus connection
& calibration
S1 VH S2
S9 Vclamp S10
S3 VL S4
S5 S8 S7 S6
+
+
VTH
AT1
AT2
Figure 44: Schematic representation of IEEE 1149.4 TBIC.
8.3 IEEE 1149.4 ABM
IEEE 1149.4 attributes an Analog Boundary Module (ABM) to each analog I/O.
Each ABM shall be able to:
Connect and disconnect its associated pin to core.

Apply VH and VL to its associated pin.
Digitize VPIN by comparing it to VTH = VH + VL VH VL .

2 4
Deliver current or voltage stimuli to its associated pin through AT1 pin and
AB1 bus.
Monitor pins voltage through AB2 bus and AT2 pin.
Connect one reference quality voltage (VG) to the external circuitry.
Support bidirectional transmission.
A simplified example of ABM implementation is shown in Figure 45. ABM

switches can also be implemented using current or voltage buffers to minimize
the impact of introduced switches on performance degradation.

VTH
VG VL VH

SG SL SH
+
SCD Analog
Analog
I/O
Core
SB1 SB2
ABM
AT1 AB1
TBIC
AT2 AB2
Figure 45: An example of ABM implementation. SCD: Switch for Core

Disconnect.
8.4 IEEE 1149.4 Instruction Set
IEEE 1149.4 supports all mandatory and optional 1149.1 instructions. It also
includes an additional mandatory instruction called probe.
When Bypass and Sample/Preload are selected:
All ATAP pins are isolated from the internal test buses and voltage sources.
All the analog function pins are isolated from the internal and external test
buses and from all test voltage sources.
All analog function pins are connected to the core.
When Extest is selected all analog function pins are separated from the core
through ABMs so that interconnect testing between different ICs can be
performed. When Intest is selected:
The boundary-scan register supplies all inputs to the digital cores.

All analog pins are connected to the core.
Any analog pin shall be capable of being connected through AB1.
Any analog pin shall be capable of being monitored through AB2.

The additional mandatory Probe instruction allows analog pins to be monitored or

stimulated while the device is operating in its normal mode. When Probe is
selected:
Boundary-scan register is connected between TDI and TDO.

All digital and analog pins are connected to the core.
ATAP pins are connected to the corresponding internal test bus.
Internal test buses are connected to the designated individual pins
determined by the contents of the corresponding ABM control registers.
8.5 Component Measurement Using IEEE 1149.4
Discrete interconnection component values between mixed-signal ICs can be

measured using IEEE 1149.4 standard. Figure 46 demonstrates how the ZCUT
can be measured using IEEE 1149.4 infrastructure by applying a current stimulus
through AT1 and measuring the resulting voltage level at AT2.
Analog ABM
I/O
Analog
ZCUT SB1 SB2 Core
TBIC
IT S5
AT1
AB1
v AB2
AT2
S6
VT

between an IC and ground. IT is a current source and VT is a voltage
measurement unit.

VL
ABM
SL' I/O
I/O
net2 ZCUT net1 Analog

Analog ABM SB1 SB2 Core
Core
TBIC
IT S5
AT1
AB1
v AB2
AT2
S6
Chip 2 VT1 Chip 1
(a) Phase 1
VL
ABM ABM
SL'
I/O I/O
Analog net2 ZCUT net1 Analog

SB2' SB1 Core
Core
TBIC
TBIC IT S5
AT1
AB1 AB1
AB2 v AB2
AT2
S6'
Chip 2 VT2 Chip 1
(b) Phase 2

between two mixed-signal ICs.
In this case, ZVT >> ZS6 + ZSB2 and therefore we can assume that VZCUT VT.
Also, ZVT + ZS6 + ZSB2 >> ZCUT and therefore IZCUT IT. This leads us to conclude
that ZCUT VT/I.
Components situated between two mixed-signal ICs can be measured using a

slightly different approach. One possible approach, described in the following,
consists of two phases.
In the phase 1, as shown in Figure 47(a), IT is applied through AT1 of chip 1 and
VT2 is measured through AT2 of chip 2. If ZVT + ZS6 + ZSB2 >> ZCUT + SL then the
current stimulus passes mainly through ZCUT and IZCUT IT. Besides, if ZVT >> ZS6
+ ZSB2 then we can assume that the measured voltage VT1Vnet1.

In the phase 2, shown in Figure 47(b), IT is applied through AT1 of chip 1 and VT2
is measured through AT2 of chip 2. In this case, IZCUT IT and ZVT >> ZS6 + ZSB2
and therefore the measured voltage VT2 Vnet2. Having measured the node
voltages of the component we can measure its value using ZCUT (VT2 - VT1)/IT.
8.6 IEEE 1149.4 Used for On-Chip Testing
IEEE 1149.4 can be used as an infrastructure to improve access to internal

nodes for applying a test stimulus or observing the test results. As shown in
Figure 48, AB1 can be used as TIB and AB2 can be use as TOB.
ABM ABM
SCD SCD
I/O
Analog Analog Analog
BB #1 BB #2 BB #3
T1 T2 SB2
ZL VT
T3 T4
TBIC
IT
S5
AT1 AB1
AT2 AB2
VT V S6
Figure 48: IEEE 1149.4 used to support Analog Test Bus (ATB) DFT technique.

9 REFERENCE
[1] Arabi, K. and B. Kaminska Design for Testability of Embedded Integrated

Operational Amplifiers, IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, April
1998, pp. 573-581.
[2] Arabi, K. and B. Kaminska, Testing Analog and Mixed-Signal Integrated Circuits
Using Oscillation-Test Method, IEEE Trans. on Computer-Aided Design of
Integrated Systems, Vol. 16, No. 7, July 1997, pp. 745-753.
[3] Arabi, K., H. Ihs, C. Dufaza, and B. Kaminska, A New Method for Dynamic
Testing of Digital Integrated Circuits, Journal of IEE Electronic Letters, Vol. 34,
No. 8, April 1998, pp. 762-763.
[4] Arabi, K., H. Ihs, C. Dufaza, and B. Kaminska, Oscillation-Test Method for
Structural and Delay Testing of Digital Integrated Circuits, IEEE International
Test Conference (ITC), Oct. 1998, pp. 91-100.
[5] Arabi, K. and B. Kaminska, Oscillation-Test Methodology for Low-Cost Testing of
Active Analog Filters, IEEE Trans. on Instrumentation and Measurement, Vol.
48, No. 4, August1999, pp. 798-806.
[6] Arabi, K. and B. Kaminska, On-Chip Testing Medium to High Resolution Data
Converters, IEEE Trans. on VLSI Systems, Vol. 9, No. 3, 1998, pp. 409-419.
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and Analog-to-Digital Converters, Journal of IEEE Design & Test of Computers,
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ABC DFT Flow 002

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cad_dd_00502 (Note Id 1110) ISSUE 3 ABC AND MABC DESIGN FOR TESTABILITY METHODOLOGY

ABC and MABC Design for Testability

Issue 3 May 17, 2007

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 1 of 86

DOC NO: cad_dd_00502 (Note Id 1110) ISSUE DATE:

PREPARED BY: REVIEWED BY:

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 2 of 86

Issue Date Originator Reviewer Details of Change

In addition two new sections were added:

1) AC JTAG [IEEE 1149.6 Std]

2) I/O control using UDRs

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 3 of 86

2.1 Order of Precedence....................................................................10

3 ABC/MABC Overview ............................................................................. 11

3.1 General Block Diagram of an ABC ............................................... 11

3.2 Block Diagram of an MABC .........................................................13

3.3 ABC/MABC Test Related Signals.................................................16

3.4 ABC/MABC Test Arbitration Logic ................................................28

3.5 Related Application Notes ............................................................30

4 ABC/MABC Digital DFT and ATPG Flow.................................................31

4.1 ABC/MABC Test Insertion and ATPG Flow ..................................31

4.2 DFT Rules ....................................................................................34

4.3 Test Synthesis Procedure ............................................................46

4.3.1 Scan Insertion Strategy for ABCs ......................................46

4.3.2 Scan Insertion Strategy for MABCs ...................................46

4.3.3 Scan Insertion and ATPG Users manual ..........................47

5 ABC/MABC Analog DFT Flow.................................................................48

5.1 Main Analog DFT Goals ...............................................................48

5.1.1 Design Debugging .............................................................48

5.1.2 Test Coverage ...................................................................48

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 4 of 86

5.1.3 Test Time ...........................................................................48

5.1.4 ATE Adaptation..................................................................49

5.2 Mixed-Signal DFT Methodology ...................................................49

5.2.1 Analog Test Bus.................................................................49

5.2.2 Connecting the Analog Test Bus at the Top-Level .............56

5.2.5 IEEE 1149.4 ......................................................................63

6 IEEE 1149.6 Standard [AC JTAG]...........................................................64

6.1 slim_ac I/O Logic Macro [IOLM] ...................................................66

6.2 AC JTAG Test Related Signals.....................................................68

6.3 Analog AC JTAG Receiver Implementation..................................72

6.3.1 Analog AC JTAG Receiver Parameters .............................73

6.3.2 Analog AC JTAG Receiver Parameter Calculator..............75

7 I/O control inputs During Test Mode........................................................76

8.1 IEEE 1149.4 .................................................................................78

8.2 IEEE 1149.4 TBIC ........................................................................79

8.3 IEEE 1149.4 ABM.........................................................................80

8.4 IEEE 1149.4 Instruction Set .........................................................81

8.5 Component Measurement Using IEEE 1149.4.............................82

8.6 IEEE 1149.4 Used for On-Chip Testing ........................................84

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 5 of 86

Figure 1: Simplified block diagram of a testable ABC. Mandatory signals

Figure 2: ABC and its interface to wrapper/shim................................................. 12

Figure 3: Simplified block diagram of an example of an MABC. ......................... 15

Figure 4: Example Test Mode Arbitration Truth Table ......................................... 28

Figure 7: Simplified view of the ABCs Digital Core............................................. 31

Figure 10: Handling internally generated clocks. SCANB is an active low

Figure 11: Internally generated clock should not go through any

Figure 13: Handling gated clocks. ...................................................................... 39

Figure 14: Handling sequential controlled set and reset. .................................... 39

Figure 16: Making Latches transparent in test mode.......................................... 41

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL 6 of 86

Figure 28: Instantiating identical instances of an MABC as a reusable