9/14/2012

1. Lab
2. Power
Outline 3. Ser/Parl
4. Small sig.
5. Applic

Lab hits
 Power Supply, Oscilloscope , Breadboard , Multimeters

Energy
 Power an Energy for R, L, C

Series / Parallel
Session 2: Analog Circuits  LTI & NLTI
 Duality
Lab  1-port 2-port Networks
 Piecewise linear
Power / Energy
Small Signal
Series / Parallel  Bias point, small signal model
 Diode example
Small Signal
Applications
Applications  Rectifier, Voltage limiter
 Zener

1 2

1. Lab
2. Power
Power Supply 3. Ser/Parl
4. Small sig.
5. Applic

001 Ishort

current
limit
Lab

- 31 + 27.9

3 4

1
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Breadboard 3. Ser/Parl
4. Small sig.
Oscilloscope 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

Trigger:
?

Vcc
GND

5 6

1. Lab 1. Lab
2. Power 2. Power
Oscilloscope Probe 3. Ser/Parl
4. Small sig.
Digital Multimeters 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

Do not use oscilloscope probe

for power cables!

7 8

2
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Energy and Power 3. Ser/Parl
4. Small sig.
Passivity 3. Ser/Parl
4. Small sig.


5. Applic 5. Applic

 

Resistance Definition:
Voltage definition:

  
I
II Passive





   # 0
H2 O

   
always in I, II
 
 receives power ; consumes power

High Pressure Low Pressure


 


Power in electrical eng! 0
Active: not passive
   
a point in III or IV   % 0
  ,     
  
 
III IV

 
delivers power ; generate power

R

   



 
& 
 



  



 
0
Generator

Network

 




Active Active
9 10

1. Lab 1. Lab
2. Power 2. Power
Energy stored in TI Capacitor 3. Ser/Parl
4. Small sig.
Energy stored in TI Inductor 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

'
.
'
'(  .
.(

capacitance inductor




NLTI NLTI

 )  
1 
 ' *   . / 
  , 
  
 
  ' '   , 
  
 

. .
 *   / 

Assume at 
0 :

0 , .
0
' Assume at 
0 : 
0 , '
0 . ( no hysteresis )
*
/
+, 
  ' '
  
+0 

. .


If '
) If .
1


0  ' 
0
.
+, 
) 
+0 
1


2) 21
Only for LTI Cap Only for LTI Inductor
11 12

3
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
4th Element, Memristor 3. Ser/Parl
4. Small sig.
Series / Parallel LTI 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

 








air fire
hot
& &
resistor
 
 4 
& 4& 



&



wet dry
voltage current

&3*
& 4& 

water cold earth

'
) .
1

inductor
capacitor

  






 4

4
 &3* & &
& &
53*
5 4 5
.
2'
' .
charge flux

memristor

13 14

1. Lab 1. Lab
2. Power 2. Power
Series / Parallel NLTI 3. Ser/Parl
4. Small sig.
Series / Parallel NLTI 3. Ser/Parl
4. Small sig.


5. Applic 5. Applic

 









 
& &
 

&63*

 4   
V0 V0

&


&6
4 &6


R R

adding voltages at equal currents

true for current controlled


analysis
   
Ideal diode


 

 &
 & & 6


53* 

 4
 
D

&

V0

56  4 56 
R

adding currents at equal voltages synthesis

true for voltage controlled Reverse the diode direction and fine  
curve
15 16

4
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Series / Parallel NLTI 3. Ser/Parl
4. Small sig.
Duality 3. Ser/Parl
4. Small sig.

 
5. Applic 5. Applic

S S*
& 


 & &  & 
&6 
 
&6 7

5
D

& 
& 5
1&
V0

R
open circuit short circuit
 
series parallel
KVL KCL

5
I0




R

 

17 18

1. Lab 1. Lab
2. Power 2. Power
? 3. Ser/Parl
4. Small sig.
2-port equal resistance 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

T 
&
1- port / 2- terminal 2- port:

;< ;? &<?
9 B 9 B
parallel /series combination of linear resistors will be linear
 & &@
;=
&<= &?=
A A A A

;< 4 ;=
&<= &<? 4 &?= 
parallel /series combination of nonlinear resistors will be

: ;? 4 ;=
&?= &<? 4 &<= 

3 unknown
nonlinear

3 eqs ,
;< 4 ;?
&<? &<= 4 &?= 
E  Y
9 &<?
parallel /series combination of bilateral resistors will be
B ;< ;? 4 ;< ;= 4 ;? ;=
&<?

&<= &<?
bilateral
;< ;=
;? ;<

&<= 4 &<? 4 &?= ;< ;? 4 ;< ;= 4 ;? ;=

&?=

;= &?= &<? ;<

parallel /series combination of voltage controlled resistors
&<= &?= ;?

&<= 4 &<? 4 &?= ;< ;? 4 ;< ;= 4 ;? ;=
&<=

will be voltage controlled

&<= &?= ;?
;<

&<= 4 &<? 4 &?=

19 A 20

5
 9/14/2012

1. Lab 1. Lab
Piecewise Linear Approximation 2. Power
3. Ser/Parl
Piecewise Linear Approximation 2. Power
3. Ser/Parl
Technique Synthesis 4. Small sig.
5. Applic
Technique Synthesis 4. Small sig.
5. Applic

5?

5?
5= & 5=
5

 
1&
 
D

G G


V0

   5<
G G R
G G

5< 5 5<
voltage controlled


   4   
voltage controlled
2




G G
5
5< 4 5?



  5<
D D



G E1 E2 I0
& 5< 4 5? 5=  5?
I0

 5=  5?

&
& 
current controlled
G G


  4
 
2
21 22

1. Lab 1. Lab
2. Power 2. Power
Quiescent Point 3. Ser/Parl
4. Small sig.
Quiescent (Bias) Point for NLTI 3. Ser/Parl
4. Small sig.

5. Applic 5. Applic

Linear 2-terminal network

<
I0  I0  R I0  I0 
O


R

Q &Q

?
I0 I0 I0

   O
<
1/RT

Q ? O Q
Thevenin equivalent
O

?
<
Q &Q
 4 H J
KL  4 M J
KL
<
4<
? <

Small signal regime VT

M 
RT
<
?
H 
<

?
dc ac dc ac

23 24

6
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Small-Signal Analysis (for NLTI) 3. Ser/Parl
4. Small sig.
Small-Signal Analysis (for NLTI) 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic






Taylor series:
V  V
& & V W 4 W V W 4 Y W 4  Y W  4
W Z W  Z
   &    

S  S 
H
O 4 H  \ H O 4 Y M 
 ]
S 
M J
KL S 
M J
KL ^

Small-signal condition M  O Small-signal condition M  dc O

H O
O
HO  O
HO  H


H U

H U H  \ Y M 
 ]

 4 M
O
  &O  O
  &O
ac
^

  O 4 M  O    O 4 M  5__
1&__

 O 4 H 
 O 4 H 

  M
&__ small signal resistance
O 4 H 
HO 4 M   O 4 H 
HO 4 M  
25 26

1. Lab 1. Lab
2. Power 2. Power
Small-Signal Analysis (for NLTI) 3. Ser/Parl
4. Small sig.
Example Diode 3. Ser/Parl
4. Small sig.

O
c
5. Applic 5. Applic



c NLTI: Diode
c
Step1:

c
S d *ef ghQ  1
& &
Find Bias Point!

o
LN D

   O c
o  ij
S  
c 4 o
c Q
Y
26n
c ' @l
p c

c
c 4
o
1 a
&__

Y
H W b ]f er
 `]
Small-signal condition
M 
bias small signal

c
S d *efghQ  1 \ S d g]q d g]q
^
Step2:
^
  O 4 M 
Small Signal Analysis! Forward biased diode:

 O 4 H  H ]f o o

o o
&__
c \ S d g]q 1 4 4 4 \ c 4 c 1
1 M 
  & KQ  KQ KQ KQ
H  \ M  & 4 &__ S
&__ M &__
o
1 a S  o KQ 1 KQ
&__

Y S 
M J
KL ;o
;o



H W b ;o c c
 `]  `]
small signal resistance
^
^ f
27 28

7
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Example Diode 3. Ser/Parl
4. Small sig.
Diode Large Signal 3. Ser/Parl
4. Small sig.

c c
o
5. Applic 5. Applic

c
-3
8x 10

KQ
small signal resistance NLTI: Diode
c c o ;o ;o

c
;o 2)s )otuu

c
S d *ef ghQ  1
6
D

ij
4

c
c 4 o Q
Y
26n
p c ' @l
2

c
c 4
o 0
0.5 0.55 0.6 0.65

bias small signal


c
S d ]fg]q  1

c 
c
c 
? How to solve bias (large signal) ideal

{  {
ideal ideal

c c c

v ~0.6  0.7V v

29 30

1. Lab 1. Lab
2. Power 2. Power
Diode Large Signal 3. Ser/Parl
4. Small sig.
Example Diode Large Signal 3. Ser/Parl
4. Small sig.

c
c
5. Applic 5. Applic

c
c
S d *ef ghQ  1 cc
c
S d *ef ghQ  1
c &
c
cc 
c &
LN D

c
? How we should bias a diode? Load line

R

c c
c
 c  cc
D
c
VDD

D D

c cc
5 , &
1i , _
5 107 , Q
26n
cc  c
c
0
c

5n
&
iteration

|}
c cc  c
c
Q ln
0.658
c

4.341n
c _ &

c cc  c
c
Q ln
0.654864
c

4.345n
_ &

c
c
Q ln
0.654889
c

31 _ 32

8
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Example Diode Large/Small Signal 3. Ser/Parl
4. Small sig.
Example Diode Large/Small Signal 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

S
1 4 0.1J
KL ; v
0.7
tg
 4 (t J
KL c c
DC / bias
100 100 100
D D

tg &  tg & 

 0.7
0.7
S
200 120
  v 200 300
v Q Q
  v 300
1V

c

1V

 &
Bias:

&
5V 3V
5V

KQ 3  1  0.7
;o
c

6.36n
c 100 4 120
;o
small signal resistance
Q
Small signal:
;o

3.9
AC / small signal
100 c
&  &
(t J
KL 
( J
KL ;o
& 4 ;o t ;o (

220 4 ;o
0.1
1.75n

0.1
120
&
D

tg
&  
  v 4 ( J
KL 
0.7 4 1.75nJ
KL
 4 (t J
KL tg & 4 ;o t
33 34

1. Lab 1. Lab
2. Power 2. Power
Example 01 3. Ser/Parl
4. Small sig.
Example 01 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

D
Find tg   assume v
0, 0.7
c D
Find tg   assume v
0, 0.7
c

tg &  tg & 

ON ON
(F) (F)

c
c
c c
 
1: (F) (R) 1: (F) (R)
If
c 0 tg & If
c 0 tg &
OFF OFF


tg 
tg
 
condition
c 0 condition
c 0

c
 & 0  0
c
 & 0  0
tg 0 ON tg 0 ON
c c
tg tg
1: (R) 1: (R)
If c % 0 If c % 0
tg &  tg & 
OFF OFF


0 condition c % 0 
0 condition c % 0
tg   % 0 tg % 0 tg   % 0 tg % 0
35 36

9
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Example 01 3. Ser/Parl
4. Small sig.
Example 01 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

 
D D

tg &  tg & 


tg 

37 38

1. Lab 1. Lab
2. Power 2. Power
Example 01 3. Ser/Parl
4. Small sig.
Voltage Limiter 3. Ser/Parl
4. Small sig.


5. Applic 5. Applic

D
 &

& 5
tg  tg 
D2

1
D1
1v
5V 5V

tg
1v

tg 1 D1:OFF , D2:OFF

5 5

1v

& 0 5

c c
tg 
1v

5V 5V 
tg


c % 0   5 % 0  % 5

c % 0   5 % 0  5

condition c % 0
tg   % 0 tg % 0
39 40

10
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Voltage Limiter 3. Ser/Parl
4. Small sig.
Voltage Limiter 3. Ser/Parl
4. Small sig.

 
5. Applic 5. Applic

& &
2 2
5 5
tg  tg 
D2 D2

1 1
D1 D1
5V 5V 5V 5V

5 5
tg 5 5
tg
2 D1:ON , D2:OFF 3 D1:OFF , D2:ON
3
5 5

c
c
&
c c & c
c
tg  
5 tg  
5
5V 5V 5V 5V

c
5  
10 % 0 c
  5
10 % 0
tg  5 tg  5

c
0 tg 5
c
0 tg % 5
& &

41 42

1. Lab 1. Lab
2. Power 2. Power
Peak Detector 3. Ser/Parl
4. Small sig.
Zener Diode 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

 

c
D1

S 
S   
Z

1F

 v

c c

c


) tg

~  1n

) 

breakdown region
1;

 @

S  <Z <Z
<Z 
  ~  20n

c In breakdown region: 
;
Z


) ) )@ 43 44

11
 9/14/2012

1. Lab 1. Lab
2. Power 2. Power
Zener Diode Voltage Regulator 3. Ser/Parl
4. Small sig.
Zener Diode Voltage Regulator 3. Ser/Parl
4. Small sig.
5. Applic 5. Applic

R
c R
c

} Z }  v } Z } & &tg % & %  v

c c
tg tg


~ ~

} }
1;  1n 1;  1n
R

b t b } }
<Z <Z
~ ~
 20n  20n

e 7]
    % <Z % <Z
}


R

}  
} &tg
;
large signal Small signal


; 4 & t
R R

e7] ]
b  
 t ;   tg  tg
} }
45 46

12