IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO.
11, NOVEMBER 2006
Design of High-Speed Power-Efficient MOS
Current-Mode Logic Frequency Dividers
Massimo Alioto, Member, IEEE, Rosario Mita, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE
AbstractA methodology to design high-speed power-efficient
MOS current-mode logic (MCML) static frequency dividers is pro-
posed. Analytical criteria to exploit the speed potential of MCML
gates are first introduced. Then, an analytical strategy is formu-
lated to progressively reduce the bias currents through the stages
without affecting the divider operation speed, thereby reducing the
overall power consumption. The proposed design approach is gen-
eral and independent of the process adopted. Due to its simplicity,
it can be used in a pencil-and-paper approach, avoiding a tedious
and time-consuming trial-and-error approach based on simula-
tions. Moreover, the analytical approach allows for a deeper un-
derstanding of the powerdelay tradeoff involved in the design. As
a design example, a 1:8 frequency divider is designed and simu-
lated by using a 0.18- m CMOS process.
Index TermsCMOS, high speed, integrated circuit, low power,
MOS current-mode logic (MCML), prescaler, RF, source coupled
logic, static frequency divider.
I. INTRODUCTION
TATIC frequency dividers are fundamental building blocks
S in a number of applications, such as frequency synthesis in
mobile or satellite communication systems, clock generation,
data recovery, synchronization, and multiple gigabits per second
optic-fiber systems [1][6]. In these applications, the frequency
divider is often the speed-limiting block; thus, a high-speed per-
formance is required. Moreover, current applications require a
low power consumption to reduce the heat generation, as well
as to extend the battery lifetime in portable devices. In this sce-
nario, the speed improvement allowed by the technology scaling
has made the CMOS technology suitable for several high-speed
applications, thereby enabling the integration of RF blocks in
complex systems-on-chip [7].
In general, a static frequency divider is obtained by
cascading 1:2 dividers whose output frequency is half that
of their input waveform, as depicted in Fig. 1. When adopting
a CMOS technology, all the stages are usually implemented
with the MOS current-mode logic (MCML) approach and a dif-
ferential signaling to achieve a very high speed performance [8],
[9]. However, the latter is obtained at the cost of a significant
static power consumption, which is associated with the bias cur-
rent of the divider stages.
Manuscript received November 17, 2005. This paper was recommended by
Associate Editor V. Kursun.
M. Alioto is with the Dipartimento di Ingegneria dellInformazione, Univer-
sit di Siena, 53100 Siena, Italy (e-mail: malioto@dii.unisi.it).
R. Mita and G. Palumbo are with the Dipartimento di Ingegneria Elettrica
Elettronica e dei Sistemi, Universit di Catania, 95125 Catania, Italy (e-mail:
rmita@diees.unict.it; gpalumbo@diees.unict.it).
Digital Object Identifier 10.1109/TCSII.2006.882350
1057-7130/$20.00 2006 IEEE
1165
Fig. 1. Architecture of a static frequency divider.
In this brief, an analytical strategy is proposed to size the bias
currents in the stages of a static frequency divider to achieve a
high-speed performance. Moreover, since each stage operates at
a halved frequency as compared to the previous one, an analyt-
ical strategy to progressively reduce the bias currents (and thus
the power consumption) of the successive stages is developed.
The analytical results are a useful tool for designing frequency
dividers since they also afford a deeper understanding of the
powerdelay tradeoff. Furthermore, the closed-form bias cur-
rent design equations avoid the time-consuming approach based
on simulations with trial-and-error values of the design param-
eters.
This brief is organized as follows. Section II deals with the
timing analysis of the basic MCML 1:2 divider stage, and its
powerdelay tradeoff is analyzed in Section III. A practical de-
sign strategy for more general dividers to properly size
the bias currents is presented in Section IV. Design examples
are discussed in Section V. Finally, conclusions are reported in
Section VI.
II. TIMING ANALYSIS OF THE MCML 1:2 DIVIDER STAGE
Let us consider the generic frequency divider depicted
in Fig. 1, in which the first stage has an input frequency ,
and the generic th 1:2 divider stage (with ) has an
input frequency given by
with (1)
since each stage has an input frequency that is halved as com-
pared to the previous one. Since the 1:2 divider stage is the fun-
damental block of the divider, its speed performance is
evaluated in the following.
A 1:2 divider stage implemented in the MCML logic style is
structured as in Fig. 2, where the two cross-coupled D latches
implement a masterslave T flip-flop (T-FF) with its clock ter-
minals being driven by the differential input signal. Indeed, the
two D latches are driven by opposite clock signals; hence, the
input of each latch crosses both gates and turns to the oppo-
site value every two clock edges due to the inversion associated
with the cross coupling. The topology of the D latch in Fig. 2 is
depicted in Fig. 3, where is the gate bias current [10],
1166 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006

A. By taking the strict equality in (2), the maximum operating

frequency of the 1:2 stage results to

(3)

From (3), it is apparent that a high-speed performance is

achieved by reducing the delay of the level shifter and the
latch. These timing parameters can be modeled by resorting to
the general approach proposed in [2] and [3], which is valid
for arbitrary MCML gates. Following this approach, the latch
delay can be expressed as a function of the bias
current according to [2] and [3]

Fig. 2. Structure of a 1:2 divider stage. (4)

where is the logic swing; is the external load

capacitance; and , , and are coefficients that depend on the
adopted technology, the voltage gain around the logic threshold
, and the supply voltage , which are evaluated according
to [2] and [3].
The level shifter delay can also be modeled by re-
sorting to the methodology in [2] and [3] according to

Fig. 3. Topology of the MCML D latch.
[11]. Moreover, a level shifter (i.e., a common-drain stage im-
plemented by M1M2) must be inserted at the clock input of
the T-FF to avoid the operation in the triode region of transis-
tors M3M4 (see Fig. 3) [10], [11]. Let be the bias current
of the level shifter circuits.
Now, let us evaluate the maximum operating frequency
of a 1:2 frequency divider. To this aim, observe that, after the
rising edge of the input signal (which is assumed to occur at time
), latch A must generate a valid output within , tion (equal to the product of
being the input period. Since the output evaluation of latch A
is performed after the delay of the level shifter and the
delay1 of latch A, the following condition must be
satisfied to ensure correct operation
(2)
The same consideration leading to (2) holds in the negative
half period for latch B; thus, it must have the same speed as latch
1The latch delay is measured from the clock transition to the output transition,
which is usually referred to as the CK-Q delay.
(5)
where is the external load capacitance of the level shifter,
is the gatesource capacitance of its transistor (M1M2),
and are its effective channel width and length, and
is its small-signal transconductance. According to [2], the
latter was expressed with the traditional small-signal model after
substituting a suitable effective mobility .
In the following section, the timing model discussed until
now is used to better understand the powerdelay tradeoff.
III. POWERDELAY TRADEOFF IN THE
MCML 1:2 DIVIDER STAGES
The bias currents of the 1:2 divider stages in Fig. 1 must
be sized to allow their correct operation, i.e., by setting their
maximum operating frequency (3) greater than their input fre-
quency (1). This is equivalent to make the level shifter and the
latch delay in (3) sufficiently low, which is achieved by making
their bias current sufficiently high. However, an increase in the
bias currents determines an increase in the power consump-
and the bias current); thus,
a powerdelay tradeoff exists.
To better understand the powerdelay tradeoff, let us express
the dependence of the delay of the latch
(level shifter) on its bias currents . In regard to
the latch delay in (4), from Fig. 2, its load capac-
itance is approximately2 equal to the input capac-
itance of an equal latch since latch A drives latch
B and vice versa. From an analytical point of view, the latch
2In this evaluation, the input capacitance of the successive stage is neglected
for latch B since from Fig. 2, it is only that of a common-drain stage (i.e., an
overlap gatedrain capacitance [2]), which is much lower than the latch input
capacitance.
ALIOTO et al.: DESIGN OF HIGH-SPEED POWER-EFFICIENT MCML FREQUENCY DIVIDERS 1167

TABLE I IV. DESIGN OF FREQUENCY DIVIDERS

PROCESS PARAMETERS FOR THE ADOPTED 0.18-m TECHNOLOGY
In practical applications, the frequency divider is often the
speed-limiting block; thus, it must be designed for an almost
maximum speed for a given process. Since from (1) the first
stage works at the highest frequency, it is the most critical block
from a speed point of view, and its design is discussed in Sec-
tion IV-A, whereas the design of the successive stages is dealt
with in Section IV-B. Section IV-C reports a simplified design
procedure.

TABLE II
NUMERICAL VALUES OF COEFFICIENTS IN (8)
A. Design of the First Stage
From (3), to fully exploit the speed potential of a given
process, the latch and level shifter delay in the first stage must
be kept as low as possible by properly setting their bias currents
and . Moreover, from (7), the minimum value
of is obtained for ,
input capacitance depends on its bias current according to the i.e.,
following relationship, as demonstrated in [2]:
(10)
(6)
In practical cases, the latch delay must be set close to (10) while
where coefficient depends on the process parameters and the keeping within reasonable limits. Thus, defining for
preliminarily assigned voltage gain . Relationship (6) can the first stage the ratio ,
be substituted into (4) to achieve the explicit dependence of the we get
latch delay on its bias current, i.e.,

(7) (11)
whose value must be chosen from considerations on the
powerdelay tradeoff. By inverting (11), the resulting bias
with coefficients , , and being defined as follows: current that allows to achieve an assigned value of
is

(8)

To have an idea about the order of magnitude of coefficients in (12)

(8), let us consider a 0.18- m CMOS process, whose main pa-
rameters are reported in Table I. The resulting numerical values
of coefficients by applying the procedure in [2] and [3], as-
suming V and , are reported in Table II.
In regard to the level shifter delay , from Fig. 2, its
load capacitance consists of the input capacitance of the
two latches A and B, which are driven by the level shifter. By
substituting the latch input capacitance in (6), the level shifter
delay results to
which, as expected, increases as decreases (i.e., improving
the speed performance).
To find a suitable value of that ensures high speed without
excessive power consumption, observe that for sufficiently high
values of , the second and third terms in (11) are much
lower than unity; thus, a very high speed performance is ob-
tained, but a further increase in does not bring a sig-
nificant delay reduction. Rather, for low values of , the
second and third terms in (11) are much greater than unity; thus,
a poor speed performance is achieved, but a further increase in
greatly improves the speed performance. As a compro-
mise, we suggest to make the sum of the second and third terms
in (11) equal to unity, which leads to

(13)
(9)
Obviously, different values of may be adopted depending
on the application requirements. For example, a choice that
The numerical value of the capacitance in (9) for a min- optimally balances speed and power consumption is achieved
imum-sized transistor in the adopted 0.18- m CMOS process is by minimizing the powerdelay product [PDP; defined as the
about 1.2 fF. product of the power consumption and the delay
1168 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006

(7)]. By finding the value of that minimizes PDP and whereas parameter of the th stage (defined in Section IV-A)
substituting it into (11), the value of minimizing PDP is is equal to that of the first stage, i.e., . Thus, from (12) and
(17), the latch current of the th stage is

(14)

In regard to the choice of the bias current , it is well

known that the level shifter delay can be made much
smaller than (7). Indeed, the common-drain stage is often added
to MCML gates to achieve a higher performance since it is able
to achieve a much lower delay than an MCML gate for a given
load capacitance and bias current [2]. Moreover, in Section III,
the level shifter load capacitance was shown to be compa-
rable to (more precisely, twice) that of the latch, i.e.,
As a consequence, the level shifter delay can be made much
smaller than that of the latch with a bias current much
lower than in (12). From these considerations and (3),
a reasonable approach to achieve a high-speed performance is
to find the value of that makes the level shifter delay equal
to a small fraction of . In the following, let
the ratio . When choosing parameter , it
is worth noting that from (9), very low values of lead to a very
high bias current , whereas values comparable to unity sig-
nificantly reduce the maximum operating frequency in (3). As
a compromise, values of ranging from 0.1 to 0.2 are sug-
gested, which make the level shifter delay equal to 10%20%
of the latch delay. By inverting (9), the resulting level shifter
bias current is
(18)
where it was observed that the term
is much greater than unity for submicrometer
technologies (for example, is equal to 17.8
for the adopted 0.18- m process). For the adopted CMOS
. process, this approximation leads to an error lower than 20%
as compared to the exact expression for and and
rapidly tends to zero for greater values of and . From (15)
and (17), the level shifter current of the th stage is
be
(19)
The design equations (18), (19) express the bias currents of the
generic th stage (including the first one) as a function of the
parameters and , which have been preliminarily assigned
in the design of the first stage, as discussed in Section IV-A.

C. Simplified Design Procedure

To quickly evaluate the stage bias currents, an easy scaling
law through the divider stages can be found by approximating
(15) (18). Indeed, from (18), the ratio of the latch current of the
th stage and the preceding th stage results to
where the transistor aspect ratio is minimum due
to the small load capacitance of the level shifter (simulations
also confirmed that a nonminimum always leads to a with
speed degradation). (20)
From the above design considerations, the maximum fre- where the approximation hold if , which from (13)
quency allowed by a 1:2 divider stage results to and (14) is certainly true for and still provides reasonably
accurate results even for . Indeed, the approximation of
(16) the scaling factor (20) to 0.7 leads to a current ratio overestima-
tion by at most 21% in the worst case and and
where the first factor is the frequency limit imposed by the much lower for greater values. Hence, in practical designs, it
adopted technology, and terms and are chosen as previ- is sufficient to size the first-stage bias current according to (12)
ously discussed. and then progressively downscale the currents of the successive
stages by a factor of 0.7.
B. Design of the Successive Stages In each stage, the level shifter bias current is still evaluated
by substituting into (19).
As already discussed in Section II, the successive stages are
not needed to be as fast as the previous ones under a given speed
requirement; thus, their bias currents can be progressively re- V. DESIGN EXAMPLES AND VALIDATION
duced to achieve a power saving. To be more specific, from (1) To verify the theoretical derivations, a 1:8 frequency divider
and (3), each stage is allowed to have a latch delay that is twice was designed and simulated with SPICE by using a 0.18- m
that of the preceding stage, and the same consideration holds for CMOS process. By substituting the coefficients reported in
the level shifter. This means that the ratio of the th stage in Table II and setting V, mV, and
(11) is twice that of the previous th stage; thus , the two above-discussed design methodologies were
applied, i.e., the high-speed design and the minimum PDP
with (17) design, by respectively setting to 2 and to (14). Moreover,
ALIOTO et al.: DESIGN OF HIGH-SPEED POWER-EFFICIENT MCML FREQUENCY DIVIDERS
TABLE III
BIAS CURRENTS WITH EXACT CURRENT SCALING IN (20)
Fig. 4. Input and output waveform of a 1:8 frequency divider (high-speed de-
sign, exact current scaling factor).
TABLE IV
BIAS CURRENTS WITH APPROXIMATE CURRENT SCALING IN (20)
the currents in the various 1:2 stages were scaled by using the
exact and the approximate current scaling factor in (20) (i.e.,
and 0.7, respectively).
The bias currents obtained for the high-speed and minimum
PDP frequency dividers with exact scaling factor in (20) are
reported in Table III, where all the level shifters bias currents
were increased to 1 A to avoid subthreshold operation. In the
high-speed design, the resulting maximum predicted frequency
(16) is equal to 415 MHz, whereas in the minimum PDP design,
it is equal to 335 MHz. Simulation results showed that the max-
imum operating frequency of the divider is 510 MHz (394 MHz)
for the high-speed (minimum PDP) design; thus, the error of
(16) is within 18% of the simulated value. This confirms the
adequate accuracy of the analytical design equations. As an ex-
ample, the input and output waveforms are plotted in Fig. 4 for
the high-speed design case with exact current scaling factor in
(20).
Finally, Table IV summarizes the bias currents of the divider
1:2 stages in both the high-speed design and the minimum PDP
design by using the approximate current scaling factor of 0.7 in
(20), which makes the design easier. As expected, comparison
of Tables III and IV shows that the bias currents are greater
than those obtained with an exact scaling factor. According to
the considerations in Section IV-C, this leads to only a slight
increase in the power consumption of about 12% (9%) in the
1169
case of high-speed (minimum PDP) design as compared to the
power consumption obtained with an exact scaling factor.
VI. CONCLUSION
In this brief, a strategy to design MCML static frequency di-
viders has been proposed. The strategy starts from the timing
model of MCML gates in [2] and [3] and aims at achieving high
speed with reasonable power consumption. To this purpose, an
analytical expression of the first-stage bias current has been pro-
vided to exploit the speed potential of the adopted technology.
From analytical considerations, the authors suggest to set the
latch delay to twice its minimum value allowed by the tech-
nology when the speed performance is of utmost importance and
to a value greater than two [see (14)] when an optimum balance
between power consumption and delay is desired. In regard to
the first-stage level shifter, it is suggested to set its bias current
to make its delay to about 20% of the latch delay.
To reduce the overall power consumption, analytical criteria
are derived to progressively scale the bias currents of the succes-
sive stages. In particular, it is shown that the latch bias current
of each stage can be downscaled by a factor of 0.7 as compared
to that of the previous stage. This affords a significant power
saving as compared to the case of equally biased stages.
The analytical design equations are general and can be used
for pencil-and-paper evaluations, thereby avoiding a tedious and
time-consuming trial-and-error approach based on simulations.
Moreover, the analytical approach allows for a deeper under-
standing of the powerdelay tradeoff involved in the design.
As a design example, a 1:8 frequency divider is designed and
simulated by using a 0.18- m CMOS process by assuming dif-
ferent powerdelay requirements. Results show that the max-
imum operating frequency of the divider is always within 18%
of the simulated value, thereby confirming the adequate accu-
racy of the analytical design equations.
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