5728
12, DECEMBER 2013
A Zero-Voltage Switching Full-Bridge DCDC
Converter With Capacitive Output Filter for Plug-In
Hybrid Electric Vehicle Battery Charging
Deepak S. Gautam, Student Member, IEEE, Fariborz Musavi, Senior Member, IEEE, Wilson Eberle, Member, IEEE,
and William G. Dunford, Senior Member, IEEE
AbstractIn this paper, a novel zero-voltage switching full-
bridge converter with trailing edge pulse width modulation and
capacitive output filter is presented. The target application for this
study is the second stage dcdc converter in a two stage 1.65 kW
on-board charger for a plug-in hybrid electric vehicle. For this
application the design objective is to achieve high efficiency and
low cost in order to minimize the charger size, charging time, and
the amount and the cost of electricity drawn from the utility. A
detailed converter operation analysis is presented along with sim-
ulation and experimental results. In comparison to a benchmark
full-bridge with an LC output filter, the proposed converter re-
duces the reverse recovery losses in the secondary rectifier diodes,
therefore, enabling a converter switching frequency of 100 kHz.
Experimental results are presented for a prototype unit converting
400 V from the input dc link to an output voltage range of 200
450 V dc at 1650 W. The prototype achieves a peak efficiency of
95.7%.
Index TermsBattery charger, capacitive filter, dcdc converter,
full-bridge, plug-in hybrid electric vehicle (PHEV), resonant con-
verters, zero-voltage switching (ZVS).
I. INTRODUCTION
PLUG-IN hybrid electric vehicle (PHEV) is a hybrid elec-
A tric vehicle with rechargeable batteries that can be restored
to full charge by connecting the vehicle plug to an external elec-
tric power source. In recent years, PHEV motor drive and energy
storage technology have developed at a rapid rate in response
to expected market demand for PHEVs. Battery chargers are
another key components required for the emergence and ac-
ceptance of PHEVs. For PHEV applications, most commonly
on-board chargers are used.
The most common charger power architecture includes an
acdc converter with power factor correction (PFC) [1][7]
followed by an isolated dcdc converter. Galvanic isolation is
Manuscript received October 31, 2012; revised January 16, 2013;
accepted February 11, 2013. Date of current version June 6, 2013. This work
was supported and sponsored by Delta-Q Technologies Corp. Recommended
for publication by Guest Editor-in-Chief Ali Emadi and Associate Editor
M. Krishnamurthy.
D. Gautam and F. Musavi are with Delta-Q Technologies Corp., Burnaby, BC
V5G 3 H3 Canada (e-mail: dgautam@delta-q.com, fmusavi@delta-q.com).
W. Eberle is with the School of Engineering, University of British Columbia,
Kelowna, BC V6T 1Z4 Canada (e-mail: Wilson.eberle@ubc.ca).
W. G. Dunford is with the Department of Electrical Engineering, University of
British Columbia, Vancouver, BC V6 T 1Z4 Canada (e-mail: wgd@ece.ubc.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2249671
0885-8993/$31.00 2013 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.
required in onboard battery chargers in order to meet the double
fault protection for the PHEV user safety [8][10].
Many high efficiency full-bridge dcdc converter solutions
have been proposed that are potential candidates for the isolated
dcdc converter in a PHEV charger [11][27]. The phase-shifted
zero voltage switching (ZVS) pulse width modulated (PWM)
dc-to-dc full-bridge converter was presented in [11][13]. ZVS
for the switches is realized by using the leakage inductance of
the transformer in addition to an external inductor and the output
capacitance of the switch. Although various improvements have
been suggested for this converter, including [14][23], these
solutions increase the component count and suffer from one
or more disadvantages including, a limited ZVS range, high
voltage ringing on the secondary side rectifier diodes, or duty
cycle loss. The wide ZVS range of operation is discussed in
[15], [20][22]. The high voltage ringing on the secondary side
rectifier diodes is addressed in [16], [18], [19] and [23][27].
Duty cycle loss is reviewed in [17]. A new complementary
gating scheme for the full-bridge dc-to-dc PWM converter is
presented in [28]. This gating scheme requires an additional zero
voltage transition circuit to achieve ZVS for all the switches for
a wide variation in the load current.
Current fed topologies with capacitive output filter inherently
minimize diode rectifier ringing since the transformer leakage
inductance is effectively placed in series with the supply side
inductor [29][34]. In addition, high efficiency can be achieved
with ZVS, in particular the trailing edge PWM full-bridge gating
scheme proposed in [35] is an attractive solution to achieve ZVS.
In this paper, a novel PWM ZVS full-bridge dcdc converter
with the trailing edge pulse width modulation and capacitive
output filter is presented.
The paper is organized as follows: section II presents the
converter operating modes. A step-by-step design procedure is
provided in Section III, followed by simulation and experimental
results in Section IV. The conclusions are presented in Section V.
II. OPERATING PRINCIPLES
The proposed ZVS full-bridge converter topology is illus-
trated in Fig. 1. The converter primary side circuit consists of
a traditional full-bridge inverter. However, rather than driving
the diagonal bridge switches simultaneously, the lower switches
(Q3 and Q4) are driven at a fixed 50% duty cycle and the upper
switches (Q1 and Q2) are PWM on the trailing edge [35].
Although the proposed converter can operate in either dis-
continuous conduction mode (DCM) [33], boundary conduction
GAUTAM et al.: ZERO-VOLTAGE SWITCHING FULL-BRIDGE DCDC CONVERTER WITH CAPACITIVE OUTPUT FILTER
Fig. 1. PWM ZVS full-bridge converter topology with a capacitive output
filter.
Fig. 2. Typical operating waveforms to illustrate the operation of the ZVS
full-bridge converter in a DCM mode.
mode (BCM), or continuous conduction mode (CCM), only the
DCM and BCM modes are desirable, as discussed in section III.
The detailed circuit operation in all three modes is given next.
This converter has six operating intervals for DCM, BCM, or
CCM. The operating intervals are determined by the ON/OFF
states of the four primary switches. Detailed operating wave-
forms are provided for DCM in Fig. 2, for BCM in Fig. 3 and
for CCM in Fig. 4. In the analysis that follows, the power semi-
conductor switches have been modeled with parallel diodes and
parasitic capacitances. All parasitic capacitances in the circuit
including winding and heatsink capacitance have been lumped
together with the switch output capacitance. The output recti-
fiers are considered ideal and the external resonant inductor also
includes the transformer leakage inductance.
5729
Fig. 3. Typical operating waveforms to illustrate the operation of the ZVS
full-bridge converter in a BCM mode.
A. Interval 1 (T 0T 1)
Referring to Figs. 24, during Interval 1 (T0T1), switches
Q1 and Q4 are ON and Q2 and Q3 are OFF. This is a power
transfer interval and the primary current flows through Q1, res-
onant inductor LR , transformer primary and Q4, as illustrated
in Fig. 5. The rate of rise of the current (di/dt) through LR is
proportional to the difference between the input voltage Vin and
the output voltage Vo . During this mode power flows to the out-
put through rectifier diodes DR 1 and DR 4 and also energy is
stored in LR . The resonant inductor current iL R (t) using initial
condition iL R (0) = 0 is given by
 
Vin Vno
iL R (t) = (t To ). (1)
LR
B. Interval 2 (T1T2)
1) Case (a): Operating in DCM: Referring to Fig. 2, inter-
val 2 begins after switch Q1 turns OFF, as determined by the
PWM duty cycle. Since the current flowing in the primary side
cannot be interrupted instantaneously, it finds an alternate path
and flows through the parasitic switch capacitances of Q3 and
Q1 which discharges the node a to 0 V and then forward
biases the body diode D3. During this switch transition, the
5730
Fig. 4. Typical operating waveforms to illustrate the operation of the ZVS
full-bridge converter in a CCM mode.
Fig. 5. Equivalent circuit for Interval 1 (T0T1) for DCM, BCM and CCM.
Fig. 6. Equivalent circuit for Interval 2 (T1T2) for DCM, BCM, and CCM
and Interval 3 (T2T3) for BCM.
energy stored in the resonant inductor LR assists in transferring
energy from the lower to upper bridge MOSFET capacitances.
Therefore switches Q3 and Q4 always achieve ZVS with the
help of the energy stored in the resonant inductor LR for nearly
the entire load current Io range. During this interval the energy
stored in LR is transferred to the output. The primary resonant
inductor LR maintains the current, which circulates around the
path of D3, resonant inductor LR , transformer primary and Q4,
as illustrated in Fig. 6. The rate of the downslope of the cur-
rent through LR is proportional to the output voltage Vo . At
T 2 the energy stored in LR is transferred to the output and the
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013
Fig. 7. Equivalent circuit for Interval 3 (T2T3) for CCM.
current becomes zero and the rectifier diodes DR 1 and DR 4
turn OFF. The resonant inductor current iL R (t) using initial
condition iL R (0) = IP 1 is given by
Vo
iL R (t) = IP 1 (t T1 ). (2)
nLR
2) Case (b): Operating in BCM and CCM: Referring to Figs.
3 and 4, the only difference in BCM or CCM as compared to
DCM during Interval 2 is that the current through the resonant
inductor does not reach zero at T 2 and the rectifier diodes DR 1
and DR 4 are ON. At the end of this interval, iL R (t) = IP 2 .
Fig. 6 illustrates the equivalent circuit for this interval.
C. Interval 3 (T2T3)
1) Case (a): Operating in DCM: Referring to Fig. 2, during
this interval no power is transferred to the secondary. Accord-
ingly, this interval is a passive interval. In this interval, the
parasitic capacitances of the rectifier diodes resonate with LR .
This resonance appears across the rectifier diodes DR 1 and DR 4
as illustrated in Fig. 2. For this interval, current in the resonant
inductor remains zero (iL R = 0).
2) Case (b): Operating in BCM: During this interval the
resonant inductor current continues to circulate around the path
of D3, resonant inductor LR , transformer primary and Q4, as
illustrated in Figs. 3 and 6. The rate of the downslope of the
current through LR is proportional to the output voltage Vo . At
T 3 the entire energy stored in LR is transferred to the output and
the current becomes zero and the rectifier diodes DR 1 and DR 4
turn OFF. The resonant inductor current iL R (t) using initial
condition iL R (0) = IP 2 is given by
Vo
iL R (t) = IP 2 (t T2 ). (3)
nLR
3) Case (c): Operating in CCM: Referring to Figs. 4 and 7,
in CCM at T 2, Q3 and Q4 toggle. The timing of this toggle is
dependent on the resonant delay which occurs prior to Q2 turn-
ing ON. When Q3 and Q4 toggle, the primary resonant inductor
current that was flowing through Q4 finds an alternate path by
charging/discharging the parasitic capacitances of switches Q4
and Q2 until the body diode of Q2 is forward biased. If the
resonant delay is set properly, switch Q2 can be turned ON with
ZVS. At T 3 the entire energy stored in LR is transferred to
the output and the current becomes zero and the rectifier diodes
DR 1 and DR 4 turn OFF. The resonant inductor current iL R (t)
using initial condition iL R (0) = IP 2 is given by
 
Vin + Vno
iL R (t) = IP 2 (t T2 ). (4)
LR
GAUTAM et al.: ZERO-VOLTAGE SWITCHING FULL-BRIDGE DCDC CONVERTER WITH CAPACITIVE OUTPUT FILTER 5731

TABLE I
DESIGN SPECIFICATIONS

Fig. 8. Equivalent circuit for Interval 4 (T3T4) for DCM, BCM, and CCM.

Fig. 9. Equivalent circuit for Interval 5 (T4T5) for DCM, BCM and CCM
and Interval 6 (T5T6) for BCM.

Fig. 10. Equivalent circuit for Interval 6 (T5-T6) for CCM.

D. Interval 4 (T3T4) Through Interval 6 (T5T6)

Intervals 4 to 6 are the negative equivalent of Intervals 1 to 3 Fig. 11. Design curve obtained for gain versus duty cycle for various values
as shown in Figs. 810. of k in DCM and BCM.

III. DESIGN CONSIDERATION the transformer, Ro is the load resistance, and T is the switching
The proposed converter can operate in DCM, BCM, or CCM. period
When the converter is operated in DCM, or BCM, the 50% fixed Vo 2n
duty cycle controlled switches (Q3 and Q4) can achieve both MDCM = =  . (5)
Vin 1+ 1+ 4k
ZVS turn-on and ZCS turn-off, and also the PWM controlled D2
switches (Q1 and Q2) can achieve ZCS turn-on. In addition, The normalized time constant of the converter is given by
the secondary-side rectifier diodes can achieve ZCS, which sig-
nificantly reduces the reverse recovery losses due to the low 4n2 LR
k= . (6)
di/dt. As an additional benefit, the voltage across the diodes is Ro T
clamped to the output voltage, enabling the use of lower break- The converter dc gain in BCM is given by
down voltage diodes and eliminating the use of lossy RCD volt-
age clamps, which are typically required in traditional CCM Vo
MBCM = = Dn. (7)
dcdc converters with inductive output filters [11][13]. When Vin
operated in BCM, the converter retains the advantages of DCM, The converter is designed to meet the specification shown in
but also has relatively low RMS currents, decreasing conduction Table I.
loss. Operation in CCM results in the lowest RMS currents and To meet the specifications, the transformer turns ratio n is
ZVS can be achieved for all switches, but the high di/dt results designed for Vin = 400 V, Vom ax = 450 V at maximum duty
in large reverse recovery losses in the secondary side rectifier cycle of Dm ax = 0.96. The transformer turns ratio is given by
diodes and high voltage ringing. Moreover to operate this con-
Vo m ax
verter in CCM, it requires a larger resonant inductor which also n= = 1.17. (8)
increases the transformer turns ratio, and thus increases stress Dm ax Vin
on the primary side switches. Thus, this converter should be Using (5) to (8) the design curves shown in Fig. 11 are pro-
designed to operate in DCM, or BCM. vided for gain versus duty cycle for various values of k in DCM
The converter dc gain in DCM (MDCM ) is given by equation and BCM. To operate the converter in BCM at maximum output
(5), where n is the transformer turns ratio, D is the duty cycle, current of Io = 5.5 A and Vo = 300 V (Pom ax = 1.65 kW),
k is the normalized time constant of the converter, LR is the k = 0.33 is selected. Then the resonant inductor LR = 33 H
resonant inductor which also includes the leakage inductance of is selected using equation (6).
5732 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013

TABLE II TABLE III

COMPONENT SELECTION SUMMARY COMPARISON OF VARIOUS PARAMETERS OBTAINED FROM SIMULATION AND
ANALYSIS AT 5.5 AND 0.7 A LOAD AND 400 V INPUT.

The RMS current through the switches Q1 and Q2, IQ 12(rm s)

is given as


1 T1
IQ 12(rm s) = iL R (t)2 dt = 4.35[A]. (9)
T T0
The RMS current through the switches Q3 and Q4, IQ 34(rm s)
is given by
  
T1  T3
1
IQ 34(rm s) = iL R (t)2 dt + iL R (t)2 dt
T T0 T1

= 5.42[A]. (10)
The average current through the antiparallel diodes of
switches Q3 and Q4, ID Q 34(ave) is given by

1 T3
ID Q 34(ave) = iL R (t) dt = 1.17[A]. (11)
T T1
A switch with voltage rating >Vin (= 400 V) and current
rating greater than the RMS currents given by (9) and (10) is
selected.
The average current through the output rectifier diodes DR 1
to DR 4 , ID R (ave) is given as
Fig. 12. Experimental prototype of the 1.65 kW ZVS full-bridge dcdc con-
Io verter with capacitive output filter.
ID R (ave) = = 2.75[A]. (12)
2
A fast recovery diode with voltage rating > Vom ax and current simulation are listed in Table III at Vin = 400 V and Io = 5.5 A
rating greater than obtained in (12) is selected. The RMS current and 0.7 A. As can be observed, there is a close match between
through the output filter capacitor Co2 is given by (13) and its the theoretical prediction and simulation results.
capacitance value is determined using (14) A 1.65 kW experimental prototype was built to verify the op-

 TP eration of the proposed converter. A photograph of the prototype
1
IC o2(rm s) = (iREC (t) Io )2 dt = 3.4[A] (13) is provided in Fig. 12.
TP 0 Figs. 13 and 14 provide the experimental waveforms for DCM
and BCM, respectively. It is noted that the MOSFET Q3 turns
IC o2(rm s) ON with ZVS and turns OFF with ZCS and the current through
C02 = = 5.4[F]. (14)
4fs Vripple the resonant inductor also has a very low di/dt.
Figs. 15 and 16 provide the voltage across and current through
An output filter capacitor with capacitance value >5.4 F
rectifier diode DR 3 in DCM and BCM, respectively. The voltage
as calculated using (14), with a voltage rating > Vom ax and
across the diode is clamped to the output voltage, at Vo = 300 V,
current rating greater than obtained in (13) is selected. The
and the di/dt through the diode is low enough to minimize the
various components selected for the circuit are listed in Table II.
losses due to reverse recovery issues inherent with ultrafast
diodes. Waveforms of the ripple free output voltage and current
IV. SIMULATION AND EXPERIMENTAL RESULTS
are provided in Fig. 17 at Vo = 300 V and Io = 5.5 A.
The performance of the converter designed in Section III was Curves of the measured efficiency of the converter versus
evaluated using PSIM. Simulations were run varying the output output power at Vin = 400 V and output voltages of 150, 200,
voltage and output load conditions. Circuit parameters, includ- 300 and 400 V are provided in Fig. 18. With the proposed dcdc
ing component stresses, obtained from theoretical analysis and converter a peak efficiency of 95.7% is achieved at Vo = 400 V
GAUTAM et al.: ZERO-VOLTAGE SWITCHING FULL-BRIDGE DCDC CONVERTER WITH CAPACITIVE OUTPUT FILTER
Fig. 13. Proposed converter experimental waveforms of the MOSFET Q3
voltage and resonant inductor L R current at V in = 400 V, V o = 300 V, P o =
200 W and fs = 100 kHz. Ch1 = V D S Q3 200 V/div. Ch2 = ILR 5 A/div.
Ch3 = V G S Q3 10 V/div. Time scale = 1.16 s/div.
Fig. 14. Proposed converter experimental waveforms of the MOSFET Q3
voltage and resonant inductor L R current at V in = 400 V, V o = 300 V, P o =
1650 W and fs = 100 kHz. Ch1 = V D S Q3 200 V/div. Ch2 = ILR 5 A/div.
Ch3 = V G S Q3 10 V/div. Time scale = 1.16 s/div.
Fig. 15. Proposed converter experimental waveforms of the Diode D R 3 volt-
age and current at V in = 400 V, V o = 300 V, P o = 200 W and fs = 100 kHz.
Ch1 = VDR 3 200 V/div. Ch2 = IDR 3 5 A/div. Time scale = 900 ns/div.
and Po = 1.2 kW. High efficiency over the entire load range is
achieved with this solution.
Fig. 19 provides an efficiency comparison including a bench-
mark ZVS full-bridge dcdc converter with inductive out-
5733
Fig. 16. Proposed converter experimental waveforms of the Diode D R 3 volt-
age and current at V in = 400 V, V o = 300 V, P o = 1650 W and fs = 100 kHz.
Ch1 = VDR 3 100 V/div. Ch2 = IDR 3 5 A/div. Time scale = 900 ns/div.
Fig. 17. Proposed converter experimental waveform of output voltage and
current at V o = 300 V and Io = 5.5 A and fs = 100 kHz. Ch1 = V o 100 V/div.
Ch2 = Io 2 A/div. Time scale = 5 ms/div.
Fig. 18. Experimental measured efficiency of the proposed converter as a
function of output power at 400 V input and different output voltages.
put filter and two versions of the proposed converter using:
ISL9R0860 (Stealth ultra-fast diodes) and IDH06S60C (SiC)
secondary rectifier diodes. The benchmark converter circuit is
illustrated in Fig. 20 and a list of its components is provided in
Table IV.
5734 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013
Fig. 19. Efficiency comparison for the proposed converter as a function of
output power at 400 V input and 300 V output voltage for different rectifier
diodes and benchmark converter.
Fig. 20. Schematic of the benchmark ZVS full-bridge converter with inductive
output filter.
TABLE IV
COMPONENTS USED IN THE BENCHMARK CONVERTER
The overall efficiency of the proposed converter, particularly
at light load conditions, is much higher than the benchmark
converter. The benchmark converter has lower efficiency due
to losses in the secondary side RCD clamp circuit. The per-
formance of the proposed converter with Stealth diodes is very
similar to that with silicon carbide (SiC) diodes. Therefore, this
converter permits use of inexpensive hyperfast diodes, which
are typically one quarter of the price of SiC diodes.
V. CONCLUSION
A novel ZVS full-bridge dcdc converter with capacitive out-
put filter has been presented for application in PHEV battery
charging. The detailed operating intervals in DCM, BCM, and
CCM were presented in addition to a step by step design pro-
cedure, simulation results and experimental waveforms. The
proposed topology achieves soft switching for the full-bridge
primary switches, naturally clamps the voltage across the out-
put rectifier to the output voltage and the current through the
rectifier diodes has a low di/dt, which helps to minimize reverse
recovery losses.
It has been shown that the converter achieves an overall
peak efficiency of 95.7% at Vo = 400 V with inexpensive hy-
perfast diodes. Finally, the converter performance in terms of
cost, size, and efficiency is superior to its inductive output filter
counterpart.
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Deepak S. Gautam (S11) received the B.E. degree
in electronics engineering from Mumbai University,
Maharashtra, India, in 2000, and the M.A.Sc. degree
in electrical engineering from the University of Vic-
toria, BC, Canada, in 2006. He is currently working
toward the Ph.D. degree in electrical engineering in
the field of power electronics from the University of
British Columbia, Vancouver, BC, Canada.
From 2000 to 2003, he worked as a Research and
Development Engineer for the Power Conversion and
Control division of Aplab Limited, Mumbai, India
where he was involved in the development of linear, switch-mode, and pro-
grammable power supplies for industrial and telecom industries. Since 2007, he
has been working for Delta-Q Technologies Corp., Burnaby, BC, Canada as a
Power Electronics Engineer where his main responsibility is to develop high-
frequency switch-mode battery chargers for automotive and industrial applica-
tion. His research interests are dcdc converters, acdc power factor correction
converters, resonant converters, and feedback control circuits.
Mr. Gautam has received the University of Victoria fellowship, the Andy
Farquharson award for excellence in graduate student teaching and best poster
presentation award at the APEC 2012 conference in Orlando, FL, USA. He also
has won travel grants from the Power Source Manufacturers Association, the
IEEE Industry Application Society, and Power Electronics Society to present
papers at conferences.
5735
Fariborz Musavi (S10M11SM12) received the
B.Sc. degree from Iran University of Science and
Technology, Tehran, Iran, in 1994, the M.Sc. degree
from Concordia University, Montreal, QC, Canada, in
2001, and the Ph.D. degree in electrical engineering
with emphasis in power electronics from the Univer-
sity of British Columbia, Vancouver, BC, Canada.
Since 2001, he has been with several high-tech
companies including EMS Technologies Inc., Mon-
treal; DRS Pivotal Power, Bedford, NS, Canada; and
Alpha Technologies, Bellingham, WA, USA. He is
currently with Delta-Q Technologies Corporation, Burnaby, BC, Canada, where
he is the Manager of Research, Engineering and is engaged in research on the
simulation, analysis, and design of battery chargers for industrial and automotive
applications. His current research interests include high-power high-efficiency
converter topologies, high-power-factor rectifiers, electric vehicles, and sustain-
able and renewable energy sources.
Dr. Musavi is a Registered Professional Engineer in the Province of BC,
Canada. He received the First Prize Paper Award from the IEEE Industry Appli-
cations Society Industrial Power Converter Committee in 2011. He also received
an award from the Power Sources Manufacturers Association to present papers
at conferences.
Wilson Eberle (S98M07) received the B.Sc.,
M.Sc., and Ph.D. degrees from the Department of
Electrical and Computer Engineering, Queens Uni-
versity, Kingston, ON, Canada, in 2000, 2003, and
2008, respectively.
He is currently an Assistant Professor with the
School of Engineering, The University of British
Columbia, Kelowna, BC, Canada. His industrial ex-
perience includes positions with Ford Motor Com-
pany, Windsor, ON, Canada, and with Astec Ad-
vanced Power Systems, Nepean, ON, Canada. He is
the holder of one U.S. patent. He is the author or coauthor of more than 40 tech-
nical papers published in various IEEE international conference proceedings
and IEEE journals. His current research interests include high-efficiency high-
power-density dcdc converters, and acdc power factor correction circuits.
Dr. Eberle received the Ontario Graduate Scholarship and awards from the
Power Sources Manufacturers Association and the Ontario Centres of Excel-
lence. He currently holds research grants from the Natural Sciences and Engi-
neering Research Council of Canada, the Canada Foundation for Innovation,
The University of British Columbia, and the Kaiser Foundation for Higher Ed-
ucation.
William G. Dunford (S78M81SM92) received
the B.Sc. (Eng.) and M.Sc. degrees in machines and
power systems from Imperial College, London, U.K.,
in 1971 and 1972, respectively, and the Ph.D. de-
gree in power electronics from University of Toronto,
Toronto, ON, Canada, in 1982.
He has been a Faculty Member with Imperial Col-
lege London and the University of Toronto and is
currently a Faculty and Senate Member with The Uni-
versity of British Columbia, Vancouver, BC, Canada.
His industrial experience includes positions with the
Royal Aircraft Establishment (now Qinetiq), Schlumberger, and Alcatel. He has
had a long-term interest in photovoltaic powered systems and is also involved in
projects in the automotive and distributed systems areas. Dr. Dunford has served
in various positions on the Advisory Committee of the IEEE Power Electronics
Society and chaired IEEE PESC in 1986 and 2001.