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2366 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO.

12, DECEMBER 2000

Polysilicon Quantization Effects on the Electrical


Properties of MOS Transistors
Alessandro S. Spinelli, Member, IEEE, Andrea Pacelli, Member, IEEE, and Andrea L. Lacaita, Senior Member, IEEE

Abstract—The quantum-mechanical behavior of charge heavily-doped polysilicon, where the band bending is usually of
carriers at the polysilicon/oxide interface is investigated. It is the order of a few tens of millivolts.
shown that a dark space depleted of free carriers is created at the In this work, we investigate the effects of QM behavior in
interface as a consequence of the abrupt potential energy barrier,
which dominates the polysilicon capacitance and voltage drop in polysilicon on the electrical properties of MOS transistors. For
all regions of operation of modern MOS devices. Quantum-me- the first time, a full quantum simulation of the entire polysil-
chanical effects in polysilicon lead to a reduction in the gate icon/oxide/silicon system is carried out. In the next section, the
capacitance in the same way as substrate quantization, and to a dark-space effect at the polysilicon/oxide interface is briefly de-
negative voltage shift, which is opposed to the positive shift caused scribed. Then, in Section III, we discuss the application of a
by carrier quantization in the channel. Effects on the extraction of
device physical parameters such as oxide thickness and polysilicon one-dimensional (1-D) quantum model to heavily-doped poly-
doping are also addressed. crystalline silicon. In Section IV the impact of QM effects in
polysilicon on the physical gate oxide thickness and polysilicon
Index Terms—MOS devices, MOSFETs, quantization, semicon-
ductor device modeling. doping extraction are evaluated on the basis of extensive device
simulations. In Section V, the impact on the device threshold
voltage is addressed, showing that QM effects at the polysil-
I. INTRODUCTION icon/oxide interface result in a negative threshold voltage shift,
as opposed to the positive shift induced by channel quantization.
T HE increased manufacturing capabilities of the semicon-
ductor industry have led to the fabrication of MOS tran-
sistors with gate lengths well below 0.1 m. The gate oxide
thickness which is needed in order to avoid short-channel ef- II. THE DARK-SPACE EFFECT
fects and reduce the threshold voltage is in the range 1.5 to 3
In normal MOSFET operation, the heavily doped polysil-
nm. In dealing with such characteristic lengths, it is now widely
icon is switched between accumulation and depletion. When
accepted that quantum-mechanical (QM) effects must be taken
in accumulation, the band bending in the polysilicon is of the
into account. Also, the finite series capacitance of the polysil-
order of a few tens of millivolts at most, while in depletion,
icon gate can no longer be neglected, since it has a significant
carriers are repelled from the poly-oxide interface. In neither
impact on the device performance [1].
case a deep quantum well is formed. For this reason, a classical
Since the pioneering works in the 1970s [2], considerable ef-
(CL) treatment of the charge distribution in the poly has been al-
fort has been devoted to the theoretical analysis and modeling
ways assumed, whether the channel was treated in a classical or
of QM effects in MOS inversion layers [3]–[7]. Later on, also
quantum-mechanical framework. However, both accumulation
majority-carrier quantization in strongly accumulated MOS sur-
and depletion of carriers occur within a distance from the oxide
faces has been given attention [8]–[10], due to its impact on the
comparable with the de Broglie wavelength of charge carriers,
gate tunneling current and capacitance. On the other hand, it
so that QM effects must be accounted for. In Fig. 1 the electron
was usually assumed that for small band bending, no QM ef-
concentration in the n -polysilicon of an n-MOS capacitor with
fects occurred. In particular, polysilicon depletion and accumu-
oxide thickness of 5 nm is plotted as a function of the distance
lation was always treated in a classical framework [1], [11], [12].
from the polysilicon/oxide interface, as obtained from a clas-
Recently, we have demonstrated that a significant QM effect
sical simulation and from a self-consistent Schrödinger-Poisson
occurs also when the device is biased near flat bands, and no
solver [14]. Results are shown in conditions of accumulation
splitting of the energy levels occurs [13]. This effect is partic-
( 2 V), at threshold ( 1 V), and in strong inversion
ularly interesting for the case of depletion and accumulation in
( 5 V). For simplicity, this system (n -polysilicon, p-sub-
strate) will be assumed in the rest of the paper. We note that
Manuscript received October 18, 1999; revised July 3, 2000. The review of for positive gate voltages, both gate and substrate are depleted,
this paper was arranged by Editor J. M. Vasi. while for negative voltages, both are accumulated. Significant
A. S. Spinelli is with the Dipartimento di Scienze Chimiche, Fisiche e Matem- differences can be seen between the CL and QM charge distribu-
atiche, Università degli Studi dell’Insubria, and Istituto Nazionale di Fisica della
Materia, Milano-Università, 22100 Como, Italy (e-mail: spinelli@fis.unico.it). tions in accumulation conditions, where the CL solution peaks
A. Pacelli is with the Department of Electrical and Computer Engineering, right at the interface. As a consequence of the presence of the
State University of New York, Stony Brook, NY 11794-2350 USA. abrupt energy barrier, interference among the majority-carrier
A. L. Lacaita is with the Dipartimento di Elettronica e Informazione, Politec-
nico di Milano, 20133 Milano, Italy. wavefunctions takes place, and the QM charge is pushed away
Publisher Item Identifier S 0018-9383(00)10402-2. from the interface. Hence, a so-called “dark space” is created,
0018–9383/00$10.00 © 2000 IEEE
SPINELLI et al.: ELECTRICAL PROPERTIES OF MOS TRANSISTORS 2367

Fig. 1. Electron concentration in the n-type polysilicon of a 5 nm gate oxide


thickness nMOS device. The polysilicon doping is 10 cm . Results are Fig. 2. Comparison among the electron dark space, the semiconductor
shown according to a classical (CL) and a QM model, for different gate bias screening length and the polysilicon depletion layer at an oxide electric field
conditions in accumulation, at threshold voltage V and at 5 V. of 1 mV cm . The electron mean free path for ionized impurity scattering is
also shown.

where the carrier concentration is reduced with respect to the


rise of the charge distribution with respect to the classical model
dopant concentration. The extent of the dark space can be ap-
is obtained.
proximately computed at flat bands as [13]
To assess the importance of QM effects in the polysilicon,
Fig. 2 shows the electron dark space obtained from (1) and the
(1) electron screening length obtained from an accurate cal-
culation accounting for Fermi–Dirac statistics. Both quantities
where is a typical energy of the carriers above the conduc- are plotted as functions of the polysilicon doping concentration
tion-band edge, . In a nondegenerate approximation, . The screening length tends to the classical Debye value
, while in a degenerate semiconductor , (proportional to ) for low values of , while it follows
where is the Fermi level. In silicon, is of the order of 2 the Thomas–Fermi dependence (proportional to ) as
to 3 nm for both electrons and holes. The dark space is a direct increases above degeneracy. It can be seen that the dark space re-
consequence of the abrupt potential energy barrier, and there- mains markedly larger than the semiconductor screening length
fore exists also for unconfined conditions in the polysilicon, for dopings higher than about cm . A reduction in
as at flat bands [13]. When the device is biased in the strong the gate capacitance, similar to what is obtained with substrate
accumulation condition, a potential well forms, increasing the quantization, is hence expected in strong accumulation. Fig. 2
average energy of the carriers above the band edge, hence re- shows also the value of the classical polysilicon depletion layer
ducing the value of below what predicted by (1) (see results at an oxide electric field of 1 MV cm , which is a typical value
for 2 V). at threshold. For polysilicon dopings higher than about
A significant difference between the CL and QM charge dis- cm , the polysilicon depletion layer becomes smaller than the
tributions can be seen even when the polysilicon is biased in de- dark space, and QM effects are expected to become important
pletion. In fact, as long as the (classical) polysilicon depletion also in strong inversion.
layer width is comparable with or smaller than the dark space,
the depleted layer will be determined by quantum effects, and
III. CARRIER QUANTIZATION IN HEAVILY DOPED POLYSILICON
will be larger than the classical value. This “QM widening” of
the depletion layer can be seen in the electron concentration at Quantization of electrons and holes at boundaries of single-
threshold, also shown in Fig. 1. Note that for this high polysil- crystal, low-doped silicon is a known and extensively studied
icon doping, the electron concentration at the interface is only effect. Quantization in polysilicon, instead, has received only
slightly reduced in the CL treatment at threshold, while is sig- cursory or no attention in the literature. Before going into de-
nificantly modified by the QM treatment. The full impact of this tailed QM simulations, one must first discuss the conditions
effect will be made clear in the following sections. under which the standard QM model for bulk silicon can be
For larger positive gate biases, the depletion layer widens and adopted for heavily doped polysilicon. Two main features have
the classical value is recovered. However, a small difference can to be taken into account in dealing with such an issue: the exis-
still be seen in the charge distributions (see Fig. 1 for 5 V). tence of the grain boundaries, and the very high doping level.
Near the interface, the QM charge distribution is larger than the Each polysilicon grain can be assumed to be a perfect crystal,
classical distribution, due to the wavefunction penetration into surrounded by an insulator-like grain boundary. Even though
the classically forbidden electrostatic potential barrier. At the traps will surely be present at the grain boundaries, these repre-
boundaries of the depleted layer, instead, the QM charge rises sent a negligible fraction of the total volume of the MOS system.
more smoothly. In fact, rapid spatial variations of the charge are Assuming that no tunneling between grains occurs, each grain
limited by the thermal wavelength of the electrons [13]. Since can be treated as a quantum box, connected to the gate electrode
this wavelength is comparable with the depletion depth, a slower by an ohmic contact. The lateral size of grains is typically of the
2368 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000

Fig. 3. Gate capacitance for a 5 nm nMOS capacitor as obtained from a CL


simulation, a QM simulation with substrate quantization and a full quantum Fig. 4. Equivalent oxide thickness of the polysilicon capacitance as a function
N = 2
simulation. Polysilicon doping is 5 10 cm . The vertical dotted of the oxide electric field. Lines are results of classical (CL) simulations,
symbols represent full quantum (FQ) simulations.
line marks the flat-band condition.

order of 100 nm [15], and should cause no significant lateral of cm . Results are shown as obtained from a clas-
confinement effect [16]. Dopant atoms segregated at the grain sical treatment, a quantum solution where quantization is ap-
boundaries can be neglected, and the net doping of the polysil- plied only in the silicon substrate, as in current state-of-the-art
icon is determined by the dopant concentration inside the grains. simulators [11], and a full quantum solution, with QM effects in
In summary, to all practical purposes, gate polysilicon can be both substrate and polysilicon. Physical parameters adopted for
treated as single-crystal, heavily doped silicon. the polysilicon are the same as for single-crystal silicon. Note
In the presence of strong scattering processes, phase co- that QM effects in polysilicon strongly influence the gate capac-
herence is destroyed, and carriers tend to behave classically. itance in all regions of operation, reducing the computed value.
Therefore, a strong QM effect is expected only if the mean Let us first focus on the accumulation bias condition. Substrate
free path is larger than the electron dark space . In the case of quantization leads to a reduction in the gate capacitance that is
heavily doped polysilicon, the relevant scattering processes are due to either a shift in the centroid of the accumulation charge (in
by phonons and by ionized impurities. The phonon scattering strong accumulation, where bound levels exist) or a dark-space
mean free path can be accurately computed from a microscopic effect (in weak accumulation and at flat bands). Note that the
description of the various electron-phonon processes in silicon maximum reduction in the gate capacitance is not located at flat
[17], [18]. At energies of the order of , which are of interest bands but, rather, where the surface concentration is increased
here, this mean free path is of the order of 10 nm or more, enough to lower its screening length below the hole dark space.
therefore much larger than . On the other hand, due to the In this regime, polysilicon capacitance is dominated by the dark
strong screening and multiple-scatterer interactions, ionized space, which is larger than the screening length (see Fig. 2), and
impurity scattering at high dopant concentrations is not easy to is negligibly dependent on the applied bias. Therefore, polysil-
estimate. However, an empirical value can be obtained from the icon quantization is almost equivalent to an increase of the ef-
average thermal velocity and the momentum relaxation time of fective oxide thickness. At flat bands, only a small reduction in
the system. The former is easily computed taking into account the gate capacitance results from substrate quantization, while a
degeneration effects; the latter can be extracted from mobility more significant contribution is due to quantization of the highly
data for electrons in heavily doped silicon [19]. The mean free doped polysilicon.
path is also shown in Fig. 2, where it can be seen that it remains An important consequence of polysilicon quantization
larger than for all doping values of interest. Note the increase is that the physical oxide thickness extracted from capaci-
of the mean free path at high dopings, consequence of the tance–voltage (C–V) measurements [10], [20]–[23] turns out to
increase of the average energy of carriers due to degeneracy. be overestimated: Fig. 4 shows the equivalent oxide thickness
We therefore conclude that a QM treatment can be applied of the polysilicon capacitance as a function of the oxide
to the polysilicon gate. However, more detailed calculations or electric field, according to a classical and a quantum model.
measurements are needed to exactly assess the magnitude of For positive oxide fields (i.e., polysilicon depletion), both
scattering at high doping concentrations and its possible influ- treatments converge to the same depletion-limited behavior. On
ence on the QM effects in polysilicon. the other hand, for low-positive or negative fields (accumulated
polysilicon) a constant value of about 0.3 nm is approached in
IV. GATE CAPACITANCE the quantum treatment, largely independent of the polysilicon
doping, due to the dark-space effect. The classical polysilicon
A. Oxide Thickness capacitance [24] is instead expected to
Fig. 3 shows the simulated low-frequency gate capacitance continuously decrease as the device is brought further in
for an nMOS capacitor with an oxide thickness of 5 nm, a con- accumulation; however, an almost constant value is reached,
stant substrate doping of cm , and a polysilicon doping due to the weak dependence of the screening length on carrier
SPINELLI et al.: ELECTRICAL PROPERTIES OF MOS TRANSISTORS 2369

Fig. 6. Values of the polysilicon doping extracted from simulated capacitance


Fig. 5. Error on the physical oxide thickness extraction from C–V according to a classical model, a quantum model applied to substrate alone and
measurements in strong accumulation due to polysilicon quantization. The a full quantum model. The considered device has an oxide thickness of 3 nm
error is shown as a function of the maximum oxide electric field reached during and a polysilicon doping of 10 cm .
the measurement and for different polysilicon doping concentrations.

level is also raised, weakening the net dependence of the cen-


concentration in the high-density limit. The difference in the troid on the applied bias. Hence, an almost constant decrease
equivalent oxide thicknesses is hence dropped on the gate oxide in the gate capacitance is expected, equivalent to about 0.3 nm
whenever a classical treatment of the polysilicon is carried out, of silicon dioxide for most doping levels and bias voltages. On
leading to an incorrect estimate of the physical oxide thickness. the contrary, the dark space effect results in a reduction of the
Note also that for high polysilicon dopings the range where QM gate capacitance at threshold, which slowly tends to the clas-
effects are important encompasses the whole normal operating sical solution as the polysilicon depletion layer width becomes
conditions of MOS devices, going up to an oxide field of 6 MV larger than the dark space itself (see Figs. 1, 3 and 4). As a con-
cm for cm . sequence, the extraction of the active polysilicon doping from
Fig. 5 highlights the error on the extraction of the physical the slope of the C–V curve in strong inversion will be affected
oxide thickness that is only due to the dark-space effect, as a by quantization at both interfaces. The polysilicon doping
function of the oxide electric field in accumulation where C–V can be extracted from the gate capacitance as [25]
data are collected. It is worth recalling that the error is a direct
consequence of quantization at the polysilicon/oxide interface
and therefore exists in all of today’s state-of-the-art extraction (2)
procedures, even when quantum effects at the oxide/substrate
interface and (classical) polysilicon accumulation are taken into where is the gate-channel capacitance (i.e., gate-
account. As Fig. 5 shows, the error due to polysilicon quantiza- source gate-drain). In Fig. 6, the polysilicon doping is shown
tion alone decreases as the device enters strong accumulation as obtained from the application of (2) to simulated C–V curves.
and can be reduced to about 0.1 to 0.15 nm, depending on the The extracted doping is plotted as a function of the applied bias
measurement field and polysilicon doping. Such an effect can for a MOS device having a 3 nm gate oxide and a polysilicon
severely affect ultrathin oxide measurements: Even if an oxide doping of cm . Three types of simulations are compared:
field as high as 8 MV cm could be reached, the relative A purely classical model, a simulation where only QM effects
error would be about 4% on a 3-nm oxide. However, in ultra-thin in the substrate are accounted for, and a model with QM effects
oxides, direct tunneling current will limit the achievable oxide both in the substrate and poly. In the CL and QM-substrate
electric field [23], significantly increasing the error. Near flat estimates, a relatively small error in the extraction is due to ne-
bands, the error can be about 5 to 10% in a 3-nm oxide thick- glecting the inversion layer capacitance, which is not accounted
ness, depending on the polysilicon doping. Full quantum simu- for in (2). On the other hand, polysilicon quantization leads to a
lation of ultrathin oxides becomes therefore a compelling issue loss of validity of the depletion approximation in the gate: The
for achieving reliable estimates in future-generation devices. polysilicon capacitance is in fact dominated by the dark space.
It can be expected that, as the gate bias is sufficiently increased,
B. Polysilicon Doping polysilicon will enter the “classical” depletion regime, and
the only remaining error will be due to substrate quantization.
We focus now our attention on the inversion bias conditions
However, this is true only for low-doped polysilicon gates. In
of Fig. 3, which shows a different behavior from the accumu-
heavily doped gates, in fact, the necessary electric field can be
lation region. In inversion, quantization at the oxide/polysilicon
too high, as shown in Fig. 4.
interface acts differently on the gate capacitance than quantiza-
tion in the substrate, which is due to a shift of the centroid of
the inversion charge from the oxide/substrate interface. As the V. THRESHOLD VOLTAGE
gate bias is increased, the surface electric field rises, deepening As shown in Fig. 1, at all bias conditions except strong accu-
the confining potential well. However, the lowest bound energy mulation a minimum depletion region exists, of the order of 1
2370 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000

Fig. 7. Electric field in the oxide and polysilicon regions at threshold


according to a quantum model applied in the substrate only (dashed line) and a
full quantum model (solid line). Device parameters are the same as in Fig. 1.
Fig. 9. Threshold voltage shift due to QM effects as a function of oxide
thickness. Results are shown for quantization at the substrate side only (QMS)
and for a full quantum (FQ) treatment.

the same for the two cases. Hence, more inversion charge is
collected at the substrate side for a given gate bias. Polysilicon
quantization then determines a negative threshold voltage shift,
as opposed to channel-carrier quantization which induces a pos-
itive shift.
From the above qualitative discussion, one expects the
strength of the dipole and the amount of threshold shift to
strongly depend on the polysilicon doping level. Fig. 9 shows
the simulated threshold voltage shift with respect to a purely
classical model, plotted as a function of the oxide thickness.
The substrate doping is cm , and results are shown for
Fig. 8. Same as Fig. 7, but referred to the electrostatic potential.
polysilicon doping ranging from cm to cm .
When quantization at the substrate side only is taken into ac-
nm, where the majority carrier concentration is smaller than the
count, a positive voltage shift ranging from about 75 mV to 125
active doping concentration. For a polysilicon doping of
mV is obtained, which is slightly dependent on the polysilicon
cm , this implies that a fixed positive charge sheet of about
doping, due to the small voltage drop it sustains (see dashed
cm exists. At threshold, the channel charge is still neg-
and dot-dashed lines in Fig. 9). Conversely, quantization at the
ligible, while the total negative depletion charge in the substrate
polysilicon/oxide interface leads to a negative threshold voltage
is typically of the order of a few cm . In order to achieve
shift which is strongly dependent on the polysilicon doping:
charge neutrality for the entire system, an extra electron distribu-
For cm , the negative voltage shift is about 80
tion in the polysilicon must supply the necessary compensating
mV, significantly offsetting traditional results obtained with a
negative charge. This distribution is visible in the curve labeled
classical simulation of the polysilicon. Moreover, it is worth
“QM ” in Fig. 1, as a low “bump” of electrons peaked at a
pointing out that the threshold voltage shift due to poly quan-
depth of around 2 nm. The presence of two substantial charge
tization is independent of the treatment (CL or QM) adopted
sheets, one positive and one negative, offset by about 1 nm,
for the substrate. This explains why traditional investigations
causes an electric dipole. In the space comprised between the
of QM effects in MOSFETs have not revealed such a negative
two charge sheets a finite voltage is dropped, which is visible as
shift. An accurate determination of this effect would require
a threshold voltage shift of the order of several tens of millivolts.
a detailed experimental analysis over devices with different
The effect of the charge dipole on the electric field and elec-
polysilicon doping and the same substrate doping. Note also
trostatic potential is illustrated in Figs. 7 and 8, respectively.
that polysilicon quantization leads to a threshold voltage shift
While in the classical solution the electric field smoothly in-
which is not dependent on the oxide thickness, the charge
creases toward the oxide interface, the quantum solution pre-
dipole being located within the gate.
dicts first a negative peak due to the extra electrons, then a rapid
rise to a positive value at the interface, corresponding to the de-
pleted space charge within the dark-space region. The negative VI. CONCLUSION
electric-field peak causes a “kink” in the electrostatic potential, We have investigated the effects of quantization at the polysil-
leading to an increased oxide field, since the total voltage drop icon/oxide interface, showing that the existence of the abrupt
between the polysilicon neutral region and the silicon bulk is discontinuity in potential energy leads to a dark space depleted
SPINELLI et al.: ELECTRICAL PROPERTIES OF MOS TRANSISTORS 2371

of free carriers of the order of 2 to 3 nm. For polysilicon dop- [21] S. V. Walstra and C.-T. Sah, “Thin oxide thickness extrapolation from
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Alessandro S. Spinelli (M’99) was born in in Bergamo, Italy, in 1966. He re-
ceived the Laurea (cum laude) and Ph.D. degrees in electronics engineering from
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12, pp. 2265–2284, 1975. of Electronics at the Politecnico of Milano, and was
[18] J. Y. Tang and K. Hess, “Impact ionization of electrons in silicon (steady appointed Full Professor in 1999. He has worked on
state),” J. Appl. Phys., vol. 54, pp. 5139–5144, 1983. physics of carrier transport in semiconductor devices, development of new ex-
[19] N. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mo- perimental methods for characterization of semiconductor materials, and ULSI
bilities in silicon as a function of concentration and temperature,” IEEE devices and low-noise design of integrated circuits for cellular receivers. He
Trans. Electron Devices, vol. ED-29, pp. 292–295, Feb. 1982. leads a research laboratory, working on the characterization and modeling of
[20] R. Rios and N. D. Arora, “Determination of ultra-thin gate oxide thick- devices and interconnects in ULSI CMOS circuits and design of RF front-end
ness for CMOS structures using quantum effects,” in IEDM Tech. Dig., for wireless communication systems. He has co-authored about 100 papers pub-
1994, pp. 613–616. lished in journals or international conference proceedings.

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