Professional Documents
Culture Documents
library
IEEE;
IEEE.STD_LOGIC_1164.ALL;
IEEE.NUMERIC_STD.ALL;
library
UNISIM;
UNISIM.VComponents.all;
entity
ripple
is
Port
(
clock
:
in
STD_LOGIC;
x
:
out
STD_LOGIC_VECTOR
(7
downto
0));
end
program;
architecture
Behavioral
of
ripple
is
signal
RP:
std_logic_vector
(7
downto
0)
<="11111111";
begin
Process(clock)
begin
if
clock='1'
and
clock'event
then
RP(0)<=RP(7);
RP(1)<=RP(0);
RP(2)<=
RP(1)
XOR
RP(7);
RP(3)<=RP(2);
RP(4)<=RP(3);
RP(5)<=RP(4);
RP(6)<=RP(5);
RP(7)<=RP(6)
XOR
RP(7);
end
if;
end
process;
x<=RP;
end
architecture
Behavioral;
library
IEEE;
IEEE.STD_LOGIC_1164.ALL;
IEEE.STD_LOGIC_unsigned.ALL;
entity
ALU
is
Port
(
A
:
in
STD_LOGIC_VECTOR
(3
downto
0);
B
:
in
STD_LOGIC_VECTOR
(3
downto
0);
S
:
in
STD_LOGIC_VECTOR
(1
downto
0);
M
:
in
STD_LOGIC;
RESET
:
in
STD_LOGIC;
Cn
:
in
STD_LOGIC;
Cout
:
out
STD_LOGIC;
Z
:
out
STD_LOGIC;
F
:
out
STD_LOGIC_VECTOR
(3
downto
0));
end
ALU;
architecture
Behavioral
of
ALU
is
signal
temp
:
STD_LOGIC_vector(
4
downto
0);
--signal
array
5bits
to
store
O/P
value
and
Cout
begin
process(M,A,B,S,Cn)
variable
TEMP1:
STD_LOGIC_vector(
2
downto
0);
Begin
If
RESET=
'1'
then
temp<="00000"
;
elsif
M
='0'
then
Z<='0';
case
S
is
when
"00"
=>temp
<='0'&(A
and
B);
when
"01"
=>
temp
<='0'&(A
or
B);
when
"10"
=>
temp
<=
'0'&(A
xor
B);
when
"11"
=>
temp
<='0'&(A
xnor
B);
when
others
=>
temp
<="11111";
end
case;
else
temp1:=
(S&Cn);
case
temp1
is
when
"000"
=>
temp(2
downto
0)
<=
B
(3
downto
1)
;
temp(3)<=
B(3);temp(4)<='0';
when"001"=>temp(2
downto
0)<=A
(3
downto
1);
temp(3)<='0';Ftemp(4)<='0';
when
"010"
=>
temp
<=
('0'&A)+
('0'&B);
when
"011"
=>
temp
<=
('0'&A)+
B
+
Cn;
when
"100"
=>
temp
<=
('0'&
A)+
('0'&
not
B);
when
"101"
=>
temp
<=
('0'&
not
B)+('0'&
A)+("0000"&
'1');
when
others
=>
temp
<="11111";
end
case;
if
temp="00000"
then
Z<='1';
else
Z<=
'0';
end
if;
end
if;
end
process;
F<=temp(3
downto
0);
Cout<=
temp(4);
end
Behavioral;