4882 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.
12, DECEMBER 2009
An Improved ACDC Single-Stage Full-Bridge
Converter With Reduced DC Bus Voltage
Pritam Das, Shumin Li, and Gerry Moschopoulos, Member, IEEE
AbstractA new acdc single-stage voltage-fed pulsewidth-
modulation (PWM) full-bridge converter is proposed in this paper.
The converter can simultaneously perform input power factor
correction and dcdc conversion using conventional phase-shift
PWM and can maintain a primary-side dc bus voltage of less
than 450 V even at a high input line voltage of 265 Vrms . This
is a combination of features that few, if any, other converters of
the same type have. The proposed converter has these features
due to the novel implementation of an asymmetrical auxiliary
transformer winding that is placed in series with the input in-
ductor and acts as a boost switch. In this paper, the operation
of the proposed converter is explained in detail, its outstanding
features are discussed, and a detailed design procedure is given
and demonstrated with an example. Experimental results that
confirm the feasibility of the converter and its ability to meet
IEC1000-3-2 Class D standards for electrical equipment are also
presented in this paper.
Index TermsACDC power conversion, full bridge, magnetic
switch, power factor correction (PFC), single-stage converters.
I. I NTRODUCTION
A CDC rectifiers are usually implemented with a boost
converter that performs power factor correction (PFC)
as the front-end converter and an isolated dcdc converter
that produces the required output voltage. The dcdc converter
is typically a flyback or a forward converter for low-power
applications and a full-bridge converter for higher power appli-
cations. ACDC rectifiers can be used as stand-alone converters
or can be used as paralleled modules.
Due to the cost and complexity involved in implementing two
separate switch-mode converters, there has been considerable
interest by power electronics researchers to try to combine
both acdc PFC and isolated dcdc conversion into a single
converter. As a result, there have been numerous publications
on the topic of single-stage acdc converters, particularly for
low-power (< 250 W) acdc flyback and forward converters
such as the ones in [1][10] and [31]. The performance of
these cheaper and simpler converters is comparable to that of
conventional two-stage converters, and they are now widely
Manuscript received April 17, 2008; revised June 16, 2009. First published
July 7, 2009; current version published November 6, 2009. This work was
supported by the Natural Science and Engineering Research Council of Canada.
P. Das and G. Moschopoulos are with the Department of Electrical and
Computer Engineering, The University of Western Ontario, London, ON N6A
5B9, Canada (e-mail: pdas2@ uwo.ca; gmoschopoulos@eng.uwo.ca).
S. Li was with the Department of Electrical and Computer Engineer-
ing, The University of Western Ontario, London, ON N6A 5B9, Canada.
She is now with Intel Corporation, DuPont, WA 98327-9728 USA (e-mail:
shumin.li@intel.com).
Digital Object Identifier 10.1109/TIE.2009.2026386
0278-0046/$26.00 2009 IEEE
used in industries as their properties and characteristics have
been well established.
Research on the topic of higher power acdc single-stage
full-bridge converters, however, has proved to be more chal-
lenging, and thus, there have been much fewer publications.
Single-stage converters operate with only one controller that is
used to regulate the output voltage, whereas two-stage convert-
ers operate with an additional controller that is used to regulate
the intermediate dc bus voltage obtained from the acdc stage.
The lack of a second controller has a greater impact on the
performance of single-stage full-bridge converters because they
must be designed to operate over a much wider range of
operating conditions. Compromises in the design that need not
be considered for lower power converters due to their narrower
range of operating conditions must be considered for higher
power full-bridge converters.
Previously proposed single-stage acdc full-bridge convert-
ers have at least one of the following drawbacks.
1) They are voltage-fed single-stage pulsewidth-modulation
(PWM) converters [11][19] with a large energy-storage
capacitor connected across the dc bus. This capacitor
prevents voltage overshoots and ringing from appearing
across the dc bus and filters out the 120-Hz ac component
so that it does not appear at the output. Although the input
power factor (pf) of a single-stage voltage-fed converter
is not as high as that of current-fed converters, the input-
current harmonic content can be made to comply with
the regulatory agency standards. The primary-side dc bus
voltage of the converter, however, may become excessive
under high-input-line and low-output-load conditions, as
it is dependent on the converters input line and output
load operating conditions and component values. This
drawback prevents the wide range of operation of the
converters, i.e., for universal input voltage range (90
265 Vrms ) and wide output load variation (from 10%
of full load to a full load that is greater than 500 W)
while maintaining a dc bus voltage less than 450 V for
all operating conditions and excellent pf. For example,
the converter in [11] has a dc bus voltage of 600 V.
2) They must operate using nonstandard switching tech-
niques and, thus, cannot be implemented using commer-
cially available ICs. For example, the converters proposed
in [14][19] must operate using novel asymmetrical
PWM techniques that are unique to the converters as
opposed to conventional phase-shift PWM.
3) They are resonant converters [20][24], [32], [33] that
must be controlled using varying switching-frequency
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE 4883

control, which makes it difficult to optimize their de-

sign as they must be able to operate over a wide range
of switching frequency. For example, the characteris-
tics of the voltage-fed resonant converters proposed in
[20][24] with respect to the dc bus capacitor voltage
are dependent on the fine tuning of the resonant tank
components.
4) They are current-fed converters with a boost inductor
connected to the input of the full-bridge circuit [24]
[26]. They can achieve a near-unity input pf but lack
an energy-storage capacitor across the primary-side dc
bus. The absence of such a capacitor can result in the
appearance of high voltage overshoots and ringing across
the dc bus whenever a converter switch is turned off,
unless some preventative measure is implemented, which Fig. 1. Proposed single-stage full-bridge converter.
results in a loss of efficiency. It also causes current-fed
single-stage converters to have an output voltage with a
large low-frequency 120-Hz ripple that restricts their use
to applications where a tightly regulated output voltage is
not required.

In [27], a promising single-stage voltage-fed PWM full-

bridge converter was proposed, but its characteristics were not
well known, and thus, its strengths were not properly taken
advantage of; this topology will be the focus of this paper.
In this paper, the operation of the converter is explained and
analyzed in detail, its outstanding features are discussed, and
a detailed design procedure is given and demonstrated with
an example. Experimental results that confirm the feasibility
of the converter and its ability to meet IEC1000-3-2 Class D
standards for electrical equipment [30] are also presented in
this paper. The proposed single-stage voltage-fed PWM full-
bridge converter has none of the aforementioned drawbacks
and is, thus, superior to other previously proposed converters of
the same typeincluding converters such as the ones proposed
in [11], [16], [18], and [19] in previous editions of these
transactions.
II. C ONVERTER O PERATION
The converter shown in Fig. 1 operates like a standard PWM
full-bridge converter. Energy is transferred from the dc bus
capacitor Cb whenever a pair of diagonally opposed switches
is on. No energy is transferred when the converter is in a
freewheeling mode of operation, where the two top switches or
the two bottom switches are both on and the voltage across the
transformer primary is zero. By appropriately alternating the se-
quence of energy transfer and freewheeling modes, an ac square
voltage is impressed across the transformer primary winding,
which is then stepped down by the transformer, rectified by
the output diodes, then filtered by the output inductorcapacitor
(LC) filter to produce an output dc voltage.
While it is performing dcdc conversion, the converter is
also performing input PFC due to the transformer winding
Naux , which is an auxiliary winding taken from the main power
transformer. A voltage is impressed across the main transformer
primary winding whenever switches S2 and S3 are on. The
polarity of this voltage is such that it causes a voltage with a
Fig. 2. Discontinuous input current waveform.
polarity that counteracts the dc bus voltage to appear across the
auxiliary winding so that a net positive voltage is impressed
across the input inductor and the input current rises. When the
converter operates in a freewheeling mode of operation so that
the voltage across the main primary transformer winding is zero
or when switches S1 and S4 are on so that this voltage is of
different polarity, then the net voltage across the input inductor
is negative, and the input current falls.
The rise and the fall of the inductor current during a converter
switching cycle are analogous to that of the inductor current in
a boost converter. Activating the asymmetric auxiliary winding
will counteract the dc bus capacitor voltage, which is the same
as turning the boost-converter switch on in a boost converter.
Deactivating the asymmetric auxiliary winding will impress
the dc bus capacitor voltage at the right-hand end of the input
inductor in Fig. 1, and this is the same as turning the boost-
converter switch off. The winding is asymmetric, as the input
current rises only when switches S2 and S3 are on. The input
current in the proposed converter can be shaped to improve
the input pf, as can be done in a standard acdc boost PFC
converter. If the input current is made discontinuous, as shown
in Fig. 2, then an excellent input pf can be achieved.
The proposed converter goes through several modes of op-
eration during a switching cycle. Typical converter waveforms
for a single switching cycle with a discontinuous output current
and a discontinuous input current are shown in Fig. 3, and
the equivalent circuit diagrams for each mode of operation are
shown in Fig. 4. The converter goes through the following
modes of operation during a switching cycle.
Mode 1 (t0 t1 ): In this mode, S2 and S3 are on, and
auxiliary diode Daux1 and output diode D1 are forward biased.
The current in the output inductor is rising and so does the input
4884 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

where N is the turns ratio of the primary winding N1 to the

secondary winding N2 , Vo is the regulated output voltage, and
Lo is the output filter inductance current.
Mode 2 (t1 t2 ): At t1 , S2 is turned off, and the primary
current starts to charge and discharge switch capacitors Cs2 and
Cs1 ; this mode ends with fully charging and discharging of Cs2
and Cs1 .
Mode 3 (t2 t3 ): At the start of this mode, the output current
starts freewheeling through D1 and D2 and so does the input
current through Daux2 and Daux1 , charging up the dc bus
capacitor. In this mode, the input and the output currents are
decreasing, and the transformer primary current freewheels
through S1 and S3 . Sometime during this mode, S1 is turned
on with zero-voltage switching (ZVS). This mode ends with the
output current reducing to zero. The negative voltage vs,k Vb
across inductor Lin forces the current to fall linearly with a
slope of
diin,k vs,k Vb
= . (5)
dt Lin

The input current Iin,k (t2 ) at t = t3 is

(vs,k Vb )(1 D)Tsw
Iin,k (t3 ) = Iin,k (t2 ) + . (6)
2Lin

Also, during this interval, the output inductor current Iout,k falls
with a slope of
diout,k Vo
= . (7)
Fig. 3. Typical waveforms describing the modes of operation. dt Lo

current if vs,k > Nx Vbus (Nx = Naux : N1 ); otherwise, there Mode 4 (t3 t4 ): In this mode, the input current continues to
will be no current in the input inductor. The slope of the rising decrease, freewheeling through Daux1 and Daux2 . This mode
input current can be expressed as ends with the turning off of S3 .
Mode 5 (t4 t5 ): This mode begins with the primary current
diin,k vs,k + (Nx 1) Vb charging and discharging switch capacitors Cs3 and Cs4 and
= . (1)
dt Lin ends with the full charging and discharging of these capacitors.
Mode 6 (t5 t6 ): During this mode, the primary current
At the end of this mode, the input current reaches a peak of
flows through the body diodes of S1 and S4 , and the input
[vs,k + (Nx 1) Vb ] D Tsw current continues to flow through Daux2 due to the asymmetry
Iin,k (t1 ) = (2) of the transformer auxiliary winding. This mode ends with the
2Lin
turning on of S4 with ZVS. The slope of the input current,
where vs,k is the magnitude of the rectified input voltage at which is still decreasing in this mode, is given by
the kth switching period, Nx = Naux : N1 , where Naux is the
number of turns on the auxiliary winding and N1 is the number diin,k vs,k Vb
= . (8)
of turns on the primary winding, Vb is the dc bus voltage across dt Lin
energy-storage capacitor Cb , D is the duty ratio, and Tsw is
Mode 7 (t6 t7 ): The primary current flows through switch
the switching period. The slope of the output current can be
S1 and the body diode of S4 during this mode, while the
described by
input current decreases as it flows through Daux2 . This mode
diout,k Vb
Vo ends with the body diode current in S4 reducing to zero and
N
= (3) eventually flowing through the switch. The output capacitor
dt Lo
feeds energy to the output load from t3 to t7 .
and it reaches its peak value at the end of the interval when Mode 8 (t7 t8 ): During this mode, the output current rises
t = t1 . The output current is discontinuous, and its peak value again, flowing through D2 , and the input current still decreases
can be expressed by as it flows through Daux2 . This mode ends with the input
 Vb  current reducing to zero.
1 Vo DTsw Mode 9 (t8 t9 ): The output current continues to increase
Iout,k (t1 ) = N (4)
2 Lo during this mode, and there is no current flowing in the input
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE 4885

Fig. 4. Equivalent circuit diagrams for the modes of operation.

4886
Fig. 5. Single-stage voltage-fed PWM converter proposed in [11].
section of the converter. This mode ends with the turning
off of S1 .
Mode 10 (t9 t10 ): This mode begins with the transformer
primary current charging and discharging switch capacitors Cs1
and Cs2 and ends with the complete charging and discharging
of Cs1 and Cs2 .
Mode 11 (t10 t11 ): The output current freewheels through
D1 and D2 during this mode. This mode ends with the output
and the transformer primary currents reducing to zero. S2 is
turned on with ZVS sometime during this mode.
Mode 12 (t11 t12 ): There is no current flowing in the
converters input section, the full-bridge circuit, and the output
diodes during this mode; the output capacitor feeds the load.
Sometime during this mode, S4 is turned off with zero-current
switching (ZCS). This mode ends with S3 getting turned on
with ZVZCS, and a new switching cycle is commenced.
III. C ONVERTER C HARACTERISTICS
The concept of using an auxiliary transformer winding to
simulate a boost switch so that the input current can rise
and fall appropriately to ensure a very good input factor has
been proposed for use in a number of low-power single-stage
acdc flyback and forward converters [2], [4], [10]. It has,
however, never been implemented in a single-stage voltage-
fed PWM full-bridge converter with the sole exception of the
one proposed in [11]. It is the use of an auxiliary winding as a
magnetic switch that allows standard phase-shift PWM control
to be used, and the converter in [11] has been the only single-
stage full-bridge converter that can operate with this control.
The converter that was proposed in that paper, which is shown
in Fig. 5, can only operate with a very high dc bus voltage that
was almost 600 V under high-line conditions. The differences
between these two converters will be explained in this section.
A. Difference in Number of Auxiliary Windings
The auxiliary windings in both the proposed converter and
the converter proposed in [11] can be considered to be like
switches that conduct current during the time that a voltage
of appropriate polarity is impressed across the transformer
primary.
Consider the operation of the dcdc full-bridge section
of both converters during a single switching cycle. In both
converters, a voltage of one polarity is impressed across the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009
transformer; then, a freewheeling mode occurs when no voltage
is impressed; thereafter, a voltage of the opposite polarity
is impressed across the transformer primary; finally, another
freewheeling mode occurs.
For the proposed converter, the sequence of events from the
point of view of the converters input section that matches this
sequence is as follows: The auxiliary winding switch Naux is
on, the auxiliary winding switch is off, the auxiliary winding
switch is off, and the auxiliary winding switch is off.
For the converter proposed in [11], the sequence of events
from the point of view of the converters input section that
matches the sequence at the dcdc full-bridge section is as
follows: The auxiliary winding switch Naux1 is on, both
auxiliary winding switches are off, the auxiliary winding
switch Naux2 is on, and both auxiliary winding switches
are off.
By referring to the typical waveforms shown in Fig. 3, it
can be seen that the rise and the fall of the input current
in the proposed converter occur once during a full switching
cycle due to the fact that the converter has only one auxiliary
winding switch. The rise and the fall in the current in the
output inductor, however, occur twice during a switching cycle.
For each rise and fall of the input inductor current, energy is
transferred from the ac source to the dc bus capacitor, whereas,
for each rise and fall of the output inductor current, energy is
transferred from the dc bus capacitor to the output load. During
each switching cycle, energy is transferred from the ac source
to the dc bus once, whereas energy is transferred from the dc
bus capacitor twice. It is a fact that there is only one auxiliary
winding that causes this 1 : 2 ratio of energy input to the dc bus
capacitor to energy output to exist.
By comparison, the converter proposed in [11] has two
auxiliary windings so that the rise and the fall of the input
current will occur twice in a switching cycle, just as the rise
and the fall of the output inductor current does. It is a fact that
there are two auxiliary winding switches that cause this 2 : 2
(or 1 : 1) ratio of energy input to the dc bus capacitor to energy
output to exist.
The dc bus voltage in single-stage converters is uncontrolled,
as these converters have only one controller that is used to
regulate the output voltage. This voltage is, instead, depen-
dent on the energy equilibrium that must exist at the dc bus
capacitorthe amount of energy or charge that is fed into this
capacitor must be equal to the amount of energy or charge that
is removed from the capacitor during a half line cycle (half of
a 60-Hz cycle because the input line is rectified by the diode
rectifier).
The fact that the proposed converter has a 1 : 2 ratio of energy
input to the dc bus capacitor to energy output instead of a 1 : 1
ratio, which is what the converter proposed in [11] has, means
that this capacitor is allowed to discharge more frequently than
it is allowed to be charged. This affects its energy equilibrium
so that its voltage is lower than that of the converter proposed in
[11]. In summary, the use of a single auxiliary winding, instead
of the two that are used in the converter proposed in [11], helps
reduce the dc bus voltage so that it is easier to ensure that it
does not exceed the 450-Vdc standard that has been accepted in
the literature.
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE
Fig. 6. Input voltage waveform and input current envelope showing the dead
angle .
B. Difference in Auxiliary Winding/Transformer Primary
Winding Turns Ratio
Unlike the converter proposed in [11], the auxiliary winding
in the proposed converter is designed so that it does not com-
pletely cancel out the voltage across the dc bus capacitor. This
means that some, but not all, of the diode bridge rectifier output
voltage is placed across the input inductor. This can reduce the
amount of energy placed in the input inductor when switches S2
and S3 are on, which, in turn, reduces the amount of energy that
is transferred to the dc bus capacitor during the time when both
these switches are not on. The reduction in energy placed into
the input inductor affects the energy equilibrium of the dc bus
capacitor in a way that reduces the dc bus voltage and makes it
lower than what it is in the converter proposed in [11].
The input section of the converter is made to operate in
discontinuous current mode so that a high pf is achieved.
Making the number of auxiliary winding turns different from
the number of transformer primary winding turns, however,
introduces deadband regions in the zero-crossing sections of the
input current waveform, as shown in Fig. 6. This is because the
diode-bridge diodes are reverse biased when the input voltage
is low, and current is not allowed to flow in the input inductor
as the dc bus voltage is not fully cancelled out by the auxiliary
winding.
This means that a compromise must therefore be made
between the input pf and the dc bus voltage reductionthe dc
bus voltage of the proposed converter can be kept lower than
450 Vdc but with some current distortion. The converter can
be designed to operate with a near-unity pf but with a dc bus
voltage which may be greater than 450 Vdc yet still lower than
that of the converter proposed in [11].
C. Transformer Primary Current DC Offset
The fact that the proposed converter has a single auxiliary
winding means that its transformer primary current will have
some dc offset. Current can flow through the auxiliary winding
when the voltage across the transformer forward biases Daux1
and reverse biases Daux2 , but current cannot flow through
the winding when the voltage across the transformer winding
forward biases Daux2 and reverse biases Daux1 .
4887
When current flows through the auxiliary winding, the trans-
former primary current is the sum of the reflected current
from the secondary and that from the auxiliary winding. When
current does not flow through the auxiliary winding, the pri-
mary current is only the reflected current from the secondary.
The transformer should be designed to accommodate this dc
offset like any other transformer that must operate without full
demagnetization.
Due to the presence of the auxiliary winding and the way it
is implemented, the proposed converter is currently the only
voltage-fed single-stage acdc full-bridge converter that can
operate with standard phase-shift PWM and with a dc bus
voltage that does not exceed the standard accepted voltage of
450 Veven if its input voltage is the maximum high line
voltage of 265 Vrms .
IV. C ONVERTER D ESIGN
A procedure for the design of the converter is presented
in this section and is demonstrated with an example. For the
example, the converter is to be designed according to the fol-
lowing specifications: output voltage Vo = 48 V, input voltage
Vin = 90265 Vrms , output power Po = 600 W, and switching
frequency fsw = 1/Tsw = 50 kHz. The dc bus capacitor should
not exceed 450 V for any operating condition. Since the design
will follow IEC1000-3-2 Class D standards for harmonic con-
tent, a pf ranging between 0.88 and 0.95 and a total harmonic
distortion (THD) that is less than or equal to 45% will be
considered acceptable [2].
Step 1Establish Appropriate Value for Maximum
Converter Duty Cycle Dmax : The maximum duty cycles
Dmax that the converter can operate with are determined by
the switch and the controller that are used. A typical value of
Dmax would be 0.7, as many controllers for phase-shift PWM
full-bridge converters use current-sensing transformers that
require a certain amount of time to reset [2], [11], [29]. The
value of Dmax that will be used in this example is Dmax = 0.7.
Step 2Determine Value for Output Inductor Lo : The
output inductor should be designed so that the output current is
made to be discontinuous under all operating conditions. This is
to avoid the possibility of the primary-side dc bus voltage Vbus
to exceed 450 V, which may happen under certain operating
conditionsparticularly if the input inductor is designed so
that the input current is made to be always discontinuous and
thus bounded by a sinusoidal envelope. This phenomenon is
common to all voltage-fed single-stage acdc converters and is
explained in detail in [15].
The maximum value of Lo should be the value of Lo with
which the converters output current will be on the boundary be-
tween being continuous and discontinuous when the converter
is operating with minimum input voltage, maximum duty cycle
(Dmax ), and full load (Po,max ). If this condition is met, then
the output current will be discontinuous for all other converters
operating conditions. The maximum value of Lo can therefore
be determined to be
Vo2 (1 Dmax ) Tsw
Lo,max = . (9)
Po,max 2 2
4888 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

Substituting Po,max = 600 W, Vo = 48 V, Tsw = 20 s, and

Dmax = 0.7 established in Step 1 gives Lo,max = 6 H. The
value of Lo should be close to the maximum to try to minimize
the output peak current but slightly lower to provide some
margin; therefore, a value of Lo = 5 H is chosen.
Step 3Determine Values for Turns Ratio of Auxiliary
Transformer Nx : Nx should be made to be less than one to
avoid placing the full input voltage across Lin when energy is
to be placed in this inductor. As was explained in the previous
section, not placing the full input voltage across Lin results in
an energy equilibrium at Cb that results in a lower value of Vbus .
If Nx is made to be too low, however, then the input current will
become very distorted and unable to meet the desired harmonic
standards, as current cannot flow through Lin when the input
voltage is less than (1 Nx ) Vbus . The input current will
therefore be a discontinuous waveform that will be confined to
an envelope with deadbands as shown in Fig. 6. The deadband
angle can be written as
 
1 (1 Nx )Vbus
= sin (10)
Vm
where Vm is the peak value of the input voltage and Vbus is the
dc bus voltage.
If it is assumed that the most significant input current har-
monics will be low-order harmonics that are dependent on the
shape of the envelope, then a Fourier series analysis of the
envelope waveform can be performed to derive the following
equations for input pf and THD, as was done in [28]:

1
sin 2 Fig. 7. Variation of THD (in percent) and pf for different values of auxiliary
pf = 2
 2
(11) winding turns ratio at input voltages of 100 and 230 Vrms .
A
2
Nx = 0.7 is chosen from these graphs, as it is the highest value
where of Nx that ensures that the input current satisfies the harmonic
standard requirements.
3
A= sin 2 + ( 2) sin2 (12) Step 4Determine Value for Turns Ratio of Main
2 2 Transformer N : The value of N affects the primary-side dc
1
pf =   . (13) bus voltage, as it determines how much reflected load current
T HD 2
100 + 1 is available at the transformer primary to discharge the bus
capacitor Cb . If N is high, then Vbus can be low, but the
Graphs of the input pf and the THD versus Nx , such as primary current may be too high to be practicaldepending
the ones shown in Fig. 7, can be generated for Vin = 100 and on the switching and conduction losses. If a lower value of N
230 Vrms using (11)(13). Vin = 100 and 230 Vrms are the is used to reduce the primary current, then the primary current
standard voltages for which harmonic measurements are made that is available to discharge Cb may be low, and thus, Vbus
to confirm compliance with IEC1000-3-2 specifications. The may become excessive under certain operating conditions (i.e.,
curves in Fig. 7 will be valid no matter what the load is, as high line).
the Vbus in a single-stage voltage-fed converter will not change The minimum value of N can be found by considering the
with the load if Vin is fixed and if both the input and the output case when the converter must operate with minimum input line
inductor currents are discontinuous [11], [15]. and, thus, minimum primary-side dc bus voltage Vbus,min and
The values of Vm = 100 1.414 = 141.14 V and Vbus = maximum duty cycle Dmax . If the converter can produce the re-
180 V are used for the 100-Vrms curves, and the values of quired output voltage and can operate with discontinuous input
Vm = 230 1.414 = 325 V and Vbus = 360 V are used for the and output currents in this case, then it can do so for all cases.
230-Vrms curves for the graphs in Fig. 7. The Vbus values that Since Lo was designed in Step 2 to make the output current
are used to generate the curves are estimated values but are valid discontinuous but close to being continuous when the converter
estimates, as the dc bus voltage must always be just slightly is operating under these conditions, the following constraint
higher (3040 V) than the input voltage if the Vbus < 450 V based on standard full-bridge operation can be placed on N :
criterion is to be met over the universal input line range. The
actual values of Vbus may be slightly higher or lower, and thus, Vbus,min
N Dmax . (14)
the graphs in Fig. 7 will not be much different. A value of Vo
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE 4889

TABLE I
C OMPONENT VALUES FOR P ROPOSED C ONVERTER AND C ONVERTER IN [11]

A value of Vbus = 160 V can be estimated for Vin = 90 Vrms section, and D = Dmax = 0.7 is used in (19); assuming the
using the reasoning described in Step 3. Substituting converter to be lossless, Pin = Po = 600 W is used. The value
Vbus = 160 V, Vo = 48 V, and Dmax = 0.7 into (14) of K can be determined to be K = 1.35 104 V s using the
results in N 2.3. A value of N = 2.5 is chosen. solver feature in MathCAD for the boundary condition of D =
With a value of N established, the actual value of Vbus 0.7, Pin = Po = 600 W, Vin = 90 Vrms , and Vbus = 166 V.
can now be determined more precisely by using the following Using this value of K in (19) and Pin = 600 W, a value of
equation, which is based on standard full-bridge operation with Lin = 18 H is found. For this design, Lin = 16 H is used.
a discontinuous output current: Step 6Verification of Converter Operation Under High-
 Line Conditions: In the previous steps of the procedure, the
16P Lo
Vo + Vo2 + Tswo,max 2
Dmax values for Lo , Lin , Naux , N , and Dmax were selected based on
Vbus,min = N . (15) low-line operating conditions (Vin = 90 Vrms ), as it is mostly
2
under these conditions that worst case converter operation
Substituting Vin = 90 Vrms , Po = 600 W, and Dmax = 0.7 into should be considered. Before settling on the values for these
this equation gives Vbus,min = 166 V. parameters, however, it should be confirmed that the primary-
Step 5Determine Value for Input Inductor Lin : The value side dc bus voltage will not exceed 450 V at the maximum input
for Lin should be low enough to ensure that the input current voltage of 265 Vrms .
is fully discontinuous under all operating conditions, but not so Consider the following. For the case when the output current
low as to result in excessively high peak currents. For the case is discontinuous, the average output power can be expressed as
where Lin is such that the input current remains discontinuous

for all operating conditions, then the average input power can D2 Vbus Vbus
Po = Vo . (21)
be expressed as 4Lo fsw N N

Assuming the converter to be lossless and equating Pin in (19)
1
Pin = |vs,k |is,k dSu t (16) with Po in (21), the following expression containing Vbus can
be obtained:



Vbus Vbus Lo
where is calculated from (10), |vs,k | = Vm | sin 2fSu tk | is Vo = Nx K. (22)
N N Lin
the magnitude of the rectified input voltage at the kth switching
interval, fSu is the input ac frequency, and Now, closely observing the integral K given by (20), it can
easily be found that K is a function of Vbus only. Hence, for
tk = kTsw (17)
the unknown values of Vbus , K can be evaluated as a function
1 D Nx |vs,k | + (Nx 1)Vbus
2
of Vbus only. For the case when Vin = 265 Vrms , the value of
is,k = |v |
8 Lin fsw 1 s,k Vbus will be approximately 393 V.
Vbus
The component values and the component stresses of the
for |vs,k | > (1 Nx )Vbus = 0 proposed converter are compared to those of the converter pro-
for |vs,k | < (1 Nx )Vbus (18) posed in [11] designed with the same specifications in Tables I
and II. The following should be noted.
is the average current of the kth switching interval. By substi- 1) The input current of the converter proposed in [11] is
tuting the value of is,k into (16), Pin can be expressed as more distorted because the converter must be designed
with a 1 : 0.5 turns ratio instead of a 1 : 0.7 turns ratio.
D 2 Nx This creates larger deadband regions in the input current
Pin = K (19)
8Lin fsw and makes the converter operate with a lower input pf.
where 2) The input current of the converter proposed in [11] has
a larger root-mean-square (rms) value because of the

additional distortion due to the larger deadband regions.
1 |vs,k | + (Nx 1)Vbus
K= |vs,k |
|vs,k |d(2fSu )t. (20) 3) The input current of the converter proposed in [11] has
1 Vbus a much larger peak value because the converter needs to

operate with a much smaller input inductance. If the con-
Vin = 90 Vrms and Vbus = 166 V as calculated in Step 4 are verter was implemented with a larger input inductor, then
used to determine K at the boundary condition for the input the input current would no longer be fully discontinuous
4890 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009

TABLE II
P ERFORMANCE FACTOR C OMPARISON B ETWEEN P ROPOSED C ONVERTER AND C ONVERTER IN [11]

Fig. 8. Typical input voltage and current waveforms. Vin = 110 Vrms ; Po = Fig. 9. Typical transformer primary voltage, input inductor current, and output
600 W; scale: V = 75 V/div., I = 10 A/div., and t = 4 ms/div. current at 110-Vrms input and 600-W output. Scale: Vpri = 100 V/div.,
ILin = 10 A/div., ILo = 5 A/div., and t = 10 s/div.
over the full line cycle but would become continuous at
certain parts of the cycle. This would make the input cur-
rent even more distorted and would reduce the input pf.
4) The switches in the converter proposed in [11] operate
with greater rms currents because the reflected currents
from both the main and the auxiliary windings of the
transformer are higher due to the lower turns ratios of the
main and the auxiliary transformer windings.
5) The secondary output diodes in the converter proposed in
[11] operate with a higher peak voltage because of the
lower main transformer winding turns ratio.

V. E XPERIMENTAL R ESULTS
An experimental prototype was built to verify the feasibility
of the proposed converter. It was designed for the follow-
ing specifications: input voltage Vin = 90265 Vrms , output
voltage Vo = 48 V, maximum output power Po,max = 600 W,
and switching frequency fsw = 50 kHz. The converter was
implemented with the following parameters: Lin = 16 H,
Lo = 5 H, N = N1 : N2 = 2.5, and Nx = Naux : N1 = 0.7.
IRFP460 MOSFETs were used for switches S1 S4 , and
Daux1 and Daux2 are implemented with GaAs Schottky diodes
DGSK40-025A, while output rectifier diodes are implemented
with GaAs Schottky diodes DGS20-018A. A standard UC3879
IC was used as the controller.
Fig. 8 shows the input voltage and the input current wave-
forms when the converter is operating with Vin = 110 Vrms
and Po = 600 W. Fig. 9 shows the transformer primary voltage
waveform when the converter is operating with Vin = 110 Vrms
Fig. 10. Typical transformer primary voltage and current waveform. Vin =
110 Vrms ; Po = 600 W; scale: V = 125 V/div., I = 15 A/div., and t =
5 s/div.
and Po = 600 W, along with the input and the output inductor
current waveforms. From the waveforms in Fig. 9, it can be
seen that the frequency of the input inductor current is half that
of the output inductor current; this difference in frequency is
due to the asymmetrical auxiliary winding. Fig. 10 shows the
typical transformer primary voltage and current waveforms.
Fig. 11 shows a typical dc bus voltage waveform. Fig. 12
shows the typical auxiliary diode waveforms. Fig. 13 shows the
experimental converter efficiency, which is around 92% at full
load. This is comparable to that of a conventional two-stage
converter.
Fig. 14 shows the dc bus voltage Vbus versus the output load
for various input voltages; it can be seen that the dc bus voltage
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE 4891

Fig. 11. Typical dc bus voltage measured at 265-Vrms input and 100-W
output (V = 60 V/div. and t = 10 ms/div.).
Fig. 13. Experimental efficiency versus output power.

Fig. 14. Experimental dc bus voltage versus output power.

Fig. 12. (a) Typical voltage and current through auxiliary diode Daux1
(V = 60 V/div., I = 5 A/div., and t = 5 s/div.) and (b) typical voltage and
current through auxiliary diode Daux2 (V = 60 V/div., I = 8 A/div., and
t = 5 s/div) at 110-Vrms input and 600-W output.
Fig. 15. Input current harmonics compared to IEC1000-3-2 Class D standard
with an output power of 600 W and an input voltage of 100 Vrms .
Vbus can be kept below 450 V over the required range. Fig. 15
shows the input current harmonics when Vin = 100 V and Po =
VI. C ONCLUSION
600 W, which was determined to be the worst case condition for
the harmonic content. It can be seen that the converter can meet A new acdc single-stage voltage-fed full-bridge converter
the IEC1000-3-2 Class D standards for electrical equipment. It has been proposed in this paper. The converter can perform
was confirmed that the standards were met when Vin = 230 V. input PFC using an auxiliary winding taken off of the main
The range of the input pf was measured to be in the range of power transformer that acts as a switch. This switch is
0.890.94 throughout the operating range. either on, causing the input current to rise, or off, causing the
4892 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 12, DECEMBER 2009
input current to fall. The winding itself is asymmetrical and is
designed so that the input current frequency is half that of the
output current and so that the switch does not allow the full
input voltage to be impressed across the input inductor.
This novel winding scheme has made the proposed converter
to be the only known single-stage voltage-fed full-bridge con-
verter that can operate with standard phase-shift PWM control,
meet the IEC1000-3-2 standards for electrical equipment, yet
maintains a primary-side dc bus voltage of less than 450 V,
regardless of line and load conditions.
In this paper, the operation of the converter has been de-
scribed in detail, and a procedure for the design of the converter
has been given and demonstrated with an example. Experi-
mental results obtained from a prototype have confirmed the
feasibility of the proposed converter.
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Pritam Das was born in Calcutta, India, in 1978.
He received the B.Eng. degree in electronics and
communication engineering from The University of
Burdwan, Bardhaman, India, and the M.A.Sc. de-
gree in electrical engineering from The University
of Western Ontario, London, ON, Canada, in 2005,
where he is currently working toward the Ph.D.
degree in electrical engineering.
His research interests include high-frequency and
high-efficiency acdc and dcdc power converters,
power factor correction and soft switching tech-
niques, and modeling and control of acdc and dcdc converters. He has
published more than 15 technical papers in referred journals and conferences.
DAS et al.: IMPROVED ACDC SINGLE-STAGE FULL-BRIDGE CONVERTER WITH REDUCED VOLTAGE
Shumin Li received the B.S. degree in industrial
automation control from China University of Min-
ing and Technology, Beijing, China, in 1995 and
the M.E.Sc. degree from The University of Western
Ontario, London, ON, Canada, in 2003.
From 1995 to 2001, she was with the Taiyuan Re-
search and Design Institute as an Electrical Engineer.
She was a Research Assistant with The University
of Western Ontario until 2004. Since 2004, she has
been with Intel Corporation, DuPont, WA, as a Se-
nior Hardware Engineer specializing in acdc power
supplies and dcdc switching-mode voltage regulators.
4893
Gerry Moschopoulos (S90M96) received the
B.Eng., M.A.Sc., and Ph.D. degrees in electrical
engineering from Concordia University, Montreal,
QC, Canada, in 1989, 1992, and 1997, respectively.
From 1996 to 1998, he was a Design Engineer
with the Advanced Power Systems Division, Nortel
Networks, Lachine, QC. From 1998 to 2000, he was
a Postdoctoral Fellow with Concordia University,
where he was engaged in research in the area of
power electronics for telecommunications applica-
tions. He is currently an Associate Professor with
The University of Western Ontario, London, ON, Canada.
Dr. Moschopoulos is a Registered Professional Engineer in the province of
Ontario.