Digital Electronics Full Lab Manual

DIGITAL ELECTRONICS LAB (TIUECE-)
List of Experiments
Experiment No. Name of the Experiment Tentative Time to Complete

the Experiment (in
hours/days/weeks)
01. Familiarization with logic 2.5 hrs

gates such as Basic, Universal
and Exclusive gates
02. Realization of NOT, OR, 2.5 hrs

AND, XOR Gates Using
Universal Gates
03. A) Gray to Binary Conversion 2.5 hrs

& Vice-Versa.
B) Code Conversion between

BCD And Excess-3
04. A) Odd and Even Parity 2.5 hrs

Generation And Checking.
B) 4-Bit Comparator Circuit
External Expert HOD Registrar Dean VC

Experiment No. Name of the Experiment Tentative Time to Complete
the Experiment (in
hours/days/weeks)
05. Design of Combinational 2.5 hrs

Circuit To Drive Seven-
Segment Display
06. Design of Combinational 2.5 hrs

Circuits Using Multiplexer
07. A) Half-Adder Circuits & 2.5 hrs

Full-Adder Circuits Using
IC And/ Or Logic Gates.
B) Half-Subtractor Circuits
& Full- Subtractor Using
IC And/ Or Logic Gates
08. Realization Of S-R, J-K, And 2.5 hrs

D Flip Flops Using Universal
Logic Gates
09. Realization of Asynchronous 2.5 hrs

Up OR Down Counter
10. Realization of Synchronous 2.5 hrs

Mod-N Counter

EXPERIMENT NO.1
NAME OF THE EXPERIMENT: Familiarization with logic gates such as Basic, Universal and
Exclusive gates
AIM & OBJECTIVE: Familiarization of Basic gates (NOT, AND ,OR), Universal gates (
NAND, NOR), Exclusive gates (XOR) and to verify their Truth Table.
Apparatus/ Components required: IC- 7404, 7408, 7432, 7400, 7402, 7486 and Digital
Lab Kit.
THEORY:
I. THE INVERTER /NOT GATE (IC- 7404):
The Inverter or the NOT gate performs the logic function of invertion/complementation. It changes
one logic level to opposite logic level, in terms of bits, it changes 1 to 0 and 0 to 1.
LOGIC- Y= , when Y is the output and A is the input.
LOGIC SYMBOL:

PIN DIAGRAM:
CIRCUIT CONNECTION:
Connect Pin 14 to VCC= +5V, pin 7 to Ground. Inputs should be feed to pins 1, 3, 5, 9, 11 & 13
and Outputs should be obtained from 2, 4, 6, 8, 10 & 12 respectively.
TRUTH TABLE:
Input Output
A Y
0 1
1 0
PROBLEM: Apply a pulse waveform to the inverter and determine the Output corresponding to the
input

II. AND GATE (IC-7408):
The AND gate performs logical multiplication, more commonly known as AND operation. It is
composed of two or more inputs and a single output.
LOGIC- Y= A.B, where Y is the output and A and B are the input(for two input AND gate).
LOGIC SYMBOL:
PIN DIAGRAM:

CIRCUIT CONNECTION:
Connect Pin 14 to VCC= +5V, pin 7 to Ground. Inputs should be feed to pins (1 & 2) or (4 & 5) or
(10 & 9) or (12 & 13) and Outputs should be obtained from 3, 6, 8 & 11 correspondingly.
TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
PROBLEM: Make the connection and verify the truth table of Two input AND gate.
III. OR GATE (IC-7432):
The OR gate performs logical addition, more commonly known as OR operation in digital
electronics. It is composed of two or more inputs and a single output.
LOGIC- Y= A + B, where Y is the output and A and B are the input(for two input OR gate).
LOGIC SYMBOL:

PIN DIAGRAM:
CIRCUIT CONNECTION:
TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
PROBLEM: Make the connection and verify the truth table of Two input OR gate.

IV. NAND GATE (IC-7400):
The term NAND is a contraction of NOT-AND and implies an AND function with a
complemented(inverted) output. The NAND gate is a very popular logic function because it is
"Universal" function; that is it can be used to construct an AND gate, OR gate and NOT gate or a
combination of these gates.
LOGIC- Y= A.B, where Y is the output and A and B are the input(for two input NAND gate).
LOGIC SYMBOL:
PIN DIAGRAM:
CIRCUIT CONNECTION:

TRUTH TABLE:
Inputs Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
PROBLEM: Make the connection and verify the truth table of Two input NAND gate.
V. NOR GATE (IC-7402):
The term NOR is a contraction of NOT-OR and implies an OR function with a

complemented(inverted) output. The NOR gate is a very popular logic function because it is
"Universal" function like NAND; that is it can be used to construct an AND gate, OR gate and NOT
gate or a combination of these gates.
LOGIC- Y= A + B, where Y is the output and A and B are the input(for two input NOR gate).
LOGIC SYMBOL:

PIN DIAGRAM:
CIRCUIT CONNECTION:
TRUTH TABLE:
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
PROBLEM: Make the connection and verify the truth table of Two input NOR gate.

VI. XOR GATE (IC-7486):
The XOR gates gives a HIGH output when the inputs are at opposite logic levels. This is a widely
used gate because of its special arithmetic property.
LOGIC- = +
= , where Y is the output and A, B is the input of XOR gate.
LOGIC SYMBOL:
PIN DIAGRAM:
CIRCUIT CONNECTION:

TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
PROBLEM: Make the connection and verify the truth table of Two input XOR gate.
PROCEDURE:
RESULTS & ANALYSIS:
CONCLUSION:
ASSIGNMENT QUESTIONS (OPTIONAL):

EXPERIMENT NO.2
NAME OF THE EXPERIMENT: Realization of basic logic gates using Universal gates.
AIM & OBJECTIVE: Realization of the function (NOT, AND ,OR, XOR, XNOR), Using
NAND gate and NOR gate and to verify their Truth Table.
Apparatus/ Components required: IC- 7400, 7402 and Digital Lab Kit.
THEORY:
The NAND and the NOR gates can be used to produce any logic function, that is why they are
referred as "universal gates".
All Boolean expressions consists of various combination of basic function like NOT, AND and OR,
however rather than using separate gates, all operation can be executed using only NAND or NOR
gate.
PIN DIAGRAM:

LOGIC ANALYSIS OF XOR & XNOR:
I. XOR GATE:
=
= +
= + + +
= + . ( + )
TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
II. XNOR GATE:
=
= +
= . ( )
= ( + ). ( + )
= +

TRUTH TABLE:
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
LOGIC DIAGRAMS :
Use of NAND gate:
I. NOT using NAND
II. AND using NAND

III. OR using NAND
IV. XOR using NAND
V. XNOR using NAND

Use of NOR gate:
I. NOT using NOR
II. OR using NOR
III. AND using NOR
IV. XOR using NOR

V. XNOR using NOR

EXPERIMENT NO. 3A
NAME OF THE EXPERIMENT: Gray to Binary conversion & vice-versa
AIM & OBJECTIVE: Design of basic logic circuit for Binary-to-Gray conversion & Gray-to-
Binary conversion.
Apparatus/ Components required: IC- 7486 and Digital Lab Kit.
THEORY:
BINARY-TO-GRAY CONVERSION:
1. The most significant digit(left most) in the Gray code is the same as the corresponding digit in
Binary number.
2. Going from left to right, add each adjacent pairs of Binary digits to get the next Gray code digit.
ignore the carries.
Conversion of Binary number 101102 to Gray:

GRAY-TO-BINARY CONVERSION:
1. The most significant digit(left most) in the Binary code is the same as the corresponding digit in
Gray code.
2. Going from left to right, add each of Binary digits generated to the Gray code in the next adjacent
position. ignore the carries.
Conversion of Gray number 11011 to Binary:
LOGIC DIAGRAM:

PIN DIAGRAM:

EXPERIMENT NO. 3B
NAME OF THE EXPERIMENT: Code conversion between BCD & EXCESS-3
AIM & OBJECTIVE: Design of basic logic circuit to realize the code conversion BCD and
EXCESS-3.
THEORY:
The EXCESS-3 is a digital code that is delivered by adding +3 to each decimal digit and then
converting the value to four-bit Binary. For instance the EXCESS-3 code for 2 is
2
+3
5 01012
The EXCESS-3 code for decimal 9 is
9
+3
12 11002
TABLE:

Notice that ten of possible 16 code combinations are used in EXCESS-3 code. The six nvalid
combinations are 0000, 0001, 0010, 1101, 1110 and 1111.
Self Complementing Property: The key feature of EXCESS-3 code is that it is self complementing.
That is the 1's complement of an EXCESS-3 number is the EXCESS-3 code for the 9's complement
of the corresponding decimal number.
for example: The EXCESS-3 code for decimal 4 is 0111, The 1's complement of this is 1000, which
is the EXCESS-3 code for decimal 5(5 is the 9's complement of 4).
PIN DIAGRAM:
CIRCUIT DIAGRAM:

EXPERIMENT NO. 4A
NAME OF THE EXPERIMENT: ODD & EVEN Parity checking and Generation.
AIM & OBJECTIVE: Design of basic logic circuit for ODD & EVEN Parity checking and
Generation .
Apparatus/ Components required: IC- 7486, 7404 and Digital Lab Kit.
THEORY:
Errors can occur as digital codes are being transferred from one point another within a digital
system or while codes are being transmitted from one system to another. The errors take the form of
undesired changes in the bits that make up the coded information; a 1 can change to 0 and vice
versa, due to component malfunction or electrical noise. Many systems however employ a parity bit
in order to detect an error. Binary information is normally handled by a group of bits called words.
A word always contains either a odd or even no, of 1-s. A parity bit is attached to the group of
information bits in order to make the total no, of 1-s always even or always odd. An even parity bit
makes total no, of 1-s even and odd parity bit makes total odd.
A given system operates with even or odd parity, but not both. For instance if a system operates
with even parity, a check is made on each group of bits received to make sure the total no, of 1-s in
the group is even. If there is an odd no, of 1-s an error has occurred.
Detecting an Error:
A parity bit provides for the detection of a single error. But cannot check for two errors. For
instance, let us assume that we wish to transmit the BCD code 0101. The code transmitted,
indicating the even parity bit is,

Now let us assume a error occurs in the 3rd bit from the left(the 1 becomes a 0) as follows
When bit code is received the parity check circuitry determines that there is only a single 1(odd
number), when there should be an even no, of 1-s. Because a even no, of 1-s does not appear in the
code when it is received, an error is indicated.
Let us now consider a case for 2 bit errors occur as follows
When a check is made an even no, of 1-s appears, and although there are 2 errors, the parity check
indicates a correct code.
PIN DIAGRAM:

LOGIC DIAGRAM:

EXPERIMENT NO. 4B
NAME OF THE EXPERIMENT: 4-bit Magnitude Comparator
AIM & OBJECTIVE: To verify the truth table of a 4-bit Magnitude Comparator
THEORY:
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3, . An, etc) against that of a constant or unknown value such as B (B1,
B2, B3, . Bn, etc) and produce an output condition or flag depending upon the result of the
comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce
the following three output conditions when compared to each other.
Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when any of the
above three conditions are achieved. For example, produce an output from a counter when a certain
count number is reached. Consider the simple 1-bit comparator below.
1-bit Digital Comparator Circuit

Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Digital Comparator Truth Table:
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
4-Bit Comparator
It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0 and B3
B2 B1 B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and produces one of
the following outputs as A = B, A < B and A>B. The output logic statements of this converter are
If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and B0
= 0, then A > B.

4-bit Comparator Truth Table:
PIN DIAGRAM OF IC 7485:

EXPERIMENT NO. 6A
NAME OF THE EXPERIMENT: 8x1 Multiplexer circuit
AIM & OBJECTIVE: To verify the truth table of a 8x1 Multiplexer
THEORY:
A Multiplexer is a combinational circuit with more than one input lines, one output line and one or
more selection lines. A Multiplexer selects binary information present on any one of the input lines,
depending upon the logic status of the selection inputs, and sends it to the output line.
If there are n selection lines, then the number of maximum possible input lines is 2n and such
multiplexer is referred to as a 2n-to-1 or 2n x 1 Multiplexer, here we will study 8x1 multiplexer.
8x1 multiplexer : A 8-to-1 multiplexer(MUX) is a combinational circuit with 8 input lines, I0, I1, I2,
I3, I4, I5, I6 and I7 one output line, O and three selection lines, S2, S1 and S0. On receiving active low
enable input, mux is able to perform the intended function.
LOGIC DIAGRAM:

Logical expression: O = 0 + 1 + 2 + 3 +
4 + 5 + 6 + 7
TRUTH TABLE:
INPUT OUTPUT
S2 S1 S0 O
1 X X X 0
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7

PIN DIAGRAM:
In the above pin diagram of IC- 74151, D0 to D7 are the input lines , S2, S1, S0 are selection lines , Y
and are the output line and is the enable line.

EXPERIMENT NO. 6B
NAME OF THE EXPERIMENT: 1-to-8 line Demultiplexer circuit
AIM & OBJECTIVE: To verify the truth table of a 1-to-8 line Demultiplexer
THEORY:
A Demultiplexer is a combinational circuit with one input line, two or more output lines and one or
more select lines. A DeMUX routes binary info present on the input, to any one of the output lines.
The output line that receives info present in the input line is selected by the bit status of the
selection lines.
A DeMUX has a single input line, 2n output lines and n selection lines. A decoder is a kind of
DeMUX without a input line.
1-to-8 line Demultiplexer: A 1-to-8 DeMUX is a combinational circuit with one input line I and
eight output lines O0, O1, O2, O3, O4, O5, O6, O7 and three select lines , S2, S1 and S0
LOGICAL DIAGRAM:

TRUTH TABLE:
INPUTS OUTPUTS
G2A G2B E S2 S1 S0 OO O1 O2 O3 O4 O5 O6 O7
0 0 0 X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0

PIN DIAGRAM:
In the above pin diagram of IC- 74138, G2A and G2B are the input lines. A , B and C are the
selection lines S2, S1, S0 respectively. O0, O1, O2, O3, O4, O5, O6, O7 are the output lines and is the
enable line.

EXPERIMENT NO. 7A
NAME OF THE EXPERIMENT: Half Adder and Full Adder circuits
AIM & OBJECTIVE: To design a Half Adder and Full Adder circuits using basic gates and to
verify its truth table
Apparatus/ Components required: IC- 7486, 7432, 7408 and Digital Lab Kit.
THEORY:
In digital electronics adder is a circuit that adds binary numbers. Adders can be constructed to carry
out many numerical representation.
Half Adder: A Half Adder is a logical circuit that performs an addition operation on two binary
digits. The Half adder produces a sum and carry value which are both binary digits.
Sum = A B;
Carry= AB.
LOGICAL DIAGRAM:

TRUTH TABLE:
Full Adder: A Full Adder is a logical circuit that performs an addition operation on three binary
digits. A Full Adder produces a Sum and Carry Values, which are both binary digits. It can be
combined with other Full adders or work on its own
Sum = (A B) Ci ;
COUT = (AB) + Ci . (A B),
LOGICAL DIAGRAM:

TRUTH TABLE:

Experiment No. 7B
Name of the experiment: Half Subtractor and Full Subtractor circuits

AIM & Objective: To design a Half Subtractor and Full Subtractor circuits using basic gates
and to verify its truth table
Apparatus/ Components required: IC- 7486, 7432, 7408, 7404 and Digital Lab Kit.
Theory:
To process numerical data, arithmetic operations are necessary. To perform arithmetic operations,
arithmetic circuits are required. To process the binary data, subtract operation needs to study.
Half Subtractor: Single-bit value is subtracted from another single bit value to produce difference
and borrow bits. Any borrow from second bit into first bit is known as borrow taken. Half
Subtractor circuit performs subtraction of single bit value from another single bit value and
produces single bit difference and borrows.
Difference = A B;
Borrow = B.
LOGICAL DIAGRAM:

TRUTH TABLE:
Full Subtractor: Single bit value is subtracted from second single bit value considering previous
borrow to produce difference and borrow bits. Any borrow from second bit into first bit is known as
borrow. Full Subtractor circuit performs subtraction of single bit from another single bit value
considering borrow and produces single bit difference and borrow.
Difference = (A B) Bi;
Borrow = B + ( ).Bi.
LOGICAL DIAGRAM:

TRUTH TABLE:

Experiment No. 8
Name of the experiment: Realization of S-R, J-K, D and T Flip-Flops using universal
gates/IC
AIM & Objective: To design a S-R ,J-K, D & T Flip-Flop circuits using universal gates and to
verify its state table.
Apparatus/ Components required: IC- 7402, 7432, 7408, 7404,7476, 7474 and Digital
Lab Kit.
Theory:
Digital circuits are differentiated between combinational logic and sequential logic circuits. In
Sequential logic circuits the instantaneous outputs depend on the present inputs and also on the past
inputs or outputs. Thus circuit contains elements or memory that can store past info.
Flip-Flop: It is the basic element of sequential circuits, which is a bistable multivibrator and can
serve as a memory element. A Flip-Flop has two states 0 and 1, the output of a Flip-Flop can remain
in one of the two states indefinitely unless an external trigger is applied to change the state.
S-R Flip-Flop: It is known as Set and Reset Flip-Flop The characteristic is defined as
a) If R=0 ,S=0, i.e. in the absence of any trigger input, the output retains its state
obtained in immediately preceding operation i.e. output Y is either 0 or 1. This
state is known as No Change state.
b) If R=0 ,S=1, i.e. if any trigger input is applied , output Y is 1. This condition
is known as SET.
c) If R=1 ,S=0, i.e. if any trigger input is applied , output Y is 0. This condition
is known as RESET.
d) If R=1 ,S=1, i.e. If a trigger is applied, a problem arises since the output Y is
forced simultaneously to 0 and 1 . Thus this state is known as Forbidden State.

LOGICAL DIAGRAM:
Nor gate realization of S-R Flip-Flop.
CHARACTERISTIC TABLE:
Qn S R Qn+1 OPERATION
0 0 0 0 NO
1 0 0 1 CHANGE
0 0 1 0 RESET
1 0 1 0
0 1 0 1 SET
1 1 0 1
0 1 1 X FORBIDDEN
1 1 1 X

D Flip-Flop: The D stands for Delay type Flip-Flop. It overcomes the disadvantage of S-R Flip-
Flop. D Flip-Flop is not dependent on previous state. When ever a clock pulse is applied the current
input is transmitted over to the output.
LOGICAL DIAGRAM:
Nor gate realization of D Flip-Flop.

PIN DIAGRAM:
Pin configuration of dual D Flip-Flop IC- 7474.

Qn D Qn+1
0 0 0
1 0 0
0 1 1
1 1 1
NOTE: while using the IC 7476 Set and Clear Inputs should be high i.e. 1.
J-K Flip-Flop: The main disadvantage of S-R Flip-Flop is its forbidden state but J-K Flip-Flop
overcomes this operation for both J=K= 1, The Output Toggles its previous states. Rest of the states
are same as S-R FF.
LOGICAL DIAGRAM:
Nor gate realization of J-K Flip-Flop.

PIN DIAGRAM:
Pin configuration of dual J-K Flip-Flop IC- 7476.
Qn J K Qn+1 OPERATION
0 0 0 0 NO
1 0 0 1 CHANGE
0 0 1 0 RESET
1 0 1 0
0 1 0 1 SET
1 1 0 1
0 1 1 1 TOGGLE
1 1 1 0
NOTE: while using the IC 7476 Preset and Clear Inputs should be high i.e. 1.

Experiment No. 9
Name of the experiment: Asynchronous UP counter
AIM & Objective: To design an Asynchronous MOD-16 UP counter using J-K Flip-Flop and
to verify its state table.
Theory:
Counter is a clocked sequential circuit that goes through a predetermined sequence of atates upon
the application of input signals. Counters are designed using J-K or T Flip-Flops because these FFs
have Toggle States. A counter follows binary sequence is called n-bit binary counter, Binary
counter has n-FFs and possible number of states are 2n , which are passed through in the order
0,1,2,, 2n -1 and repeats from 0.
Asynchronous counter is also known as ripple counter,
serial or series counter, Here all the inputs are kept at logic state 1 and clock pulse is applied to the
LSB bit FF and each output servers as a clock input for the next FF.
LOGICAL DIAGRAM:

PIN DIAGRAM:
Pin configuration of dual J-K Flip-Flop IC- 7476.
Timing Diagram of MOD-16 UP Counter:

CLK J K Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0 +
0 1 1 0 0 0 0 0 0 0 1
1
0 0 0 1 0 0 1 0
2 0 0 1 0 0 0 1 1
3
0 0 1 1 0 1 0 0
4 0 1 0 0 0 1 0 1
5
0 1 0 1 0 1 1 0
6
0 1 1 0 0 1 1 1
7
0 1 1 1 1 0 0 0
8
1 0 0 0 1 0 0 1
9
1 0 0 1 1 0 1 0
10
1 0 1 0 1 0 1 1
11
1 0 1 1 1 1 0 0
12 1 1 0 0 1 1 0 1

13 1 1 0 1 1 1 1 0
14 1 1 1 0 1 1 1 1
15 1 1 1 1 0 0 0 0

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DIGITAL ELECTRONICS LAB (TIUECE-)

Experiment No. Name of the Experiment Tentative Time to Complete

01. Familiarization with logic 2.5 hrs

02. Realization of NOT, OR, 2.5 hrs

03. A) Gray to Binary Conversion 2.5 hrs

B) Code Conversion between

04. A) Odd and Even Parity 2.5 hrs

B) 4-Bit Comparator Circuit

External Expert HOD Registrar Dean VC

05. Design of Combinational 2.5 hrs

06. Design of Combinational 2.5 hrs

07. A) Half-Adder Circuits & 2.5 hrs

08. Realization Of S-R, J-K, And 2.5 hrs

09. Realization of Asynchronous 2.5 hrs

10. Realization of Synchronous 2.5 hrs

External Expert HOD Registrar Dean VC

I. THE INVERTER /NOT GATE (IC- 7404):

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

III. OR GATE (IC-7432):

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

V. NOR GATE (IC-7402):

The term NOR is a contraction of NOT-OR and implies an OR function with a

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

RESULTS & ANALYSIS:

ASSIGNMENT QUESTIONS (OPTIONAL):

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

II. XNOR GATE:

External Expert HOD Registrar Dean VC

I. NOT using NAND

II. AND using NAND

External Expert HOD Registrar Dean VC

IV. XOR using NAND

V. XNOR using NAND

External Expert HOD Registrar Dean VC

I. NOT using NOR

II. OR using NOR

III. AND using NOR

IV. XOR using NOR

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

NAME OF THE EXPERIMENT: Gray to Binary conversion & vice-versa

Apparatus/ Components required: IC- 7486 and Digital Lab Kit.

Conversion of Binary number 101102 to Gray:

External Expert HOD Registrar Dean VC

Conversion of Gray number 11011 to Binary:

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

NAME OF THE EXPERIMENT: Code conversion between BCD & EXCESS-3

Apparatus/ Components required: IC- 7483 and Digital Lab Kit.

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

External Expert HOD Registrar Dean VC

NAME OF THE EXPERIMENT: 4-bit Magnitude Comparator

Apparatus/ Components required: IC- 7485 and Digital Lab Kit.

Which means: A is greater than B, A is equal to B, and A is less than B