Project description

This project consists in making a logical analyzer,which can help us analyze digital hardware,
project verification and integration of software analysis. The logical analyzors are usually made
of 34 and 136 channels, each channel has a single digital signal. It does not measure analog
details, but instead detects levels of logic thresholds.

We use the logic analyzer to be able to:

- Trigger and check the operation of the digital system;

- Track and correct multiple digital signals simultaneously;

- Detect and analyze sync errors;

- Track the execution of embedded software.

Using the LabView project system, we will transmit a sequence of 11 bits serially via the RS-232
interface. Those 11 bits have the following meaning: the first bit is the start bit value(0 logic), the
next 8 bits are the data bits, the penultimate bit represents the parity bit and the last bit represents
the stop bit (1 logic) which indicates the end of receiving a byte. The logical analyzer consists of
3 large sub-blocks: the block of registers, the FIFO memory block and the logical block of
acquisition.

The block of registers is also made of five sub-blocks:

-The address register consists of 8 D-type bistabs, connected to a common clock signal;it should
be analyzed along with the address decoder because it's like a buffer which has the role of
sending the data to the address decoder so that data can be interpreted. At the level of the decoder
we have an exit which when the 0 logic signal is given,it begins to decode the received data. It
works on two bits;

-The command register activates when it receives a clock signal from the address decoder. At the
input we have 8 bits of data and at the output we have 6 bits,the first 4 bits represent the ROM
entry(sets the sampling frequency) and the next 2 bits are input bits for the data acquisition logic;

-The control register sets the mode and trigger type;

-The status register consists of 2 D-type bistabs with 3 entries. By the first input the register
receives the clock signal from the acquisition logic, starting to work.
The other two entries have the following meaning: one of the bits signals that the FIFO data
memory is empty, which means that the data will be transmitted by the status register to an
analyzer output. The other bit ihas the main role to reset this registry after a full purchase has
been made.

-The register who orders the acquisition logic has as inputs those 8 data bits and a clock signal,
given by the address decoder.

The logic block of acquisition has the primary role of determining the number of bits of the
received data sequence. This function is performed with a numerator and a 2x4 multiplexer.
According to the communication parameters we have a number of 16,32,64 or 128 samples of
input data. Depending on the number of samples selected, the counter will count up to that value,
then using the multiplexer will display a signal indicating that a complete purchase has been
made.

The FIFO memory block has a FIFO memory as the primary element(First in First out). It has the
role of memorizing a data set (it can store up to 128 bytes). In addition to this memory, it also
contains two blocks: one consisting of "AND" gates and one consisting of 8x1 multiplexers. The
sub-block consisting of 8 logical "AND" has the role of letting the information pass, or to block
its arrival in FIFO memory, based on a signal. The block of multiplexers is designed to sort out
which information will reach the transmission block, the set of bytes in FIFO memory, and if the
memory is empty, based on a signal given by the register block, will start transmitting the data
from the status register.

Communication with the PC is done using the RS-232 serial interface and the LabView software.
At the serial RS-232 interface, the transmission and reception is bit-bitted, requiring only one
thread for transmission. RS-232 is a standard,in the sense that all computer models and most
measuring instruments incorporate them. Serial data can be sent synchronously(clocked) or
asynchronously(clocked). This interface has two types of connectors available: DB25S and
DB9S. The first ensures the total functionality of the interface while the second provides a
minimal space for the smaller instrumentation in dimensions.

The signals of this interface are divided into 3 categories:

-data (TxD, RxD). There are two data channels that allow full-duplex communication
(bidirectional);

-Communication control (RTS, CTS). These signals provide the support through which data
traffic is controlled.

-timing (TC, RC). For synchronous communications, it is necessary to transmit a tact signal to
synchronize the receiver with the transmitter.
The data is transmitted as packets, each representing a single ASCII character and containing
sufficient information to be decoded without the help of a tact signal.

LabVIEW is a graphical programming language that uses block diagrams to create applications.
With this software we can display the data, where you can see and interpret the resulting
waveforms. These applications are built to control and acquire data, analyze them and present
results. In the graphical programming environment provided by LabVIEW, the virtual tool
defines a program that consists of a user-interface, the front panel and a block schema program.

On the front panel you can make multiple selections based on user choices:

*Comm Settings :

-Port name;

-Baud rate;

-Data bits;

-Parity;

-Stop bits.

*ACQ Settings:

-Number of samples;

-Frequency of sampling(which has defined values);

- Trigger(ON,OFF);

-Trigger Edge.

*RUN button that starts a data acquisition

*FIFO EMPTY - Signals when the FIFO data memory is empty;

*ACQ COMPLETE - Signals when signal acquisition (equivalent to bits in the status
register) is completed;

*The stop button has the role of stopping the program running;

*Serial visa sets the serial port setting;