EEE 525: VLSI Design, L-02

CMOS Technology and

Transistor Modeling

Spring 2007, ASU

Yu (Kevin) Cao, yu.cao@asu.edu, GWC 336

Highlight
ƒ CMOS technology
– MOSFET fabrication
– Evolution with scaling
ƒ MOSFET modeling
– Intuitive understanding
– Models for a long channel transistor
• Threshold voltage (Vth)
• Current-voltage relations (IV)

ƒ Reading: Chapter 2 and 3

ƒ Announcement for the CAD Lab
EEE525, ASU, Y. Cao Lecture 02 -2-

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Announcement (I)
ƒ If you have any questions
– Check MyASU; discuss with your teammates
– Come to the office hours
– Contact TA for lab questions
ƒ CAD tools needed:
– Cadence for layout and extraction
– Spectre for circuit simulation
– Technology: TSMC 0.25µm
– You can NOT run them off campus
ƒ Online students:
– Need to have your own Cadence tools
– Have your own access to a 0.25µm CMOS technology
– Project done by yourself
– Email TA regarding your lab questions

EEE525, ASU, Y. Cao Lecture 02 -3-

Announcement (II)
ƒ Lab: GWC 273 Time Mon Tue Wed Thu Fri
ƒ TA: Bashir Mahmud 8:00

(ERC 520) 10:00

Bashir.Mahmud@asu.edu 12:00

ƒ Lab hours: 2:00

Tue: 8am – 1pm 4:00

Wed: 4:30 – 8:30pm 6:00

Thu: 8am – 1pm 8:00

EEE525, ASU, Y. Cao Lecture 02 -4-

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Highlight
ƒ CMOS technology
– MOSFET fabrication
– Evolution with scaling
ƒ MOSFET modeling
– Intuitive understanding
– Models for a long channel transistor
• Threshold voltage (Vth)
• Current-voltage relations (IV)

ƒ Reading: Chapter 2 and 3

ƒ Announcement for the CAD Lab
EEE525, ASU, Y. Cao Lecture 02 -5-

A Modern CMOS Technology

Front End Backend
A. Poly-Si gate D. Channel
B. Source/Drain E. Active well
C. Trench isolation H. Contact

EEE525, ASU, Y. Cao Lecture 02 -6-

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3D Perspective of a MOSFET
ƒ MOSFET:
Metal-Oxide-Semiconductor Field Effect Transistor
Polysilicon/Metal Gate Aluminum/Copper

N+

EEE525, ASU, Y. Cao Lecture 02 -7-

NMOS and PMOS Structures

N-Type MOSFET (NMOS)

p- substrate te D D D
Ga W
p+ n+ L n+ G B G G
Oxide
Bulk Source Drain

P-Type MOSFET (PMOS) S S S

te S S S
Ga W
n+ p+ L p+ G B G G
Oxide
Source Drain
N-well
D D D

ƒ Symmetrical along width (W), but changing along length (L)

EEE525, ASU, Y. Cao Lecture 02 -8-

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Basic MOSFET Operations
NMOS PMOS
D S

G B Ids ∝ W G B

S D

VGS=VG-VS>Vth VGS=VG-VS<Vth
VDS>0 VDS<0
(VB=0) (VB=VDD)
Vth: threshold voltage (>0 for NMOS and <0 for PMOS)

EEE525, ASU, Y. Cao Lecture 02 -9-

A CMOS Process Flow

Define active areas
Lithography, oxidation
Etch and fill trenches

Implant well regions Doping

Deposit and pattern

polysilicon layer Lithography, oxidation

Implant source and drain

regions and substrate contacts Doping, lithography

Create contact and via windows

Deposit and pattern metal layers Lithography, metallization

EEE525, ASU, Y. Cao Lecture 02 - 10 -

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Photo-Lithographic Process
optical
mask
oxidation

photoresist photoresist coating

removal (ashing)
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process spin, rinse, dry
step

EEE525, ASU, Y. Cao Lecture 02 - 11 -

Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

EEE525, ASU, Y. Cao Lecture 02 - 12 -

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 Layer / Feature ID
Top & Cross-Section View Source-to-Drain
(Layered) Cross-Section
Source Gate Drain metal lines
• • •
contact / via
Source Gate Drain
interlayer • • •
dielectric
(ILD)
N+
poly-Si gate
N+ N+
gate oxide

source P-
/ drain

trench
isolation
substrate
/ well

EEE525, ASU, Y. Cao Lecture 02 - 13 -

Layout View: Dual-Well Process

NMOS PMOS

p+ n+ n+ p+ p+ n+
Source Drain Drain Source
P- N-well

EEE525, ASU, Y. Cao Lecture 02 - 14 -

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A CMOS Inverter

VDD VDD

PMOS

Vin Vout

Vin VOUT
NMOS

ƒ Fabricated together through Dual-

GND
Well Trench-Isolated CMOS Process

EEE525, ASU, Y. Cao Lecture 02 - 15 -

Critical Process Steps

Vth Control:
~100 dopants

12Å (~5 atoms)

Critical Dimension
EEE525, ASU, Y. Cao Lecture 02 - 16 -

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Technology Evolution
ƒ International Technology Roadmap for Semiconductors:
1947 http://public.itrs.net/
2002
(90nm node)
2015? ????

e
15nm

at
G

n
ai
Dr
ec
50nm

ur
So
ƒ New materials and structures to keep the scaling
– Improve carrier mobility (e.g., SiGe channel)
– Reduce gate/S/D resistance (e.g., metal-gate, Ge for S/D)
– Suppress gate and channel leakage (e.g., high-k insulator)
EEE525, ASU, Y. Cao Lecture 02 - 17 -

Highlight
ƒ CMOS technology
– MOSFET fabrication
– Evolution with scaling
ƒ MOSFET modeling
– Intuitive understanding
– Models for a long channel transistor
• Threshold voltage (Vth)
• Current-voltage relations (IV)

ƒ Reading: Chapter 2 and 3

ƒ Announcement for the CAD Lab
EEE525, ASU, Y. Cao Lecture 02 - 18 -

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 A Transistor in Digital Circuits
A MOSFET A Switch!
Vgs=Vg-Vs |Vgs|>Vth

S L D S Ron D

ƒ Ids is a non-linear function

of: W, L, Vgs, Vds, and Vth
ƒ Ron ∝ V/I ∝ 1/W
Ids

Vgs
EEE525, ASU, Y. Cao Lecture 02 - 19 -

A CMOS Inverter
ƒ The simplest logic unit of digital circuits

VDD Vin Vout

Vin
CL

Vin Vout

CL
In Out
0 1
Vin
1 0

EEE525, ASU, Y. Cao Lecture 02 - 20 -

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Switching Behavior
VDD

Rp

Vout
Vin Vout
CL
CL

(a) Low-to-high

VDD

ƒ Current driving a load capacitor

ƒ MOSFET: a voltage-controlled
Vout
CL
Rn
current source, with parasitic
capacitance (b) High-to-low

EEE525, ASU, Y. Cao Lecture 02 - 21 -

MOSFET Operations
Ids = Q·v·W= Qinv·(µE)·W ƒ Two electrical fields:
– G-S
µ: mobility; W: width
– D-S
ƒ Threshold voltage (Vth):
+ + -
VGS
Vgs when strong
VDS
- inversion happens
Φs ƒ Depletion (cut-off)
– Vgs < Vth
n+ n+
n+ n+ ƒ Inversion
Ids – Vgs > Vth
p- substrate (i.e., channel surface
potential Φs > 2ΦB)

EEE525, ASU, Y. Cao Lecture 02 - 22 -

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The Threshold Voltage (Vth)
V th = V th 0 + ∆ V th (V sb ) − ∆ V th (L , V ds ) + ∆ V th (W )
Qdep
Vth 0 = (Φ MS − 2Φ B ) +
Qit
+ +
COx COx
VGS
- Vg ΦMS: work function difference

Φs Cox ΦB: band voltage

Qdep: depletion charge

n+ Vs
n+ n+
n+
Qit: interface charge
Vb ε ox
p- substrate Cox =
tox
tox: electrical oxide thickness

ƒ More understanding: EEE 436 or come to my office hours

EEE525, ASU, Y. Cao Lecture 02 - 23 -

Body Bias (Vsb) Dependence

+
- + D
VSB VGS
-
Φs G B

n+ Vs
n+ n+
n+ +S
VSB

Vb -
p- substrate

ƒ If Vsb>0, Φs at threshold: − 2Φ B − 2Φ B + Vsb

Vth = Vth 0 + γ ( − 2Φ B + Vsb − − 2Φ B ) γ=

2qε Si N A
Cox
EEE525, ASU, Y. Cao Lecture 02 - 24 -

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 Vth Extraction

Ids (A) Ids (A)

(linear) (logarithm) NMOS: 10-7·(W/L)
PMOS: 6x10-8·(W/L)
Vsb>0

Vth Vgs Vth Vgs

(1) (2)

EEE525, ASU, Y. Cao Lecture 02 - 25 -

Current-Voltage Relations
VGS VDS Ids = Q·v·W= Qinv·(µE)·W

Qinv ( x) = Cox (Vgs − Vth − V ( x) )

dx
n+
n+ n+ dV ( x)
V(x) E ( x) =
dx

I ds ⋅ dx = µCox ⋅ W ⋅ (Vgs − V ( x) − Vth )⋅ dV ( x)

⎞ ⎡ Vds2 ⎤
Linear ⎛W
I ds = µCox ⋅ ⎜ ⋅ ( − )
⎟ ⎢ gs th ds
V V ⋅ V − ⎥
⎝L ⎠ ⎣ 2 ⎦

EEE525, ASU, Y. Cao Lecture 02 - 26 -

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Saturation Operations
⎛W ⎞ ⎡ V2⎤
I ds = µCox ⋅ ⎜ ⎟ ⋅ ⎢(Vgs − Vth )⋅ Vds − ds ⎥ How about Vds > (Vgs-Vth)?
⎝L⎠ ⎣ 2 ⎦
Qinv ( x) = Cox (Vgs − Vth − V ( x) ) < 0 ?
VGS VDS
The impact of Vds stops at
n+
n+ n+ V(x)=(Vgs-Vth)

µC ox ⋅ ⎜ ⎟ ⋅ (V gs − Vth )2
1 ⎛W ⎞
pinch-off I ds =
2 ⎝ L⎠

ID(SAT)
ID

channel
source
channel
source
drain
Linear Saturation
drain
EEE525, ASU, Y. Cao Lecture 02 - 27 -

Channel Length Modulation

4.0

VGS VDS
3.0
I DS (mA)

n+
n+ n+ 2.0

1.0

Channel length shortened 0.0

0 1 2 3 4 5
VDS (V)

⎟ ⋅ (Vgs − Vth ) ⋅ (1 + λVds )

1 ⎛W ⎞
I ds = µCox ⋅ ⎜ 2

2 ⎝L ⎠
ƒ λ: an empirical parameter for CLM
ƒ CLM: important for output resistance
EEE525, ASU, Y. Cao Lecture 02 - 28 -

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IV Curves
-4
x 10
6
VGS= 2.5 V

Linear Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Dependence
2
on Vgs
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

EEE525, ASU, Y. Cao Lecture 02 - 29 -

A Model for Long-Channel MOSFET

Threshold voltage (Vth)
Vth = Vth 0 + γ ( − 2Φ B + Vsb − − 2Φ B )
Linear: Vds < (Vgs – Vth)

⎛W ⎞ ⎡ Vds2 ⎤ ε ox
I ds = µCox ⋅ ⎜ ⎟ ⋅ ⎢(Vgs − Vth )⋅ Vds − ⎥ Cox =
⎝L⎠ ⎣ 2 ⎦ tox
Saturation: Vds > (Vgs – Vth)

µCox ⋅ ⎜ ⎟ ⋅ (Vgs − Vth )2 ⋅ (1 + λVds )

1 ⎛W ⎞
I ds =
2 ⎝L⎠
ƒ PMOS: Vgs, Vth, and Vds are negative
– Direct calculation: Ids is negative ⇒ I from S to D
– If we use absolute values, the formulas are the same.
EEE525, ASU, Y. Cao Lecture 02 - 30 -

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