Ldic-2 Eee PDF

COURSE FILE
LINEAR & DIGITAL IC APPLICATIONS
R13
III B.TECH I SEMESTER
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TABLE OF CONTENT
S.NO. Content
1 Course Objectives & Outcomes
2 Syllabus
3 Lecture Plan
4 Unit wise course Material (As per given format)
Unit-I: Introduction to Op-Amps
Unit-II:OP-Amps Parameters
Unit-III: Ideal operational amplifier theory and basic circuits
Unit-IV: Waveform generator in angular waveform generator using op-

amps and PLL
Unit-V: Active Filters
Unit-VI: Digital To Analog And Analog To Digital Converters
5 Reference text books/web material etc.,
6 Mid Question Paper + Schemes of Evaluation.
7 Fast track material for Back-Log students.
8 Sample Question Papers with solutions
9 Virtual Labs if required

Mapping of Assignments / Question Papers with course objective learning
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outcomes.
11 Blooms Taxonomy checklist
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1. Course Objectives & Outcomes
Course Objectives
The objectives of the course are:
- Study characteristics, realize circuits, design for signal analysis using Op-amp
ICs.
- Study the linear and non-linear applications of operational amplifiers.
- Study IC 555 timer, PLL and VCO with their applications.
- Study and understand different types of ADCs and DACs
- Acquire skills required for designing and testing integrated circuits
Course Outcomes
After completing this Course, the student should be able to:
- Design circuits using operational amplifiers for various applications

- Analyze and design amplifiers and active filters using Op-amp
- Acquire skills required for designing and testing integrated circuits
- Understand the gain-bandwidth concept and frequency response of the amplifiers.
- Understand thoroughly the operational amplifiers with linear integrated circuits.
2. Syllabus
UNIT I
Introduction to Operational Amplifier:

Block diagram of Typical OpAmp With Various Stages BJT Differential Amplifier
With RE DC Analysis AC Analysis BJT differential amplifier with constant current
source Analysis Different input/output configurations dual input balanced output
Dual input unbalanced outputSignal input balanced outputSignal input unbalanced
outputAC analysis with r parameters Current repeater circuitsCurrent mirror
circuitsAnalysis Level translator Cascade differential amplifier FET differential
amplifier.
UNIT II
OPAMP Parameter:
Input offset voltage Input offset currentInput bias currentDifferential input
resistanceCommon mode rejection ratioSlew ratioPSRRLarge signal voltage gain
Output voltage swing transients responsedefinitions and explanations. Measurement of
bias currentMeasurement of offset currents Measurement of offset voltage
Measurement of slew rate Output offset voltage balancing circuitsBias current
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compensations circuitDual power suppliers with shunt capacitance filterFix voltages
Regulators 78XX79XX sering and as currents sources Dual power supply using
78XX and 79XX series.
UNIT III
Ideal Operational Amplifier Theory and Basic Circuits

Ideal operational amplifier propertiesIdeal assumptionsBasic circuits such as non
inverting type comparatorInverting type comparatorVoltage follower Inverting
amplifierNoninverting amplifierSumming amplifier Noninverting summing
amplifiersub-tractor DifferentiatorIntegrator Scale changerInstrumentation
amplifier V to I and I to V convertorsLog and Antilog amplifiersZero crossing
detectorSchmitt-trigger peak detector Half-wave and full-wave rectifiers Precision
diode Non-ideal operational amplifier noninverting amplifier inverting amplifier
closedloop gainInput and output resistance equivalent circuits.
UNIT IV
Wave form generator in angular waveform generator using opamps and PLL
Design of Astable multivibrator Monostable multivibrator using signal op-amp
Triggering waveform generator 555 timer: Introduction Pin diagramFunctional
diagram for 8pin DIPDesign of Astable and monostable multi Astable applications
Monostable applications PLL: Introduction, basic block diagram Functions of each
block566 VC0 565 PLL block diagram Function of each blockApplications of
PLLFrequency multiplier role of each pin frequency transalation AMFM
and FSK demodulators.
UNITV:
Active filters
Introduction Merits and demerits of active filtersOver passive filters First order low
pass ButterWorth filter Design and frequency responseSecond order LPF design and
frequency response First order HPF design and frequency response Second order
HPF design and frequency response Higher-order filters BPF wide bandpass and
narrow bandpass filterWide band reject filterNotch filterAll-pass filter.
UNITVI:
D to A and A to D Convertors
Digital to Analog Convertors(D to A) IntroductionSpecificationsBasic DAC
techniques Weighted resistor DAC R2R ladder DACInvested R 2R Output
expression for each type.
Analog to Digital Convertors

IntroductionSpecificationsParallel comparator typeCounter typeDual slope
Successive approximation type ADCs Merits and demerits of each type, Comparison
of different types.
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3. Lecture Plan
Lecture Unit Number Topic
no.
Brief explanation about block diagram of typical Op
1 1
Amp with various stages
2 1 DC Analysis of BJT Differential Amplifier With RE
3 1 AC Analysis of BJT Differential Amplifier With RE
Analysis of different input/output configurations of
4 1
differential amplifier
DC & AC Analysis of Diff.Amp. with swamping
5 1
resistors
6 1 AC & DC analysis of DIUBO Differential Amplifier
7 1 AC & DC analysis of SIBO Differential Amplifier
8 1 AC & DC analysis of SIUBO Differential Amplifier
9 1 BJT differential amplifier with constant current source
Analysis of BJT differential amplifier with Current
10 1
repeater circuitsCurrent mirror circuits
11 1 Analysis of Level translator
12 1 Cascade differential amplifier
13 1 FET differential amplifier
Definitions of various op-amp parameter and ideal op-
14 2
amp characteristics
Explanation of Input offset voltage; Input offset current
15 2
Input bias current of the op-amp.
Explanation of Differential input resistance, Common
16 2
mode rejection ratio, Slew rate of the op-amp.
Explanation of PSRR, Large signal voltage gain, Output
17 2
voltage swing transients response of the op-amp.
Measurement of bias current offset currents and offset
18 2
voltage of the op-amp.
Measurement of slew rate, Output offset voltage and
19 2
PSRR of the op-amp.
Bias current compensations circuit, Dual power suppliers
20 2
with shunt capacitance filter.
Series op-amp regulator, fixed voltage series regulator
21 3
78XX79XX
currents sources, Dual power supply using 78XX and
22 3
79XX series
23 3 Ideal operational amplifier propertiesIdeal assumptions
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of op-amp.
Basic circuits such as non inverting type comparator
24 3
Inverting type comparatorVoltage follower
25 3 Inverting amplifier
26 3 Noninverting amplifier
Summing amplifier, Noninverting summing amplifier
27 3
and subtractor
28 3 Ideal and Practical Differentiator
29 3 Ideal and Practical Integrator
30 3 Instrumentation Amplifier using op-amp
31 3 V to I and I to V convertors using op-amp
32 3 Logarithmic amplifier using op-amp
33 3 Anti-Logarithmic amplifier using op-amp
34 3 Zero crossing detector, Schmitt-trigger and
Precision diode, Half-wave and full-wave rectifier, peak
35 3
detector using op-amp
36 3 AC analysis of non-ideal non inverting amplifier
37 3 AC analysis of non-ideal inverting amplifier
38 4 Design of Astable multivibrator using op-amp.
39 4 Design of Monostable multivibrator using op-amp.
Introduction of 555 timer pin diagram and functional
40 4
diagram for 8pin DIP.
41 4 Design of Astable multivibrator using 555 timer.
42 4 Applications of Astable multivibrator using 555 timer.
43 4 Design of Monostable multivibrator using 555 timer.
Applications of Monostable multivibrator using 555
44 4
timer.
45 4 Design of Schmitt trigger using 555 timer
46 4 Introduction of PLL basic block diagram
47 4 Functions of each block in IC 566
48 4 Voltage controller oscillator using IC 566
49 4 Monolithic Phase Locked loop
50 4 Applications of PLLFrequency
51 5 Introduction and comparison of active and passive filters.
52 5 First order low pass and high pass Butter Worth filter.
53 5 Design and frequency responseSecond order LPF
54 5 Design and frequency responseSecond order HPF
55 5 Design of Higher-order wide band pass filter.
56 5 Design of Higher-order narrow band pass filter.
57 5 Design of Higher-order wide band reject filter.
58 5 Design of Higher-order notch filter.
59 5 Design of Higher-order All pass filter.
Digital to Analog Convertors(D to A) Introduction,
60 6 Specifications
61 6 Basic DAC techniques Weighted resistor DAC
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62 6 R2R ladder DAC
63 6 Inverted R 2R ladder DAC
Introduction Specifications of basic Analog to Digital
64 6 convertors
65 6 Parallel comparator type ADC
66 6 Counter type ADC
67 6 Servo Tracking ADC
68 6 Dual slope type ADC
69 6 Successive approximation type ADCs
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4. Unit-wise course material
4.1 UNIT-I INTRODUCTION TO OP-AMPS
Block diagram of Typical OpAmp With Various Stages BJT Differential

Amplifier With RE DC Analysis AC Analysis BJT differential amplifier with
constant current source Analysis Different input/output configurations dual input
balanced outputDual input unbalanced outputSignal input balanced outputSignal
input unbalanced outputAC analysis with r parameters Current repeater circuits
Current mirror circuitsAnalysis Level translator Cascade differential amplifier
FET differential amplifier.
4.1.1 Unit Objectives:
After reading this Unit, you should be able to understand:
- Analysis and design of differential amplifier

- Types of differential amplifiers
- Individual stages of differential amplifier
4.1.2 Unit Outcomes:
Student will be able to design different differential amplifier configurations and

perform DC and AC analysis.
4.1.3 Unit Lecture Plan:
Session Teaching
Topics to be covered Reference
No Aids
Brief explanation about block diagram of typical Op T.B: 1- Ch:02
1 BB
Amp with various stages Page No: 53-55
T.B: 2- Ch:01
2 DC Analysis of BJT Differential Amplifier With RE BB
Page No: 1.4-1.5
T.B: 2- Ch:01
3 AC Analysis of BJT Differential Amplifier With RE BB
Page No: 1.5-1.11
Analysis of different input/output configurations of T.B: 2- Ch:01
4 BB
differential amplifier Page No: 1.1-1.4
T.B: 2- Ch:01
5 DC & AC Analysis of Diff.Amp. with swamping resistors BB
Page No: 1.12-1.12
T.B: 2- Ch:01
6 AC & DC analysis of DIUBO Differential Amplifier BB
Page No:1.13-1.14
T.B: 2- Ch:01
7 AC & DC analysis of SIBO Differential Amplifier BB
Page No:1.13-1.14
8
T.B: 2- Ch:01
8 AC & DC analysis of SIUBO Differential Amplifier BB
Page No:1.13-1.14
T.B: 1- Ch:02
9 BJT differential amplifier with constant current source BB
Page No: 64-65
Analysis of BJT differential amplifier with Current T.B: 1- Ch:02
10 BB
repeater circuitsCurrent mirror circuits Page No: 65-73
T.B: 1- Ch:02
11 Analysis of Level translator BB
Page No: 79-81
T.B: 1- Ch:02
12 Cascade differential amplifier BB
Page No: 82-83
T.B: 1- Ch:02
13 FET differential amplifier BB
Page No: 89-90
Content beyond syllabus covered (if any):
DC & AC Analysis of Diff.Amp. with swamping resistors
Course Outcome (CO1): To analyze the concepts of operational amplifier.
* Session duration: 50 mins
4.1.4 Teaching Material / Teaching Aids as per above lecture plan.
4.1.4.1 Lecture-1
Introduction
Their applications were initially in the area of analog computation and instrumentation
Op amp is very popular because of its versatility
Op amp circuits work at levels that are quite close to their predicted theoretical
performance
The op amp is treated a building block to study its terminal characteristics and its
applications
Opamp symbol and terminals
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Two input terminals: 1) (-) inverting
input terminal
2) (+) Non- inverting input terminal

3) One output terminal
4) Two dc power supplies V + and V

-
5) Other terminals are for frequency

compensation and offset.
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Circuit symbol for op amp Op amp with dc power supplies
Fig.1.1
Ideal characteristics of op amp
Differentialinput singleendedoutput amplifier
Infinite input impedance i1 = i2 = 0 (regardless of the input voltage
Zero output impedance vO= A(v2v1) (regardless of the load)
Infinite openloop differential gain
Infinite commonmode rejection
Infinite bandwidth
Fig.1.2 Ideal Op-amp Structure
Differential and commonmode signals
- Two independent input signals: v1 and v2
- Differentialmode input signal (vId): vId = (v2v1)
- Commonmode input signal (vIcm): vIcm = (v1+v2)/2
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- Alternative expression of v1 and v2:
- v1 = vIcmvId/2
- v2 = vIcm+vId/2
741 op-amp & its features:
The 741 IC was designed by Dave Fullagar of Fairchild Semiconductor in 1968. The
741 IC is the successful predecessor of the LM 101 IC, and the only difference
between the two was that an additional 30pF internal compensation capacitor was
added for the 741 IC. But, this simple addition has made this IC evergreen in the
electronics world and is still manufactured by different companies in different versions
and specifications, and is made recognizable by adding the famous number 741 in the
series.
Fig.1.3 IC741 Pin Configuration
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Features of 741 IC
1. Short circuit and overload protection provided.
2. In theory, the dc output voltage will be zero if both the inputs of the 741 IC are
connected to the ground. But in practice, a small dc output may appear due to minor
internal unbalances. It is usually unnoticed in normal applications. But for critical
conditions, the output voltage can be set precisely to zero by connecting a 10K
potentiometer between terminals marked offset-null.
3. Low power consumption.
4. Large common mode rejection ratio (CMRR) and differential voltage ranges.
5. No external frequency compensation is required. It also does not need any
external compensation for phase component. This simplifies the circuit design and
minimizes the number of components used.
6. No latch-up problem.
4.1.4.2 Lecture-2
Differential Amplifiers:
Differential amplifier is a basic building block of an op-amp. The function of a
differential amplifier is to amplify the difference between two input signals.
How the differential amplifier is developed? Let us consider two emitter-biased circuits
as shown in fig. 1.4
Fig. 1.4 Dual Input, Balanced Output Differential Amplifier
The two transistors Q1 and Q2 have identical characteristics. The resistances of the
circuits are equal, i.e. RE1 =R E2, RC1 = R C2 and the magnitude of +VCC is equal to
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the magnitude of VEE. These voltages are measured with respect to ground. To make a
differential amplifier, the two circuits are connected as shown in fig. 1. The two +VCC
and VEE supply terminals are made common because they are same. The two emitters
are also connected and the parallel combination of RE1 and RE2 is replaced by a
resistance RE. The two input signals v1 & v2 are applied at the base of Q1 and at the
base of Q2. The output voltage is taken between two collectors. The collector
resistances are equal and therefore denoted by RC = RC1 = RC2.
The four differential amplifier configurations are following:
1. Dual input, balanced output differential amplifier.
2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.
Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig. 1.4; v1 and v2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors C1
and C2, which are at same dc potentials.
D.C. Analysis:
To obtain the operating point (ICC and VCEQ) for differential amplifier dc equivalent
circuit is drawn by reducing the input voltages v1 and v2 to zero as shown in fig. 1.5
Fig.1.5 D.C. Analysis of DIBO Configuration

The internal resistances of the input signals are denoted by RS because RS1= RS2.
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Since both emitters biased sections of the different amplifier are symmetrical in all
respects, therefore, the operating point for only one section need to be determined. The
same values of ICQ and VCEQ can be used for second transistor Q2. Applying KVL to
the base emitter loop of the transistor Q1.
The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of
VEE. The emitter current in Q1 and Q2 are independent of collector resistance RC.
The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop
across R is negligible. Knowing the value of IC the voltage at the collector VCis given
by
VC =VCC -IC RC and VCE = VC - VE
= VCC - IC RC + VBE VCE = VCC + VBE - ICRC (E-2)
From the two equations VCEQ and ICQ can be determined. This dc analysis is
applicable for all types of differential amplifier.
4.1.4.3 Lecture-3
A.C. Analysis:
In previous lecture dc analysis has been done to obtain the operatiing point of the two
transistors. To find the voltage gain Ad and the input resistance Ri of the differential
amplifier, the ac equivalent circuit is drawn using r-parameters as shown in fig. 1.6. The
dc voltages are reduced to zero and the ac equivalent of CE configuration is used.
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Fig.1.6 A.C. Analysis of DIBO Configuration
Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also
equal and designated by r'e . This voltage across each collector resistance is shown 180
out of phase with respect to the input voltages v1 and v2. This is same as in CE
configuration. The polarity of the output voltage is shown in Figure. The collector C2 is
assumed to be more positive with respect to collector C1 even though both are negative
with respect to ground.
Applying KVL in two loops 1 & 2.
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Again, assuming RS1 / and RS2 / are very small in comparison with RE and re'
and therefore neglecting these terms,
Solving these two equations, ie1 and ie2 can be calculated.
Thus a differential amplifier amplifies the difference between two input signals.
Defining the difference of input signals as vd = v1 ? v2 the voltage gain of the dual
input balanced output differential amplifier can be given by
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4.1.4.4 Lecture 4
Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be
measured at either input terminal with the other terminal grounded. This means that the
input resistance Ri1 seen from the input signal source v1 is determined with the signal
source v2 set at zero. Similarly, the input signal v1 is set at zero to determine the input
resistance Ri2 seen from the input signal source v2. Resistance RS1 and RS2 are
ignored because they are very small.
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Output Resistance:
Output resistance is defined as the equivalent resistance that would be measured at
output terminal with respect to ground. Therefore, the output resistance RO1 measured
between collector C1 and ground is equal to that of the collector resistance RC.
Similarly the output resistance RO2 measured at C2 with respect to ground is equal to
that of the collector resistor RC.
The current gain of the differential amplifier is undefined. Like CE amplifier the
differential amplifier is a small signal amplifier. It is generally used as a voltage
amplifier and not as current or power amplifier.
4.1.4.5 Lecture-5
Dual Input, Unbalanced Output Differential Amplifier:

In this case, two input signals are given however the output is measured at only one of
the two-collector w.r.t. ground as shown in fig. 1.7. The output is referred to as an
unbalanced output because the collector at which the output voltage is measured is at
some finite dc potential with respect to ground.
Fig.1.7 Dual Input, Unbalanced Output Differential Amplifier

In other words, there is some dc voltage at the output terminal without any input signal
applied. DC analysis is exactly same as that of first case.
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AC Analysis:
The output voltage gain in this case is given by
The voltage gain is half the gain of the dual input, balanced output differential amplifier.
Since at the output there is a dc error voltage, therefore, to reduce the voltage to zero,
this configuration is normally followed by a level translator circuit.
4.1.4.6 Lecture-6
Single Input, Balanced Output Differential Amplifier:
Fig.1.8 Single Input, Balanced Output Differential Amplifier
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4.1.4.7 Lecture-7
Single Input, Unbalanced Amplifier:
Fig.1.9 Single Input, Unbalanced Output Differential Amplifier
4.1.4.8 Lecture-8
Cascaded differential amplifier stages:

Fig. 1.10 shows a complete OPAMP circuit having input different amplifiers with
balanced output, intermediate stage with unbalanced output, level shifter and an output
amplifier.
Fig.1.10 Cascaded differential amplifier
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4.1.4.09 Lecture-09
Integrated circuits-Types
Fig.1.11 Classification of ICs

Below is the classification of different types of ICs basis on their chip size.
- SSI: Small scale integration. 3 30 gates per chip.
- MSI: Medium scale integration. 30 300 gates per chip.
- LSI: Large scale integration. 300 3,000 gates per chip.
VLSI: Very large scale integration. More than 3,000 gates per chip.
Based on the method or techniques used in manufacturing them, types of ICs can be
divided into three classes:
1. Thin and thick film ICs
2. Monolithic ICs
3. Hybrid or multichip ICs

Thin and Thick ICs:
In thin or thick film ICs, passive components such as resistors, capacitors are integrated
but the diodes and transistors are connected as separate components to form a single and
a complete circuit. Thin and thick ICs that are produced commercially are merely the
combination of integrated and discrete (separate) components.
Thick and thin ICs have similar characteristics, similar appearance except the method of
film deposition. Method of deposition of films distinguished Thin ICs from Thick ICs.
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Thin film ICs are made by depositing films of a conducting material on a glass surface
or on a ceramic base. By varying the thickness of the films deposited on the materials
having different resistivity, Passive electronic components like resistors and capacitors
can be manufactured.
Fig.1.12 Hybrid Chips

In Thick film ICs, silk printing technique is used to create the desired pattern of the
circuit on a ceramic substrate. Thick-film ICs are sometimes referred to as printed thin-
film.
The screens are actually made of fine stainless steel wire mesh and the links
(connections) are pastes having conductive, resistive or dielectric properties. The
circuits are fired in a furnace at a high temperature so as to fuse the films to the
substrate after printing.
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4.1.4.10 Lecture-10
4.1.4.11 Lecture-11
Level Translator:
Because of the direct coupling the dc level at the emitter rises from stages to stage. This
increase in dc level tends to shift the operating point of the succeeding stages and
therefore limits the
output voltage swing and may even distort the output signal. To shift the output dc level
to zero, level translator circuits are used. An emitter follower with voltage divider is the
simplest form of level translator as shown in fig.1.6. Thus a dc voltage at the base of Q
produces 0V dc at the output. It is decided by R1 and R2. Instead of
Voltage divider emitter follower either with diode current bias or current mirror bias as
shown in fig. 1.7 may be used to get better results.
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Fig.1.8 Level Translator Circuits
In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V.
If this shift is not sufficient, the output may be taken at the junction of two resistors in
the emitter leg.
4.1.4.12 Lecture 12
Cascade differential amplifier:
A single stage amplifier didnt provide sufficient gain and bandwidth and moreover
didnt have matched input and output impedance.
To overcome such problems multiple amplifiers are combined for better performance
and amplification.
Multiple amplifiers are connected in cascade to increase the overall voltage gain of the
amplifier.
When n numbers of amplifier stages are connected in succession it is called multistage
or cascade amplifier.
The overall gain of the amplifier is the product of all the gain of each amplifier within
the stage which is given by Av= A1*A2*..*An.Cascade amplifier.
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Work on amplifier has already carried out by different researches with different
approaches. To increase the overall gain, hybrid combination of BJT-FET-BJT in Triple
Darlington topology has already proposed and successfully implemented as high power
gain small-signal amplifiers in audio-frequency-range.
Two identical JFET in Darlington pair for small signal amplification with wide
bandwidth is also carried out.
This work is carried on cascade amplifier with two stages having an overall gain of
A1*A2 for very small signal amplification in audio frequency range.
Between the two stage emitter follower is inserted for impedance matching to deliver
maximum power to the preceding stage.
Both the two stages are biased in the active mid- point operating region for maximum
output swing without distortion
Both AC and DC analysis of the amplifier is also presented. All important parameters
of amplifiers like operating point, AC analysis, transient analysis, DC sweep and output
noise analysis is also analysed.
4.1.4.13 Lecture 13
FET Differential amplifiers PPT:
Differential amplifiers apply gain not to one input signal but to the difference between
two input signals. This means that a differential amplifier naturally eliminates noise or
interference that is present in both input signals.
Differential amplification also suppresses common-mode signalsin other words, a

DC offset that is present in both input signals will be removed, and the gain will be
applied only to the signal of interest (assuming, of course, that the signal of interest is
not present in both inputs). This is particularly advantageous in the context of IC
design because it eliminates the need for bulky DC-blocking capacitors.
The subtraction that occurs in a differential pair makes it easy to incorporate the circuit
into a negative-feedback amplifier, and if youve read the Negative Feedback series,
you know that negative feedback is about the best thing that could ever happen to an
amplifier circuit.
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It is only sensible to expect these benefits to be accompanied by significant
disadvantages, but the nature of IC fabrication has rendered the differential
configuration almost wholly beneficial. Two concerns are 1) higher component count
and 2) the importance of symmetrical component characteristics. You can forget about
number 1 because the cost of adding a few more transistors to an IC is negligible. As
for number 2, IC technology happens to be very good at achieving consistency among
the components within a chip (this consistency is referred to as matching).
In this article, we will explore the basic MOSFET differential-amplifier configuration

by means of conceptual discussion and simulations (i.e., not too much math or
complicated circuit analysis). Because this topic is relevant primarily to IC
implementation, we will use an NMOS model that is specific to 0.35 m CMOS
technology; the various LTspice files and some related information can be found here.
A Pair of MOSFETs
Fig 1.9: FET Differential Amplifier
In real life, the current-source symbol would be replaced by a circuit that generates a
constant current. (Refer to The Basic MOSFET Constant-Current Source for more
information.) However, we want to keep things nice and simple for this introductory
analysis, so in our simulations well use an ideal current source instead of a constant-
current circuit.
An actual IC implementation of this circuit would replace the resistors with a current
mirror functioning as an active load. However, if our goal is to understand the
functionality of the differential pair, I think we should start with the resistor version.
The differential pair is all about balance. Thus, for optimal performance the resistors
and MOSFETs must be matched. This means that the channel dimensions of both
27
FETs must be the same and that R 1 must equal R2. The resistance value chosen for the
two resistors will be referred to as RD (for drain resistance).
DC Analysis
Lets determine the biasing conditions of this circuit when both inputs are grounded.
Fig: 1.10: DC analysis of Differential Amplifier
The sum of the two drain currents ID1 and ID2 must equal IBIAS. We also know that the
two drain currents are equal because, in this idealized analysis, both halves of the
circuit are identical. Thu
Lets assume for the moment that the transistors are in saturation. The equation for
saturation-mode drain current is the following:
The output voltages are as expected. The source voltage seems reasonable considering
that the threshold voltage (VTH) for this SPICE model is about 0.5 V; the simulation is
telling us that the VGS corresponding to a drain current of 250 A is about 0 V (725
mV) = 725 mV, which is about 225 mV above VTH.
Lets go back to our assumption about the transistors being in saturation (aka active
mode). A MOSFET amplifier needs to remain in the saturation portion of its transfer
characteristic, because the gain is higher and more stable in the saturation region
compared to the triode region. To ensure saturation, the drain voltage must always be
higher than the gate voltage minus the threshold voltage
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4.1.5 Test Questions
a. Fill in the blanks type of questions
Difference amplifier is also called as differential amplifier.
The ability of the differential amplifier to reject the common mode ratio is
high.
1. The common mode rejection ratio is defined as Ad/Ac.
2. The differential amplifier is classified in to four types.
3. The circuit in which the output current is forced to equal to input current is
known as current mirror.
4. The purpose of the level shifter is to bring the dc level of the second stage down
to ground.
5. The differential amplifier is used to amplify the difference between two signals.
6. What are the circuits used for improving CMRR constant current source
circuit.
b. Multiple choice questions
Which is not the internal circuit of operational amplifier?
a) Differential amplifier
b) Level translator
c) Output driver
d) Clamper
The purpose of level shifter in Op-amp internal circuit is to
a) Adjust DC voltage
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b) Increase impedance
c) Provide high gain

d) Decrease input resistance
How a symmetrical swing is obtained at the output of Op-amp
a) Providing amplifier with negative supply voltage
b) Providing amplifier with positive voltage

c) Providing amplifier with positive& negative voltage
d) None of the mentioned
What is the purpose of differential amplifier stage in internal circuit of Op- amp?
a) Low gain to differential mode signal
b) Cancel difference mode signal
c) Low gain to common mode signal
d) Cancel common mode signal
Which of the following is not preferred for input stage of Op-amp?
a) Dual Input Balanced Output

b) Differential Input Single ended Output
c) Cascaded DC amplifier
d) Single Input Differential Output
What will be the emitter current in a differential amplifier, where both the transistor are
biased and matched? (Assume current to be IQ)
a) IE = IQ/2
b) IE = IQ
c) IE = (IQ)2/2
d) IE = (IQ)2
From the circuit, determine the output voltage (Assume F=1)
30
a) VO1=3.9v , VO2=12v
b) VO1=12v , VO2=3.9v
c) VO1=12v , VO2=0v
d) VO1=3.9v , VO2=-3.9v
At what condition differential amplifier function as a switch
a) 4VT < Vd < -4VT

b) -2VT Vd 2VT
c) 0 Vdd < -4VT
d) 0 Vd 2VT
For Vd > 4VT, the function of differential amplifier will be
a) Switch
b)Limiter
c) Automatic gain control
d) Linear Amplifier
Find collector current IC2, given input voltages are V1=2.078v & V2=2.06v and total
current IQ=2.4mA. (Assume =1)
a) 0.8mA
b) 1.6mA
c) 0.08mA
d) 0.16mA
31
c. True or False questions
When a number of stages are connected in parallel, the overall gain is the product of the
individual stage gains.
a) True b)False
One of the key characteristics of an instrumentation amplifier is high input impedance.
a)True b) False
Instrumentation amplifiers are commonly used in environments with high common-

mode noise.
a) True b)False
A constant-current source delivers a load current that remains constant only when the
load resistance remains constant.
a) True b)False
An OTA is primarily a current-to-voltage amplifier.
a) True b)False
Current mirror is the circuit used to improve CMMR.
a)True b)False
CMMR is defined as ratio of Ad to Ac
a) True b)False
Level shifter is used to bring the dc level to unity
a) True b)False
Wildar and Wilson current sources are used to improve CMMR
a) True b)False
32
The output stage of op amp used to provide load current and low impedance output.
a) True b)False
4.1.6 Review Questions

a. Objective type of questions
1. What is a differential amplifier? Classify the same.
2. Examine the performance of four differential amplifier configurations.
3. What is the purpose of a level translator circuit?
4. What is the need for cascading differential amplifier stages?
5. Mention the important stages of op-amp and their purpose briefly.
b. Essay type Questions
1. Explain the properties of dual input unbalanced output differential amplifier with
relevant diagrams.
2. (a) Compare the four differential amplifier configurations.

(b) Give the reasons for using level translator in an IC op-amp.
3. (a) Explain DC coupling of cascaded differential amplifiers using relevant diagrams
and necessary expressions.
(b) Explain why RE is replaced by a constant current source in a differential amplifier
circuit.
c. Problems
An emitter-biased single input balanced output differential amplifier has the following
specifications: VCC=-VEE=10V, RC1=RC2=5.6K and RE=3.9K; the transistor array is CA3086
with ac=dc=100 and VBE=0.715V. Calculate:
(a) The operating current and voltage values for each transistor.
(b) The voltage gain
(c) The input resistance of the circuit.
6. Design a constant current bas circuit using zener diode for the following
specifications: IE3=5mA, zener diode with Vz=4.7V, Izt=5.3mA, transistor with _ac=
_dc=100 and VBE =0.175V, VCC=VEE= 9 Volts.
33
d. Case study <As per required Number>
-----Not Applicable----
4.1.7 Skill Building
Exercises/Assignments
Assignment-1
1. (a) Present the detailed AC analysis of dual-input balanced output configuration.
(b) Explain the properties of single ended input balanced output differential amplifier.
2. (a) Compare the four differential amplifier configurations.
(b) Give the reasons for using level translator in an IC op-amp.
3. Draw the circuit of a single input balanced output differential amplifier and find
voltage gain, input resistance and output resistance.
4. Explain the properties of dual input unbalanced output differential amplifier with
relevant diagrams.
5. (a) What is a differential amplifier? Mention the classification of differential
amplifiers.
(b) Draw the circuit diagram of dual input unbalanced output differential amplifier
and derive the expressions for DC analysis.
6. With suitable circuit diagram explain about single input unbalanced output
differential amplifier. And derive necessary expressions for DC & AC analysis.
7. An emitter-biased DIBO differential amplifier has the following specifications:
VCC=-VEE=10V, RC1=RC2=2.7K and RE=3.9K; the transistor array is CA3086 with
ac=dc=100 and VBE=0.715V. Calculate:
8. An emitter-biased single input balanced output differential amplifier has the
following specifications: VCC=-VEE=10V, RC1=RC2=5.6K and RE=3.9K; the
transistor array is CA3086 with ac=dc=100 and VBE=0.715V. Calculate:
(d) The operating current and voltage values for each transistor.
34
(e) The voltage gain
(f) The input resistance of the circuit.
9. Give the reasons for using level translator in an IC op-amp. Draw the circuits that
can be used as level translators
10. An emitter-biased dual input unbalanced output differential amplifier has the
following specifications: VCC=-VEE=10V, RC1=RC2=2.7K and RE=3.9K; the
transistor array is CA3086 with ac=dc=100 and VBE=0.715V. Calculate:
4.1.8 Previous Questions (Asked by JNTUK from the concerned Unit)

1.(a) Draw the circuit diagram of dual input unbalanced output differential amplifier
and derive the expression for dc analysis.
(b) Design a constant current bas circuit using zener diode for the following
specifications: IE3=5mA, zener diode with Vz=4.7V, Izt=5.3mA, transistor with
_ac= _dc=100 and VBE =0.175V, VCC=VEE= 9 Volts.
2. (a) Explain DC coupling of cascaded differential amplifiers using relevant diagrams
and necessary expressions.
(b) Explain why RE is replaced by a constant current source in a differential amplifier
circuit.
4.1.9 GATE Questions
1. If the differential voltage gain and the common mode voltage gain of a
differential amplifier are 48 dB and 2 dB respectively, then common mode
rejection ratio is
a. 23 dB
b. 25 dB
c. 46 dB
d. 50 dB
2. In the differential amplifier shown in figure, a large value of RE
35
a. Increases both the differential and common mode gains
b. Increases the common mode gain only
c. Decreases the differential mode gain only
d. Decreases the common mode gain only
e.
4.1.10 Interview questions (which are frequently asked in a Technical
round - Placements)
4.1.11 Real-Word (Live) Examples / Case studies wherever applicable
4.1.12 Suggested Expert Guest Lectures (both from in and outside of the campus)
4.1.13 Literature references of Relevant NPTEL Videos/Web/You Tube

videos etc.
https://www.youtube.com/watch?v=clTA0pONnMs
4.1.14 Any Lab requirements; if so link it to Lab Lesson Plan.
4.1.15 Reference Text Books / with Journals Chapters etc.
T1. Op-amps and Linear Integrated Circuits --- Ramakant A Gaykwad
36
T2. Linear Integrated Circuits --- D.Roy Choudhury & Shail B.Jain
4.2 Unit II OPERATIONAL AMPLIFIER PARAMETERS
Input offset voltage Input offset currentInput bias currentDifferential input resistance
Common mode rejection ratioSlew ratioPSRRLarge signal voltage gainOutput voltage
swing transients responsedefinitions and explanations. Measurement of bias current
Measurement of offset currents Measurement of offset voltage Measurement of slew rate
Output offset voltage balancing circuitsBias current compensations circuitDual power
suppliers with shunt capacitance filterFix voltages Regulators 78XX79XX series and as
currents sources Dual power supply using 78XX and 79XX series
- Different types of Op-amp Parameters

- Op-amp non-idealities and their compensation techniques
- Different types of ICs
- Measurement of Op-amp parameters
- Fixed Voltage Regulators
- Student will able to analyze non-idealities of operational amplifier.
- Student will get knowledge on different types of Voltage Regulators.
4.2.3 Unit Lecture Plan
Session Teaching
No Aids
Definitions of various op-amp parameter and ideal op- T.B: 1- Ch:03
1 BB
amp characteristics Page No: 104-111
Explanation of Input offset voltage; Input offset current T.B: 1- Ch:03
2 BB
Input bias current of the op-amp. Page No: 104-110
Explanation of Differential input resistance, Common T.B: 1- Ch:03
3 BB
mode rejection ratio, Slew rate of the op-amp. Page No: 123-126
Explanation of PSRR, Large signal voltage gain, Output T.B: 1- Ch:03
4 BB
voltage swing transients response of the op-amp. Page No: 129-130
Measurement of bias current offset currents and offset T.B: 1- Ch:03
5 BB
voltage of the op-amp. Page No: 104-110
Measurement of slew rate, Output offset voltage and T.B: 1- Ch:03
6 BB
PSRR of the op-amp. Page No: 124-125
7 Bias current compensations circuit, Dual power suppliers T.B: 1- Ch:03 BB
37
with shunt capacitance filter. Page No: 124-125
Series op-amp regulator, fixed voltage series regulator T.B: 1- Ch:06
8 BB
78XX79XX Page No: 240-247
currents sources, Dual power supply using 78XX and T.B: 1- Ch:06
9 BB
79XX series Page No: 245-248
Content beyond syllabus covered (if any):Nil
Course Outcome (CO1): To analyze the concepts of operational amplifier.
4.2.4.1 Lecture-1
Op amp Parameters:
Input Bias Current:
The input bias current (IB) is the average of the currents enters into the two input terminals
with the output at zero volts.
Typically the input bias current is around 80nA. This input bias current makes a
voltage drop across the equivalent source impedance seen from the input side of op-
amp.
Input Offset Current:
The input offset current is the difference between the two input currents of the opamp
with the output at zero volts.
Typically the input offset current for a 741 op-amp is 20 nA .
Input Offset Voltage:
In the ideal op amp when both inputs are at zero volts the output should be zero volts.
Due to imbalances within the device a small amount of voltage will appear at the output.
This extra voltage can be eliminated by giving a small voltage called Input offset
voltage (VOS) to the amplifier.
Typically the input offset voltage for a 741 op-amp is around 1mV.
Common-Mode Rejection Ratio:
In OPAMP, the output voltage is proportional to the difference between the voltages
applied to its two input terminals.
When the two input voltages are equal ideally the output voltages should be zero.
38
A signal applied to both input terminals of the opamp is called as common-mode signal.
Usually it is an unwanted noise voltage.
The ability of an op amp to suppress common-mode signals is expressed in terms of its
common-mode rejection ratio (CMRR).
Typically the CMRR for a 741 op-amp is around 90 dB.
CMRR=20 log10[Differential Voltage Gain/Common Mode Gain] dB
Slew Rate
The slew rate is the maximum rate of change of output voltage for a step input
voltage.
The slew rate makes the output voltage to change at a slower rate than the
applied input.
Eventually the output waveform is a distortion of the input waveform.
The typical value for the slew rate is 0.5V/s.
4.2.4.2 Lecture 2
Input Offset Voltage
Input offset voltage is the voltage that is applied between the two input terminals of the
op-amp to null the output. The figure is show below.
Fig. 2.1 Input Offset Voltage of Op-amp
39
In the figure V1 and V2 are the input dc voltages are Ra represents the resistance
applied. The input offset voltage Vio could have a positive value or a negative value.
Therefore, its absolute value is listed in the datasheet. It is always better to have
smaller values of input offset voltage and this indicates that the input terminals are
matched better. Lowest values are 15uV for an ideal precision op-amp and the
maximum value if 6mV dc.
2. Input Offset Current
Input Offset Current is the algebraic difference between the currents into the
inverting and non-inverting terminals.
Input Offset Current, Iio = |Ib1 Ib2|
Ib1 Non-inverting input current
Ib2 Inverting input current
The maximum input offset current value for 741 IC is 200nA. This value decreases
as the matching between the two input terminals is improved and may reduce down
to almost 6nA.
4.2.4.3 Lecture-3
Slew Rate (SR)
Slew Rate is one of the most important parameters for selecting op-amps for high
frequencies. SR is the maximum rate of change of output voltage per unit of time
and is expressed in volts per microseconds.
Slew Rate, SR = dVo/dt
By calculating slew rate we can easily find out the rate in which the output of the op-
amp changes in response to changes in the input frequency. The slew rate changes
with change in voltage gain and is usually specified at unity gain. The slew rate of an
40
op-amp is always fixed. Hence, if the slope requirements of the output signals are
greater than the slew rate, then distortion occurs.
In the case of the 741 IC the slew rate is 0.5V/uS, which is very small. This is one
reason why the 741 IC is considered not suitable for high frequency applications,
such as oscillators, comparators, and filters.
Common Mode Rejection Ratio (CMRR)
CMRR is the ratio of the differential voltage gain to the common mode voltage gain.
CMRR = Differential Voltage Gain (Ad)/ Common Mode Voltage Gain (Acm)
If the value of CMRR is high, there is better matching between the 2 input terminals.
For 741IC, CMRR is 90dB.
4.2.4.4 Lecture-4
Introduction
- Their applications were initially in the area of analog computation and
instrumentation
- Op amp is very popular because of its versatility
- Op amp circuits work at levels that are quite close to their predicted
theoretical performance
- The op amp is treated a building block to study its terminal characteristics and
its applications
41
- Two input terminals:
And non- inverting input
(-)inverting input
terminal terminal (+)
- One output terminal
- Two dc power supplies

V + and V -
- Other terminals for

frequency
compensation and
offset nulling.
42
Fig.2.2 Ideal op-amp with dc supplies
- Differentialinput singleendedoutput amplifier
- Infinite input impedance i1 = i2 = 0 (regardless of the input voltage)
- Zero output impedance vO= A(v2v1) (regardless of the load)
- Infinite openloop differential gain
- Infinite commonmode rejection
- Infinite bandwidth
Fig.2.3 Ideal Op-amp Structure
Differential and commonmode signals

- Two independent input signals: v1 and v2
- Differentialmode input signal (vId): vId = (v2v1)
- Commonmode input signal (vIcm): vIcm = (v1+v2)/2
- Alternative expression of v1 and v2:
43
- v1 = vIcmvId/2
- v2 = vIcm+vId/2
4.2.4.5 Lecture-5
741 op-amp & its features:
The 741 IC was designed by Dave Fullagar of Fairchild Semiconductor in 1968. The
741 IC is the successful predecessor of the LM 101 IC, and the only difference
between the two was that an additional 30pF internal compensation capacitor was
added for the 741 IC. But, this simple addition has made this IC evergreen in the
electronics world and is still manufactured by different companies in different
versions and specifications, and is made recognizable by adding the famous number
741 in the series.
Fig.2.4 IC741 Pin Configuration
44
Features of 741 IC

11.No external frequency compensation is required. It also does not need any
4.2.4.6 Lecture-6
Input offset voltage is the voltage that is applied between the two input terminals of
the op-amp to null the output. The figure is show below.
45
Fig. 2.5 Input Offset Voltage of Op-amp
In the figure V1 and V2 are the input dc voltages are Ra represents the resistance
applied. The input offset voltage Vio could have a positive value or a negative value.
Therefore, its absolute value is listed in the datasheet. It is always better to have
smaller values of input offset voltage and this indicates that the input terminals are
matched better. Lowest values are 15uV for an ideal precision op-amp and the
maximum value if 6mV dc.
Input Offset Current is the algebraic difference between the currents into the
inverting and non-inverting terminals.
Input Offset Current, Iio = |Ib1 Ib2|
Ib1 Non-inverting input current
Ib2 Inverting input current
The maximum input offset current value for 741 IC is 200nA. This value decreases
as the matching between the two input terminals is improved and may reduce down
to almost 6nA.
4.2.4.7 Lecture-7
Slew Rate (SR)
Slew Rate is one of the most important parameters for selecting op-amps for high
frequencies. SR is the maximum rate of change of output voltage per unit of time
and is expressed in volts per microseconds.
Slew Rate, SR = dVo/dt
By calculating slew rate we can easily find out the rate in which the output of the op-
amp changes in response to changes in the input frequency. The slew rate changes
46
with change in voltage gain and is usually specified at unity gain. The slew rate of an
op-amp is always fixed. Hence, if the slope requirements of the output signals are
greater than the slew rate, then distortion occurs.
In the case of the 741 IC the slew rate is 0.5V/uS, which is very small. This is one
reason why the 741 IC is considered not suitable for high frequency applications,
such as oscillators, comparators, and filters.
Common Mode Rejection Ratio (CMRR)
CMRR is the ratio of the differential voltage gain to the common mode voltage gain.
CMRR = Differential Voltage Gain (Ad)/ Common Mode Voltage Gain (Acm)
If the value of CMRR is high, there is better matching between the 2 input terminals.
For 741IC, CMRR is 90dB.
Supply Voltage Rejection Ratio (SVRR)
The change in the op-amps offset voltage caused by variations in supply voltage is
called SVRR. The change in supply voltage can be denoted by dV and the
corresponding change in input offset voltage can be denoted by dVio.
SVRR = Change in input offset voltage (dVio) / Change in supply voltage (dV)
For 741 IC, SVRR = 150uV/V.
The lower the value of SVRR, the better will be the op-amp performance.
Drift
The dependence of operational amplifier (op-amps) parameters with temperature

which affects its behavior/performance is specified as op-amp thermal drift. There can
be changes in op-amp bias currents, input offset voltage and input offset current with
temperature as given in the manufacturers data sheet of specific op-amp. For
precision applications many zero drift (with temperature) operational amplifiers are
available.
47
4.2.4.8 Lecture-8
Frequency Compensation techniques:
Most amplifiers use negative feedback to trade gain for other desirable properties, such
as decreased distortion, improved noise reduction or increased invariance to variation
of parameters such as temperature. Ideally, the phase characteristic of an
amplifier's frequency response would be linear; however, device limitations make this
goal physically unattainable. More particularly, capacitances within the amplifier's
gain stages cause the output signal to lag behind the input signal by 90 for
each pole they create. If the sum of these phase lags reaches 360, the output signal
will be in phase with the input signal. Feeding back any portion of this output signal to
the input when the gain of the amplifier is sufficient will cause the amplifier to
oscillate. This is because the feedback signal will reinforce the input signal. That is,
the feedback is then positive rather than negative.
4.2.4.9 Lecture-9
Block Diagram of Operational Amplifier (Op-amp)
The block diagram of a multi-stage operational amplifier is given below.
Fig.2.6 Block Diagram of Operational Amplifier (Op-Amp)
48
The op-amp begins with a differential amplifier stage, which operates in the
differential mode. Thus the inputs noted with + & - . The positive sign is for the
non-inverting input and negative is for the inverting input. The non-inverting input is
the ac signal (or dc) applied to the differential amplifier which produces the same
polarity of the signal at the output of op-amp. The inverting signal input is the ac
signal (or dc) applied to the differential amplifier. This produces a 180 degrees out of
phase signal at the output.
The inverting and non-inverting inputs are provided to the input stage which is a dual
input, balanced output differential amplifier. The voltage gain required for the
amplifier is provided in this stage along with the input resistance for the op-amp. The
output of the initial stage is given to the intermediate stage, which is driven by the
output of the input stage.In this stage direct coupling is used, which makes the dc
voltage at the output of the intermediate stage above ground potential. Therefore, the
dc level at its output must be shifted down to 0Volts with respect to the ground. For
this, the level shifting stage is used where usually an emitter follower with the
constant current source is applied. The level shifted signal is then given to the output
stage where a push-pull amplifier increases the output voltage swing of the signal and
also increases the current supplying capability of the op-amp.
1. The op amp response equally to both positive and negative input voltages.
2. Input bias current is defined as average of the base currents entering into
terminals of the opamp.
3. Input offset current is defined as difference of the base currents entering

into terminals of the opamp.
4. The amount of the input voltage that should be applied between two input
terminals of the op amp to nullify the output is called input offset voltage.
49
5. PSSR expressed in V/V.
6. The AC characteristics of the op amp are frequency response and slew

rate.
7. Slew rate is expressed in V/s and ideal value is 0.5 V/s.
1. An ideal operational amplifier has

a) infinite output impedance
b) zero input impedance
c) infinite bandwidth
d) All of the above
2. The ratio between differential gain and common-mode gain is called:

a) Amplitude
b) differential-mode rejection
c) common-mode rejection
d) Phase
3. With a differential gain of 50,000 and a common-mode gain of 2, what is the

common-mode rejection ratio?
a) 87.9 dB
b) 43.9 dB
c) 43.9 dB
d) 87.9 dB
4.The major difference between ground and virtual ground is that virtual
ground is only a:
a) voltage reference
b) current reference
c) power reference
50
d) difference reference
5.The common-mode voltage gain is
a) smaller than differential voltage gain
b) equal to voltage gain
c) greater than differential voltage gain

d) None of the above
6.An ideal amplifier should have:

a) high input current
b) zero offset
c) high output impedance
d) moderate gain
7. A differential amplifier has a common-mode gain of 0.2 and a common-mode rejection

ratio of 3250. What would the output voltage be if the single-ended input voltage was 7
mV rms?
a) 1.4 mV rms
b) 650 mV rms
c) 4.55 V rms
d) 0.455 V rms
8. What is the difference between common-mode and differential-mode input signals?

a) phase relationship
b) Voltage
c) Current
d) apparent power
9.The input offset current equals the

a) average of two base currents
b) collector current divided by the current gain
c) difference between two base-emitter voltages

d) difference between two base currents
51
10. How many leads does the TO-5 metal can package of an operational amplifier have?
a) 8, 10, or 12
b) 6, 8, or 10
c) 8 or 14
d) 8or 16
c. True or False questions
1. For 741 bipolar op amp the bias current is 500nA or less
a)True b)False
2. The equation for input bias current is IB+ +IB-/2
a)True b)False
3. To design inverting amplifier the value of Rcomp is R1||R2
a)True b)False
4. Thermal voltage drift is expressed in micro volts/oC
a)True b)False
5. Slew rate is defined as maximum rate of change of output voltage with

respective to time
a)True b)False
6. Change in the op amp input offset voltage caused by change in supply voltage
is referred to as PSSSR
a)True b)False
7. The expression for PSSR is
a)True b)False
8. Thermal current drift is denoted as
a)True b)False
9. Differential amplifier output is proportional to difference between 2 input
52
signals
a)True b)False

1. What is meant by offset voltage?
2. Define slew rate?
3. What is an op amp?
4. What are different linear IC packages?
5. List out six characteristics of an ideal op amp?
6. Define common mode rejection ratio?
7. What is a practical op amp and draw its equivalent circuit?
8. What is the difference between open and closed loop gains of an op amp?
9. What is thermal drift?
10. Mention AC & DC characteristics of the op amp?
b. Analytical type questions
1. Design the compensation circuit for input offset voltage in inverting configuration.
2. Design the compensation circuit for input offset current in non inverting
configuration.
3. Design the compensation circuit for input bias current in inverting configuration.
4. Derive the expression for slew rate.
5. Derive the expression for fmax for input signal for undistorted output.
6. What is the need for frequency compensation in opamp?
7. Mention all the characteristics of an ideal op amp.
8. Define CMRR and derive expression for it.

53
9. What is the need for Rcomp in inverting opamp?
10. What is meant by virtual ground concept?
Exercises/Assignments Assignment-2
1. (a) Draw the pin diagram and schematic symbol of a typical op-amp IC741 and
explain the function of each pin.
(b) List out the characteristics of ideal op-amp. Explain the concept of virtual
short in op-amp.
2. Define input bias current, input offset current and also present the methods of
compensation for the same.
3. (a) What is an op-amp? Draw the functional block diagram of an op-amp and
explain each block in detail.
(b) Explain the following characteristics of an op-amp: Slew rate, CMRR, and
PSRR.
4. Explain about the following two frequency compensation techniques: dominant
pole compensation and pole-zero (lag) compensation.
5. (a) Write ideal and practical specifications of 741 op-amp.
(b) Define thermal drift and PSRR.
6. (a) For an op-amp PSRR = 60dB(min), CMRR = 104 and differential mode gain is
105, the voltage changes by 20V in 4sec. Calculate:
(i) numerical value of the PSRR (ii) common mode gain (iii) slew rate.
(b) Define PSRR of an op-amp. Is an op-amp with smaller PSRR better or larger
PSRR better? Justify.
7. (a) Discuss the three basic types of linear IC packages and briefly explain the
characteristics of each.
(b) Draw pin diagram of IC741 op-amp and explain its features.
8. What is input bias current and explain the bias current compensation in an
inverting and non-inverting amplifier.
9. (a) What is thermal drift and mention the techniques to minimize its effect.
54
(b) Explain input offset current and present the solution for inverting amplifier
with T-feedback network.
10. List out the AC characteristics of an op-amp and discuss about them.

1. a) What is input bias current and explain the bias current compensation in an inverting
and non inverting amplifier.
b) A square wave of peak to peak amplitude of 500mV has to be amplified to a peak to
peak amplitude of 3 V with a rise time of 4s or less. Can a typical 741 Op-amp be used?
Justify.
c) What is thermal drift and mention the techniques to minimize the effect of thermal
drift.
2. a) What are the important features of an instrumentation amplifier and also Draw the
diagram of an instrumentation amplifier and explain.
b) Explain the operation of a I V converter using relevant diagrams and expressions.
3. (a) An op-amp has a slew rate of 2V/s. Find the rise time for an output voltage of 15V
amplitude resulting from a rectangular pulse input if the op-amp is slew rate limited.
(b) Define input offset voltage, total output offset voltage and also present the methods of
compensation.
4. (a) Design a circuit using op-amp to generate a output Vo= 0.1V1-V2+10V3 where
V1,V2,V3 are input voltages.
(b) Explain the working of a Transconductance amplifier with floating and grounded
loads. Is there any limitation on the size of the load when grounded?
5. (a) Draw the pin diagram and schematic symbol of a typical OP-AMP IC741 and
(b)For an OP-AMP, PSRR is 70dB, CMRR is 105, and differential mode gain is 105. The
output voltage changes by 20V in 4 sec. Calculate: (i) numerical value of PSRR (ii)
Common mode gain and (iii) Slew rate.
6. (a) Draw and explain the ideal differentiator circuit using an Op-Amp. Mention its
drawbacks and how these can be eliminated by using a practical differentiator.
55
(b)For the non-inverting a.c amplifier Rin=50, Ci=0.1f, R1=100, RF=1k and
RO=10k.Determine the gain & band width of the amplifier.
4.1.9 GATE Questions (Where relevant)
1. The CMRR of the differential amplifier shown is
a. Infinity
b. Zero
c. 900
d. 1800
Answer: C
2. An OP-AMP is used as a zero crossing detector. If the maximum output

available from the OP-AMP is 12 volts peak to peak, and the slew rate of the
OP-AMP is 12 V/sec, then the maximum frequency of the input signal that can
be applied without causing a reduction in the peak to peak output is
Answer: 1.59 KHz
3.The first pole encountered in the frequency response of a compensated OP-

AMP is approximately at
a. 5 Hz
b. 10 kHz
c. 1 MHz
d. 100 MHz
Answer: A
4.The frequency compensation is used in operational amplifiers is to increase its
56
Answer: Stability
5. From a measurement of the rise time of the output pulse of an amplifier, whose
input is a small amplitude square wave, one can estimate the following parameter
of the amplifier
a. Gain-bandwidth product
b. Slew rate
c. Upper 3 dB frequency
d. Lower 3 dB frequency
Answer: C
4.1.10 Interview questions (which are frequently asked in a Technical

round - Placements)
NA
NA
NA
4.1.13 Literature references of Relevant NPTEL Videos/Web/You Tube videos etc.
https://www.youtube.com/watch?v=nqk714QpRos
NA

57
4.3 Unit III - Ideal Operational Amplifier Theory and Basic Circuits
Ideal operational amplifier propertiesIdeal assumptionsBasic circuits such as non inverting

type comparatorInverting type comparatorVoltage follower Inverting amplifierNon
inverting amplifierSumming amplifier Noninverting summing amplifiersub-tractor
DifferentiatorIntegrator Scale changerInstrumentation amplifier V to I and I to V
convertorsLog and Antilog amplifiersZero crossing detectorSchmitt-trigger peak
detector Half-wave and full-wave rectifiers Precision diode Non-ideal operational
amplifier noninverting amplifier inverting amplifier closedloop gainInput and output
resistance equivalent circuits.
- Design & Analysis of op-amp based circuits

- Deviation of practical values from ideal values
- Linear applications of Op-amps
- Non-Linear applications of Op-amps
- Student will be able to design different op-amp based circuits.

Session Topics to be covered Reference Teaching Aids

No
1 Ideal operational amplifier T.B: 1- Ch:04 BB
propertiesIdeal assumptions Page No: 135-136
of op-amp.
2 Basic circuits such as non T.B: 1- Ch:05 BB
inverting type comparator Page No: 207-210
Inverting type comparator
Voltage follower
3 Inverting amplifier T.B: 1- Ch:02 BB
Page No: 41-44
4 Noninverting amplifier T.B: 1- Ch:02 BB
Page No: 47-48
5 Summing amplifier, Non T.B: 2- Ch:04 BB
inverting summing amplifier Page No: 135-139
and subtractor
6 Ideal and Practical T.B: 1- Ch:04 BB
Differentiator Page No: 164-168
58
7 Ideal and Practical Integrator T.B: 1- Ch:04 BB
Page No: 168-171
8 Instrumentation Amplifier T.B: 1- Ch:04 BB
using op-amp Page No: 141-143
9 V to I and I to V convertors T.B: 1- Ch:04 BB
10 Logarithmic amplifier using T.B: 1- Ch:04 BB
op-amp Page No: 155-157
11 Anti-Logarithmic amplifier T.B: 1- Ch:04 BB
12 Zero crossing detector, T.B: 1- Ch:05 BB
Schmitt-trigger and Page No: 210-215
13 Precision diode, Half-wave and T.B: 1- Ch:05 BB
full-wave rectifier, peak Page No: 148-151
detector using op-amp
14 AC analysis of non-ideal non T.B: 1- Ch:02 BB
inverting amplifier Page No: 47-48
15 AC analysis of non-ideal T.B: 1- Ch:02 BB
inverting amplifier Page No: 44-47
Course Outcome (CO2): To construct various applications by using analog ICs.
4.3.4.1 Lecture-1
Operational Amplifiers (in short op amps) are made from discrete components.
The op-amp is a direct coupled high gain(negative feedback) amplifier.
It can amplify signals having frequency ranging from 0Hz to 1MHz.
It is used to perform a wide variety of linear functions and some non linear
functions too.
Thus it is also called as basic linear integrated circuit.
This device is named as Operational amplifier because it was originally designed to
perform mathematical operations like addition, subtraction, differentiation, integration
and multiplication etc in an analog computer.
The main properties of an op amp are:
1. A very high open loop voltage gain A O = 105 for d.c. and low-frequency a.c.,
which decreases with frequency increase
59
2. A very high input impedance (Ri = 106 to 1012) so that the input voltage is passed on
to the op amp with little loss
3.A very low output impedance(RO around 100) , such that efficiently the output
voltage(VO) is transferred to any load greater than a few k.
Basically an op-amp is a differential voltage amplifier. It means it amplifies the
difference between input voltages V1 and V2. Here 3 situations are possible:
If V2 > V1 --> Vo is positive
If V2 < V1 --> Vo is negative
If V2 = V1, Vo = 0
Ideal Operational Amplifier:
The ideal opamp is a differential input, single ended output device. It has the following
characteristics
1. Infinite input resistance [Ri = Infinity]
2. Zero output resistance [RO = 0]
3. Infinite voltage gain [AV = Infinity]
4. Infinite bandwidth [BW = Infinity]
5. Infinite Common Mode Rejection Ratio
6. Infinite slew rate
7. Zero offset [ ie,V1 = V2 , VO =0]
8. Characteristics do not drift with temperature
4.3.4.1 Lecture 2
Op-amp Comparator Circuit
60
Fig. 3.1 Op-amp Comparator and its Characteristics
With reference to the op-amp comparator circuit above, lets first assume that V IN is less
than the DC voltage level at VREF, ( VIN < VREF ).
As the non-inverting (positive) input of the comparator is less than the inverting
(negative) input, the output will be LOW and at the negative supply voltage, -Vcc
resulting in a negative saturation of the output.
If we now increase the input voltage, VIN so that its value is greater than the reference
voltage VREF on the inverting input, the output voltage rapidly switches HIGH towards
the positive supply voltage +Vcc resulting in a positive saturation of the output.
If we reduce again the input voltage V IN, so that it is slightly less than the reference
voltage, the op-amps output switches back to its negative saturation voltage acting as
a threshold detector.
Then we can see that the op-amp voltage comparator is a device whose output is
dependent on the value of the input voltage, V IN with respect to some DC voltage level
as the output is HIGH when the voltage on the non-inverting input is greater than the
voltage on the inverting input, and LOW when the non-inverting input is less than the
inverting input voltage.
This condition is true regardless of whether the input signal is connected to the
inverting or the non-inverting input of the comparator.
We can also see that the value of the output voltage is completely dependent on the op-
amps power supply voltage. In theory due to the op-amps high open-loop gain the
magnitude of its output voltage could be infinite in both directions, (). However
practically, and for obvious reasons it is limited by the op-amps supply rails
giving VOUT = +Vcc or VOUT = -Vcc.
61
Comparator Reference Voltages:
5
Fig 3.2 Comparator
In theory the comparators reference voltage can be set to be anywhere between 0v and
the supply voltage but there are practical limitations on the actual voltage range
depending on the op-amp comparator being device used.
Positive and Negative Voltage Comparators

A basic op-amp comparator circuit can be used to detect either a positive or a negative
going input voltage depending upon which input of the operational amplifier we
connect the fixed reference voltage source and the input voltage too. In the examples
above we have used the inverting input to set the reference voltage with the input
voltage connected to the non-inverting input.
But equally we could connect the inputs of the comparator the other way around
inverting the output signal to that shown above. Then an op-amp comparator can be
configured to operate in what is called an inverting or a non-inverting configuration.
Positive Voltage Comparator
The basic configuration for the positive voltage comparator, also known as a non-
inverting comparator circuit detects when the input signal, VIN is ABOVE or more
positive than the reference voltage, VREF producing an output at VOUT which is HIGH as
shown.
62
Non-inverting Comparator Circuit
Fig.3.3 Negative Comparator Circuit
In this non-inverting configuration, the reference voltage is connected to the inverting

input of the operational amplifier with the input signal connected to the non-inverting
input. To keep things simple, we have assumed that the two resistors forming the
potential divider network are equal and:R1 = R2 = R. This will produce a fixed
reference
voltage which is one half that of the supply voltage, that is Vcc/2, while the input
voltage is variable from zero to the supply voltage.
When VIN is greater than VREF, the op-amp comparators output will saturate towards
the positive supply rail, Vcc. When V IN is less than VREF the op-amp comparators
output will change state and saturate at the negative supply rail, 0v as shown.
Negative Voltage Comparator
The basic configuration for the negative voltage comparator, also known as an
inverting comparator circuit detects when the input signal, V IN is BELOW or more
negative than the reference voltage, VREFproducing an output at VOUT which is HIGH as
shown.
63
Inverting Comparator Circuit
6
Fig.3.4 Inverting Comparator Circuit

In the inverting configuration, which is the opposite of the positive configuration
above, the reference voltage is connected to the non-inverting input of the operational
amplifier while the input signal is connected to the inverting input. Then when V IN
is less than VREF the op-amp comparators output will saturate towards the positive
supply rail, Vcc.
Likewise the reverse is true, when V IN is greater than VREF, the op-amp comparators
output will change state and saturate towards the negative supply rail, 0v.
Then depending upon which op-amp inputs we use for the signal and the reference
voltage, we can produce an inverting or non-inverting output.
We can take this idea of detecting either a negative or positive going signal one step
further by combining the two op-amp comparator circuits above to produce a window
comparator circuit.
64
4.3.4.3 Lecture 3
The Inverting Configuration
The inverting closeloop configuration
Fig.3.5
External components R1 and R2 form a close loop
Output is fed back to the inverting input terminal
Input signal is applied from the inverting terminal
Invertingconfiguration using ideal op amp
Fig.3.6 Inverting Op-amp

The required conditions to apply virtual short for opamp circuit:
Negative feedback configuration
Infinite openloop gain
Closedloop gain: G vO/vI = - R2/R1
Infinite differential gain: v2-v1 = vO/A = 0
Infinite input impedance: i2 = i1 = 0
65
Zero output impedance: vO = v1-i1R2 = -vIR2/R1
Voltage gain is negative. Input and output signals are out of phase.
Closedloop gain depends entirely on external passive components
(independent of opamp gain)
Closeloop amplifier trades gain (high openloop gain) for accuracy (finite but
accurate closedloop gain).
Equivalent circuit model for the inverting configuration
Fig.3.7 Equivalent Circuit Model for inverting

Input impedance: Ri vI/iI = vI /(vI/R1) = R1
For high input closedloop impedance, R1 should be large, but is limited to
provide sufficient G
In general, the inverting configuration suffers from a low input impedance
Output impedance: Ro = 0
Voltage gain: Avo = R2/R1
Other circuit example for inverting configuration
Fig: 3.8 Inverting Configurration
66
4.3.4.4 Lecture-4
Non-inverting Configuration
Fig. 3.9 Non Inverting Configuration
The non-inverting closeloop configuration

External components R1 and R2 form a close loop
Output is fed back to the inverting input terminal
Input signal is applied from the non-inverting terminal
Non-inverting configuration using ideal op amp
Fig.3.10 Non-Inverting using Ideal Opamp

The required conditions to apply virtual short for opamp circuit:
- Negative feedback configuration
- Infinite openloop gain
Closedloop gain: G vO/vI = 1+R2/R1
Infinite differential gain: v+ -v- = vO/A = 0
Infinite input impedance: i2 = i1 = v- /R1
67
Zero output impedance: vO = v- +i1R2 = vI(1+R2/R1)
Closedloop gain depends entirely on external passive components
(independent of opamp gain)
Closeloop amplifier trades gain (high openloop gain) for accuracy (finite but
accurate closed-loop gain)
Equivalent circuit model for the non-inverting configuration
68
=0
Fig.3.11Equivalent circuit
for Non inverting
I
n
p
u
t
i
m
p
e
d
a
n
c
e
:
R
i
=

O
u
t
p
u
t
i
m
p
e
d
a
n
c
e
R
0
69
4.3.4.5 Lecture-5
The inverting operational amplifier that the inverting amplifier has a single input
voltage, (Vin) applied to the inverting input terminal. If we add more input resistors to
the input, each equal in value to the original input resistor, (Rin) we end up with
another operational amplifier circuit called a Summing Amplifier, summing
inverter or even a voltage adder circuit as shown below.
Fig:3.12 Summing Amplifier Circuit
In this simple summing amplifier circuit, the output voltage, ( Vout ) now becomes proportional
to the sum of the input voltages, V1, V2, V3, etc. Then we can modify the original equation for
the inverting amplifier to take account of these new inputs thus:
70
However, if all the input impedances,( Rin ) are equal in value, we can simplify the
above equation to give an output voltage of:
Summing Amplifier Equation
We now have an operational amplifier circuit that will amplify each individual input
voltage and produce an output voltage signal that is proportional to the algebraic
SUM of the three individual input voltages V1, V2 and V3. We can also add more
inputs if required as each individual input sees their respective resistance, Rin as the
only input impedance.
This is because the input signals are effectively isolated from each other by the virtual
earth node at the inverting input of the op-amp. A direct voltage addition can also be
obtained when all the resistances are of equal value and R is equal to Rin.
Note that when the summing point is connected to the inverting input of the op-amp
the circuit will produce the negative sum of any number of input voltages. Likewise,
when the summing point is connected to the non-inverting input of the op-amp, it will
produce the positive sum of the input voltages.
71
A Scaling Summing Amplifier can be made if the individual input resistors are
NOT equal. Then the equation would have to be modified to:
To make the maths a little easier, we can rearrange the above formula to make the
feedback resistor RF the subject of the equation giving the output voltage as:
This allows the output voltage to be easily calculated if more input resistors are
connected to the amplifiers inverting input terminal. The input impedance of each
individual channel is the value of their respective input resistors, ie, R1, R2, R3 etc.
Sometimes we need a summing circuit to just add together two or more voltage signals
without any amplification. By putting all of the resistances of the circuit above to the
same value R, the op-amp will have a voltage gain of unity and an output voltage
equal to the direct sum of all the input voltages as shown:
Fig:3.13 3-input Inverting amplifier
The Summing Amplifier is a very flexible circuit indeed, enabling us to effectively

Add or Sum (hence its name) together several individual input signals. If the
inputs resistors, R1, R2, R3 etc, are all equal a unity gain inverting adder will be
made. However, if the input resistors are of different values a scaling summing
amplifier is produced which will output a weighted sum of the input signals.
72
4.3.4.6 Lecture-6
Integrators and Differentiators

Inverting configuration with general impedance
Fig.3.14 Integerator
o R1 and R2 in inverting configuration can be replaced by Z1(s) and Z2(s)
o The closedloop transfer function: Vo(s)/Vi(s) = -Z2(s)/Z1(s)
o The transmission magnitude and phase for a sinusoid input can be evaluated by
replacing s with j
Inverting integrator
Time domain analysis:
Frequency domain analysis:
73
Fig: 3.15 Miller Integerator
Also known as Miller integrator
4.3.4.7 Lecture 7
74
75
4.3.4.8 Lecture 8
Instrumentation amplifier using op-amp
Instrumentation amplifier is a kind of differential amplifier with additional input buffer

stages. The addition of input buffer stages makes it easy to match (impedance
matching) the amplifier with the preceding stage. Instrumentation are commonly used
in industrial test and measurement application. The instrumentation amplifier also has
some useful features like low offset voltage, high CMRR (Common mode rejection
ratio), high input resistance, high gain etc. The circuit diagram of a typical
instrumentation amplifier using opamp is shown below.
Fig: 3.16 Instrumentation amplifier
A circuit providing an output based on the difference between two inputs (times a scale
factor) is given in the above figure. In the circuit diagram, opamps labelled A1 and A2
are the input buffers. Anyway the gain of these buffer stages are not unity because of
the presence of R1 and Rg. Op amp labelled A3 is wired as a standard differential
amplifier. R3 connected from the output of A3 to its non inverting input is the
feedback resistor. R2 is the input resistor. The voltage gain of the instrumentation
amplifier can be expressed by using the equation below.
Voltage gain (Av) = Vo/(V2-V1) = (1 + 2R1/Rg ) x R3/R2
76
If need a setup for varying the gain, replace Rg with a suitable potentiometer.
Instrumentation amplifiers are generally used in situations where high sensitivity,
accuracy and stability are required. Instrumentation amplifiers can be also made using
two opamps, but they are rarely used and the common practice is to make it using
three opamps like what is shown here. The only advantages of making an
instrumentation amplifier using 2 opamps are low cost and improved CMRR.
A high gain accuracy can be achieved by using precision metal film resistors for all the
resistances. Because of large negative feedback employed, the amplifier has good
linearity, typically about 0.01% for a gain less than 10. The output impedance is also
low, being in the range of milli-ohms. The input bias current of the instrumentation
amplifier is determined by the op-amps A1 and A2.
A simplified instrumentation amplifier design is shown below. Here the resistances

labelled R1 are shorted and Rg is removed. This results in a full series negative
feedback path and the gain of A1 and A2 will be unity. The removal of R1 and Rg
simplifies the equation to Av = R3/R2.
Fig:3.17 Simplified Instrumentation amplifier
77
Practical instrumentation amplifier using opamp.
A practical instrumentation amplifier circuit designed based on uA 741 op amp is

shown below. The amplifier operates from +/-12V DC and has a gain 10.If you need a
variable gain, then replace Rg with a 5K POT. Instead of using uA741 you can use any
opamp but the power supply voltage must be changed according to the op amp. A
single LM324 op amp Ic is a good choice. Out of the four opamps inside the LM324,
three can be used for IC1, IC2, IC3 and the remaining one can be left alone. This
reduces the PCB size a lot and makes the circuit compact.
Fig: 3.18 Practical Instrumentation amplifier
An instrumentation amplifier is a differential amplifier optimized for high input

impedance and high CMRR. An instrumentation amplifier is typically used in
applications in which a small differential voltage and a large common mode voltage
are the inputs of the amplifier and hence figure describes the use of three op-amps.
78
4.3.4.9 Lecture-09
Fig.3.19 I to V converter
79
Fig.3.20 I to V converter
80
Fig.3.21: V to I converter
81
4.3.4.10 Lecture-10
LOG and ANTILOG Amplifiers PPT:
82
83
84
85
4.3.4.11 Lecture -11
Precision rectifier
The precision rectifier, also known as a super diode, is a configuration obtained with
an operational amplifier in order to have a circuit behave like an ideal diode and
rectifier. It is useful for high-precision signal processing.
The op-amp based precision rectifier should not be confused with the power
MOSFET- based active rectification ideal diode.
Basic circuit
Fig.3.22 A simple precision rectifier circuit
The basic circuit implementing such a feature is shown on the right, where R L can be any
load. When the input voltage is negative, there is a negative voltage on the diode, so it
works like an open circuit, no current flows through the load, and the output voltage is
zero.
When the input is positive, it is amplified by the operational amplifier which switches the
diode on. Current flows through the load and, because of the feedback, the output voltage
is equal to the input voltage.
The actual threshold of the super diode is very close to zero, but is not zero. It equals the
actual threshold of the diode, divided by the gain of the operational amplifier.
This basic configuration has a problem so it is not commonly used. When the input
becomes (even slightly) negative, the operational amplifier runs open loop, as there is no
86
feedback signal through the diode. With a typical high open loop gain operational
amplifier, the output saturates. If the input then becomes positive again, the op-amp has
to get out of the saturated state before positive amplification can take place again. This
change generates some ringing and takes some time, greatly reducing the frequency
response of the circuit.
Fig.3.23 An improved precision rectifier circuit

Improved circuit
In this case, when the input is greater than zero, D1 is OFF and D2 is ON, so the output is
zero because one side of is connected to the virtual ground, and there is no current
through it. When the input is less than zero, D1 is ON and D2 is OFF, and the output is
like the input with an amplification of . Its input-output relationship is the

following:
This circuit has the benefit that the op-amp never goes into saturation, but its output must
change by two diode voltage drops (about 1.2 V) each time the input signal crosses zero.
Hence, the slew rate of the operational amplifier, and its frequency response (gain-
87
bandwidth product) will limit high frequency performance - especially for low signal
levels - although an error of less than 1% at 100 kHz is possible.
Similar circuitry can be used to create a precision full-wave rectifier circuit
Peak detector
With a little modification, the basic precision rectifier can be used for detecting signal
level peaks. In the following circuit, a capacitor retains the peak voltage level of the
signal, and a switch is used for resetting the detected level.
Fig.3.24 Peak Detector
4.3.4.11Lecture-11
A.C. Analysis:
In previous lecture dc analysis has been done to obtain the operatiing point of the two
transistors. To find the voltage gain Ad and the input resistance Ri of the differential
amplifier, the ac equivalent circuit is drawn using r-parameters as shown in fig.The dc
voltages are reduced to zero and the ac equivalent of CE configuration is used.
88
Fig.3.25 A.C. Analysis of DIBO Configuration
equal and designated by r'e . This voltage across each collector resistance is shown
180 out of phase with respect to the input voltages v1 and v2. This is same as in CE
configuration. The polarity of the output voltage is shown in Figure. The collector C2
is assumed to be more positive with respect to collector C1 even though both are
negative with respect to ground.
Applying KVL in two loops 1 & 2.
5
Again, assuming RS1 / and RS2 / are very small in comparison with RE and re'
and therefore neglecting these terms,
89
Thus a differential amplifier amplifies the difference between two input

signals. Defining the difference of input signals as vd = v1 ? v2 the
voltage gain of the dual input balanced output differential amplifier can be
given by
90
4.3.5. Test Questions
1. The gain of the inverting amplifier is G vO/vI = - R2/R1.
2. The gain of the non-inverting amplifier is G vO/vI = 1+R2/R1.
3. The gain of the buffer amplifier is unity.
4. In integrating amplifier the output voltage is time integral of the input voltage.
5. I to V converter is also called as transresistance amplifier.
6. In V to I converter output current is proportional to input voltage signal.

7. In logarithmic amplifier output voltage is logarithm of the input voltage.
8. Schmitt trigger converts an irregular waveform into square waveform.
1. Refer to the given figure. This circuit is known as
a) a noninverting amplifier.
b) a differentiator.
c) an integrator.
d) a summing amplifier.
2. Refer to the given figure. This circuit is known as

85
a) a noninverting amplifier.
b) a differentiator.
c) an integrator.
d) a summing amplifier.
3.Refer to the given figure. What is the output voltage?
a) 2V
b) 2 V
c) +Vsat
d) Vsat
4. If an op-amp comparator has a gain of 100,000, an input difference of 0.2

mV above reference, and a supply of 12 V, the output will be
a) 20 V.
b) 12 V.
c) 10 V.
d) 15 V.
86
f. Refer to the given figure. Determine the upper trigger point.
a) V(out)max
b) V(out)max
c) 1.41 V
d) +1.41 V
g.Refer to the given figure. If Vin = 5 V, the rate of change of

the output voltage in response to a single pulse input is:
a) 15.2 s
b) 1.52 s
c) 1.52 s
d) 15.2 s
h. An op-amp has an open-loop gain of 90,000. Vsat = 13 V. A differential
voltage of 0.1 Vp-p is applied between the inputs. What is the output voltage?
87
a) 13 V
b) 13 V
c) 13 Vp-p
d) 26 Vp-p
i. Refer to the given figure. With the inputs shown, determine the output
voltage.
a) 7V
b) 7 V
c) +Vsat
d) Vsat
j. Refer to the given figure. What is the output voltage?
a) 0.5 V
88
b) 0.5 V
c) 2V
c) 2 V
C) True or False questions
The output equation of inverting amplifier is Rf/R1
a)True b)False
The output equation of non-inverting amplifier is (1+ Rf/R1 )
a)True b)False
Floating load is connected between 2 nodes
a)True b)False
The output of the differentiator is integral of the input voltage
a)Trueb)False
In Antilogarithmic amplifier output voltage is logarithmic of the input voltage

a)True b)False
Peak Detector is nothing but output follows the peak of the input voltage
a)True b)False
Sample and hold circuit samples the input signal and holds on to next sampled value
until the input is sampled again
a)True b)False
The output of the comparator is positive or negative saturation voltages

depending up on which input is larger
a)True b)False
Zero crossing detector is also called as square to sine wave converter
a)True b)False
89
The Schmitt trigger consist of VUT & VLT
a)True b)False
1. What is the gain of the inverting amplifier?
2. What is the gain of the non inverting amplifier?
3. What is meant by Schmitt trigger?
4. What is meant by comparator?
5. Write the output equation of integrating amplifier?
6. Write the output equation of practical integrating amplifier?
7. Write the output equation of differentiating amplifier?
8. Write the output equation of practical differentiating amplifier?
9. What is meant by astable and monostable multivibrator?
10. What is Schmitt trigger?
90
1. Design an inverting amplifier with a gain of -20?
2. Draw the output waveform of a inverting comparator with reference voltage

of 2V?
3. Draw the ideal integrator circuit and derive the expression for output voltage?
4. Draw the practical integrator circuit and derive the expression for
output voltage?
5. Draw the ideal differentiator circuit and derive the expression for output
voltage?
6. Draw the practical differentiator circuit and derive the expression for output
voltage?
7. Derive the output expression for log amplifier?
8. Derive the output expression for anti log amplifier?
9. Write the output equation of an I to V converter?
10. Write the output equation of a V to I converter?

Exercises/Assignments Assignment-3
1. What are the important features of an instrumentation amplifier and also draw
the diagram of an instrumentation amplifier and explain.
2. (a) Explain the working of a transresistance amplifier.
(b) Draw the circuit diagram of a practical differentiator and write the design steps of a
good differentiator.
3. (a) Explain the operation of high input impedance non-inverting AC amplifier.
(b) Draw the circuit of an anti-log amplifier and support with appropriate derivation.
4. Discuss how op-amp is used as comparator. What are the limitations of the op-
amp as comparators?
5. (a) Draw and explain the operation of V-I converter with floating load.
(b) Explain the working of an op-amp inverting amplifier and derive the expression for
voltage gain.
6. Draw the diagram of a logarithmic amplifier and derive the expression for its
output voltage and also discuss log-amp with saturation current and temperature
compensation.
7. Explain the operation of triangular wave generator and derive the expression for
frequency of oscillation.
8. Explain the operation of Schmitt trigger.
9. With neat circuit diagram, explain the operation of monostable multivibrator using
an op-amp. And also derive an expression for the time period.
10. What is precision rectifier? Explain the full wave precision rectifier.
1.(a) What are the important features of an instrumentation amplifier and also Draw
the diagram of an instrumentation amplifier and explain.
Explain the operation of a I V converter using relevant diagrams and expressions.
2. a) Explain the operation of Half wave rectifier using Op-amp with relevant
diagrams and waveforms.
b) Draw the diagram of anti-log amplifier and derive the expression for its output
voltage.
3. (a) Construct a full wave rectifier using op-amps and explain the operation using the
equivalent circuits and wave forms for Vi>0 and Vi<0 , where Vi is input voltage.
(b) What is the purpose of clamp diodes in a comparator? Draw a comparator where
clamp diodes are used and explain the operation of a basic comparator.
4. (a) Explain the principle of operation of a log amplifier with neat circuit diagram.
(b)Design a Schmitt trigger with an Op-Amp A741 with the following
specifications and also determine the threshold voltages VUT and VLT. R1 = 100k_,
R2 = 56k_, VIN(pp) = 1V and VCC = VEE = 15V.
1. In the OP-AMP circuit given in the figure, the load current iL is
a. VS / R2
b. V S / R2
c. VS / RL
d. V S / R1
Answer: A
2. The input resistance Ri of the amplifier shown in figure is
a. 30/4 K
b. 10 K
c. 40 K
d. Infinite
Answer: B
3. Given the ideal operational amplifier circuit shown in figure indicate the
correct transfer characteristics assuming ideal diodes with zero cut-in voltage.
Answer: B
4. For the circuit shown in the following figure, the capacitor C is initially uncharged.
At t = 0, the switch S is closed. The voltage VC across the capacitor at t = 1 ms is
. Assume the OP AMP is supplied with 15 volts.
a. 0 volts
b. 6.3 volts
c. 9.45 volts
d. 10 volts
Answer: D
5. For the OP-AMP circuit shown in the figure, Vo is
a. 2 volts
b. 1 volts
c. 0.5 volts
d. + 0.5 volts
Answer: C
6. In the OP-AMP circuit shown, assume that the diode current follows the equation I
= ISexp(V/VT). For Vi = 2 Volts, Vo = V01, and for Vi = 4 Volts, Vo = V02.
The relationship between V01 and V02 is
a. V02 = 2 V01
b. V02 = e2 V01
c. V02 = V01 ln2
d. V02 - V01 = VT ln2
Answer: D
7. Consider the following circuit using an ideal OP-AMP. The I-V characteristic of
the diode is described by the relation I = I o(exp(V/VT) - 1), where VT = 25 mV, I o =
1A and V is the voltage across the diode(taken as positive for forward bias). For an
input voltage Vi = - 1 volts, the output voltage
Vo is
a. 0 volts
b. 0.1 volts
c. 0.7 volts
d. 1.1 volts
Answer: B
8. Assuming the OP-AMP is ideal, the voltage gain of the amplifier shown below is
a. - R2/R1
b. - R3/R1
c. - (R2 || R3) / R1
d. - (R2 + R3)/R1
Answer: A
9.In the circuit shown below, what is the output voltage (Vout), if a silicon transistor Q
and an ideal OP-AMP are used?
a. - 15 volts
b. - 0.7 volts
c. + 0.7 volts
d. + 15 volts
Answer: B
10. In the circuit shown below, the OP-AMPs are ideal. Then Vout in volts is
a. 4
b. 6
c. 8
d. 10
Answer: C
4.3.10 Interview questions (which are frequently asked in a Technical round -

Placements)
NA
NA
NA
https://www.youtube.com/watch?v=clTA0pONnMs
NA

T2. Linear Integrated Circuits --- D.Roy Choudhury & Shail B.Jai
4.4 WAVEFORM GENEREATOR IN ANGULAR WAVEFORM GENERATOR USING
OP-AMPS AND PLL
Design of Astable Multivibrator-Monostable multivibrator using signal op amp-Triggering waveform

generator -555 Timer-Introduction-Pin diagram-Functional diagram for 8-pin DIP-Design of astable
and Monostable Multivibrators-Astable and Monostable applications-PLL: Introduction, Block
diagram-Functions of each block -566 VCO-565 PLL block diagram-Functions of each block-
Applications of PLL- Frequency Multiplier in each role of pin Frequency Translation-AM FM
FSK Demodulator
- Design of different Multivibrators using op-Amps

- Waveform generators
- Operation of 555 timer
- PLL design and its applications
- Design of VCO and its applications.
- Student can be able to design different circuits using 555 timer, VCO and PLL.

Session Teaching
No Aids
T.B: 1- Ch:05
1 Design of Astable multivibrator using op-amp. BB
Page No: 216-218
Design of Monostable multivibrator using op-amp. T.B: 1- Ch:05
2 BB
Page No: 218-220
Introduction of 555 timer pin diagram and functional T.B: 1- Ch:08
3 BB
diagram for 8pin DIP. Page No: 311-312
T.B: 1- Ch:08
4 Design of Astable multivibrator using 555 timer. BB
Page No: 318-321
T.B: 1- Ch:08
5 Applications of Astable multivibrator using 555 timer. BB
Page No: 322-324
T.B: 1- Ch:08
6 Design of Monostable multivibrator using 555 timer. BB
Page No: 312-314
T.B: 1- Ch:08
7 Applications of Monostable multivibrator using 555 timer. BB
Page No: 315-318
T.B: 1- Ch:08
8 Design of Schmitt trigger using 555 timer BB
Page No: 324-324
T.B: 1- Ch:09
9 Introduction of PLL basic block diagram BB
Page No: 327-328
T.B: 1- Ch:09
10 Functions of each block in IC 566 BB
Page No: 329-333
T.B: 1- Ch:09
11 Voltage controller oscillator using IC 566 BB
Page No: 334-336
T.B: 1- Ch:09
12 Monolithic Phase Locked loop BB
Page No: 337-342
Applications of PLLFrequency T.B: 1- Ch:09
13 BB
Page No: 342-345
Course Outcome (CO2): To construct various applications by using ICs
4.4.4.1 Lecture-1
Op-amp Astable Multivibrator Circuit (Square wave generator)

Fig.4.1
So how does it work? Firstly lets assume that the capacitor is fully discharged and the
output of the op-amp is saturated at the positive supply rail. The capacitor, C starts to
charge up from the output voltage, Vout through resistor, R at a rate determined by
their RC time constant.
We know from our tutorials about RC circuits that the capacitor wants to charge up
fully to the value of Vout (which is +V (sat)) within five time constants. However, as
soon as the capacitors charging voltage at the op-amps inverting (-) terminal is equal to
or greater than the voltage at the non-inverting terminal (the op-amps output voltage
fraction divided between resistors R1 and R2), the output will change state and be
driven to the opposing negative supply rail.
But the capacitor, which has been happily charging towards the positive supply rail
(+V (sat)), now sees a negative voltage, -V (sat) across its plates. This sudden reversal
of the output voltage causes the capacitor to discharge toward the new value of Vout at
a rate dictated again by their RC time constant.
Op-amp Multivibrator Voltages
Fig.4.2
Once the op-amps inverting terminal reaches the new negative reference voltage, -Vref
at the non-inverting terminal, the op-amp once again changes state and the output is
driven to the opposing supply rail voltage, +V (sat). The capacitor now sees a positive
voltage across its plates and the charging cycle begins again. Thus, the capacitor is
constantly charging and discharging creating an astable op-amp multivibrator output.
The period of the output waveform is determined by the RC time constant of the two
timing components and the feedback ratio established by the R1, R2 voltage divider
network which sets the reference voltage level. If the positive and negative values of
the amplifiers saturation voltage have the same magnitude, then t1 = t2 and the
expression to give the period of oscillation become:
Then we can see from the above equation that the frequency of oscillation for an Op-
amp Multivibrator circuit not only depends upon the RC time constant but also upon
the Feedback fraction. However, if we used resistor values that gave a feedback
fraction of 0.462, ( = 0.462), then the frequency of oscillation of the circuit would
be equal to just 1/2RC as shown because the linear log term becomes equal to one.
4.4.4.2 Lecture-2
MONOSTABLE MULTIVIBRATOR USING OP AMP 741
Monostable multivibrator is also called as One Shot Multivibrator. It has a Stable State
and a Quasi-Stable State. The circuit remains in stable state until a triggering signal is
applied to its input. After getting the triggering signal the output transit from stable to
Quasi-stable state and return back after a time period. So a Single Pulse is generated
for single Trigger.
Fig.4.3
Consider the instant at which the output Vo=+Vsat. At that time diode D1 damps the
Capacitor voltage, Vc at 0.7V. Feedback voltage is +Vsat at Non-Inverting terminal.
When the negative trigger is applied, the potential at Non-Inverting terminal becomes
less than 0.7v the output switches to -Vsat, which makes the diode more negative than
- Vsat. Comparator switches back to +Vsat. The Capacitor C starts charging to +Vsat
through R until Vc reaches 0.7v and C becomes damped to 0.7v.
The pulse width is given by T=RC*ln (1/1-).
4.4.4.3 Lecture 3
555 Timers:
IC 555 timer is a well-known component in the electronic circles but what is not
known to most of the people is the internal circuitry of the IC and the function of
various pins present there in the IC. Let me tell you a fact about why 555 timer is
called so, the timer got its name from the three 5 kilo-ohm resistor in series employed
in the internal circuit of the IC.
IC 555 timer is a one of the most widely used IC in electronics and is used in various
electronic circuits for its robust and stable properties. It works as square-wave form
generator with duty cycle varying from 50% to 100%, Oscillator and can also provide
time delay in circuits. The 555 timer got its name from the three 5k ohm resistor
connected in a voltage-divider pattern which is shown in the figure below. A simplified
diagram of the internal circuit is given below for better understanding as the full
internal circuit consists of over more than 16 resistors, 20 transistors, 2 diodes, a flip-
flop and many other circuit components.
The 555 timer comes as 8 pin DIP (Dual In-line Package) device. There is also a 556
dual version of 555 timer which consists of two complete 555 timers in 14 DIP and a
558 quadruple timer which is consisting of four 555 timer in one IC and is available as
a 16 pin DIP in the market.
Fig.4.4 IC555 Pin Diagram and Functional Diagram
Basics Concepts:
Comparator: The Comparator are the basic electronic component which compares the
two input voltages i.e. between the inverting (-) and the non-inverting (+) input and if
the non-inverting input is more than the inverting input then the output of the
comparator is high. Also the input resistance of an ideal comparator is infinite.
Voltage Divider: As we know that the input resistance of the comparators is infinite
hence the input voltage is divided equally between the three resistors. The value being
Vin/3 across each resistor.
Flip/Flop: Flip/Flop is a memory element of Digital-electronics. The output (Q) of the
flip/flop is high if the input at S terminal is high and R is at Low and the output
(Q) is low when the input at S is low and at R is high.
Function of different Pins:-
1. Ground: This pin is used to provide a zero voltage rail to the Integrated circuit to
divide the supply potential between the three resistors shown in the diagram.
2. Trigger: As we can see that the voltage at the non-inverting end of the comparator is
Vin/3, so if the trigger input is used to set the output of the F/F to high state by
applying a voltage equal to or less than V in/3 or any negative pulse, as the voltage at
the non-inverting end of the comparator is Vin/3.
3. Output: It is the output pin of the IC, connected to the Q (Q-bar) of the F/F with an
inverter in between as show in the figure.
4. Reset: This pin is used to reset the output of the F/F regardless of the initial
condition of the F/F and also it is an active low Pin so it connected to high state to
avoid any noise interference, unless a reset operation is required. So most of the time it
is connected to the Supply voltage as shown in the figure.
5. Control Voltage: As we can see that the pin 5 is connected to the inverting input
having a voltage level of (2/3) Vin. It is used to override the inverting voltage to change
the width of the output signal irrespective of the RC timing network.
6. Threshold: The pin is connected to the non-inverting input of the first comparator.
The output of the comparator will be high when the threshold voltage will be more
than (2/3) Vin thus resetting the output (Q) of the F/F from high to low.
7. Discharge: This pin is used to discharge the timing capacitors (capacitors involved
in the external circuit to make the IC behave as a square wave generator) to ground
when the output of Pin 3 is switched to low.
8. Supply: This pin is used to provide the IC with the supply voltage for the
functioning and carrying of the different operations to be fulfilled with the 555 timer.
Uses:-
The IC 55 timer is used in many circuits, for example One-shot pulse generator in
Monostable mode as an Oscillator in Astable Mode or in Bistable mode to produce
a flip/flop type action. It is also used in many types of other circuit for achievement
of various purposes for instance Pulse Amplitude Modulating (PAM), Pulse Width
Modulation (PWM) etc.
4.4.4.4 Lecture-4
Astable 555 Oscillator Circuit:
Fig.4.5 Astable Multivibrator with Waveforms
1 1
In the 555 Oscillator circuit above, pin 2 and pin 6 are connected together
allowing the circuit to re-trigger itself on each and every cycle allowing it to
operate as a free running oscillator. During each cycle capacitor, C charges up
through both timing resistors, R1 and R2 but discharges itself only through resistor,
R2 as the other side of R2 is connected to the discharge terminal, pin 7.
Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is
determined by the0.693(R1+R2)C combination and discharges itself down to
1/3Vcc (the lower comparator limit) determined by the 0.693(R2.C) combination.
This results in an output waveform whose voltage level is approximately equal to
Vcc 1.5V and whose output ON and OFF time periods are determined by the
capacitor and resistors combinations. The individual times required to complete one
charge and discharge cycle of the output is therefore given as:
Astable 555 Oscillator Charge and Discharge Times
Where, R is in s and C in Farads.
When connected as an astable multivibrator, the output from the 555 Oscillator
will continue indefinitely charging and discharging between 2/3Vcc and 1/3Vcc
until the power supply is removed. As with the monostable multivibrator these
charge and discharge times and therefore the frequency are independent on the
supply voltage.
The duration of one full timing cycle is therefore equal to the sum of the two
individual times that the capacitor charges and discharges added together and is
given as:
555 Oscillator Cycle Time
2 2
The output frequency of oscillations can be found by inverting the equation above
for the total cycle time giving a final equation for the output frequency of an
Astable 555 Oscillator as:
555 Oscillator Frequency Equation
By altering the time constant of just one of the RC combinations, the Duty
Cycle better known as the Mark-to-Space ratio of the output waveform can be
accurately set and is given as the ratio of resistor R2 to resistor R1. The Duty Cycle
for the 555 Oscillator, which is the ratio of the ON time divided by the OFF
time is given by:
555 Oscillator Duty Cycle
The duty cycle has no units as it is a ratio but can be expressed as a percentage
( % ). If both timing resistors, R1 and R2 are equal in value, then the output duty
cycle will be 2:1 that is, 66% ON time and 33% OFF time with respect to the
period.
4.4.4.5 Lecture 5
Applications of Astable Multivibrator:
1. Square wave Generation

2. Pulse Position Modulator
3. Frequency Modulator
Design of Pulse Position Modulation using Astable multivibrator:
In pulse position Modulation,the position of pulses varied according to the modulating
3 3
signal while the amplitude and width of the pulses are kept constant. The position of
each pulse changes according to the instantaneous value of the sampled signal of
modulator. In order to achieve the modulation we use two timers which one operates in
astable mode and other in monostable mode.
The modulating signal is applied at pin 5of first IC 555 that is operating is astable
mode. The output of this IC 555 is a pulse width modulated wave. This PWM signal is
applied as the trigger input to the second IC555changes according to the PWM signal
which is again dependent upon the modulating signal. The schematic diagram of PPM
using 555 timer is shown in fig 4.6
Fig 4.6 Pulse Position Modulator using Astable Multivibrator

The threshold voltage determined by the control voltage is changed according to
upper threshold voltage and is given by:
UTL =2/3VCC +VMOD
As the threshold voltage changes with respect to modulating voltage ,the width of
the pulse changes and hence time delay is varied. As this pulse width is modulated
signal is applied to trigger of the second 555 timer, there will be no change in either
amplitude or width of the output signal but only position of the output pulse will be
changed. The waveforms are shown in the Fig 4.7
4 4
Fig 4.7: PPM waveforms
4.4.4.6 Lecture 6
Monostable 555 Timer
The operation and output of the 555 timer monostable is exactly the same as that
for the transistorized one we look at previously in the Monostable Multivibrators
tutorial. The difference this time is that the two transistors have been replaced by
the 555 timer device. It has one stable state and other is quasi state and requires one
external triggering to change its state from low to high state, and to automatically it
reaches to its original stable state after some period of time which is called Pulse
duration Consider the 555 timer monostable circuit below.
5 5
Fig.4.8 Monostable Multivibrator using IC555
When a negative ( 0V ) pulse is applied to the trigger input (pin 2) of the
Monostable configured 555 Timer oscillator, the internal comparator, (comparator
No1) detects
this input and sets the state of the flip-flop, changing the output from a LOW
state to a HIGH state. This action in turn turns OFF the discharge transistor
connected to pin 7, thereby removing the short circuit across the external timing
capacitor, C1.
This action allows the timing capacitor to start to charge up through resistor, R1
until the voltage across the capacitor reaches the threshold (pin 6) voltage of
2/3Vcc set up by the internal voltage divider network. At this point the comparators
output goes HIGH and resets the flip-flop back to its original state which in
turn turns ON the transistor and discharges the capacitor to ground through pin 7.
This causes the output to change its state back to the original stable LOW value
awaiting another trigger pulse to start the timing process over again. Then as
before, the Monostable Multivibrator has only ONE stable state.
6 6
The Monostable 555 Timer circuit triggers on a negative-going pulse applied to
pin 2 and this trigger pulse must be much shorter than the output pulse width
allowing time for the timing capacitor to charge and then discharge fully. Once
triggered, the 555 Monostable will remain in this HIGH unstable output state
until the time period set up by the R1 x C1 network has elapsed. The amount of
time that the output voltage remains HIGH or at a logic 1 level, is given by the
following time constant equation.
Where, t is in seconds, R is in s and C in Farads.
4.4.4.7 Lecture 7
Applications:
Missing Pulse Detector:

To implement this circuit, we use a 555 IC configured as an astable multivibrator.
See the diagram. The output of the 555 timer remains high while the pulses applied
to its input occur in the correct intervals of time. If a pulse fall behind, or it is
absent, the output of the 555 IC goes low, detecting a problem.
Fig.4.9 Missing Pulse Detector
7 7
The values of resistor R1 and capacitor C1 are chosen depending on
the application you have. The values of R1 and C1 on this circuit were chosen to
observe its operation when the input is activated manually.
The input pulses are detected by pin 2 of the 555 timer. At this same point we
connect the base of a PNP transistor (Q1) in order to discharge the capacitor C1,
each time the expected pulse appears, and thus start a new charging.
If the pulses arrive at pin 2 of the 555 integrated circuit on the correct intervals of
time, the capacitor C1 is discharged before its voltage level reaches the level that
causes the output of the 555 timer to go low.
Note: This missing pulse detector circuit does not detect:
If pulses are closely spaced
If the pulse frequency increases.
4.4.4.8 Lecture 8
Schmitt Trigger
The high and low transitions on the inputs of most of the CMOS devices should be
fast edges. If the edges are not fast enough, they tend to provide more current and
this might damage the device. Analog signals are generally not perfect and might
not have clean edges all the times. Schmitt Trigger is a special type of comparator
that is used to avoid such signals.
A comparator is a device that compares two voltages and the outcome is the
indication of whether one voltage is higher than the other or not. Schmitt trigger,
also called as Regenerative Comparator, compares the input voltage to two
references
Voltages and produces an equivalent output. The output of a Schmitt trigger is

always a square or rectangular wave irrespective of the shape of the input. It is
often used when we need to do the following:
8 8
Convert sine wave to square wave
To clean up the noisy signals
To convert slow edges (like in a triangular wave) into fast edges
(like a square wave)
Schmitt can be constructed from a 555 timer. Some of the other function of the 555
timer, apart from the timer operation, is to use the two internal comparators as
independent units to form a Schmitt Trigger. The general operation of the Schmitt
trigger built from a 555 timer is inverting but the discussion will be for non-
inverting.
Circuit of 555 timer as Schmitt Trigger
The following circuit shows the structure of a 555 timer used as a Schmitt trigger.
Fig.4.10 Schmitt Trigger using IC555

Pins 4 and 8 are connected to the supply (VCC). The pins 2 and 6 are tied together
and the input is given to this common point through a capacitor C. this common
point is supplied with an external bias voltage of VCC / 2 with the help of the
voltage divider circuit formed by the resistors R1 and R2.
9 9
The important characteristic of the Schmitt trigger is Hysteresis. The output of the
Schmitt trigger is high if the input voltage is greater than the upper threshold value
and the output of the Schmitt trigger is low if the input voltage is lower than the
lower threshold value.
The output retains its value when the input is between the two threshold values.
The usage of two threshold values is called Hysteresis and the Schmitt trigger acts
as a memory element (a bistable multivibrator or a flip-flop).
The threshold values in this case are 2/3 VCC and 1/3 VCC i.e. the upper
comparator trips at 2/3 VCC and the lower comparator trips at 1/3 VCC. The input
voltage is compared to these threshold values by the individual comparators and the
flip-flop is SET or RESET accordingly. Based on this the output becomes high or
low.
When a sine wave of amplitude greater than VCC / 6 is applied at the input, the
flip- flop is set and reset alternately for the positive cycle and the negative cycle.
The output is a square wave and the waveforms for input sine wave and output
square wave are shown below.
Fig.4.11 Waveforms of Schmitt Trigger

10 10
Inverting Schmitt Trigger
The normal operation of the 555 timer as a Schmitt trigger is inverting in nature.
When the trigger input, which is same as the external input, falls below the
threshold value of 1/3 VCC, the output of the lower comparator goes high and the
flip-flop is SET and the output at pin 3 goes high.
Similarly, when the threshold input, which is same as the external input, rises above
the threshold value of 2/3 VCC, the output of the upper comparator goes high and
the flip-flop is RESET and the output at pin 3 goes low.
The waveform of the inverting Schmitt trigger is shown below.
Fig.4.12 Waveforms of Inverting Schmitt Trigger
4.4.4.9 Lecture-9
Phase Locked Loops
(PLL) Introduction:
The concept of Phase Locked Loops (PLL) first emerged in the early 1930s.But
the technology was not developed as it now, the cost factor for developing this
technology was very high. Since the advancement in the field of integrated circuits,
PLL has become one of the main building blocks in the electronics technology. In
11 11
present, the PLL is available as a single IC in the SE/NE560 series (560, 561, 562,
564, 565 and 567) to further reduce the buying cost, the discrete ICs are used to
construct a PLL.
PLL Block Diagram
The block diagram of a basic PLL is shown in the figure below. It is basically a flip
flop consisting of a phase detector, a low pass filter (LPF),and a Voltage Controlled
Oscillator (VCO).
Fig.4.13 Block Diagram - Phase Locked Loops
The input signal Vi with an input frequency fi is passed through a phase detector. A
phase detector basically a comparator which compares the input frequency fi with
the feedback frequency fo .The phase detector provides an output error voltage Ver
(=fi+fo),which is a DC voltage. This DC voltage is then passed on to an LPF. The
LPF removes the high frequency noise and produces a steady DC level, Vf (=Fi-
Fo). Vf also represents the dynamic characteristics of the PLL.
The DC level is then passed on to a VCO. The output frequency of the VCO (fo) is
directly proportional to the input signal. Both the input frequency and output
frequency are compared and adjusted through feedback loops until the output
frequency equals the input frequency. Thus the PLL works in these stages free-
12 12
running, capture and phase lock.
As the name suggests, the free running stage refer to the stage when there is no
input voltage applied. As soon as the input frequency is applied the VCO starts to
change
and begin producing an output frequency for comparison this stage is called the
capture stage. The frequency comparison stops as soon as the output frequency is
adjusted to become equal to the input frequency. This stage is called the phase
locked state.
Now let us study in detail about the various parts of a PLL The phase detector,
Low Pass Filter and Voltage Controlled Oscillator.
4.4.4.10 Lecture -10
Phase Detector
This comparator circuit compares the input frequency and the VCO output
frequency and produces a dc voltage that is proportional to the phase difference
between the two frequencies. The phase detector used in PLL may be of analog or
digital type. Even though most of the monolithic PLL integrated circuits use analog
phase detectors, the majority of discrete phase detectors are of the digital type. One
of the most commonly used analog phase detector is the double balanced mixer
circuit. Some of the common digital type phase detectors are
Exclusive OR Phase Detector

An exclusive OR phase detector is shown in the figure below.
13 13
Fig.4.14 Exclusive-OR Phase Detector
It is obtained as a CMOS IC of type 4070. Both the frequencies are provided as an

input to the EX OR phase detector. Obeying the EX-OR concept the output
becomes HIGH only if either of the inputs fi or fo becomes HIGH. All other
conditions will produce a LOW output. Let us consider a waveform where the input
frequency leads the output frequency by degrees. That is, fi and fo has a phase
difference of degrees. The dc output voltage of the comparator will be a function
of the phase difference between its two inputs.
The figure shows the graph of DC output voltage as a function of the phase
difference between fi and fo. The output DC voltage is maximum when the phase
detector is 180.This type of phase detector is used when both fi and fo are square
waves.
14 14
Fig.4.15 Exclusive-OR Phase Detector-Waveform
Edge Triggered Phase Detector

Edge triggered phase detector is used when fi and fo are pulse waveforms with less
than 50% duty cycles. The figure of such a phase detector using an R-S Flip Flop is
shown below. Two NOR Gate (CD4001) are cross-coupled to form an R-S Flip
Flop. The output of the phase detector changes its logic state by triggering of the
R-S Flip Flop. That is, the output of the phase detector changes its logic state on the
positive
edge of the input fi and fo. The advantage of such a detector can be understood
from the graph below. It is clear that the DC output voltage is linear over 360.
4.4.4.11 Lecture 11
VCO (Voltage controlled oscillator).
Voltage controlled oscillator is a type of oscillator where the frequency of the

output oscillations can be varied by varying the amplitude of an input voltage
signal. Voltage controlled oscillators are commonly used in frequency (FM), pulse
(PM) modulators and phase locked loops (PLL). Another application of the voltage
controlled oscillator is the variable frequency signal generator itself. Block diagram
of a typical voltage controlled oscillator is shown below.
Fig.4.16 VCO
Voltage controlled oscillators can be broadly classified into linear voltage
controlled oscillators and relaxation type voltage controlled oscillators. Linear
voltage controlled oscillators are generally used to produce a sine wave. In such
oscillators an LC tank circuit is used for producing oscillations. An active element
like transistor is used for amplifying the output of the LC tank circuit,
compensating the energy lost in the tank circuit and for establishing the necessary
15 15
feedback conditions. Here a varactor (varicap) diode is used in place of the
capacitor in the tank circuit. Varactor diode is type of semiconductor diode whose
capacitance across the junction can be varied by varying the voltage across the
junction. Thus by varying the voltage across the varicap diode in the tank circuit,
the output frequency of the VCO can be varied.
Relaxation type voltage controlled oscillators are used to produce a saw tooth or
triangular waveform. This is achieved by the gradual charging and sudden
discharge of a capacitor connected appropriately to an active element (UJT, PUT
etc) or a
Monolithic IC (LM566 etc).Now a days relaxation type VCOs are generally

realized using monolithic ICs.
Voltage controlled oscillator using LM566 IC.
LM566 is a monolithic voltage controlled oscillator from National semiconductors.

It can be used to generate square and triangle waveforms simultaneously. The
frequency of the output waveform can be adjusted using an external control
voltage. The output frequency can be also programmed using a set of external
resistor and capacitor. Typical applications of LM566 IC are signal generators, FM
modulators, FSK modulators, tone generators etc. The LM566 IC can be operated
from a single supply or dual supply. While using single supply, the supply voltage
range is from 10V to 24V. The IC has a very linear modulation characteristic and
has excellent thermal stability. The circuit diagram of a voltage controlled oscillator
using LM566 is shown in the figure below.
16 16
Fig.4.17 VCO using IC566
Resistor R1 and capacitor C1 forms the timing components. Capacitor C2 is used to
prevent the parasitic oscillations during VCO switching. Resistor R3 is used to
provide the control voltage Vc. Triangle and square wave outputs are obtained from
pins 4 and 3 respectively.Output frequency of the VCO can be obtained using the
following equation:
Fout = 2.4(V+-V5) /(R1C1V+) . Where Fout is the output frequency, R1 and C1 are
the timing components and V+ is the supply voltage.
4.4.4.12 Lecture 12
Monolithic Phase Detectors

The monolithic type phase detector uses a CMOS type 4044 IC ,Which is highly
advantages as the harmonic sensitivity and duty cycle problems are neglected and
the circuit will be respond only to the transition in the input signals. This is the
most preferred phase detector in the critical applications as the phase error and the
output error voltage are independent of variations in the amplitude and duty cycles
of the input waveforms.
17 17
Low Pass Filter (LPF)
A Low Pass Filter (LPF) is used in Phase Locked Loops (PLL) to get rid of the high
frequency components in the output of the phase detector. It also removes the high
frequency noise. All these features make the LPF a critical part in PLL and helps
control the dynamic characteristics of the whole circuit. The dynamic
characteristics include capture and lock ranges, bandwidth, and transient response.
The lock range is the tracking range where the range of frequencies of the PLL
system follows the changes in the input frequency. The capture range is the range in
which the Phase Locker Loops attains the Phase Lock.
When the filter bandwidth is reduced, the response time increases .But this reduces
the capture range. But it also helps in reducing noise and in maintaining the locked
loop through momentary losses of signal. Two types of passive filter are used for
the LPF circuit in a PLL. An amplifier is used also with LPF to obtain gain. The
active filter used in PLL is shown below.
Voltage Controlled Oscillator (VCO)
The main function of the VCO is to generate an output frequency that is directly
proportional to the input voltage. The connection diagram of a SE/NE 566 VCO is
shown in the figure below. The macimum frequency of the VCO is 500 KHz.
This VCO provides simultaneous square wave and triangular wave outputs as a
function of the input voltage. The frequency of oscillation is determined by the
resistor R and capacitor C along with the voltage Vc applied to the control terminal.
Monolithic Phase Locked Loop
PLL is now readily available as ICs which were developed in the SE/NE 560
series. Some of the commonly used ones are the SE/NE 560,561,562,564,565 and
567.The difference between each one of them is in the different parameters like
operating frequency range, power supply requirements, and frequency and
bandwidth ranges. Out of all the series the SE/NE 565 is the most famous. It is
18 18
available as a 14-pin DIP and also as a 10-pin metal can package. The 14-pin DIP
and its characteristics are given below.
Monolithic PLL Characteristics

Operating frequency range: 0.001 Hz to 500 kHz.
Operating voltage range: 6 to 12 V.
Input impedance: 10 k Q typically.
Output sink current: 1mA typically.
Output source current: 10 m A typically.
Drift in VCO centre frequency with temperature: 300 ppm/ C typically.
Drift in VCO centre frequency with supply voltage: 1.5 %/V maximum.
Input level required for tracking: 10 mVrms minimum to 3 V peak-to-peak
maximum.
Bandwidth adjustment range: < 1 to > 60 %.
The block diagram and connection diagrams are shown in the figure below.
The block diagram consist of a phase detector which acts as a phase comparator, an
amplifier, and a low pass filter with the combination of the resistor (3.6 kilo ohm)
and capacitor C2. The output of the amplifier is fed back to the VCO. The different
pins representing that of the IC are also shown in the block diagram. Pins 1 and 10
are the positive and negative supply pins. The pins 2 and 3 are the input to the
phase detector.
The input signals are fed through these pins in differential mode. Pin 4 is the VCO
output and pin 5 is the phase comparator VCO input. If both these pins are shorted
the output of the VCO is supplied back to the phase comparator. The output of the
phase comparator is given to the amplifier. The amplifier has two outputs that goes
to the external pins as the demodulator output (pin 7) and the reference output (pin
6). An LPF circuit is formed by connecting the capacitor C2 between pin 7 and 10
with a resistor of value 3.6 kilo ohms. The value of C2 must be large enough to
eliminate the variations in demodulated output and stabilize the VCO frequency.
19 19
Pins 8 and 9 are used to connect the external resistor (R1) and external capacitor
(C1). The values of R1 and C1 help to adjust the free running frequency (fr) of the
PLL. Though the value of C1 can be anything, the value of resistor R1 must have a
value between 2 to 20 kilo ohms. All these factors can be used to determine the
center frequency of the PLL.
The free running frequency of the PLL is given as fr = (1.2)/(4R1C1) Hertz
The lock range of the PLL is given as fLock = (+/-){(8fr)/V} Hertz
The capture range of PLL is given as fc = (fLock/[2* 10^3*C2])^1/2
The lock range usually increases with an increase in input voltage but falls with an
increase in supply voltage.
4.4.4.13 Lecture-13
PLL Applications
Frequency Modulation (FM) stereo decoders, FM Demodulation networks

for FM operation.
Frequency synthesis that provides multiple of a reference signal frequency.
Used in motorspeed controls, tracking filters.
Used in frequency shift keying (FSK) decodes for demodulation carrier
frequencies.
Monolithic PLL IC 565 applications
The output from a PLL system can be obtained either as the voltage signal vc(t)
corresponding to the error voltage in the feedback loop, or as a frequency signal at
VCO output terminal. The voltage output is used in frequency discriminator

applications whereas the frequency output is used in signal conditioning, frequency
synthesis or clock recovery applications. Consider the case of voltage output. When
PLL is locked to an input frequency, the error voltage vc(t) is proportional to (fs-fo). If
the input frequency is varied as in the case of FM signal, vc will also vary in order to
20 20
maintain the lock. Thus the voltage output serves as a frequency discriminator which
converts the input frequency changes to voltage changes. In the case
of frequency output, if the input signal is comprised of many frequency components
corrupted with noise and other disturbances, the PLL can be made to lock, selectively
on one particular frequency component at the input. The output of VCO would then
regenerate that particular frequency (because of LPF which gives output for beat
frequency) and attenuate heavily other frequencies. VCO output thus can be used for
regenerating or reconditioning a desired frequency signal (which is weak and buried in
noise) out of many undesirable frequency signals. Some of the typical applications of
PLL are discussed below.
(i) Frequency Multiplier:
Frequency divider is inserted between the VCO & phase comparator. Since the output
of the divider is locked to the fIN, VCO is actually running at a multiple of the input
frequency. The desired amount of multiplication can be obtained by selecting a proper
divide-by- N network, where N is an integer.
21 21
Fig.4.18 PLL IC565
(ii) Frequency Shift Keying (FSK) demodulator:
In computer peripheral & radio (wireless) communication the binary data or code is
transmitted by means of a carrier frequency that is shifted between two preset
frequencies. Since a carrier frequency is shifted between two preset frequencies, the
data transmission is said to use a FSK. The frequency corresponding to logic 1 &
logic 0 states are commonly called the mark & space frequency. For example, When
transmitting teletype writer information using a modulator-demodulator (modem) a
1070-1270 (mark-space) pair represents the originate signal, while a 2025-2225 Hz
(mark-space) pair represents the answer signal.
Fig.4.19 as an FSK Demodulator
Frequency multiplication/division:
The block diagram shown below shows a frequency multiplier/divider using PLL. A
divide by N network is inserter between the VCO output and the phase comparator
input. In the locked state, the VCO output frequency fo is given by fo = Nfs. The
multiplication factor can be obtained by selecting a proper scaling factor N of the
counter.
Frequency multiplication can also be obtained by using PLL in its harmonic locking
22 22
mode. If the input signal is rich in harmonics e.g. square wave, pulse train etc., then
the VCO can be directly locked to the n-th harmonic of the input signal without
connecting any frequency divider in between. However, as the amplitude of the higher
order harmonics becomes less, effective locking may not take place for high values of
n. Typically n is kept less than 10. The circuit of the figure above can also be used for
frequency division. Since the VCO output (a square wave) is rich in harmonics, it is
possible to lock the m-th harmonic of the VCO output with the input signal fs. The
output fo of VCO is now given by fo=fs/m
Fig.4.20 Frequency multiplication/division
PLL Frequency Synthesis:
In digital wireless communication systems (GSM, CDMA etc), PLL's are used to
provide the Local Oscillator (LO) for up-conversion during transmission, and
down-conversion during reception. In most cellular handsets this function has
been largely integrated into a single integrated circuit to reduce the cost and size of
the handset. However due to the high performance required of base station
terminals, the transmission and reception circuits are built with discrete
components to achieve the levels of performance required. GSM LO modules are
typically built with a Frequency Synthesizer integrated circuit and discrete
resonator VCO's. Frequency Synthesizer manufacturers include Analog Devices,
National Semiconductor and Texas Instruments. VCO manufacturers include
23 23
Sirenza, Z-Communications, Inc. (Z- COMM).
Fig.4.21 PLL synthesizer
The key to the ability of a frequency synthesizer to generate multiple frequencies

is the divider placed between the output and the feedback input. This is usually in
the form of a digital counter, with the output signal acting as a clock signal. The
counter is preset to some initial count value, and counts down at each cycle of the
clock signal. When it reaches zero, the counter output changes state and the count
value is reloaded. This circuit is straightforward to implement using flip-flops, and
because it is digital in nature, is very easy to interface to other digital components
or a microprocessor. This allows the frequency output by the synthesizer to be
easily controlled by a digital system.
TUTORIAL
a. Fill in the blanks type of questions <Minimum of ten>

b. Multiple choice questions <Minimum of ten>
c. True or False questions <Minimum of ten>
NA
24 24
a. Objective type of questions(Very short notes) <Minimum of ten>

b. Analytical type questions <Minimum of ten>
c. Essay type Questions <As per requirements>
d. Problems <As per required Number>
e. Case study <As per required Number>
NA
4.1.7 Skill Building Exercises/Assignments
Eg:- -Prepare a model of something

-Trace something
-Prepare a report on something etc.,
1. Draw the functional diagram of monostable multivibrator using 555 timer.
Explain the operation using relevant waveforms.
2. Discuss the application of PLL
as (a)Frequency Translator
(b) AM demodulator
3. Draw the diagram of Schmitt trigger using 555 timer. Explain the operation
using relevant waveforms.
4. Explain the operation of PLL using a block schematic. Also explain the terms
Lock-in range, capture range, pull-in time.
5. Give the block diagram of IC566 VCO and explain the operation.
6. Discuss the applications of VCO in detail.
7. Applying 555 timer explain PWM generation using relevant block diagrams
and waveforms.
8. Explain Astable multivibrator circuit using 555. Also derive expression for time
25 25
period.
9. List the applications of PLL. Explain any two applications of PLL in detail.
10. Draw the diagram of Schmitt trigger using 555 timer. Explain the operation
using relevant waveforms.
1. a) Draw the functional diagram of monostable multi vibrator using 555 timer.
Explain the operation using relevant waveforms.
b) Discuss the application of PLL as a frequency translator.
2. (a) Draw the block diagram of a 565 PLL and explain its salient features. Derive the
expression for capture range.
(b) Explain the application of PLL as a frequency translator.
3. (a)Design an astable multivibrator using 555 Timer to operate at 10 KHz with 40%
duty cycle.
(b)With a suitable circuit diagram using NE 565 PLL IC, explain the implementation of
a frequency translation.
NA
4.1.10 Interview questions (which are frequently asked in a

Technical round - Placements)
NA
NA
26 26
NA
NA
NA
T1. Op-amps and Linear Integrated Circuits --- Ramakant A

Gaykwad
27 27
4.5 Unit V ACTIVE FILTERS
4.5.1 Syllabus
Introduction, Butter worth filters 1st order, 2nd order LPF, HPF filters. Band pass, Band reject
and All pass filters. Four Quadrant multiplier, balanced modulator, IC1496,Applications of
analog switches and MultipSample & Hold amplifiers

- Types of filters
- Difference between active & passive filters
- Design of filters using op-amps

Student designing gets knowledge on different types of filters.
4.5.4 Unit Lecture Plan:
28 28
Lecture Topic Methodology Quick reference
no.
4.5.5 1. Butter worth filters Chalk & Board T2: Ch-7 Pg. T
1st order, 2nd order No. 264-268 e
LPF a
2. HPF, Band pass Chalk & Board T2: Ch-7
Filters Pg. No. 271-276 c
3. Band reject and All Chalk & Board T2: Ch-7 h
pass filters Pg. No. 277-281 i
4. TUTORIAL
5. Four Quadrant Chalk & Board T2: Ch-4 n
multiplier Pg. No. 159-161 g
6. Balanced modulator, Chalk & Board www.onsemi.com/pub/Collate
IC1496 ral/MC1496-D.PDF
7. Applications of Chalk & Board www.analog.com/media/en/tr
analog switches and aining-seminars/tutorials/MT-
Multiplexers 088.pdf
8. Sample & Hold Chalk & Board T2: Ch-4
amplifiers Pg. No. 153
9. TUTORIAL
Material / Teaching Aids as per above lecture plan
4.5.5.1 Lecture-1
First Order Low Pass Filter:
Fig.5.1 1st Order LPF

This first-order low pass active filter consists simply of a passive RC filter stage
providing a low frequency path to the input of a non-inverting operational amplifier.
The amplifier is configured as a voltage-follower (Buffer) giving it a DC gain of
one, Av = +1 or unity gain as opposed to the previous passive RC filter which has a
DC gain of less than unity.
29 29
The advantage of this configuration is that the op-amps high input impedance
prevents excessive loading on the filters output while its low output impedance
prevents the filters cut-off frequency point from being affected by changes in the
impedance of the load.
While this configuration provides good stability to the filter, its main disadvantage is
that it has no voltage gain above one. However, although the voltage gain is unity the
power gain is very high as its output impedance is much lower than its input
impedance. If a voltage gain greater than one is required we can use the following
filter circuit.
Active Low Pass Filter with Amplification
Fig.5.2 Active LPF with Amplifier

The frequency response of the circuit will be the same as that for the passive RC
filter, except that the amplitude of the output is increased by the pass band gain, A F of
the amplifier. For a non-inverting amplifier circuit, the magnitude of the voltage gain
for the filter is given as a function of the feedback resistor ( R 2 ) divided by its
corresponding input resistor ( R1 ) value and is given as:
DC gain =
30 30
Therefore, the gain of an active low pass filter as a function of frequency will be:
Gain of a first-order low pass filter
Where:
AF = the pass band gain of the filter, (1 + R2/R1) = the frequency of the input
signal in Hertz, (Hz)
c = the cut-off frequency in Hertz, (Hz)
Thus, the operation of a low pass active filter can be verified from the frequency gain
equation above as:
1. At very low frequencies, <
2. At the cut-off frequency, = c
3. At very high frequencies, >
Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high
frequency cut-off point,C. At C the gain is 0.707AF, and after C it decreases at a
constant rate as the frequency increases. That is, when the frequency is increased
tenfold (one decade), the voltage gain is divided by 10.
In other words, the gain decreases 20dB (= 20log 10) each time the frequency is
increased by 10. When dealing with filter circuits the magnitude of the pass band gain
of the circuit is generally expressed indecibels or dB as a function of the voltage gain,
and this is defined as:
Magnitude of Voltage Gain in (dB)

31 31
Second-order Low Pass Active Filter
As with the passive filter, a first-order low-pass active filter can be converted into a
second-order low pass filter simply by using an additional RC network in the input
path. The frequency response of the second-order low pass filter is identical to that of
the first-order type except that the stop band roll-off will be twice the first-order
filters at 40dB/decade (12dB/octave). Therefore, the design steps required of the
second-order active low pass filter are the same.
Second-order Active Low Pass Filter Circuit
Fig.5.3 2nd Order Active LPF
When cascading together filter circuits to form higher-order filters, the overall gain of
the filter is equal to the product of each stage. For example, the gain of one stage may
be 10 and the gain of the second stage may be 32 and the gain of a third stage may be
32 32
100. Then the overall gain will be 32,000, (10 x 32 x 100) as shown below.
4.5.5.2 Lecture-2
First Order High Pass Filter

Fig.5.4 1st Order HPF
Technically, there is no such thing as an active high pass filter. Unlike Filters which
have an infinite frequency response, the maximum pass band frequency response of
an active high pass filter is limited by the open-loop characteristics or bandwidth of
the operational amplifier being used, making them appear as if they are band pass
filters with a high frequency cut-off determined by the selection of op-amp and gain.
In the Operational Amplifier tutorial we saw that the maximum frequency response of
an op-amp is limited to the Gain/Bandwidth product or open loop voltage gain ( A V )
of the operational amplifier being used giving it a bandwidth limitation, where the
closed loop response of the op amp intersects the open loop response.
A commonly available operational amplifier such as the uA741 has a typical open-
loop (without any feedback) DC voltage gain of about 100dB maximum reducing at
a roll off rate of -20dB/Decade (-6db/Octave) as the input frequency increases. The
gain of the uA741 reduces until it reaches unity gain, (0dB) or its transition
frequency ( t ) which is about 1MHz. This causes the op-amp to have a frequency
response curve very similar to that of a first-order low pass filter and this is shown
below.
33 33
Fig.5.5 Frequency response curve of a typical Operational Amplifier
Then the performance of a high pass filter at high frequencies is limited by this
unity gain crossover frequency which determines the overall bandwidth of the open-
loop amplifier. The gain-bandwidth product of the op-amp starts from around 100kHz
for small signal amplifiers up to about 1GHz for high-speed digital video amplifiers
and op-amp based active filters can achieve very good accuracy and performance
provided that low tolerance resistors and capacitors are used.
Under normal circumstances the maximum pass band required for a closed loop
active high pass or band pass filter is well below that of the maximum open-loop
transition frequency. However, when designing active filter circuits it is important to
choose the correct op-amp for the circuit as the loss of high frequency signals may
result in signal distortion.
Active High Pass Filter
A first-order (single-pole) Active High Pass Filter as its name implies, attenuates
low frequencies and passes high frequency signals. It consists simply of a passive
filter section followed by a non-inverting operational amplifier. The frequency
response of the circuit is the same as that of the passive filter, except that the
amplitude of the signal is increased by the gain of the amplifier and for a non-
inverting amplifier the value of the pass band voltage gain is given as 1 + R2/R1, the
same as for the low pass filter circuit.
Active High Pass Filter with Amplification

34 34
Fig.5.6 Active HPF with Amplifier
This first-order high pass filter consists simply of a passive filter followed by a non-
inverting amplifier. The frequency response of the circuit is the same as that of the
passive filter, except that the amplitude of the signal is increased by the gain of the
amplifier.
For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is
given as a function of the feedback resistor ( R2 ) divided by its corresponding input
resistor ( R1 ) value and is given as:
Gain for an Active High Pass Filter
Where:
AF = the Pass band Gain of the filter,
= the Frequency of the Input Signal in Hertz, (Hz) c = the Cut-off Frequency in
Hertz, (Hz)
Just like the low pass filter, the operation of a high pass active filter can be verified
from the frequency gain equation above as:
35 35
Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the low
frequency cut-off point, C at 20dB/decade as the frequency increases. At C the gain
is 0.707AF, and after C all frequencies are pass band frequencies so the filter has a
constant gain AF with the highest frequency being determined by the closed loop
bandwidth of the op-amp.
When dealing with filter circuits the magnitude of the pass band gain of the circuit is
generally expressed in decibels or dB as a function of the voltage gain, and this is
defined as:
For a first-order filter the frequency response curve of the filter increases by
20dB/decade or 6dB/octave up to the determined cut-off frequency point which is
always at -3dB below the maximum gain value. As with the previous filter circuits,
the lower cut-off or corner frequency ( c ) can be found by using the same formula:
36 36
The corresponding phase angle or phase shift of the output signal is the same as that
given for the passive RC filter and leads that of the input signal. It is equal to +45o at
the cut-off frequency c value and is given as:
A simple first-order active high pass filter can also be made using an inverting
operational amplifier configuration as well, and an example of this circuit design is
given along with its corresponding frequency response curve. A gain of 40dB has
been assumed for the circuit.
Inverting Operational Amplifier Circuit
Fig.5.7 Inverting Op-amp
Frequency Response Curve
37 37
Fig.5.8 Frequency Response Curve
Second-order High Pass Active Filter
As with the passive filter, a first-order high pass active filter can be converted into a
second-order high pass filter simply by using an additional RC network in the input
path. The frequency response of the second-order high pass filter is identical to that of
the first-order type except that the stop band roll-off will be twice the first-order
filters at 40dB/decade (12dB/octave). Therefore, the design steps required of the
second-order active high pass filter are the same.
Second-order Active High Pass Filter Circuit
Fig.5.9 2nd Order Active HPF
Active Band Pass Filter Circuit
38 38
Fig.5.10 Active BPF
This cascading together of the individual low and high pass passive filters produces a
low Q-factor type filter circuit which has a wide pass band. The first stage of the
filter will be the high pass stage that uses the capacitor to block any DC biasing from
the source. This design has the advantage of producing a relatively flat asymmetrical
pass band frequency response with one half representing the low pass response and
the other half representing high pass response as shown.
Fig.5.11 Frequency Response of BPF

The higher corner point ( H ) as well as the lower corner frequency cut-off
point( L ) are calculated the same as before in the standard first-order low and high
pass filter circuits. Obviously, a reasonable separation is required between the two
cut-off points to prevent any interaction between the low pass and high pass stages.
The amplifier also provides isolation between the two stages and defines the overall
voltage gain of the circuit.
The bandwidth of the filter is therefore the difference between these upper and lower-
3dB points. For example, suppose we have a band pass filter whose -3dB cut-off
points are set at 200Hz and 600Hz. Then the bandwidth of the filter would be given
as: Bandwidth (BW) = 600 200 = 400Hz.
The normalized frequency response and phase shift for an active band pass filter will
be as follows.
39 39
Fig.5.12 Active Band Pass Frequency Response
While the above passive tuned filter circuit will work as a band pass filter, the pass
band (bandwidth) can be quite wide and this may be a problem if we want to isolate a
small band of frequencies. Active band pass filter can also be made using inverting
operational amplifier.
So by rearranging the positions of the resistors and capacitors within the filter we can
produce a much better filter circuit as shown below. For an active band pass filter, the
lower cut-off -3dB point is given by C1 while the upper cut-off -3dB point is given by
C2.
Inverting Band Pass Filter Circuit
40 40
Fig.5.13 Inverting BPF
This type of band pass filter is designed to have a much narrower pass band. The
centre frequency and bandwidth of the filter is related to the values of R1, R2,
C1 and C2. The output of the filter is again taken from the output of the op-amp.
4.5.5.3 Lecture-3
Band Reject filters:
The band pass filter passes one set of frequencies while rejecting all others. The band-
stop filter does just the opposite. It rejects a band of frequencies, while passing all
others. This is also called a band-reject or band-elimination filter. Like band pass
filters, band-stop filters may also be classified as (i) wide-band and (ii) narrow band
reject filters. The narrow band reject filter is also called a notch filter. Because of its
higher Q, which exceeds 10, the bandwidth of the narrow band reject filter is much
smaller than that of a wide band reject filter.
Wide Band-Stop (or Reject) Filter
41 41
Fig.5.14 Wide band stop filter
A wide band-stop filter using a low-pass filter, a high-pass filter and a summing
amplifier is shown in figure. For a proper band reject response, the low cut-off
frequency fL of high-pass filter must be larger than the high cut-off frequency fH of
the low-pass filter. In addition, the pass band gain of both the high-pass and low-
pass sections must be equal.
Narrow Band-Stop Filter
Fig.5.15 Narrow Band-Stop Filter
Fig.5.16 Narrow Band-Stop Filter Response
network illustrated in Fig.5.16 . This is a passive filter composed of two T-shaped

networks. One T-network is made up of two resistors and a capacitor, while the other
is made of two capacitors and a resistor. One drawback of above notch filter (passive
twin-T network) is that it has relatively low figure of merit Q. However, Q of the
network can be increased significantly if it is used with the voltage follower, as
illustrated in fig. (a). Here the output of the voltage follower is supplied back to the
junction of R/2 and 2 C. The frequency response of the active notch filter is shown
in fig (b).
42 42
Fig.5.17 Frequency Response of Narrow Band-Stop Filter
Notch filters are most commonly used in communications and biomedical

instruments for eliminating the undesired frequencies.
A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a
phase angle, shown in fig. (b). Again, there is a frequency f c at which the phase shift
is equal to 0. In fig. (c), the voltage gain is equal to 1 at low and high frequencies.
In between, there is a frequency fc at which voltage gain drops to zero. Thus such a
filter notches out, or blocks frequencies near fc. The frequency at which maximum
attenuation occurs is called the notch-out frequency given by
Notice that two upper capacitors are C while the capacitor in the centre of the
network is 2 C. Similarly, the two lower resistors are R but the resistor in the centre
of the network is 1/2 R. This relationship must always be maintained.
All pass filters:
An all-pass filter is that which passes all frequency components of the input signal
without attenuation but provides predictable phase shifts for different frequencies of
the input signals. The all-pass filters are also called delay equalizers or phase
correctors. An all-pass filter with the output lagging behind the input is illustrated in
figure.
43 43
Fig. 5.18 All Pass Filter
The output voltage Vout of the filter circuit shown in Fig .5.18 can be obtained by
using the superposition theorem.
Where f is the frequency of the input signal in Hz.
From equations given above it is obvious that the amplitude of vout / vin is unity, that is
|Vout | = |Vin| throughout the useful frequency range and the phase shift between the
input and output voltages is a function of frequency
By interchanging the positions of R and C in the circuit shown in fig. (a), the output
can be made leading the input. These filters are most commonly used in
communications. For instance, when signals are transmitted over transmission lines
(such as telephone wires) from one point to another point, they undergo change in
phase. To compensate for such phase changes, all-pass filters are employed
44 44
a) Fill in the blanks type of questions

1) This circuit is known as a ________ filter, and the fc is ________( high-
pass, 15.9 kHz)
2) Filters with the ________ characteristic are used for filtering pulse
waveforms.( Bessel)
3) Which filter exhibits a linear phase characteristic(Bessel)
4) The critical frequency is defined as the point at which the response
drops ________ from the passband(3 dB)
5) Filters with the ________ characteristic provide a very flat amplitude in
the passband and a roll-off rate of 20 dB/decade/pole.( Butterworth)
6) Which filter exhibits the most rapid roll-off rate(Chebyshev)
7) Which filter has a maximally flat response(Butterworth)
8) Identify the frequency response curve for a high-pass filter (b)
45 45
9) A ________ filter rejects all frequencies within a specified band and
passes all those outside this band.( band-stop)
10) A ________ filter significantly attenuates all frequencies below fc and
passes all frequencies above fc(high-pass)
b) True or False questions

1) A band-pass filter can be created by cascading a high-pass filter and a low-
pass filter(T).
2) The bandwidth of a band-pass filter is the sum of the two cutoff
frequencies(F).
3) A Sallen-Key filter is a second-order filter(T).
4) Filters with Bessel characteristics are used for filtering pulse
waveforms(T).
5) Filters with Bessel characteristics are used for filtering pulse waveforms(F).
6) Filters with Bessel characteristics are used for filtering pulse
waveforms(T).
7) A band-pass filter passes all frequencies within a band between a lower and
an upper cut-off frequency(T)
8) An active filter uses capacitors and inductors in the feedback network(F).
9) A second-order filter has a roll-off of 20 dB/decade(F)
c) Multiple choice questions
1) Which filter performs exactly the opposite to the band-pass filter?

a) Band-reject filter
b) Band-stop filter
c) Band-elimination filter
d) All of the mentioned
2) Given the lower and higher cut-off frequency of a band-pass filter are 2.5kHz
and 10kHz. Determine its bandwidth.
a) 750 Hz
b) 7500 Hz
c) 75000 Hz
3) In which filter the output and input voltages are equal in amplitude for all
frequencies?
a) All-pass filter
b) High pass filter
c) Low pass filter
46 46
4) The gain of the first order low pass filter

a) Increases at the rate 20dB/decade
b) Increases at the rate 40dB/decade
c) Decreases at the rate 20dB/decade
d) Decreases at the rate 40dB/decade
5) Which among the following has the best stop band response?
a) Butterworth filter
b) Chebyshev filter
c) Cauer filter
6) the order of filter used, when the gain increases at the rate of 60dB/decade
on the stop band.
a) Second-order low pass filter
b) Third-order High pass filter
c) First-order low pass filter
7) Name the filter that has two stop bands?

a) Band-pass filter
b) Low pass filter
c) High pass filter
d) Band-reject filter
8) The frequency response of the filter in the stop band.

i. Decreases with increase in frequency
ii. Increase with increase in frequency
iii. Decreases with decrease in frequency
iv. Increases with decrease in frequency
a) i and iv
b) ii and iii
c) i and ii
d) ii and iv

1) Define the term roll of rate?
2) What is the gain of 1st order Butterworth low pass filter?
3) Draw the frequency response of 3rd order Butterworth low pass
filter?
47 47
1) This filter has a roll-off rate of
2) This is a ________ filter, and it has a cutoff frequency of ________
3) A low-pass filter has a cutoff frequency of 1.23 kHz. Determine the

bandwidth of the filter ?
C) Essay type Questions

1) Derive the gain for 1st order butterworth low pass filter?
2) Derive the gain and magnitude for all pass filter?
3) Draw and explain the expression for sallen and key high
pass filter?
D) Problems
1) Form the the given figure. RA = 2.2 k and RB = 1.2 k . This
filter is probably a
48 48
E) Case study
NA

-Trace something
1. Draw the functional diagram of monostable multivibrator using 555 timer. Explain the
operation using relevant waveforms.
2. Discuss the application of PLL as (a)Frequency Translator
(b) AM demodulator
3. Draw the diagram of Schmitt trigger using 555 timer. Explain the operation using
relevant waveforms.
4. Explain the operation of PLL using a block schematic. Also explain the terms Lock-in
range, capture range, pull-in time.
49 49
5 Give the block diagram of IC566 VCO and explain the operation.
6 Discuss the applications of VCO in detail.
7 Applying 555 timer explain PWM generation using relevant block diagrams and
waveforms.
8 Explain Astable multivibrator circuit using 555. Also derive expression for time
period.
9 List the applications of PLL. Explain any two applications of PLL in detail.
10 Draw the diagram of Schmitt trigger using 555 timer. Explain the operation using
relevant waveforms.
1. a) Draw the functional diagram of monostable multi vibrator using 555 timer. Explain
the operation using relevant waveforms.
b) Discuss the application of PLL as a frequency translator.
2. (a) Draw the block diagram of a 565 PLL and explain its salient features. Derive the
expression for capture range.
(b) Explain the application of PLL as a frequency translator.
3. (a)Design an astable multivibrator using 555 Timer to operate at 10 KHz with 40% duty
cycle.
(b)With a suitable circuit diagram using NE 565 PLL IC, explain the implementation of a
frequency translation.
50 50
NA
4.5.11
Interview questions (which are frequently asked in a Technical round - Placements)
NA
4.5.12
Real-Word (Live) Examples / Case studies wherever applicable
NA
4.5.13
Suggested Expert Guest Lectures (both from in and outside of the campus)
51 51
NA
4.5.14
Literature references of Relevant NPTEL Videos/Web/You Tube videos etc.
NA
NA

4.6 Unit VI DIGITAL TO ANALOG & ANALOG TO DIGITAL CONVERTERS

4.6.1 Syllabus
Introduction, basic DAC techniques, weighted resistor DAC, R-2R ladder DAC, inverted R-2R
DAC, and IC 1408 DAC, Different types of ADCs parallel Comparator type ADC, counter
type ADC, successive approximation ADC and dual slope ADC.DAC and ADC Specifications,
Specifications AD 574 (12 bit ADC)

- Purpose of DACs and ADCs

- Design of different types of DACs
160
- Design of different types of ADCs
4.6.3 Unit Outcomes
- Student will understand the purpose of ADCs and DACs.

- Student will be able to analyze different types of DACs and ADCs.
Lecture no. Topic Methodology Quick reference

54. Introduction, DAC and ADC Presentation T2: Ch-10
Specifications Pg.No.348, 366
55. Weighted resistor DAC Presentation T2: Ch-10
Pg.No.349-351
56. R-2R ladder DAC Presentation T2: Ch-10
Pg.No.352-353
57. Inverted R-2R DAC, and IC Presentation T2: Ch-10
1408 DAC Pg.No.353-354
58. TUTORIAL
59. Counter type ADC Presentation T2: Ch-10
Pg.No.360-361
60. Successive approximation Presentation T2: Ch-10
ADC Pg.No.361-363
61. Parallel Comparator type Presentation T2: Ch-10
ADC Pg.No.358-359
62. Dual slope ADC Presentation T2: Ch-10
Pg.No.363-365
63. Specifications AD 574 (12 Presentation T2: Ch-10
bit ADC) Pg.No.367
64. TUTORIAL
4.6.5 Teaching Material / Teaching Aids as per above lecture plan

4.6.5.1 Lecture-1
DAC.ppt
4.6.5.2 Lecture-2
161
DAC.ppt
Binary-Weighted Resistor DAC
The binary-weighted-resistor DAC employs the characteristics of the inverting summer
Op Amp circuit. In this type of DAC, the output voltage is the inverted sum of all the
input voltages. If the input resistor values are set to multiples of two: 1R, 2R and 4R, the
output voltage would be equal to the sum of V1, V2/2 and V3/4. V1 corresponds to
Fig.6.1 Binary weighted resistor network
the most significant bit (MSB) while V3 corresponds to the least significant bit
(LSB).The circuit for a 4-bit DAC using binary weighted resistor network is shown
Fig.6.2 4-bit DAC using binary weighted resistor network
below .The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The
value, 0, represents an open switch while 1 represents a closed switch. The operational
amplifier is used as a summing amplifier, which gives a weighted sum of the binary
input based on the voltage, Vref. For a 4-bit DAC, the relationship between Vout and the
binary input is as follows:
162
The negative sign associated with the analog output is due to the connection to a
summing amplifier, which is a polarity-inverting amplifier. When a signal is applied to
the latter type of amplifier, the polarity of the signal is reversed (i.e. a + input
becomes -, or vice versa). For a n-bit DAC, the relationship between Vout and the
binary input is as follows:
4.6.5.3 Lecture-3
DAC.ppt
163
Fig.6.3: R-2R ladder network
Vref is nothing but the input binary value reference voltage, that is for
binary 1, Vref=5V and for binary 0, Vref=0V.
For 0001 only D0=Vref, all other inputs are at 0V and can be treated as ground.
So finally Vref/16 volt is appearing as the input to op amp. This value gets
multiplied by the gain of op amp circuit (Rf/Ri).
If we proceed in this manner (Thevenin equivalent reduction), we will get
Note that you can build a DAC with any number of bits you want, by simply
enlarging the resistor network, by adding more R-2R resistor branches.
In this circuit the 7493 IC simply provides digital inputs to DAC. It is a
counter IC and not an integral part of the DAC circuit. You can apply any
combinations of binary inputs to D3D2D1D0
4.6.5.4 Lecture-4
164
Inverted R-2R ladder DAC
Fig.6.4: Inverted R-2R ladder DAC
4.6.5.5 Lecture-5
ADC.ppt
Counter Type ADC (Analog to Digital Converter)
The Counter type ADC is the basic type of ADC which is also called as digital ramp
type ADC or stair case approximation ADC. This circuit consists of N bit counter,
DAC and Op-amp comparator as shown in below figure.
Operation of counter type ADC

Counter type ADC or Digital
The N bit counter generates
Ramp antypen bit digital output which is applied as an input to the
165
DAC. The analog output corresponding to the digital input from DAC is compared with
the input analog voltage using an opamp comparator. The opamp compares the two
voltages and if the generated DAC voltage is less, it generates a high pulse to the N bit
counter as a clock pulse to increment the counter. The same process will be repeated
until the DAC output equals to the input analog voltage.
If the DAC output voltage is equal to the input analog voltage, then it generates low
clock pulse and it also generates a clear signal to the counter and load signal to the
storage resistor to store the corresponding digital bits. These digital values are closely
matched with the input analog values with small quantization error.
For every sampling interval the DAC output follows a ramp fashion so that it is called
as Digital ramp type ADC. And this ramp looks like stair cases for every sampling time
so that it is also called as staircase approximation type ADC.
Fig.6.5: Counter type ADC
Conversion time of Counter type ADC

Conversion time of ADC is the time taken by the ADC to convert the input sampled
analog value to digital value. Here the maximum conversion of high input voltage for a
N bit ADC is the clock pulses required to the counter to count its maximum count value.
So The maximum conversion of Counter type ADC is = (2 N-1) T Where, T is the time
period of clock pulse.
If N=2 bit then the Tmax = 3T.
By observing the above conversion time of Counter type ADC it is illustrated that the
166
sampling period of Counter type ADC should be as shown below.
Ts >= (2N-1) T
Advantages of Counter type ADC
Simple to understand and operate.
Cost is less because of less complexity in design.
Disadvantages or limitations of Counter type of ADC
Speed is less because every time the counter has to start from ZERO.
There may be clash or aliasing effect if the next input is sampled before
completion of one operation.
4.6.5.6 Lecture 6
TUTORIAL
4.6.5.7 Lecture 7
ADC.ppt
Successive Approximation ADC
method of addressing the digital ramp ADCs shortcomings is the so- called
successive-approximation ADC. The only change in this design is a very special counter
circuit known as a successive-approximation register. Instead of counting up in binary
sequence, this register counts by trying all values of bits starting with the most-
significant bit One and finishing at the least-significant bit. Throughout the count
process, the register monitors the comparators output to see if the binary count is less
than or greater than the
analog signal input, adjusting the bit values accordingly. The way the register counts is
identical to the trial-and-fit method of decimal-to-binary conversion, whereby
167
different values of bits are tried from MSB to LSB to get a binary number that equals
the original decimal number. The advantage to this counting strategy is much faster
results: the DAC output converges on the analog signal input in much larger steps than
with the 0-to-full count sequence of a regular counter.
Fig.6.6: Successive Approximation ADC
Without showing the inner workings of the successive-approximation register (SAR),
the circuit looks like this:
It should be noted that the SAR is generally capable of outputting the binary number in
serial (one bit at a time) format, thus eliminating the need for a shift register. Plotted
over time, the operation of a successive-approximation ADC looks like this:
Note how the updates for this ADC occur at regular intervals, unlike the digital ramp
ADC circuit
168
4.6.5.8 Lecture 8
ADC.ppt
Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique
reference voltage. The comparator outputs connect to the inputs of a priority encoder
circuit, which then produces a binary output. The following illustration shows a 3-bit
Fig.6.7: Flash ADC
ADC circuit:
Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds
the reference voltage at each comparator, the comparator outputs will sequentially
saturate to a high state. The priority encoder generates a binary number based on the
highest-order active input, ignoring all other active inputs.
When operated, the flash ADC produces an output that looks something like this:
169
For this particular application, a regular priority encoder with all its inherent complexity
isnt necessary. Due to the nature of the sequential comparator output states (each
comparator saturating high in sequence from lowest to highest), the same highest-
order-input selection effect may be realized through a set of Exclusive-OR gates,
allowing the use of a simpler, non-priority encoder:
Fig.6.8 Flash type ADC

And, of can be made from a matrix of diodes, demonstrating just how simply this
converter design may be constructed course, the encoder circuit itself:
170
Fig.6.9: Flash ADC with internal circuit of 8 to 3 encoder
Not only is the flash converter the simplest in terms of operational theory, but it is the
most efficient of the ADC technologies in terms of speed, being limited only in
comparator and gate propagation delays. Unfortunately, it is the most component-
intensive for any given number of output bits. This three-bit flash ADC requires seven
comparators. A four-bit version would require 15 comparators. With each additional
output bit, the number of required comparators doubles. Considering that eight bits is
generally considered the minimum necessary for any practical ADC (255 comparators
needed), the flash methodology quickly shows its weakness.
An additional advantage of the flash converter, often overlooked, is the ability for it to
produce a non-linear output. With equal-value resistors in the reference voltage divider
network, each successive binary count represents the same amount of analog signal
increase, providing a proportional response. For special applications, however, the
resistor values in the divider network may be made non-equal. This gives the ADC a
custom, nonlinear response to the analog input signal. No other ADC design is able to
grant this signal-conditioning behavior with just a few component value changes.
4.6.5.9 Lecture 9
171
ADC.ppt
Slope (integrating) ADC
So far, weve only been able to escape the sheer volume of components in the flash
converter by using a DAC as part of our ADC circuitry. However, this is not our only
option. It is possible to avoid using a DAC if we substitute an analog ramping circuit
and a digital counter with precise timing. The is the basic idea behind the so-called
single-slope, or integrating ADC. Instead of using a DAC with a ramped output,
we use an op-amp circuit called an integrator to generate a sawtooth waveform
which is then compared against the analog input by a comparator. The time it takes for
the sawtooth waveform to exceed the input signal voltage level is measured by means of
a digital counter clocked with a precise-frequency square wave (usually from a crystal
oscillator). The basic schematic diagram is shown here:
The IGFET capacitor-discharging transistor scheme shown here is a bit oversimplified.
In reality, a latching circuit timed with the clock signal would most likely have to be
connected to the IGFET gate to ensure full discharge of the capacitor when the
comparators output goes high. The basic idea, however, is evident in this diagram.
When the comparator output is low (input voltage greater than integrator output), the
integrator is allowed to charge the capacitor in a linear fashion. Meanwhile, the counter
is counting up at a rate fixed by the precision clock frequency. The time it takes for the
capacitor to charge up to the same voltage level as the input depends on the input signal
level and the combination of - Vref, R, and C. When the capacitor reaches that voltage
level, the comparator output goes high, loading the counters output into the shift
register for a final output. The IGFET is triggered on by the comparators high output,
discharging the capacitor back to zero volts. When the integrator output voltage falls to
zero, the comparator output switches back to a low state, clearing the counter and
enabling the integrator to ramp up voltage again.
172
This ADC circuit behaves very much like the digital ramp ADC, except that the
comparator reference voltage is a smooth sawtooth waveform rather than a
stairstep:
The single-slope ADC suffers all the disadvantages of the digital ramp ADC, with the
added drawback of calibration drift. The accurate correspondence of this ADCs output
with its input is dependent on the voltage slope of the integrator being matched to the
counting rate of the counter (the clock frequency). With the digital ramp ADC, the clock
frequency had no effect on conversion accuracy, only on update time. In this circuit,
since the rate of integration and the rate of count are independent of each other,
variation between the two is inevitable as it ages, and will result in a loss of accuracy.
The only good thing to say about this circuit is that it avoids the use of a DAC, which
reduces circuit complexity.
An answer to this calibration drift dilemma is found in a design variation called the
dual-slope converter. In the dual-slope converter, an integrator circuit is driven positive
and negative in alternating cycles to ramp down and then up, rather than being reset to 0
volts at the end of every cycle. In one direction of ramping, the integrator is driven by
the positive analog input signal (producing a negative, variable rate of output voltage
change, or output slope) for a fixed amount of time, as measured by a counter with a
precision frequency clock. Then, in the other direction, with a fixed reference voltage
173
(producing a fixed rate of output voltage change) with time measured by the same
counter. The counter stops counting when the integrators output reaches the same
voltage as it was when it started the fixed- time portion of the cycle. The amount of time
it takes for the integrators capacitor to discharge back to its original output voltage, as
measured by the magnitude accrued by the counter, becomes the digital output of the
ADC circuit.
The dual-slope method can be thought of analogously in terms of a rotary spring such
as that used in a mechanical clock mechanism. Imagine we were building a
mechanism to measure the rotary speed of a shaft. Thus, shaft speed is our input
signal to be measured by this device. The measurement cycle begins with the spring
in a relaxed state. The spring is then turned, or wound up, by the rotating shaft
(input signal) for a fixed amount of time. This places the spring in a certain amount of
tension proportional to the shaft speed: a greater shaft speed corresponds to a faster
rate of winding. and a greater amount of spring tension accumulated over that period
of time. After that, the spring is uncoupled from the shaft and allowed to unwind at a
fixed rate, the time for it to unwind back to a relaxed state measured by a timer
device. The amount of time it takes for the spring to unwind at that fixed rate will be
directly proportional to the speed at which it was wound (input signal magnitude)
during the fixed-time portion of the cycle.
This technique of analog-to-digital conversion escapes the calibration drift problem of
the single-slope ADC because both the integrators integration coefficient (or gain)
and the counters rate of speed are in effect during the entire winding and
unwinding cycle portions. If the counters clock speed were to suddenly increase,
this would shorten the fixed time period where the integrator winds up (resulting in
a lesser voltage accumulated by the integrator), but it would also mean that it would
count faster during the period of time when the integrator was allowed to unwind at
a fixed rate. The proportion that the counter is counting faster will be the same
proportion as the integrators accumulated voltage is diminished from before the
clock speed change. Thus, the clock speed error would cancel itself out and the digital
output would be exactly what it should be.
174
Another important advantage of this method is that the input signal becomes averaged
as it drives the integrator during the fixed-time portion of the cycle. Any changes in the
analog signal during that period of time have a cumulative effect on the digital output at
the end of that cycle. Other ADC strategies merely capture the analog signal level at a
single point in time every cycle. If the analog signal is noisy (contains significant
levels of spurious voltage spikes/dips), one of the other ADC converter technologies
may occasionally convert a spike or dip because it captures the signal repeatedly at a
single point in time. A dual-slope ADC, on the other hand, averages together all the
spikes and dips within the integration period, thus providing an output with greater
noise immunity. Dual-slope ADCs are used in applications demanding high accuracy.
4.6.5.10 Lecture 10
ADC.ppt
4.6.5.11
TUTORIAL
4.6.6
a. Multiple choice questions
1.Find out the resolution of 8 bit DAC/ADC?

a) 562
b) 625
c) 256
d) 265
2.Non-linearity in the output of converter is expressed in

a) none of the mentioned
b) Percentage of reference voltage
c) Percentage of resolution
d) Percentage of full scale voltage
3. A binary input 000 is fed to a 3bit DAC/ADC. The resultant output is 101. Find
the type of error?
a) Settling error
b) Gain error
175
c) Offset error
d) Linearity error
4.How many equal intervals are present in a 14-bit D-A converter?

a) 16383
b) 4095
c) 65535
d) 1023
5. Resolution of a 6 bit DAC can be stated as

a) All of the mentioned
b) 6-bit resolution
c) Resolution of 1.568% of full scale d)
Resolution of 1 part in 63
6. Find the resolution of a 10-bit AD converter for an input range of 10v?
a) 97.7mv
b)9.77mv
c) 0.977mv
d) 977mv
7. A good converter exhibits a linearity error a) Less than or equal to (1/2) LSB
b) Greater than equal to (1/2) LSB

c)Greater than or equal to (1/2) LSB
b) none of the mentioned
8. The maximum deviation between actual and ideal converter output after the removal of
error is
a)Absolute accuracy
b)Relativeaccuray
c) Relative /absolute accuracy
d) Linearity
9. A monotonic DAC is one whose analog output increases for

a) Decreases in digital input
b) An increases in analog input
c) An increases in digital input
d) Decreases in analog input
10.Ina flash analog-to-digital converter, the output of each comparator is connected
to an input of a:
a) Decoder
176
b) Priority encoder
c) Multiplixer
d) demultiplixer
11. Which is not an analog-to-digital (ADC) conversion error?

a) Differential nonlinearity
b) Missing code
c) Incorrect code
d) Offset
12. Sample-and-hold circuits in analog-to digital converters (ADCs)
177
a) Sample and hold output off the binary counter during the conversion process
b) Stabilize the comparators threshold voltage during the conversion process
c) Stabilize the input analog signal during the conversion process
d) Sample and hold the D/A converter staircase waveform during the conversion process
178
b) True Or False
1)A sample-and-hold circuit samples an analog value and holds it long enough for the
analog-to-digital conversion to occur.(T)
2)Incorrect codes are a form of output error for a digital-to-analog converter (DAC).(F)
3)A digital-to-analog converter (DAC) is said to be nonmonotonic if the magnitude of
the output voltage increases every time the input code increases(F)
4)The relative accuracy of a digital-to-analog converter (DAC) is determined by settling
time.(F)
5)The key advantage of the successive approximation analog-to-digital converter
(ADC) is its conversion speed(T)
6)One way to determine the resolution of a digital-to-analog converter (DAC) is to
compare the ratio of one step voltage to the maximum output voltage(T)
7)In a binary-weighted digital-to-analog converter (DAC), the values of the input
resistors are chosen to be proportional to the binary weights of the corresponding input
bits(F)
8)An 8-bit digital-to-analog converter (DAC) has a resolution of 0.125 V(F)
c) Fill in the Blanks
1) _______ analog-to-digital converters (ADCs) use no clock signal, because there is no
timing or sequencing required.(FLASH)
2) ______ analog-to-digital converters (ADCs) have a fixed value of conversion time
that is not dependent on the value of the analog input(Successive approximation)
3) The problems of the binary-weighted resistor digital-to-analog converter (DAC) can
be overcome by using ___________(an R/2R ladder DAC)
4) The number of binary bits at the input of a digital-to-analog converter (DAC) is
known as ________(resolution)
5) A(n) ________ converts an analog input to a digital output.( ADC)
6) The characteristic that a change of one binary step on the input of a digital-to-analog
converter (DAC) should cause exactly one step change on the output is called
________.(monotonicity)
179
7) Inaccurate analog-to-digital conversion may be due to ____________. (faulty
sample-and-hold circuitry)
8) A binary-weighted resistor used in a digital-to-analog converter (DAC) is only
practical up to a resolution of ________(4 bits)

a) Objective type of questions
1) Draw the block diagram of DAC?
2) Classifications of DAC?
3) Explain types of ADC?
b) Analytical type questions
1) Explain the limitation of binary-weighted digital-to-analog converters?
2) A binary-weighted digital-to-analog converter has an input resistor of 100 k
. If the resistor is connected to a 5 V source, the current through the
resistor is ?
3) A binary-weighted digital-to-analog converter has a feedback resistor, Rf, of
12 k. If 50 A of current is through the resistor, the voltage out of the
circuit is
c) Essay type Questions
1) Explain 3-bit binary weighted Resistor
2) Explain the classification of DAC and explain inverted R-2R ladder circuit?
d) Problems
1) A given 4-bit digital to analog converter has a reference voltage of 15 volts
and a binary inout of 0101. What is the proportionality factor?
2) Consider the following 3-bit ADC. Draw the conversion transfer function
(binary output vs input voltage) on the top graph. Draw the quantization
error transfer function (error voltage vs input voltage) on the bottom graph.
Make sure the transition points are clear. Assume Vref is 5V
3) Assume you have a 3-bit SAR ADC. The analog input is 0.65 V and the Vref
is 1V. Show how the SAR would approximate the analog input over three
cycles. Label the cycles on the x-axis and show the approximation as a
meandering stair-step line on the graph.
e) Case study NA

-Trace something
180
Assignment-6
1. Explain the operation of Flash ADC using relevant diagrams.
2. Compare and contrast Flash, dual slope, SAR type of ADCs.
3. Explain the operation of weighted resistor DAC with the help of relevant diagrams
and sketches.
4. Explain the operation of dual slope ADC.
5. Explain the various sources of errors in DAC.
6. Explain the counter type A/D converter in detail.
7. Discuss various DAC/ADC specifications.
8. Describe the operation of SAR type ADC.
9. Explain in detail with a neat circuit diagram the operation of a parallel comparator
type analog to digital converter.
10. Explain the following characteristics of ADC: resolution, accuracy, settling time,
linearity, conversion time.
1. a) Explain the operation of Flash ADC using relevant diagrams.

a) A dual slope ADC uses a 18-bit counter with a 5mHz clock. The maximum input
voltage is+12 V and the maximum integrator output voltage at 2N count is -10 V. If R=
100K_, find the size of the capacitor to be used for integrator.
2(a) A dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The maximum input
voltage is +10V. The maximum integrator output voltage should be -8 V when the counter
has cycled through 2n counts. The capacitor used in the integrator is 0.1F. Find the value
of the resistor R of the integrator. If the analog signal voltage is +4.129 V, find the
equivalent digital number.
(b)Explain the working of successive approximation type converter and compare the
conversion times of tracking and successive approximation type ADCs.
3. a) List and compare different types of analog to digital converters.
(b) Explain the operation of successive approximation type ADC with neat circuit
181
diagram.
NA
4.6.11 Interview questions (which are frequently asked in a Technical round -

Placements)
NA
NA
NA
NA
NA

182
5. Reference text books/web material etc.,

Made Easy Ies Writtem Material
6. Mid question Papers/Scheme Of Valuation

MID-1{Set-1}
1. Describe the AC analysis to the DIBO Diff. Amp. to find the parameters Ad, Ri and Ro?
2. Define the terms Input Offset Voltage, Input Bias current? Design a circuit to
compensate the input bias current in Op-amp?
3. What is an instrumentation amplifier? Draw a Three op-amp DC instrumentation
amplifier and derive the expression for its output?
{set-2}
a) Draw the internal block diagram of Op-amp and explain about each block ?
b) i)Explain the term Slew rate and how it effects the frequency response of an op-amp?
ii) An Op-amp has a Slew rate of 2V/Sec. What is the maximum frequency of an output signal
peak value 5V at which the distortion sets in due to the Slew rate limitation?
183
c) Explain the operation of a precision Full wave rectifier using relevant equivalent
circuits?
MID-2{set-1}
Calculate the gain and cutoff frequency for low-pass sallenkey circuit?
Derive the output voltage for 110 using R-2R ladder DAC technique?
Design a second order Butterworth LPF for a cutoff frequency
2.5KHz,C=25nf,R1=10K, and sketch the frequency response?
{set-2}
a) Derive the transfer function for all pass filter?
b) Derive the expression for 3-bit weighted resistor DAC technique an calculate output
voltage for input data 110 ?
c) Caluclte the bandwidth for narrow band pass filter?
7. Fast track material for Back-Log students
OPERATION AMPLIFIER
An operational amplifier is a direct coupled high gain amplifier consisting of one or

more differential amplifiers, followed by a level translator and an output stage.
It is a versatile device that can be used to amplify ac as well as dc input signals
& designed for computing mathematical functions such as addition, subtraction
,multiplication, integration & differentiation
Ideal characteristics of OPAMP
1. Open loop gain infinite
2. Input impedance infinite
3. Output impedance low
4. Bandwidth infinite
5. Zero offset, ie, Vo=0 when V1=V2=0
DC characteristics
Input offset current The difference between the bias currents at the input terminals
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of the op- amp is called as input offset current. The input terminals conduct a small
value of dc current to bias the input transistors. Since the input transistors cannot be
made identical, there exists a difference in bias currents.
Input offset voltage

A s m a l l voltage applied to the input terminals to make the output voltage as zero
when the two input terminals are grounded is called input offset voltage.
THERMAL DRIFT
Bias current, offset current and offset voltage change with temperature. A circuit
o o
carefully nulled at 25 c may not remain so when the temperature rises to 35 c. This is
called drift.
AC characteristics Slew Rate
The slew rate is defined as the maximum rate of change of output voltage
caused by a step input voltage.
An ideal slew rate is infinite which means that op-amps output voltage
should change instantaneously in response to
input step voltage
Need for frequency compensation in practical op-amps
Frequency compensation is needed when large

bandwidth and lower closed loop gain is desired.
Compensating networks are used to control the phase shift and hence to
improve the stability
Instrumentation Amplifier
In a number of industrial and consumer applications, the measurement of physical
quantities is usually done with the help of transducers. The output of transducer has
to be amplified So that it can drive the indicator or display system. This function is
performed by an instrumentation amplifier.
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Features of instrumentation amplifier
1. high gain accuracy

2. high CMRR
3. high gain stability with low temperature co-efficient
4. low dc offset
5. low output impedance
Differential amplifier
This circuit amplifies only the difference between the two inputs. In this circuit there
are two resistors labeled R Which means that their values are equal. The differential
IN
amplifier amplifies the difference of two inputs while the differentiator amplifies the
slope of an input.
Comparator
A comparator is a circuit which compares a signal voltage applied at one input of an
op- amp with a known reference voltage at the other input. It is an open loop op - amp
with output + Vsat.
Schmitt trigger
Schmitt trigger is a regenerative comparator. It converts sinusoidal
input into a square wave output. The output of
Schmitt trigger swings between upper and lower threshold
voltages, which are the reference voltages of
the input waveform. Multivibrator
Multivibrators are a group of regenerative circuit that are used extensively in
timing applications. It is a wave shaping circuit which gives symmetric or
asymmetric square output. It has two states stable or quasi- stable depending on the type
of multivibrator.
Monostable multivibrator
Monostable multivibrator is one which generates a single pulse of specified duration
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in response to each external trigger signal. It has only one stable state.
Application of a trigger causes a change to the quasi-stable state.An external
trigger signal generated due to charging and discharging of the capacitor produces the
transition to the original stable state.
Astable multivibrator Astable multivibrator is a free running oscillator having two

quasi- stable states. Thus there are oscillations between these two states and no
external signal is required to produce the change in state.
Bistable multivibrator
Bistable multivibrator is one that maintains a give output voltage level
unless an external trigger is applied . Application of an external trigger signal causes a
change of state, and this output level is maintained indefinitely until an second
trigger is Applied. Thus, it requires two external triggers before it returns to its initial
state.
Filter Filter is frequency selective circuit that pass signal of specified Band of
frequencies and attenuates the signals of frequencies outside the band.
Passive filters
Passive filters works well for high frequencies But at audio frequencies, the
inductors become problematic, as they become large, heavy and expensive.For
low frequency applications, more number of turns of wire must be used which in
turn adds to the series resistance degrading inductors performance ie, low Q,
resulting in high power dissipation.
Active filters
Active filters used op-amp as the element and resistors and capacitors as passive
elements by enclosing a capacitor in the feed back loop , inductor less active filters
can be obtained.
Classification of ADCs
1. Direct type ADC.
2. Integrating type ADC
Direct type ADCs
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1. Flash (comparator) type converter 2.Counter type converter 3.Tracking or servo
converter.
4.Successive approximation type converter
Sample and hold circuit
A sample and hold circuit is one which samples an input signal and holds on to its last
sampled value until the input is sampled again. This circuit is mainly used in digital
interfacing, analog to digital systems, and pulse code modulation systems.
188
7 Sample Question Papers with solutions
Question Paper-1
1.(a) Present the detailed AC analysis of dual-input balanced output configuration.
(b) Explain the properties of single ended input balanced output differential amplifier.
AC analysis of dual-input balanced output configuration:
To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the
ac equivalent circuit is drawn using r-parameters as shown in fig. 3. The dc voltages are
reduced to zero and the ac equivalent of CE configuration is used.
equal and designated by r'e . This voltage across each collector resistance is shown 180
out of phase with respect to the input voltages v1 and v2. This is same as in CE
configuration. The polarity of the output voltage is shown in Figure. The collector C2 is
assumed to be more positive with respect to collector C1 even though both are negative
with respect to ground. Applying KVL in two loops 1 & 2.
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Again, assuming RS1 / and RS2 / are very small in comparison with RE and
re' and therefore neglecting these terms,
189
Thus a differential amplifier amplifies the difference between two input signals.
Defining the difference of input signals as vd = v1 ? v2 the voltage gain of the dual
input balanced output differential amplifier can be given by
Differential Input Resistance:
Differential input resistance is defined as the equivalent resistance that would be

measured at either input terminal with the other terminal grounded. This means that the
input resistance Ri1 seen from the input signal source v1 is determined with the signal
source v2 set at zero. Similarly, the input signal v1 is set at zero to determine the input
resistance Ri2 seen from the input signal source v2. Resistance RS1 and RS2 are
ignored because they are very small.
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Output Resistance:
Output resistance is defined as the equivalent resistance that would be measured at

output terminal with respect to ground. Therefore, the output resistance RO1 measured
between collector C1 and ground is equal to that of the collector resistance RC.
Similarly the output resistance RO2 measured at C2 with respect to ground is equal to
that of the collector resistor RC.
The current gain of the differential amplifier is undefined. Like CE amplifier the
differential amplifier is a small signal amplifier. It is generally used as a voltage
amplifier and not as current or power amplifier.
191
Single Ended Input Balanced Output Differential Amplifier:
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the magnitude of VEE. The two +VCC and VEE supply terminals are made common
because they are same. The two emitters are also connected and the parallel
combination of RE1 and RE2 is replaced by a resistance RE. The input signal v1 is
applied at the base of Q1. The output voltage is taken between two collectors.
2 (a) Draw the pin diagram and schematic symbol of a typical op-amp IC741 and
(b) List out the characteristics of ideal op-amp. Explain the concept of virtual short in
op- amp.
Two input terminals: inverting input terminal ( ) and noninverting input terminal
(+)
One output terminal

193
Two dc power supplies V + and V -
Other terminals for frequency compensation and offset nulling
Differential-input single-ended-output amplifier
Infinite input impedance i1 = i2 = 0 (regardless of the input voltage)
Zero output impedance vO= A(v2v1) (regardless of the load)
Infinite open-loop differential gain
Infinite common-mode rejection
Infinite bandwidth
194
Features of 741 IC
5. No external frequency compensation is required. It also does not need any
195
3.a) Write ideal and practical specifications of 741 op-amps.
(b) Define thermal drift and PSRR.
Input offset voltage is the voltage that is applied between the two input terminals of the
op-amp to null the output. The figure is show below.
196
In the figure V1 and V2 are the input dc voltages are Ra represents the resistance applied.
The input offset voltage Vio could have a positive value or a negative value. Therefore,
its absolute value is listed in the datasheet. It is always better to have smaller values of
input offset voltage and this indicates that the input terminals are matched better.
Lowest values are 15uV for an ideal precision op-amp and the maximum value if 6mV
dc.
Input Offset Current is the algebraic difference between the currents into the inverting
and non- inverting terminals.
Input Offset Current, Iio = |Ib1 Ib2| Ib1 Non-inverting input current Ib2 Inverting
input current
The maximum input offset current value for 741 IC is 200nA. This value decreases as
the matching between the two input terminals is improved and may reduce down to
almost 6nA.
Drift
The dependence of operational amplifier (op-amps) parameters with temperature which

affects its behavior/performance is specified as op-amp thermal drift. There can be
changes in op-amp bias currents, input offset voltage and input offset current with
temperature as given in the
manufacturers data sheet of specific op-amp. For precision applications many zero drift
(with temperature) operational amplifiers are available.
200
Supply Voltage Rejection Ratio (SVRR)
The change in the op-amps offset voltage caused by variations in supply voltage is called
SVRR. The change in supply voltage can be denoted by dV and the corresponding
change in input offset voltage can be denoted by dVio.
SVRR = Change in input offset voltage (dVio) / Change in supply voltage (dV) For 741
IC, SVRR = 150uV/V.
The lower the value of SVRR, the better will be the op-amp performance.
What are the important features of an instrumentation amplifier and also draw the
diagram of an instrumentation amplifier and explain.
4. Draw the diagram of a second order low pass filter and obtain the expression for
transfer function, write the expression for cut-off frequency.
Second-order Low Pass Active Filter

As with the passive filter, a first-order low-pass active filter can be converted into a
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second-order low pass filter simply by using an additional RC network in the input path.
The frequency response of the second-order low pass filter is identical to that of the
first-order type except that the stop band roll-off will be twice the first-order filters at
40dB/decade (12dB/octave). Therefore, the design steps required of the second-order
active low pass filter are the same.
Second-order Active Low Pass Filter Circuit
Fig. 2nd Order Active LPF
When cascading together filter circuits to form higher-order filters, the overall gain of
the filter is equal to the product of each stage. For example, the gain of one stage may
be 10 and the gain of the second stage may be 32 and the gain of a third stage may be
100. Then the overall gain will be 32,000, (10 x 32 x 100).
5.Draw the diagram of Schmitt trigger using 555 timer. Explain the operation using
relevant waveforms.
Schmitt Trigger
The high and low transitions on the inputs of most of the CMOS devices should be fast
edges. If the edges are not fast enough, they tend to provide more current and this might
damage the device. Analog signals are generally not perfect and might not have clean
edges all the times. Schmitt Trigger is a special type of comparator that is used to avoid
such signals.
202
A comparator is a device that compares two voltages and the outcome is the indication
of whether one voltage is higher than the other or not. Schmitt trigger, also called as
Regenerative Comparator, compares the input voltage to two reference voltages and
produces an equivalent output. The output of a Schmitt trigger is always a square or
rectangular wave irrespective of the shape of the input. It is often used when we need to
do the following:
To convert slow edges (like in a triangular wave) into fast edges (like a square
wave)
trigger built from a 555 timer is inverting but the discussion will be for non-inverting.
203
Pins 4 and 8 are connected to the supply (VCC). The pins 2 and 6 are tied together and
the input is given to this common point through a capacitor C. this common point is
supplied with an external bias voltage of VCC / 2 with the help of the voltage divider
circuit formed by the resistors R1 and R2.
Schmitt trigger is high if the input voltage is greater than the upper threshold value and
the output of the Schmitt trigger is low if the input voltage is lower than the lower
threshold value.
The output retains its value when the input is between the two threshold values. The
usage of two threshold values is called Hysteresis and the Schmitt trigger acts as a
memory element (a bistable multivibrator or a flip-flop).
The threshold values in this case are 2/3 VCC and 1/3 VCC i.e. the upper comparator
trips at 2/3 VCC and the lower comparator trips at 1/3 VCC. The input voltage is
compared to these threshold values by the individual comparators and the flip-flop is
SET or RESET accordingly. Based on this the output becomes high or low.
When a sine wave of amplitude greater than VCC / 6 is applied at the input, the flip-flop
is set and reset alternately for the positive cycle and the negative cycle. The output is a
square wave and the waveforms for input sine wave and output square wave are shown
below.
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Fig.5.6 Waveforms of Schmitt Trigger
6. List the applications of PLL. Explain any two applications of PLL in detail.
Monolithic PLL IC 565 applications

The output from a PLL system can be obtained either as the voltage signal v c(t)
corresponding to the error voltage in the feedback loop, or as a frequency signal at VCO
output terminal. The voltage output is used in frequency discriminator applications
whereas the frequency output is used in signal conditioning, frequency synthesis or
clock recovery applications. Consider the case of voltage output. When PLL is locked to
an input frequency, the error voltage vc(t) is proportional to (fs-fo). If the input
frequency is varied as in the case of FM signal, vc will also vary in order to maintain the
lock. Thus the voltage output serves as a frequency discriminator which converts the
input frequency changes to voltage changes. In the case of frequency output, if the input
signal is comprised of many frequency components corrupted with noise and other
disturbances, the PLL can be made to lock, selectively on one particular frequency
component at the input. The output of VCO would then regenerate that particular
frequency (because of LPF which gives output for beat frequency) and attenuate heavily
other frequencies. VCO output thus can be used for regenerating or reconditioning a
desired frequency signal (which is weak and buried in noise) out of many undesirable
frequency signals. Some of the typical applications of PLL are discussed below.
(i) Frequency Multiplier:
Frequency divider is inserted between the VCO & phase comparator. Since the output of
the divider is locked to the fIN, VCO is actually running at a multiple of the input
frequency. The desired amount of multiplication can be obtained by selecting a proper
divide-by-N network, where N is an integer.
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(i) Frequency Shift Keying (FSK) demodulator:
In computer peripheral & radio (wireless) communication the binary data or code is
transmitted by means of a carrier frequency that is shifted between two preset
frequencies. Since a carrier frequency is shifted between two preset frequencies, the
data transmission is said to use a FSK. The frequency corresponding to logic 1 & logic
0 states are commonly called the mark & space frequency. For example, When
transmitting teletype writer information using a modulator-demodulator (modem) a
1070-1270 (mark-space) pair represents the originate signal, while a 2025-2225 Hz
(mark-space) pair represents the answer signal.
FSK Generator:
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The FSK generator is formed by using a 555 as an astable multivibrator, whose frequency
is controlled by the state of transistor Q1. In other words, the output frequency of the
FSK generator depends on the logic state of the digital data input. 150 Hz is one the
standards frequencies at which the data are commonly transmitted. When the input is
logic 1, the transistor Q1 is off. Under the condition, 555 timer works in its
normal mode as an astable multivibrator i.e., capacitor C charges through RA & RB to
2/3 Vcc & discharges through RB to 1/3 Vcc. Thus capacitor C charges & discharges
between 2/3 Vcc & 1/3 Vcc as long as the input is logic 1. The frequency of the
output waveform is given by,
When the input is logic 0, (Q1 is ON saturated) which in turn connects the resistance Rc across RA.
This action reduces the charging time of capacitor C1 increases the output frequency, which is given
by,
By proper selection of resistance Rc, this frequency is adjusted to equal the space
frequency of 1270 Hz. The difference between the FSK signals of 1070 Hz & 1270 Hz is
200 Hz, this difference is called frequency shift. The output 150 Hz can be made by
connecting a voltage comparator between the output of the ladder filter and pin 6 of
PLL. The VCO frequency is adjusted with R1 so that at fIN = 1070 Hz.
FSK Demodulator:
The output of 555 FSK generators is applied to the 565 FSK demodulator.
Capacitive coupling is used at the input to remove dc line. At the input of 565, the
loop locks to the input frequency & tracks it between the 2 frequencies. R1 & C1
determine the free running frequency of the VCO, 3 stage RC ladder filter is used to
remove the carrier component from the output. In digital data communication and
computer peripheral, binary data is transmitted by means of a carrier frequency which is
207
shifted between two preset frequencies. This type of data transmission is called frequency
shift keying (FSK) technique. The binary data can be retrieved using FSK demodulator.
The figure below shows FSK demodulator using PLL for tele-typewriter signals of 1070
Hz and 1270 Hz. As the signal appears at the input, the loop locks to the input frequency
and tracks it between the two frequencies with a corresponding dc shift at the output. A
three stage filter removes the carrier component and the output signal is made logic
compatible by a voltage comparator.
7. a) Design an astable multivibrator with 50 % duty cycle using 555 timer.

b) Derive the expression for Time period of an astable multivibrator using 555 timer.
Ans: Astable 555 Oscillator Circuit:
Fig.4.5 Astable Multivibrator with Waveforms

In the 555 Oscillator circuit above, pin 2 and pin 6 are connected together allowing
the circuit to re-trigger itself on each and every cycle allowing it to operate as a free
running oscillator. During each cycle capacitor, C charges up through both timing
resistors, R1 and R2 but discharges itself only through resistor, R2 as the other side
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of R2 is connected to the discharge terminal, pin 7.
Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is
determined by the0.693(R1+R2)C combination and discharges itself down to 1/3Vcc
(the lower comparator limit) determined by the 0.693(R2.C) combination. This results
in an output waveform whose voltage level is approximately equal to Vcc 1.5V and
whose output ON and OFF time periods are determined by the capacitor and
resistors combinations. The individual times required to complete one charge and
discharge cycle of the output is therefore given as:
Astable 555 Oscillator Charge and Discharge Times
Where, R is in s and C in Farads.
When connected as an astable multivibrator, the output from the 555 Oscillator will
continue indefinitely charging and discharging between 2/3Vcc and 1/3Vcc until the
power supply is removed. As with the monostable multivibrator these charge and
discharge times and therefore the frequency are independent on the supply voltage.
The duration of one full timing cycle is therefore equal to the sum of the two
individual times that the capacitor charges and discharges added together and is given
as:
555 Oscillator Cycle Time
The output frequency of oscillations can be found by inverting the equation above for
the total cycle time giving a final equation for the output frequency of an Astable 555
Oscillator as:
555 Oscillator Frequency Equation
209
By altering the time constant of just one of the RC combinations, the Duty Cycle
better known as the Mark-to-Space ratio of the output waveform can be accurately
set and is given as the ratio of resistor R2 to resistor R1. The Duty Cycle for the 555
Oscillator, which is the ratio of the ON time divided by the OFF time is given by:
555 Oscillator Duty Cycle
The duty cycle has no units as it is a ratio but can be expressed as a percentage ( % ).
If both timing resistors, R1 and R2 are equal in value, then the output duty cycle will
be 2:1 that is, 66% ON time and 33% OFF time with respect to the period.
8.a) Design and explain the operation of first order wide band pass filter with its
characteristics?
b) Design and explain the operation of All Pass Filter with its characteristics?
Ans: All pass filters:
An all-pass filter is that which passes all frequency components of the input signal
without attenuation but provides predictable phase shifts for different frequencies of
the input signals. The all-pass filters are also called delay equalizers or phase
correctors. An all-pass filter with the output lagging behind the input is illustrated in
figure.
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Fig. 5.18 All Pass Filter
The output voltage Vout of the filter circuit shown in Fig .5.18 can be obtained by using
the superposition theorem.
Where f is the frequency of the input signal in Hz.
From equations given above it is obvious that the amplitude of v out / vin is unity, that is |
Vout | = |Vin| throughout the useful frequency range and the phase shift between the input
and output voltages is a function of frequency
By interchanging the positions of R and C in the circuit shown in fig. (a), the output can
be made leading the input. These filters are most commonly used in communications.
For instance, when signals are transmitted over transmission lines (such as telephone
wires) from one point to another point, they undergo change in phase. To compensate
for such phase changes, all-pass filters are employed
b)Ans: Active Band Pass Filter Circuit
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Fig.5.10 Active BPF
This cascading together of the individual low and high pass passive filters produces a
low Q-factor type filter circuit which has a wide pass band. The first stage of the filter
will be the high pass stage that uses the capacitor to block any DC biasing from the
source. This design has the advantage of producing a relatively flat asymmetrical
pass band frequency response with one half representing the low pass response and the
other half representing high pass response as shown.
Fig.5.11 Frequency Response of BPF

The higher corner point ( H ) as well as the lower corner frequency cut-off point( L )
are calculated the same as before in the standard first-order low and high pass filter
circuits. Obviously, a reasonable separation is required between the two cut-off points to
prevent any interaction between the low pass and high pass stages. The amplifier also
provides isolation between the two stages and defines the overall voltage gain of the
circuit.
The bandwidth of the filter is therefore the difference between these upper and lower-
3dB points. For example, suppose we have a band pass filter whose -3dB cut-off points
are set at 200Hz and 600Hz. Then the bandwidth of the filter would be given as:
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Bandwidth (BW) = 600 200 = 400Hz.
The normalized frequency response and phase shift for an active band pass filter will be
as follows.
Fig.5.12 Active Band Pass Frequency Response
While the above passive tuned filter circuit will work as a band pass filter, the pass band
(bandwidth) can be quite wide and this may be a problem if we want to isolate a small
band of frequencies. Active band pass filter can also be made using inverting
operational amplifier.
So by rearranging the positions of the resistors and capacitors within the filter we can
produce a much better filter circuit as shown below. For an active band pass filter, the
lower cut-off -3dB point is given by C1 while the upper cut-off -3dB point is given by
C2.
Question Paper-2
213
1. a) How many comparators are required to build an n bit flash type A/D converter?
b) Explain a R-2R Ladder type D/A converter.
Ans: Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique
reference voltage. The comparator outputs connect to the inputs of a priority encoder
circuit, which then produces a binary output. The following illustration shows a 3-bit
Fig.6.7: Flash ADC
ADC circuit:
Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds the
reference voltage at each comparator, the comparator outputs will sequentially saturate to
a high state. The priority encoder generates a binary number based on the highest-order
active input, ignoring all other active inputs.
When operated, the flash ADC produces an output that looks something like this:
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For this particular application, a regular priority encoder with all its inherent complexity
isnt necessary. Due to the nature of the sequential comparator output states (each
comparator saturating high in sequence from lowest to highest), the same highest-
order-input selection effect may be realized through a set of Exclusive-OR gates,
allowing the use of a simpler, non-priority encoder:
Fig.6.8 Flash type ADC

And, of can be made from a matrix of diodes, demonstrating just how simply this
converter design may be constructed course, the encoder circuit itself:
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Fig.6.9: Flash ADC with internal circuit of 8 to 3 encoder
Not only is the flash converter the simplest in terms of operational theory, but it is the
most efficient of the ADC technologies in terms of speed, being limited only in
comparator and gate propagation delays. Unfortunately, it is the most component-
intensive for any given number of output bits. This three-bit flash ADC requires seven
comparators. A four-bit version would require 15 comparators. With each additional
output bit, the number of required comparators doubles. Considering that eight bits is
generally considered the minimum necessary for any practical ADC (255 comparators
needed), the flash methodology quickly shows its weakness.
An additional advantage of the flash converter, often overlooked, is the ability for it to
produce a non-linear output. With equal-value resistors in the reference voltage divider
network, each successive binary count represents the same amount of analog signal
increase, providing a proportional response. For special applications, however, the resistor
values in the divider network may be made non-equal. This gives the ADC a custom,
nonlinear response to the analog input signal. No other ADC design is able to grant this
signal-conditioning behavior with just a few component value changes.
b)ans:
216
Fig.6.3: R-2R ladder network
Vref is nothing but the input binary value reference voltage, that is for
binary 1, Vref=5V and for binary 0, Vref=0V.
For 0001 only D0=Vref, all other inputs are at 0V and can be treated as ground. So
finally Vref/16 volt is appearing as the input to op amp. This value gets multiplied
by the gain of op amp circuit (Rf/Ri).
If we proceed in this manner (Thevenin equivalent reduction), we will get
Note that you can build a DAC with any number of bits you want, by simply
enlarging the resistor network, by adding more R-2R resistor branches.
In this circuit the 7493 IC simply provides digital inputs to DAC. It is a counter
IC and not an integral part of the DAC circuit. You can apply any combinations
of binary inputs to D3D2D1D0
217
Inverted R-2R ladder DAC
Fig.6.4: Inverted R-2R ladder DAC
2.a)Discuss the 555 timer in monostable operation. Also discuss the applications for it.
b) Explain about PLL and draw its Block diagram?
Ans: Monostable 555 Timer
The operation and output of the 555 timer monostable is exactly the same as that for
the transistorized one we look at previously in the Monostable Multivibrators tutorial.
The difference this time is that the two transistors have been replaced by the 555
timer device. It has one stable state and other is quasi state and requires one external
triggering to change its state from low to high state, and to automatically it reaches to
its original stable state after some period of time which is called Pulse duration
Consider the 555 timer monostable circuit below.
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Fig.4.8 Monostable Multivibrator using IC555
When a negative ( 0V ) pulse is applied to the trigger input (pin 2) of the Monostable
configured 555 Timer oscillator, the internal comparator, (comparator No1) detects
this input and sets the state of the flip-flop, changing the output from a LOW
state to a HIGH state. This action in turn turns OFF the discharge transistor
connected to pin 7, thereby removing the short circuit across the external timing
capacitor, C1.
This action allows the timing capacitor to start to charge up through resistor, R1 until
the voltage across the capacitor reaches the threshold (pin 6) voltage of 2/3Vcc set up
by the internal voltage divider network. At this point the comparators output goes
HIGH and resets the flip-flop back to its original state which in turn turns ON
the transistor and discharges the capacitor to ground through pin 7. This causes the
output to change its state back to the original stable LOW value awaiting another
trigger pulse to start the timing process over again. Then as before, the Monostable
Multivibrator has only ONE stable state.
219
The Monostable 555 Timer circuit triggers on a negative-going pulse applied to pin
2 and this trigger pulse must be much shorter than the output pulse width allowing
time for the timing capacitor to charge and then discharge fully. Once triggered, the
555 Monostable will remain in this HIGH unstable output state until the time
period set up by the R1 x C1 network has elapsed. The amount of time that the output
voltage remains HIGH or at a logic 1 level, is given by the following time
constant equation.
Where, t is in seconds, R is in s and C in Farads.

b)Ans: The concept of Phase Locked Loops (PLL) first emerged in the early
1930s.But the technology was not developed as it now, the cost factor for developing
this technology was very high. Since the advancement in the field of integrated
circuits, PLL has become one of the main building blocks in the electronics
technology. In present, the PLL is available as a single IC in the SE/NE560 series
(560, 561, 562, 564, 565 and 567) to further reduce the buying cost, the discrete ICs
are used to construct a PLL.
PLL Block Diagram
The block diagram of a basic PLL is shown in the figure below. It is basically a flip
flop consisting of a phase detector, a low pass filter (LPF),and a Voltage Controlled
Oscillator (VCO).
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Fig.4.13 Block Diagram - Phase Locked Loops
The input signal Vi with an input frequency fi is passed through a phase detector. A
phase detector basically a comparator which compares the input frequency fi with the
feedback frequency fo .The phase detector provides an output error voltage Ver
(=fi+fo),which is a DC voltage. This DC voltage is then passed on to an LPF. The
LPF removes the high frequency noise and produces a steady DC level, Vf (=Fi-Fo).
Vf also represents the dynamic characteristics of the PLL.
The DC level is then passed on to a VCO. The output frequency of the VCO (fo) is
directly proportional to the input signal. Both the input frequency and output
frequency are compared and adjusted through feedback loops until the output
frequency equals the input frequency. Thus the PLL works in these stages free-
running, capture and phase lock.
As the name suggests, the free running stage refer to the stage when there is no input
voltage applied. As soon as the input frequency is applied the VCO starts to change
and begin producing an output frequency for comparison this stage is called the
capture stage. The frequency comparison stops as soon as the output frequency is
adjusted to become equal to the input frequency. This stage is called the phase locked
state.
Now let us study in detail about the various parts of a PLL The phase detector, Low
Pass Filter and Voltage Controlled Oscillator.
3. Draw the functional diagram of a dual slope integrating type ADC and also obtain
expression for the output voltage.
Ans: ADC.ppt
Slope (integrating) ADC
So far, weve only been able to escape the sheer volume of components in the flash
converter by using a DAC as part of our ADC circuitry. However, this is not our only
221
option. It is possible to avoid using a DAC if we substitute an analog ramping circuit and a
digital counter with precise timing. The is the basic idea behind the so-called single-slope,
or integrating ADC. Instead of using a DAC with a ramped output, we use an op-
amp circuit called an integrator to generate a sawtooth waveform which is then
compared against the analog input by a comparator. The time it takes for the sawtooth
waveform to exceed the input signal voltage level is measured by means of a digital
counter clocked with a precise-frequency square wave (usually from a crystal oscillator).
The basic schematic diagram is shown here:
The IGFET capacitor-discharging transistor scheme shown here is a bit oversimplified. In
reality, a latching circuit timed with the clock signal would most likely have to be
connected to the IGFET gate to ensure full discharge of the capacitor when the
comparators output goes high. The basic idea, however, is evident in this diagram. When
the comparator output is low (input voltage greater than integrator output), the integrator
is allowed to charge the capacitor in a linear fashion. Meanwhile, the counter is counting
up at a rate fixed by the precision clock frequency. The time it takes for the capacitor to
charge up to the same voltage level as the input depends on the input signal level and the
combination of - Vref, R, and C. When the capacitor reaches that voltage level, the
comparator output goes high, loading the counters output into the shift register for a final
output. The IGFET is triggered on by the comparators high output, discharging the
capacitor back to zero volts. When the integrator output voltage falls to zero, the
comparator output switches back to a low state, clearing the counter and enabling the
integrator to ramp up voltage again.
This ADC circuit behaves very much like the digital ramp ADC, except that the
comparator reference voltage is a smooth sawtooth waveform rather than a stairstep:
222
The single-slope ADC suffers all the disadvantages of the digital ramp ADC, with the
added drawback of calibration drift. The accurate correspondence of this ADCs output
with its input is dependent on the voltage slope of the integrator being matched to the
counting rate of the counter (the clock frequency). With the digital ramp ADC, the clock
frequency had no effect on conversion accuracy, only on update time. In this circuit, since
the rate of integration and the rate of count are independent of each other, variation
between the two is inevitable as it ages, and will result in a loss of accuracy. The only
good thing to say about this circuit is that it avoids the use of a DAC, which reduces
circuit complexity.
An answer to this calibration drift dilemma is found in a design variation called the dual-
slope converter. In the dual-slope converter, an integrator circuit is driven positive and
negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts
at the end of every cycle. In one direction of ramping, the integrator is driven by the
positive analog input signal (producing a negative, variable rate of output voltage change,
or output slope) for a fixed amount of time, as measured by a counter with a precision
frequency clock. Then, in the other direction, with a fixed reference voltage (producing a
fixed rate of output voltage change) with time measured by the same counter. The counter
stops counting when the integrators output reaches the same voltage as it was when it
started the fixed- time portion of the cycle. The amount of time it takes for the integrators
capacitor to discharge back to its original output voltage, as measured by the magnitude
accrued by the counter, becomes the digital output of the ADC circuit.
The dual-slope method can be thought of analogously in terms of a rotary spring such as
that used in a mechanical clock mechanism. Imagine we were building a mechanism to
measure the rotary speed of a shaft. Thus, shaft speed is our input signal to be
measured by this device. The measurement cycle begins with the spring in a relaxed
state. The spring is then turned, or wound up, by the rotating shaft (input signal) for a
fixed amount of time. This places the spring in a certain amount of tension proportional
to the shaft speed: a greater shaft speed corresponds to a faster rate of winding. and a
greater amount of spring tension accumulated over that period of time. After that, the
spring is uncoupled from the shaft and allowed to unwind at a fixed rate, the time for it
223
to unwind back to a relaxed state measured by a timer device. The amount of time it
takes for the spring to unwind at that fixed rate will be directly proportional to the speed
at which it was wound (input signal magnitude) during the fixed-time portion of the
cycle.
4Q) Draw the circuit of Single input balanced and unbalanced output differential
amplifier stages?
Ans: Single Input, Balanced Output Differential Amplifier:
Single Input, Unbalanced Amplifier:
Fig. Single Input, Unbalanced Output Differential Amplifier
224
5Q) Discuss the role of a level translator in op amp?
Level Translator:
Because of the direct coupling the dc level at the emitter rises from stages to stage. This
increase in dc level tends to shift the operating point of the succeeding stages and
therefore limits the
output voltage swing and may even distort the output signal. To shift the output dc level
to zero, level translator circuits are used. An emitter follower with voltage divider is the
simplest form of level translator as shown in fig. Thus a dc voltage at the base of Q
produces 0V dc at the output. It is decided by R1 and R2. Instead of
Voltage divider emitter follower either with diode current bias or current mirror bias as
shown in fig. may be used to get better results.
In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V.
If this shift is not sufficient, the output may be taken at the junction of two resistors in
the emitter leg.
6Q) Explain the principle of VCO?

Ans: VCO (Voltage controlled oscillator).
Voltage controlled oscillator is a type of oscillator where the frequency of the output
oscillations can be varied by varying the amplitude of an input voltage signal. Voltage
controlled oscillators are commonly used in frequency (FM), pulse (PM) modulators
and phase locked loops (PLL). Another application of the voltage controlled oscillator
is the variable frequency signal generator itself. Block diagram of a typical voltage
225
controlled oscillator is shown below.
Fig. VCO
Voltage controlled oscillators can be broadly classified into linear voltage controlled
oscillators and relaxation type voltage controlled oscillators. Linear voltage controlled
oscillators are generally used to produce a sine wave. In such oscillators an LC tank
circuit is used for producing oscillations. An active element like transistor is used for
amplifying the output of the LC tank circuit, compensating the energy lost in the tank
circuit and for establishing the necessary feedback conditions. Here a varactor
(varicap) diode is used in place of the capacitor in the tank circuit. Varactor diode is
type of semiconductor diode whose capacitance across the junction can be varied by
varying the voltage across the junction. Thus by varying the voltage across the
varicap diode in the tank circuit, the output frequency of the VCO can be varied.
Relaxation type voltage controlled oscillators are used to produce a saw tooth or
triangular waveform. This is achieved by the gradual charging and sudden discharge
of a capacitor connected appropriately to an active element (UJT, PUT etc) .
7Q) Explain about the working on instrumentation amplifier?

Ans: Instrumentation amplifier using op-amp
Instrumentation amplifier is a kind of differential amplifier with additional input buffer

stages. The addition of input buffer stages makes it easy to match (impedance
matching) the amplifier with the preceding stage. Instrumentation are commonly used
in industrial test and measurement application. The instrumentation amplifier also has
some useful features like low offset voltage, high CMRR (Common mode rejection
ratio), high input resistance, high gain etc. The circuit diagram of a typical
instrumentation amplifier using opamp is shown below.
226
Fig: Instrumentation amplifier
A circuit providing an output based on the difference between two inputs (times a scale
factor) is given in the above figure. In the circuit diagram, opamps labelled A1 and A2
are the input buffers. Anyway the gain of these buffer stages are not unity because of
the presence of R1 and Rg. Op amp labelled A3 is wired as a standard differential
amplifier. R3 connected from the output of A3 to its non inverting input is the
feedback resistor. R2 is the input resistor. The voltage gain of the instrumentation
amplifier can be expressed by using the equation below.
Voltage gain (Av) = Vo/(V2-V1) = (1 + 2R1/Rg ) x R3/R2
If need a setup for varying the gain, replace Rg with a suitable potentiometer.
Instrumentation amplifiers are generally used in situations where high sensitivity,
accuracy and stability are required. Instrumentation amplifiers can be also made using
two opamps, but they are rarely used and the common practice is to make it using
three opamps like what is shown here. The only advantages of making an
instrumentation amplifier using 2 opamps are low cost and improved CMRR.
A high gain accuracy can be achieved by using precision metal film resistors for all the
resistances. Because of large negative feedback employed, the amplifier has good
linearity, typically about 0.01% for a gain less than 10. The output impedance is also
low, being in the range of milli-ohms. The input bias current of the instrumentation
amplifier is determined by the op-amps A1 and A2.
227
A simplified instrumentation amplifier design is shown below. Here the resistances
labelled R1 are shorted and Rg is removed. This results in a full series negative
feedback path and the gain of A1 and A2 will be unity. The removal of R1 and Rg
simplifies the equation to Av = R3/R2.
Fig: Simplified Instrumentation amplifier
8Q) Draw the internal circuit diagram of IC 741 operational amplifier and explain the
function of each stage.
Ans:
555 Timers:
IC 555 timer is a well-known component in the electronic circles but what is not
known to most of the people is the internal circuitry of the IC and the function of
various pins present there in the IC. Let me tell you a fact about why 555 timer is
called so, the timer got its name from the three 5 kilo-ohm resistor in series employed
in the internal circuit of the IC.
IC 555 timer is a one of the most widely used IC in electronics and is used in various
228
electronic circuits for its robust and stable properties. It works as square-wave form
generator with duty cycle varying from 50% to 100%, Oscillator and can also provide
time delay in circuits. The 555 timer got its name from the three 5k ohm resistor
connected in a voltage-divider pattern which is shown in the figure below. A simplified
diagram of the internal circuit is given below for better understanding as the full
internal circuit consists of over more than 16 resistors, 20 transistors, 2 diodes, a flip-
flop and many other circuit components.
The 555 timer comes as 8 pin DIP (Dual In-line Package) device. There is also a 556
dual version of 555 timer which consists of two complete 555 timers in 14 DIP and a
558 quadruple timer which is consisting of four 555 timer in one IC and is available as
a 16 pin DIP in the market.
229
Basics Concepts:
Comparator: The Comparator are the basic electronic component which compares the
two input voltages i.e. between the inverting (-) and the non-inverting (+) input and if
the non-inverting input is more than the inverting input then the output of the
comparator is high. Also the input resistance of an ideal comparator is infinite.
Voltage Divider: As we know that the input resistance of the comparators is infinite
hence the input voltage is divided equally between the three resistors. The value being
Vin/3 across each resistor.
Flip/Flop: Flip/Flop is a memory element of Digital-electronics. The output (Q) of the
flip/flop is high if the input at S terminal is high and R is at Low and the output
(Q) is low when the input at S is low and at R is high.
Function of different Pins:-
Ground: This pin is used to provide a zero voltage rail to the Integrated circuit to
divide the supply potential between the three resistors shown in the diagram.
Trigger: As we can see that the voltage at the non-inverting end of the comparator is
Vin/3, so if the trigger input is used to set the output of the F/F to high state by
applying a voltage equal to or less than V in/3 or any negative pulse, as the voltage at
the non-inverting end of the comparator is Vin/3.
Output: It is the output pin of the IC, connected to the Q (Q-bar) of the F/F with an
inverter in between as show in the figure.
Reset: This pin is used to reset the output of the F/F regardless of the initial condition
of the F/F and also it is an active low Pin so it connected to high state to avoid any
noise interference, unless a reset operation is required. So most of the time it is
connected to the Supply voltage as shown in the figure.
Control Voltage: As we can see that the pin 5 is connected to the inverting input having
a voltage level of (2/3) Vin. It is used to override the inverting voltage to change the
width of the output signal irrespective of the RC timing network.
Threshold: The pin is connected to the non-inverting input of the first comparator. The
output of the comparator will be high when the threshold voltage will be more than
(2/3) Vin thus resetting the output (Q) of the F/F from high to low.
230
Discharge: This pin is used to discharge the timing capacitors (capacitors involved in
the external circuit to make the IC behave as a square wave generator) to ground when
the output of Pin 3 is switched to low.
Supply: This pin is used to provide the IC with the supply voltage for the functioning
and carrying of the different operations to be fulfilled with the 555 timer.
Question Paper-3
1Q) What is a precision rectifier? Explain how it acts as Rectifier compare to Normal diode?
Ans: Precision rectifier
The precision rectifier, also known as a super diode, is a configuration obtained with
an operational amplifier in order to have a circuit behave like an ideal diode and
rectifier. It is useful for high-precision signal processing.
The op-amp based precision rectifier should not be confused with the power
MOSFET- based active rectification ideal diode.
Basic circuit
Fig.3.22 A simple precision rectifier circuit
The basic circuit implementing such a feature is shown on the right, where R L can be any
load. When the input voltage is negative, there is a negative voltage on the diode, so it
works like an open circuit, no current flows through the load, and the output voltage is
zero.
When the input is positive, it is amplified by the operational amplifier which switches the
diode on. Current flows through the load and, because of the feedback, the output voltage
231
is equal to the input voltage.
The actual threshold of the super diode is very close to zero, but is not zero. It equals the
actual threshold of the diode, divided by the gain of the operational amplifier.
This basic configuration has a problem so it is not commonly used. When the input
becomes (even slightly) negative, the operational amplifier runs open loop, as there is no
feedback signal through the diode. With a typical high open loop gain operational
amplifier, the output saturates. If the input then becomes positive again, the op-amp has
to get out of the saturated state before positive amplification can take place again. This
change generates some ringing and takes some time, greatly reducing the frequency
response of the circuit.
Fig.3.23 An improved precision rectifier circuit

Improved circuit
In this case, when the input is greater than zero, D1 is OFF and D2 is ON, so the output is
zero because one side of is connected to the virtual ground, and there is no current
232
through it. When the input is less than zero, D1 is ON and D2 is OFF, and the output is
like the input with an amplification of . Its input-output relationship is the

following:
This circuit has the benefit that the op-amp never goes into saturation, but its output must
change by two diode voltage drops (about 1.2 V) each time the input signal crosses zero.
Hence, the slew rate of the operational amplifier, and its frequency response (gain-
bandwidth product) will limit high frequency performance - especially for low signal
levels - although an error of less than 1% at 100 kHz is possible. Similar circuitry can be
used to create a precision full-wave rectifier circuit.
2Q) Explain any one of the application of Mono stable multi vibrator?
Ans: Applications:
Missing Pulse Detector:

To implement this circuit, we use a 555 IC configured as an astable multivibrator. See
the diagram. The output of the 555 timer remains high while the pulses applied to its
input occur in the correct intervals of time. If a pulse fall behind, or it is absent, the
output of the 555 IC goes low, detecting a problem.
Fig.4.9 Missing Pulse Detector

233
The values of resistor R1 and capacitor C1 are chosen depending on
the application you have. The values of R1 and C1 on this circuit were chosen to
observe its operation when the input is activated manually.
The input pulses are detected by pin 2 of the 555 timer. At this same point we connect
the base of a PNP transistor (Q1) in order to discharge the capacitor C1, each time the
expected pulse appears, and thus start a new charging.
If the pulses arrive at pin 2 of the 555 integrated circuit on the correct intervals of
time, the capacitor C1 is discharged before its voltage level reaches the level that
causes the output of the 555 timer to go low.
3Q) Briefly explain the use of PLL for FM Multiplication and synthesis?
Ans: Frequency multiplication/division:
The block diagram shown below shows a frequency multiplier/divider using PLL. A
divide by N network is inserter between the VCO output and the phase comparator
input. In the locked state, the VCO output frequency fo is given by fo = Nfs. The
multiplication factor can be obtained by selecting a proper scaling factor N of the
counter.
Frequency multiplication can also be obtained by using PLL in its harmonic locking
mode. If the input signal is rich in harmonics e.g. square wave, pulse train etc., then the
VCO can be directly locked to the n-th harmonic of the input signal without connecting
any frequency divider in between. However, as the amplitude of the higher order
harmonics becomes less, effective locking may not take place for high values of n.
Typically n is kept less than 10. The circuit of the figure above can also be used for
frequency division. Since the VCO output (a square wave) is rich in harmonics, it is
possible to lock the m-th harmonic of the VCO output with the input signal fs. The
output fo of VCO is now given by fo=fs/m
234
Fig.4.20 Frequency multiplication/division
PLL Frequency Synthesis:
In digital wireless communication systems (GSM, CDMA etc), PLL's are used to
provide the Local Oscillator (LO) for up-conversion during transmission, and down-
conversion during reception. In most cellular handsets this function has been largely
integrated into a single integrated circuit to reduce the cost and size of the handset.
However due to the high performance required of base station terminals, the
transmission and reception circuits are built with discrete components to achieve the
levels of performance required. GSM LO modules are typically built with a
Frequency Synthesizer integrated circuit and discrete resonator VCO's. Frequency
Synthesizer manufacturers include Analog Devices, National Semiconductor and
Texas Instruments. VCO manufacturers include Sirenza, Z-Communications, Inc. (Z-
COMM).
235
Fig. PLL synthesizer
The key to the ability of a frequency synthesizer to generate multiple frequencies is

the divider placed between the output and the feedback input. This is usually in the
form of a digital counter, with the output signal acting as a clock signal. The counter
is preset to some initial count value, and counts down at each cycle of the clock
signal. When it reaches zero, the counter output changes state and the count value is
reloaded. This circuit is straightforward to implement using flip-flops, and because it
is digital in nature, is very easy to interface to other digital components or a
microprocessor. This allows the frequency output by the synthesizer to be easily
controlled by a digital system.
4Q) Explain the operation of D/A converter with binary weighted resistors.
Ans:
Binary-Weighted Resistor DAC
The binary-weighted-resistor DAC employs the characteristics of the inverting summer
Op Amp circuit. In this type of DAC, the output voltage is the inverted sum of all the input
voltages. If the input resistor values are set to multiples of two: 1R, 2R and 4R, the output
voltage would be equal to the sum of V1, V2/2 and V3/4. V1 corresponds to
Fig. Binary weighted resistor network
the most significant bit (MSB) while V3 corresponds to the least significant bit (LSB).The
circuit for a 4-bit DAC using binary weighted resistor network is shown
236
Fig.4-bit DAC using binary weighted resistor network
below .The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The
value, 0, represents an open switch while 1 represents a closed switch. The operational
amplifier is used as a summing amplifier, which gives a weighted sum of the binary input
based on the voltage, Vref. For a 4-bit DAC, the relationship between Vout and the binary
input is as follows:
The negative sign associated with the analog output is due to the connection to a summing
amplifier, which is a polarity-inverting amplifier. When a signal is applied to the latter
type of amplifier, the polarity of the signal is reversed (i.e. a + input becomes -, or vice
versa). For a n-bit DAC, the relationship between Vout and the binary input is as follows:
5Q) Explain the Operation of the Schmitt Trigger using 555 Timer and draw its
waveform?
Ans: Schmitt Trigger
The high and low transitions on the inputs of most of the CMOS devices should be
fast edges. If the edges are not fast enough, they tend to provide more current and this
might damage the device. Analog signals are generally not perfect and might not have
clean edges all the times. Schmitt Trigger is a special type of comparator that is used
to avoid such signals.
237
A comparator is a device that compares two voltages and the outcome is the
indication of whether one voltage is higher than the other or not. Schmitt trigger, also
called as Regenerative Comparator, compares the input voltage to two references
Voltages and produces an equivalent output. The output of a Schmitt trigger is always
a square or rectangular wave irrespective of the shape of the input. It is often used
when we need to do the following:

To convert slow edges (like in a triangular wave) into fast edges
(like a square wave)
trigger built from a 555 timer is inverting but the discussion will be for non-inverting.
238
Fig.4.10 Schmitt Trigger using IC555
Pins 4 and 8 are connected to the supply (VCC). The pins 2 and 6 are tied together
and the input is given to this common point through a capacitor C. this common point
is supplied with an external bias voltage of VCC / 2 with the help of the voltage
divider circuit formed by the resistors R1 and R2.
Schmitt trigger is high if the input voltage is greater than the upper threshold value
and the output of the Schmitt trigger is low if the input voltage is lower than the lower
threshold value.
The output retains its value when the input is between the two threshold values. The
usage of two threshold values is called Hysteresis and the Schmitt trigger acts as a
memory element (a bistable multivibrator or a flip-flop).
The threshold values in this case are 2/3 VCC and 1/3 VCC i.e. the upper comparator
trips at 2/3 VCC and the lower comparator trips at 1/3 VCC. The input voltage is
compared to these threshold values by the individual comparators and the flip-flop is
SET or RESET accordingly. Based on this the output becomes high or low.
When a sine wave of amplitude greater than VCC / 6 is applied at the input, the flip-
flop is set and reset alternately for the positive cycle and the negative cycle. The
output is a square wave and the waveforms for input sine wave and output square
wave are shown below.
239
Fig. Waveforms of Schmitt Trigger
6Q) Explain the operation of differential amplifier with its transfer characteristics?
Ans: Differential Amplifiers:
Differential amplifier is a basic building block of an op-amp. The function of a

differential amplifier is to amplify the difference between two input signals.
How the differential amplifier is developed? Let us consider two emitter-biased circuits
as shown in fig. 1.4
Fig. 1.4 Dual Input, Balanced Output Differential Amplifier
240
the magnitude of VEE. These voltages are measured with respect to ground. To make a
differential amplifier, the two circuits are connected as shown in fig. 1. The two +VCC
and VEE supply terminals are made common because they are same. The two emitters
are also connected and the parallel combination of RE1 and RE2 is replaced by a
resistance RE. The two input signals v1 & v2 are applied at the base of Q1 and at the
base of Q2. The output voltage is taken between two collectors. The collector
resistances are equal and therefore denoted by RC = RC1 = RC2.
The four differential amplifier configurations are following:
1. Dual input, balanced output differential amplifier.
2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.
Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig. 1.4; v1 and v2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors C1
and C2, which are at same dc potentials.
D.C. Analysis:
To obtain the operating point (ICC and VCEQ) for differential amplifier dc equivalent
circuit is drawn by reducing the input voltages v1 and v2 to zero as shown in fig. 1.5
241
Fig. D.C. Analysis of DIBO Configuration
The internal resistances of the input signals are denoted by RS because RS1= RS2.
Since both emitters biased sections of the different amplifier are symmetrical in all
respects, therefore, the operating point for only one section need to be determined. The
same values of ICQ and VCEQ can be used for second transistor Q2. Applying KVL to
the base emitter loop of the transistor Q1.
The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of
VEE. The emitter current in Q1 and Q2 are independent of collector resistance RC.
The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop
across R is negligible. Knowing the value of IC the voltage at the collector VCis given
by
VC =VCC -IC RC and VCE = VC - VE
= VCC - IC RC + VBE VCE = VCC + VBE - ICRC (E-2)
From the two equations VCEQ and ICQ can be determined. This dc analysis is
applicable for all types of differential amplifier.
7Q) Write the features of 741 IC op-amp?

Ans: Features of 741 IC
Short circuit and overload protection provided.

In theory, the dc output voltage will be zero if both the inputs of the 741 IC are
connected to the ground. But in practice, a small dc output may appear due to
minor internal unbalances. It is usually unnoticed in normal applications. But
for critical conditions, the output voltage can be set precisely to zero by
connecting a 10K potentiometer between terminals marked offset-null.
242
Low power consumption.
Large common mode rejection ratio (CMRR) and differential voltage ranges.
No external frequency compensation is required. It also does not need any
external compensation for phase component. This simplifies the circuit design
and minimizes the number of components used.
No latch-up problem.
8Q) Design and explain the operation of First order active Low-pass filter?
Ans: First Order Low Pass Filter:
This first-order low pass active filter consists simply of a passive RC filter stage
providing a low frequency path to the input of a non-inverting operational amplifier.
The amplifier is configured as a voltage-follower (Buffer) giving it a DC gain of one,
Av = +1 or unity gain as opposed to the previous passive RC filter which has a DC gain
of less than unity.
The advantage of this configuration is that the op-amps high input impedance prevents
excessive loading on the filters output while its low output impedance prevents the
filters cut-off frequency point from being affected by changes in the impedance of the
load.
While this configuration provides good stability to the filter, its main disadvantage is
that it has no voltage gain above one. However, although the voltage gain is unity the
power gain is very high as its output impedance is much lower than its input impedance.
If a voltage gain greater than one is required we can use the following filter circuit.
Active Low Pass Filter with Amplification
243
Fig.Active LPF with Amplifier
The frequency response of the circuit will be the same as that for the passive RC filter,
except that the amplitude of the output is increased by the pass band gain, A F of the
amplifier. For a non-inverting amplifier circuit, the magnitude of the voltage gain for
the filter is given as a function of the feedback resistor ( R2 ) divided by its
corresponding input resistor ( R1 ) value and is given as:
DC gain =
Therefore, the gain of an active low pass filter as a function of frequency will be: Gain
of a first-order low pass filter
Where:
AF = the pass band gain of the filter, (1 + R2/R1) = the frequency of the input signal
in Hertz, (Hz)
c = the cut-off frequency in Hertz, (Hz)
Thus, the operation of a low pass active filter can be verified from the frequency gain
equation above as:
244
Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high
frequency cut-off point,C. At C the gain is 0.707AF, and after C it decreases at a
constant rate as the frequency increases. That is, when the frequency is increased tenfold
(one decade), the voltage gain is divided by 10.
245
246

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COURSE FILE

LINEAR & DIGITAL IC APPLICATIONS

III B.TECH I SEMESTER

ELETRICAL AND ELECTRONICS ENGINEERING

VIGNANS INSTITUTE OF ENGINEERING FOR WOMEN

1 Course Objectives & Outcomes

4 Unit wise course Material (As per given format)

Unit-I: Introduction to Op-Amps

Unit-III: Ideal operational amplifier theory and basic circuits

Unit-IV: Waveform generator in angular waveform generator using op-

Unit-VI: Digital To Analog And Analog To Digital Converters

5 Reference text books/web material etc.,

6 Mid Question Paper + Schemes of Evaluation.

7 Fast track material for Back-Log students.

8 Sample Question Papers with solutions

9 Virtual Labs if required

The objectives of the course are:

After completing this Course, the student should be able to:

- Design circuits using operational amplifiers for various applications

Introduction to Operational Amplifier:

Ideal Operational Amplifier Theory and Basic Circuits

Analog to Digital Convertors

Block diagram of Typical OpAmp With Various Stages BJT Differential

4.1.1 Unit Objectives:

After reading this Unit, you should be able to understand:

- Analysis and design of differential amplifier

4.1.2 Unit Outcomes:

Student will be able to design different differential amplifier configurations and

4.1.3 Unit Lecture Plan:

* Session duration: 50 mins

4.1.4 Teaching Material / Teaching Aids as per above lecture plan.

2) (+) Non- inverting input terminal

4) Two dc power supplies V + and V

5) Other terminals are for frequency

Ideal characteristics of op amp

Differentialinput singleendedoutput amplifier

Infinite input impedance i1 = i2 = 0 (regardless of the input voltage

Zero output impedance vO= A(v2v1) (regardless of the load)

Infinite openloop differential gain

Infinite commonmode rejection

Fig.1.2 Ideal Op-amp Structure

Differential and commonmode signals

- Two independent input signals: v1 and v2

- Differentialmode input signal (vId): vId = (v2v1)

- Commonmode input signal (vIcm): vIcm = (v1+v2)/2

741 op-amp & its features:

Fig.1.3 IC741 Pin Configuration

Fig. 1.4 Dual Input, Balanced Output Differential Amplifier

The four differential amplifier configurations are following:

1. Dual input, balanced output differential amplifier.

2. Dual input, unbalanced output differential amplifier.

3. Single input balanced output differential amplifier.

4. Single input unbalanced output differential amplifier.

Dual Input, Balanced Output Differential Amplifier:

Fig.1.5 D.C. Analysis of DIBO Configuration

Solving these two equations, ie1 and ie2 can be calculated.

Differential Input Resistance:

Dual Input, Unbalanced Output Differential Amplifier:

Fig.1.7 Dual Input, Unbalanced Output Differential Amplifier

Single Input, Balanced Output Differential Amplifier:

Fig.1.8 Single Input, Balanced Output Differential Amplifier

Single Input, Unbalanced Amplifier:

Fig.1.9 Single Input, Unbalanced Output Differential Amplifier