Virata Activity2

Activity 2 - #1
Title: Characterization and Modeling of ESD

Diodes in RF circuits
I. Describing the Tools of Research
a. The Library and its Resources
The researchers used several library resources at their disposal to provide

useful information in the paper. They included information from pages 1 to 12
of a magazine entitled Compliance Engineering that was published on
August 2005 wherein the researchers defined Transmission Line Pulse as a
standard characterization method used for ESD devices. They also include
several journals from different symposiums and dissertation such as the
International Symposium on Quality Electronic Design (ISQED) in Stanford
University on 2001, Electrical Overstress/ Electrostatic Discharge Symposium
in Advanced Micro Devices on 2004 and ESD Protection Circuits for Advanced
CMOS Technologies dissertation in which the researchers cited about the
fatality of Electrostatic Discharge.
b. The Computer and its Software
The use of computer is the main tool that almost all researchers of the
current generation use. In the paper, the researchers used computer
programs for the simulations such as Agilent's Advanced Design System
(ADS) for the small signal RF simulation which shows the extracted
capacitance values of each test structure and Cadence Spectre for the
Transmission Line Pulse simulation which shows the TLP and leakage plot for
the diode arrays. These programs were used to determine the correlation of a
subject in different scenarios.
c. Techniques of Measurement
The research followed the standard in getting measurement. It exhibits

interval scale of measurement in which the measured values where
interpreted into different qualities of effectiveness.
d. Statistics
Not stated in the article.
e. The Human Mind
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The research is very theoretical, much of it is concerned with developing but

the way it was presented was understandable and easy to comprehend,
exploring or testing the theories or ideas. But it is also less empirical in which
the research is based on observations and measurements of reality.
II. The Problem and its Setting

1. Write the statement of the problem
Electrostatic discharge (ESD) is fatal to the integrated circuit (IC) without

proper protection. Thus, ESD protection circuits have become a must-have for
the IC industry. Under normal circuit operation ESD protection circuits must
remain turned off. However, during an ESD event they must tum on quickly
to dissipate large currents in a short time period. For radio frequency
integrated circuits (RFICs), the off-state ESD protection circuit needs to be
well characterized
2. Identify the research objective/s.
The objective of the paper is to investigate the ESD and RF performance of

ESD diode arrays and to look at how these are modeled.
3. What are the delimitations?
The simulation used a single diode array configuration. For the simulation of
RF characterization for the diode arrays, the researchers limited the
simulation in a frequency range of 0.4GHz to 10GHz
4. Enumerate the importance of the study
The study focused on characterization of diode arrays fabricated in IBM's

O.18um CSOI7RF technology under both ESD and Radio Frequency (RF) test
conditions. The research also focused on the connection between asymmetry
in the diode structures (mismatch) and the even harmonic responses of
bidirectional shunted ESD diode connected circuits.
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
To fully characterize ESD diodes, multiple back to back diode arrays have
been designed and fabricated. The stack number in the arrays range from 4
to 28 diodes. The test structure has a ground-signal-ground (GSG)
configuration for RF on wafer probe measurements. The unit cell of each
diode is identical.
2. Experimentation
For the ESD characterization, HBM and TLP measurements and simulations
are conducted. The leakage current data point is measured after each TLP
pulse to check whether the device is damaged or not. All the diode array test
structures have been characterized a specific frequency range using a 2-
PortVector Network Analyzer (VNA). The reverse bias capacitance of the test
structures is extracted from the S-Parameters across frequency at 0V reverse
bias. Because ESD diodes are nonlinear devices, the harmonics generated by
ESD diodes also need to be well characterized. For the odd harmonics, there
appears to be reasonable agreement between measurement and simulation.
In this case, there are significant discrepancies between measurement and
simulation. The simulation results using diode models that are totally
symmetric shows that no even harmonic are generated while measured
results indicate the presence of strong 2nd and 4th harmonic components in
the output.
3. Evaluation/Testing
From theory, the even harmonic components are present in a system that is
asymmetric about the horizontal V=O axis. A full-wave rectifier is a typical
example. In this work the addition of various asymmetric mechanisms were
explored including nonlinear substrate capacitance coupling and nonlinear
substrate resistance. However, none of them can explain the measured
results completely. The data suggests that there is an intrinsic asymmetry of
the diode structure even though all diode test structures use the same unit
cell in their layout.
4. Processes to arrive at a conclusion in order to meet the

objectives and eventually solve the problem.
To mimic a possible asymmetry in the intrinsic diode structure, we
deliberately changed the diode size slightly for one direction in the stack to
introduce a specific asymmetry. With a less than 1% bias introduced, the
even harmonic component in large signal can be aligned with measurement
data.
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.
Activity 2- #2
Title: Methods of Early Short-Circuit Detection
for Low Voltage Systems
The researchers used several library resources to provide useful information

in the paper. They included information from a book entitled Computer
relaying for power systems that was published by Wiley and Sons on 1988
wherein the researchers defined Regression Analysis as a statistic standard in
analyzing data. They also include several journals from different conferences
and dissertation such as the 23rd International Conference on Electrical
Contacts Japan on 2006, 52nd IEEE Holm Conference on Electrical Contacts
in Canada on 2006 and Fast fault detection for power distribution systems in
which the researchers cited about the importance of fault detection.
In the paper, the researchers used computer programs for data interpretation
such as the three-dimensional locus curves criterion and regression analysis
and also when doing wavelet analysis.

ordinal scale of measurement in which the measured values where
interpreted into ranks.
d. Statistics
e. The Human Mind
developments.
f. Language


In modern power distribution networks, short-circuit currents should be

limited as much as possible to prevent damages to distribution lines and
loads. Low-voltage systems comprise rising short-circuit powers and coupling
of several networks. Conventional mechanical low-voltage protection devices
obtain the mechanical energy required for switching off from a spring energy
store and failure detection based on thermal-magnetic tripping units.
The objective of the research is to provide new approaches for low-voltage

system protection. The three-dimensional locus curves criterion will be
pointed out as one opportunity for short-circuit detection. Regression
analysis, used to predict the amplitude of a sinusoidal function and therefore
the prospective short-circuit current, provides another possible detection
algorithm. Also a method based on combined three-phase quantities, e.g.
phase currents, has been studied for network failure identification.
The research justified that there were still methods that can be done, and
these possible techniques are the analysis of short-circuit depend voltage
drops in the network or wavelet methods interpreting the network currents
via dyadic filter banks of a Multiresolution Analysis.
The study focused on electronic tripping units that offer new methods in
system protection. Intelligent protection device and communication principles
are needed for realization. Most important is a fast detection and a reliable
behavior at grid bound disturbances to avoid nuisance tripping.
III. Methodology
1. Data Gathering
The different short-circuit protection algorithms have been developed and

analyzed. Most of the early short-circuit detection algorithms presented in
literature are based on a combined current and rate of current rise analysis.
Among these, the locus curves criteria are most commonly used. The limits
for short circuit detection are extracted from locus-curves framing all possible
regular conditions in ohmic-inductive networks. The envelope of the locus-
curves, describing the regular conditions, is approximated by a cuboid. All
measured or calculated data points lying beyond this cuboid are stated as
failure.
In the next steps, the researchers looked for a function, with functional
characteristics differing from the given values at a minimum.
2. Experimentation
The two-dimensional locus curve short-circuits detection criteria analyze the

instantaneous values of current and the rate of current rise at the same point
of time. The principle is based on an ohmic-inductive equivalent circuit Locus
curves represent possible constellations of regular system states in the
equivalent circuit, including switching operations.
Rapid failure detection and no nuisance tripping (reliability) are the key
performance parameters to benchmark early short-circuit detection
algorithms. Three phase faults are generally inherently faster to detect than
single phase faults as evidenced by combined three phase quantities.
Furthermore, a well-defined tripping value is necessary to realize
discrimination for several protection devices installed in series, as it is typical
for low-voltage power distribution networks.
The performance of the presented short-circuit detection algorithms is

estimated in a benchmark, which assigns points between 1 (negative) and 10
(positive). Shortest detection times are rated with 10. The three-
dimensional locus curves criterion was used as reference in this claim. Rising
detection times have been rated proportional lower.
If some hardware complexity can be tolerated, the 3D locus curve criterion is

superior for it combines shortest one- and three-phase failure detection
times, among with high reliability and good tripping value definition. Wavelet
methods are very unlikely to perform, for decomposition level definition is
complicated, especially under reliability aspects, hardware complexity is very
high and no defined tripping value definition in classical manner can be
realized. Criteria based on voltage dips cannot assure discrimination, too, and
depend very
much on network factors and protected loads. Therefore voltage dip criteria
have not been included in the benchmark. If longer tripping times can be
tolerated, instantaneous current methods offer a reliable failure detection
method with lowest hardware complexity. Regression analysis might offer an
alternative, but requires more hardware complexity, especially to realize a
sufficient reliability in disturbed industrial networks.
Activity 2 - #3
Title: Analysis and Design of ESD Protection

Circuits for High-Frequency Applications

useful information in the paper. They included information from a book
entitled ESD in Silicon Integrated Circuits that was published on 1995
wherein the researchers described that the protection circuit may be
composed of various devices, such as diodes, transistors, or silicon controlled
rectifiers (SCRs). They also include several journals from symposium and
patent such as the EOS/ESD Symposium in 1999, and US Patent # 5929969
in which the researchers cited about the importance of ESD devices in RF
systems.
In the paper, the researchers used computer programs for data interpretation
such as the Smith Chart representation for S-Parameter performance analysis
that introduces a coplanar waveguide.

d. Statistics
e. The Human Mind
developments.
f. Language


As the demand for wireless (RF) systems continues to increase rapidly,

providing sufficient ESD protection for these systems poses a major design
and reliability challenge. This is due to the fact that in applying ESD
protection to RF systems, the protection system must be transparent--the
protection circuit must not affect the signal under normal operating
conditions.
The objective of the research is to provide an s-parameter based analysis of

the performance of RF circuits with various ESD protection designs.
Additionally, a design methodology for distributed ESD protection using
coplanar waveguides is developed to achieve a better impedance match over
a broad frequency range. By using this technique, an ESD device with a
parasitic capacitance of 200 fF will attenuate the signal power by only 0.27
dB at IO GHz.
The research justified that the most general ESD protection was the basis of
their design which consists of the source, load, a resistor representing
interconnect and device loss, and the protection device and pad parasitic
capacitance.
The study focused on the importance of designing a Electrostatic discharge

(ESD) protection devices that can have an adverse effect on the performance
of high frequency and RF circuits because a poorly designed protection
system can generate impedance mismatches, causing reflections of signals,
corruption of signal integrity, and inefficient power transfer between the
signal pin and the core circuit. Also, while the operation frequency continues
to rise, the size of the protection circuits and their associated capacitances
are not decreasing as rapidly, resulting in increasingly inefficient
power transfer.
III. Methodology
1. Data Gathering
The simple approach of minimizing capacitance while maintaining high

protection levels is becoming increasingly infeasible as the operation
frequency rises beyond a few GHz, protection schemes such as the
distributed transmission line ESD protection system is necessary.
Starting with a standard 5 0ohms system as is commonly found in RF

systems, four different implementations of ESD protection is investigated.
2. Experimentation
A 50 ohm signal source drives the input to the protection circuit, and the
output of the protection circuit is connected to the system to be protected, as
modeled by a 50 ohms load. In each circuit, the protection device is modeled
as a capacitance and input resistance, and interconnects between the pin and
ESD circuit or between distributed ESD elements are modeled by a resistance
or a coplanar waveguide (CPW). Initially, the capacitance is assumed to be
200 fF, a value sufficient to provide a 2 kV ESD protection level. The required
CPW length was calculated using Smith Charts and impedance
transformations to minimize reflections.
Prior to determining the proper CPW length, three parameters must be fixed.
They are the maximum operating frequency, the equivalent ESD capacitance
and the CPW characteristic impedance. Selecting fmax; should consist only of
determining the maximum frequency specification for the core circuit. ESD
capacitance should be calculated after determining the proper ESD device
size required for a particular protection level. The equivalent capacitance may
then be calculated from the device junction areas, or obtained through
simulations. The CPW characteristic impedance is mainly a function of
transmission line width and signal to-ground spacing. A high characteristic
impedance is desirable, but losses should be kept to a minimum.
Since the whole system is lossless, all the power loss is due to signal
reflection caused by impedance mismatch. While most of the power reaches
the load at low frequencies, the capacitance loads the circuit at higher
frequencies.
One last consideration is to determine whether this analysis, performed for a

system operating at fmax is valid when the system operates at a frequency
lower than fmax. Thus the fmax case is the worst case, and if the
performance there is satisfactory, then the performance at any lower
frequency will be at least as good as that seen at fmax.

A Detailed s-parameter analysis of R circuits with different ESD protection

design options has been presented. The effect of the interconnect and device
losses, together with the parasitic device capacitances on RF performance has
been quantified. It has also been shown that a 4-stage distributed ESD
protection can be beneficial at frequencies greater than 3 GHz. A generalized
design methodology has been developed to optimize the number and length
of coplanar waveguides separating the distributed ESD elements. By using
this methodology, an ESD protection scheme with a parasitic capacitance of
200 fF will attenuate the signal power by only 0.27 dB at 10 GHz.
Activity 2 - #4
Title: The State of the Art of Electrostatic

Discharge Protection: Physics, Technology,
Circuits, Design, Simulation, and Scaling

useful information in the paper. They included information from a book from
pages 85 to 89, entitled The effect of VLSI scaling on EOS/ESD failure
threshold that was published on 1981 wherein the researchers described
that the scaling of semiconductor devices introduces new materials, process,
and structures that impact ESD robustness. They also include several journals
from different symposiums and dissertation such as the EOS/ESD Symposium
Technical Proceedings on 1990, and U.S. Patent #5465186, about ESD
Testing and protection.
programs for the simulations such as SPICE-like (Simulation Program with
Integrated Circuit Emphasis) circuit simulation and electrothermal circuit
simulation which shows the analysis of ESD circuits. These programs were
used to determine the correlation of a subject in different scenarios.

d. Statistics
e. The Human Mind
developments.
f. Language


Electrostatic discharge (ESD) phenomena continue to be an issue because of

technology scaling, higher frequency requirements, and increasing customer
expectation. Concurrently, ESD networks, techniques, and design practices
are constantly changing with both evolutionary and revolutionary changes in
semiconductor technology. As ESD engineering matures, new techniques and
practices are being adapted in characterization and testing. As growth in
these areas continues in the marketplace, customer demand will continue for
ESD protection and performance objectives.
The objective of the paper is to review the ESD protection practices and
techniques, ESD protection networks, design concepts, device simulation,
circuit simulation, and other ESD issues.
Highlighted is the unique and interesting role in ESD phenomenon that the
BJT plays in bipolar-, MOSFET-, or BiCMOS-based technologies.
The study focused on understanding the ESD phenomenon and its protection.
The researcher also focused on the physics behind it, the technology used, its
circuitry and design, the simulation made, and scaling.
III. Methodology
1. Data Gathering
To understand the ESD phenomenon, it is necessary to include electrical as

well as thermal physics. The researcher discussed the physics behind ESD-
related devices, wherein it stated that it concerns differ from those of
standard very large-scale integration (VLSI) concerns because ESD analysis
extends into a large-signal transient high-current regime where self-heating is
important. The researcher also credited the early investigators, Wunsch and
Bell, whom explained that the failure of semiconductor devices can be
understood from a universal curve where the power-to-failure is plotted
versus pulse width. The WunschBell curve explains the relationship of
physical failure to a critical temperature (melting temperature) and addresses
the relationship of the heat transfer time constant to the applied pulse width.
The WunschBell curve provided an early universal framework for
understanding diodes, BJTs, MOSFETs, and interconnect ESD robustness.
2. Experimentation
ESD standards have been developed for the pulse waveform to represent
different physical interactions with semiconductor chips. Today, ESD models,
including the human-body model (HBM), machine model (MM), charged-
device model (CDM), and socketed-device model (SDM), are being used for
manufacturing qualification of product chips. The HBM source consists of a
1.5-k resistor and 100-pF capacitor in series applied to the device under test.
The MM source is a 200- pF capacitor. In the CDM and SDM test, the package
itself is charged, either in a standing electric field or through the ground or
power-supply leads. TLP and dynamic transmission-line pulse test systems
are being commercially offered as a technique to characterize semiconductor
components. TLP testing varies the pulse width applied to the structure under
test, allowing determination of the power-to-failure versus applied pulse
width. The WunschBell curve of power-to-failure versus pulse width provides
a universal characterization curve for ESD robustness evaluation of the
semiconductor structure. Today, an industry-standard specification does not
exist for TLP testing. As commercial systems become available, and ESD
benchmarking becomes a standard practice, TLP testing may become a tool
to evaluate the ESD robustness of semiconductor technologies and eventually
phase out todays standard testing practices for HBM and MM testing.
Advances in computer-aided design (CAD) are beginning to address ESD
issues in the design implementation and release process. ESD design
checking and verification, as well as development of ESD guidelines have
been established based on physics and unique problems that occur in
providing ESD solutions for semiconductor chips. For ESD protection, ESD
ground rules are established for the ESD networks, layout, and peripheral
circuits.

ESD improvement can be maintained by using ESD robust circuitry, new

circuitry innovation, judicial design layout, and good design synthesis. A
significant ESD protection challenge still remains in high-frequency
applications, the magnetic recording head industry, and other related fields.
Work continues in pursuing the high-voltage/high-current simulation and the
optimization and prediction of EOS/ESD events in future microelectronic
devices. As a result, ESD continues to remain an important quality, reliability,
and design integration issue in advanced semiconductor chips.
Activity 2 - #5
Title: ESD Protection for SOI Technology using

an Under-The-Box (Substrate) Diode Structure

useful information in the paper. They included information from a book
entitled ESD in Silicon Integrated Circuits that was published on 2002
wherein the researchers described that the ESD protection for
microprocessors has proved to be a challenging issue as the emergence of
SOI as a viable and appealing technology in the manufacturing of
microprocessors. They also include several journals from different
symposiums and dissertation such as the International Conference on Solid
State Devices and Materials (SSDM) of IEEE in September 2002, about
Electrostatic Discharge - Silicon on Insulator (ESD SOI)
programs for the simulations such as TCAD (Technology Computer-Aided
Design) circuit simulation which shows the SOI ESD applications. This
program was used to determine the correlation of a subject in different
scenarios.

d. Statistics
e. The Human Mind
developments.
f. Language


Electrostatic discharge (ESD) protection for microprocessors has proved to be

a challenging issue as it progresses from one technology to another and with
the emergence of SOI as a viable and appealing technology in the
manufacturing of microprocessors, ESD is now even more challenging. In SOI
architecture, the buried oxide (BOX) limits the number of structures that can
be used for ESD protection because it does not allow any vertical structures
to be created, e.g., vertical NPN or diodes. Also, due to the poor thermal
conductivity of the buried oxide the failure levels are much lower than what
can be achieved by the bulk structures.
The objective of the paper is to present a new integrated SOI substrate diode
structure for ESD protection of SOI I/O circuits that is built under the buried
oxide of the SOI wafer using a standard CMOS process. It will also aim that
the protection level can reach four times what is achieved by the standard-
lateral SOI diode structure. Also, it aims that the device and process
simulation results to understand the self-heating effect of both standard SOI
and substrate diodes, as well as how to optimize the structure using a deep
N-well implant.
The paper provided a new approach for building ESD protection structures for
SOI technologies that are built underneath the buried oxide layer, using a
standard process flow. The diode is constructed in two ways: one is an
inherent substrate diode that forms an N+/P-substrate junction, and the
other forms a P+/N-well junction by incorporating an extra deep-well implant.
These structures will be compared to the standard SOI Polybond lateral diode
for ESD protection capability via transmission line pulsed (TLP) and intrinsic
device characteristics (leakage and capacitance) measurements.
The study focused on understanding the ESD Protection structure for SOI
Technology based on the integrated SOI substrate diode.
III. Methodology
1. Data Gathering
In the first few content of the paper, the researcher has indicated
comparisons between SOI ESD and bulk. Th researchers demonstrated the
use of an integrated substrate diode as a new way of protecting against ESD
for SOI technologies to provide 4x improvement in the ESD protection
capabilities, which is an improvement over previous findings that combined
bulk and SOI structures showing a 2x improvement.
2. Experimentation
The structure is formed by integrating a buried oxide opening in an SOI

process flow, and then using standard source and drain implants to form the
anode (P+) and cathode (N+) regions in the substrate (or handle-wafer
region), creating an N+/p-substrate
junction diode. A deep N-well can also be introduced to isolate the structure
by adding a high-energy implant to the process flow to create the P+/Nwell
junction diode. Contacts are then added to connect the diode to the I/O
circuit for protection. Note that the diode is defined using the STI and the
buried oxide and the distance between the substrate openings determines the
length of the diode. In this case the gate poly defines the diode and the
length of the diode base (Ld) is the length of the gate poly.
As a result, it is said that two problems might arise as a result of moving the
ESD protection diode from the SOI layer to the substrate under the buried
oxide. The first one is the increase in capacitance. The second problem
encountered is the increased diode leakage current.
The researchers presented a new ESD protection structure for SOI technology
based on the integrate SOI substrate diode. The SOI substrate diode comes
in either N+/P substrate junction with no extra implant or a P+/N well
junction with extra deep N-well implant. The It2 of the P+/N-well substrate
diode is almost 4 times that of the lateral diode. It is showed that the
substrate diode sensitivity to diode length as well as the problems associated
with the new structure such as increased junction capacitance, which can be
overcome by reducing the diode size without affecting the protection level.
Increased junction leakage was another problem, and by using process and
device simulation the researchers was able to show that it could optimize the
deep N-well for minimum I/O.

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Activity 2 - #1

Title: Characterization and Modeling of ESD

I. Describing the Tools of Research

a. The Library and its Resources

The researchers used several library resources at their disposal to provide

b. The Computer and its Software

The research followed the standard in getting measurement. It exhibits

Not stated in the article.

e. The Human Mind

The research is very theoretical, much of it is concerned with developing but

II. The Problem and its Setting

Electrostatic discharge (ESD) is fatal to the integrated circuit (IC) without

2. Identify the research objective/s.

The objective of the paper is to investigate the ESD and RF performance of

3. What are the delimitations?

4. Enumerate the importance of the study

The study focused on characterization of diode arrays fabricated in IBM's

4. Processes to arrive at a conclusion in order to meet the

I. Describing the Tools of Research

a. The Library and its Resources

The researchers used several library resources to provide useful information

b. The Computer and its Software

The research followed the standard in getting measurement. It exhibits

Not stated in the article.

e. The Human Mind

The research is very theoretical, much of it is concerned with developing but

II. The Problem and its Setting

In modern power distribution networks, short-circuit currents should be

2. Identify the research objective/s.

The objective of the research is to provide new approaches for low-voltage

3. What are the delimitations?

4. Enumerate the importance of the study

The different short-circuit protection algorithms have been developed and

The two-dimensional locus curve short-circuits detection criteria analyze the

The performance of the presented short-circuit detection algorithms is

If some hardware complexity can be tolerated, the 3D locus curve criterion is

Title: Analysis and Design of ESD Protection

I. Describing the Tools of Research

a. The Library and its Resources

The researchers used several library resources at their disposal to provide

b. The Computer and its Software

The research followed the standard in getting measurement. It exhibits

Not stated in the article.

e. The Human Mind

The research is very theoretical, much of it is concerned with developing but

II. The Problem and its Setting

As the demand for wireless (RF) systems continues to increase rapidly,

The objective of the research is to provide an s-parameter based analysis of

3. What are the delimitations?

4. Enumerate the importance of the study

The study focused on the importance of designing a Electrostatic discharge

The simple approach of minimizing capacitance while maintaining high

Starting with a standard 5 0ohms system as is commonly found in RF

One last consideration is to determine whether this analysis, performed for a

4. Processes to arrive at a conclusion in order to meet the

A Detailed s-parameter analysis of R circuits with different ESD protection

Title: The State of the Art of Electrostatic

I. Describing the Tools of Research

a. The Library and its Resources

The researchers used several library resources at their disposal to provide

b. The Computer and its Software

The research followed the standard in getting measurement. It exhibits

Not stated in the article.

e. The Human Mind