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Constraint Checking
• check_timing -verbose is a powerful construct in Primetime and is recommended
to run on all designs to check the constraints. Primetime can report unconstrained
clocks in the design, combinational timing loops, inputs or outputs that are not
constrained, multiple clocks clocking the same flop or flops that do not have a
clock defined on them. This aids the designer to identify incorrect or undefined
constraints earlier in the cycle.
By default, report_constraint generates all the violations in the design and the reports
can be segregated by using appropriate switches. For example, to report only max fanout
violations, a -max_fanout switch can be added.
Timing Reports
• report_timing reports design timing information for each path group (or clock
group) and offers several switches to segregate the timing results based on max
delay, min delay, recovery, removal etc. The level of detail that can be viewed in
the reports can also be customized. Simple syntax for this construct is
# Detailed timing report that traces clocks at both launch and capture flops with all nets,
input pins and a maximum of 1000 paths.
report_timing -from [get_clocks clk] -to [get_clocks clk] -path full_clock_expanded
-nets \
-input_pins -capacitance -transition -max_paths 1000 -nworst 100 -delay max
pwd
/
proj/verde_pd11/kutukuru/DRMDMA/NL1p0/main/pd/tiles/drmdma_t_TileB
uilder_Aug06-1329_drmdma_t_exp1
zless
rpts/PtTimScanShiftMultTyptyprc110ctt0p85v110cReRouteSiStp/clock_freque
ncy.rpt.gz
=== TEST_SCLK ===
Period: 4.545 ns
Slack: 0.524 ns
****************************************
Report : timing
-path_type full_clock_expanded
-delay_type max
-input_pins
-nets
-nworst 10
-max_paths 10000
-unique_pins
-group **clock_gating_default**
-transition_time
-capacitance
Design : drmdma_t
Version: D-2009.12-SP2
zless
rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/update_timing.log.g
z
report_disable_timing
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/tie_fanout.rpt.gz
Report : timing
-path_type full
-delay_type max
-input_pins
-nets
-nworst 10
-max_paths 10000
-unique_pins
-transition_time
-capacitance
-crosstalk_delta
Design : drmdma_t
Version: D-2009.12-SP2
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/si_qor.rpt.gz
****************************************
Report : qor
Design : drmdma_t
Version: D-2009.12-SP2
****************************************
Timing Path Group 'async_default' (max_delay/setup)
---------------------------------------------
Levels of Logic: 15
---------------------------------------------
---------------------------------------------
Levels of Logic: 11
---------------------------------------------
---------------------------------------------
Levels of Logic: 14
---------------------------------------------
---------------------------------------------
Levels of Logic: 34
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 9
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 20
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 4
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 4
---------------------------------------------
ESCOB
ESCOB
---------------------------------------------
Levels of Logic: 3
Critical Path Length: 0.51743
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 1
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 2
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 3
---------------------------------------------
ESCOB
---------------------------------------------
Levels of Logic: 2
---------------------------------------------
ESCOB
ESCOB
Cell Count
---------------------------------------------
---------------------------------------------
ESCOB
ESCOB
Area
---------------------------------------------
---------------------------------------------
ESCOB
ESCOB
---------------------------------------------
clock_gating_setup Count: 15
max_capacitance Count: 17
min_capacitance Count: 85
max_fanout Count: 23
---------------------------------------------
when you set the timing analysis for BC- WC mode , the same clock path is
subjected to both fast op-cond and the slow op-cond,which introduces
pessimism .
A setup check at a flip-flop in a circuit ensures that the latest arriving signal at
the data pin arrives before the earliest arriving signal on the clock pin.
Similarly, a hold check ensures that the earliest arriving data signal arrives
after the latest arriving clock signal. The earliest or latest arriving signal on the
data pin of a flip-flop is usually triggered by another flip-flop.
If both the clock and the data signals share a portion of the clock network ,
then for common clock network , a pessimism ( maximum delay - minimum
delay ) will be introduced , we need to remove the same ,also if clk source
insertion delays are defined they do count.
Static timing analysis in a chip is largely dependent on Process, Temperature and Voltage
variations (PVT), the cell delays and interconnect delays vary largely with these factors.
Hence it is necessary to run timing analysis in both worst and best case operating
conditions and ensure we meet setup/hold requirements for the chip.
For worst case corners, we specify the chip running at high temperature, low voltage and
a slow process (high cap). For best case corner, the voltage is high, temperature is low
and a fast process (low cap). Setup is more problematic in slow corner because of larger
cell/interconnect delays and hold is more problematic in the fast corner.
Another factor that needs to be considered during timing analysis is on-chip variation
(OCV). On a single chip, there can be variations for two exactly similar gates due to other
variables during manufacturing process. This variation can be anywhere between 8-12%
and needs to be included in timing analysis for a more accurate and foolproof picture.
To add OCV analysis in Synopsys Primetime, we use timing derate factor for min/max
cases (8-12%) as shown below. This specifies that the min paths can be faster than the
max paths by 40% !
However, if you look at the reports carefully, you will notice that Primetime is overtly
pessimistic i.e. if there is a common branch of clock tree between launch and capture
flops, Primetime varies this clock tree delay depending on OCV (for example, for setup
analysis, it will slow down the common clock tree branch delay for launch flop and will
fasten the same branch to capture flop!)
To counter this, Clock Reconvergence Pessimism Removal (CRPR) feature is added in
Primetime. CRPR is enabled by using the command below
By enabling this feature, Primetime looks at the common logic in clock and data path,
removes the difference between their max and min delays thus projecting a more realistic
picture.
For more details on OCV and CRPR, please refer to the paper at the link below.