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Then the DFT region is exercised for all DFT activities, such as DFT structures insertion, pattern
generation and verification.
This section identifies the necessary documents/trainings related to TSB level, for successful
execution of DFT activity and pattern delivery to Product Engineering.
Update all these information into ATPG prep to give state of the TSB that help cross-functional team
to expect the possible outcome of ATPG results.
Note : Please use the appropriate PM number & revision for each prep.
Knowledge of these Memory BIST information help to execute the RAMBIST in right manner and
prevent the false simulation failures. Apart from these details, also note if the TSB contain non-PMC
standard RAMBIST architecture, such as MIPS and ARM.
ARM RAMBIST Architecture
Refer and populate below CAD component to understand the procedure to execute RAMBIST flow in
PMC.
PMC SV RAMBIST application note (cad_dd_00938)
This CAD component consists of reference manual to describe the PMC RAMBIST structure and flow
to generate RAMBIST wgl. Fill up the jtag_bist_vector_setup.gt.tcl to generate jtag_info.txt and
RAMBIST WGL. During the dry run phase, perform no-timing simulation of all RAMBIST structures in
a TSB. Make sure side-B of DPRs are also exercised without fail. Upon availability of timing clean
SPEF (in RAMBIST mode), the timing simulation must be completed by tape-in phase.
Other top DFT activities begins only after confirming that BSDL verification is passing for at least UDR
chain integrity test.
These Top-mapped WGLs (all modes of all instances) are expected to be simulated (no-timing) prior
to tape-out date. ATPG team is advised to align with PE and PD on number of patterns to be
simulated, in case of any deviation from this milestone, which can happen due to functional ECOs
close to tape-out date.
The Top-mapping flow currently generates 83k resim testbench, whereas actual production test
program is 93k. So, to ensure no translation errors from 83k to 93k, ATPG team expected to
simulate at least 5 patterns from 93k production test program resim testbench obtained from PE.
This activity is expected to be completed prior to silicon bring-up.
During ICTEST only these IB/OB chains of each TSB are made active (for shift and capture), through
scan_en_i & scan_en_o signals as discussed in TSB DFT-005 architecture. Core chains of each
TSB are disconnected and turned off (no shift), through scan_en_c UDR bit.
Following document describes the flow to execute Inter-connect Test (ICTEST) by reading all the TSB
level PDFs.
ICTEST Flow using PDFs (Prepare Detected Faults)
7.1.2 Tape In
ATPG Quality Checklist (Pre-tapeout)
DFT Pre Tape-out Verification Checklist