VLSI Design

Assignment #1
Design, Characterization, and Use of Custom
Standard Cells
 INTRODUCTION

This project demonstrates the Use of Cadence dfII tools to implement

the layout of 4 standard cell elements (NOT,2-input NAND, 2-input
NOR, and 2-input XOR).
The design Project accomplished the following
• Layout designs of 2-input XOR,NOT,NAND,NOR gates were
implemented using Cadence Custom IC design tools and TSMC
0.18micrometer technology
• The devices were built from component pmos and nmos
transistors, the transistor sizes were chosen so as to as to
implement a low power circuits with reduced area design.
• A DRC check was used to verify the layout design against
process-specific rules and limitations.
• Simulation or the devices were carried out in an Analog
Environment to determine the delay times, rise and fall times
and power consumption.
• The simulations were repeated with the circuit parasitic
capacitances.
INVERTER (NOT)
This was implemented by connecting n-mos and p-mos transistors in
series with each other
The size of both the nmos and pmos (W/L) were chosen at 220n/180n,
representing minimum sizes they could be scaled to, without violating
DRC rules.
Standard cell dimensions of the inverter was 7.75um by 2.830um
(height-width) representing a total area of 21.93um2
Input pins were connected to the poly and out put to metal 1.
Metal 1 width was also reduced to 0.25um to further minimise space
and allow for greater routing.
The inverters final dimensions were 7.75um in height by 2.83um.The
height represents the standard cell design which was used for
subsequent gate designs.
The simulation of the inverter was carried out using a modified circuit
consisting of four inverters in series Connected to a v pulse and vdc
generator
the vdc generator had its DC voltage set to 1.8 V.
the vpulse generator had its properties set as follows:
DC voltage: 0 V
Voltage 1: 0 V
Voltage 2: 1.8 V
Delay time:200 s
Rise Time 200p s
Fall time: 200p s
Pulse width: 3.6n s
Period: 8n s
From the output graph the following were recorded
Rise Input Rise dx/dy (ps) dx/dy/2
(ns) Output (ps)
(ns)
10% 4.133 4.221 87.4 43.7
Voltage
90% 4.235 4.239 57.67 28.835
Voltage
Input rise 0.102 Output 0.018
time rise time
fall Input fall
(ns) Output
 (ns)
10% 8.346 8.407 60.31 30.155
Voltage
90% 8.277 8.366 88.61 44.305
Voltage
Input FALL 0.069 Output fall 0.041
time time

The average delay was (43.7+28.835+30.155+44.305) /4 = 36.748ps

The power consumed by the inverter was obtained by placing two 0V

D.C. sources as passive devices in our circuit to isolate the inverters
from the remaining circuit . Using the calculator to integrate current
over one period, and multiplying by 1.8V we have 8.006fJ

Average power = 8.006fJ/T

= 8.006f/8.067n
= 0.99uW at 125MHz

The transfer characteristics was obtained using a D.C. Response

Analysis for the inverter to obtain switching values of 583.6mV
at1.623V(90%) and 738.8mV at 181.1mV(10%)

The same tests were repeated using parasitic capacitances. This was
achieved by setting the DRC switches to ‘parasitic capacitance’ during
the extraction process
From the output graph the following were recorded
Rise Input Rise dx/dy (ps) dx/dy/2
(ns) Output (ps)
(ns)
10% 4.126 4.216 90.03 45.015
Voltage
90% 4.24 4.30 63.79 31.895
Voltage
Input rise 0.114 Output 0.084
time rise time
fall Input fall Output
(ns) (ns)
10% 8.349 8.415 66.46 33.23
Voltage
90% 8.279 8.372 92.87 46.435
Voltage
Input fall 0.007 Output 0.043
time fall time

The average delay was (45.015+31.895+33.23+46.435) /4 = 39.143ps

The power consumed by the inverter with parasitic capacitances was

obtained by placing two 0V D.C. sources as passive devices in our
circuit to isolate the inverters from the remaining circuit . Using the
calculator to integrate current over one period, and multiplying by 1.8V
we have

5.843fX1.8= 10.518fJ

Average power = 10.518fJ /T

= 10.518fJ /8.092n
= 1.299uW at 125MHz

INVERTER SCREENSHOTS

INVERTER OUTPUT
DC RESPONSE

DELAY CHARACTERISTICS

FALL/RISE TIME
DELAY XTICS WITH PARASITIC CAPACITANCE
MEASURING DELAY AND POWER(SCHEMATIC)

MEASURING DELAY
LAYOUT
THE 2 INPUT NAND GATE
This layout was implemented using a combination of 3 nmos and pmos
cells each. The P-channel transistors are connected in parallel while
the two N-channel are connected in series The overall dimensions for
this gate were height 7.75um by 5.100um in Width giving a total area
of 39.525um2
The delay characteristics as obtained from the graph are recorded as
follows

Rise Input Rise dx/dy (ps) dx/dy/2

(ns) Output (ps)
(ns)
10% 4.138 4.292 154.1 77.05
Voltage
90% 4.3179 4.3702 52.355 26.175
Voltage
Input rise 0.1799 Output 0.0787
time rise time
fall Input fall Output
(ns) (ns)
10% 16.413 16.506 92.535 46.267
Voltage
90% 16.312 16.425 112.54 56.27
Voltage
Input fall 0.101 Output 0.081
time fall time
The average delay is (77.05+26.175+46.267+56.27) /4 = 51.44ps

The power consumed by the NAND was obtained by placing two 0V

D.C. sources as passive devices in our circuit to isolate the NAND from
the remaining circuit . Using the calculator to integrate current over
one period, and multiplying by 1.8V we have
6.13fX1.8= 11.04fJ

Average power = 11.04fJ /T

= 11.04fJ /8.167n
= 1.352uW at 125MHz
The same tests were repeated using parasitic capacitances
From the output graph the following were recorded
Rise Input Rise dx/dy (ps) dx/dy/2
(ns) Output (ps)
(ns)
10% 4.147 4.339 182.34 91.17
Voltage
90% 4.258 4.45 192.5 96.25
Voltage
Input rise 0.111 Output 0.111
time rise time
fall Input fall Output
(ns) (ns)
10% 16.44 16.57 133.8 66.9
Voltage
90% 16.3 16.46 156.9 78.45
Voltage
Input fall 0.14 Output 0.11
time fall time

The average delay is (91.17+96.25+66.9+78.45) /4 = 83.1925ps

The power consumed by the NAND was obtained by placing two 0V

D.C. sources as passive devices in our circuit to isolate the inverters
from the remaining circuit . Using the calculator to integrate current
over one period, and multiplying by 1.8V we have
10.02fX1.8= 18.50fJ

Average power = 18.50fJ /T

= 18.50fJ /8.016n
= 2.3uW at 125MHz
 A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NAND TRUTH TABLE

OUTPUT
DELAY
POWER OUTPUT/ MEASUREMENT SCHEMATIC

LAYOUT
THE 2 INPUT NOR GATE

This layout was implemented using a combination of 2 nmos and pmos

cells each. P-mos are connected in series while n-mos in parallel The
overall dimensions for this gate were height 7.75um by 5.00um in
Width representing a total area of 38.75um2

The delay characteristics as obtained from the graph are recorded as

follows
Rise Input Rise dx/dy (ps) dx/dy/2
(ns) Output (ps)
(ns)
10% 12.15 12.29 141.7 70.85
Voltage
90% 12.4 12.55 143.9 71.95
Voltage
Input rise 0.25 Output 0.26
time rise time
fall Input fall Output
(ns) (ns)
10% 16.33 16.469 136.04 68.02
Voltage
90% 16.27 16.41 131 65.5
Voltage
Input fall 0.06 Output 0.059
time fall time

The average delay is (70.85+71.95+68.02+65.5) /4 = 69.08ps

The power consumed by the NOR was obtained by placing two 0V D.C.
sources as passive devices in our circuit to isolate it from the
remaining circuit . Using the calculator to integrate current over one
period, and multiplying by 1.8V we have
7.8fX1.8= 14.147fJ

Average power = 14.147fJ /T

= 1.801uW at 125MHz

The same tests were repeated using parasitic capacitances

From the output graph the following were recorded
Rise Input Rise dx/dy dx/dy/2
(ns) Output (ps) (ps)
(ns)
Rise Input Rise dx/dy dx/dy/2
(ns) Output (ps) (ps)
(ns)
10% 12.15 12.343 193.01 96.505
Voltage
90% 12.488 12.685 196.87 98.435
Voltage
Input rise 0.338 Output 0.342
time rise time
fall Input fall Output
(ns) (ns)
10% 16.346 16.537 190.71 95.355
Voltage
90% 16.28 16.45 174.5 87.25
Voltage

Input fall time 0.066ps output fall time 0.087ps

The average delay is (96.505+98.435+95.355+87.25) /4 = 94.386ps

The power consumed by the NOR was obtained by placing two 0V D.C.
sources as passive devices in our circuit to isolate it from the
remaining circuit . Using the calculator to integrate current over one
period, and multiplying by 1.8V we have
10.640fX1.8= 19.15fJ

Average power = 19.15fJ /T

= 21.29fJ /8.233n
= 2.32uW at 125MHz

NOR TRUTH TABLE

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

NOR OUTPUT
POWER OUTPUT
LAYOUT
THE 2 INPUT XOR GATE

This layout was implemented using a combination of 6 nmos and pmos

cells,3 of each. The overall dimensions for this gate were height
7.75um by 7.63um in Width
The delay characteristics as obtained from the graph are recorded as
follows

Rise Input Rise dx/dy (ps) dx/dy/2

(ns) Output (ns) (ps)
10% 4.132 4.272 139.73
Voltage
90% 4.278 4.409 130.69
Voltage

fall Input fall Output

(ns) (ns)
10% 8.369 8.511 142.02
Voltage
90% 8.281 8.424 142.44
Voltage

The average delay is (43.7+28.835+30.155+44.305) /4 = 36.748ps

The power consumed by the XOR was obtained by placing two 0V D.C.
sources as passive devices in our circuit to isolate the inverters from
the remaining circuit . Using the calculator to integrate current over
one period, and multiplying by 1.8V we have
10.230fX1.8= 7.698fJ

Average power = 7.698fJ /T

= 7.698fJ /8.045n
= 2.31uW at 125MHz

The same tests were repeated using parasitic capacitances

From the output graph the following were recorded
Rise Input Rise Output dx/dy (ps) dx/dy/2
(ns) (ns) (ps)
10% Voltage 16.38 16.62 236.9
90% Voltage 16.625 16.886 261.05
 fall Input fall Output
(ns) (ns)
10% Voltage 20.286 20.552 266.05
90% Voltage 20.053 20.375 322.78

The average delay is (43.7+28.835+30.155+44.305) /4 = 36.748ps

The power consumed by the XOR was obtained by placing two 0V D.C.
sources as passive devices in our circuit to isolate the inverters from
the remaining circuit . Using the calculator to integrate current over
one period, and multiplying by 1.8V we have
11.830fX1.8= 21.29fJ

Average power = 21.29fJ /T

= 21.29fJ /8.011n
= 2.65uW at 125MHz

XOR TRUTH TABLE

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
XOR OUTPUT

RISE/FALL TIMES
This layout was implemented using a combination of 4 of the cells
above.( XOR,NAND,NOR,NOT)
The overall dimensions for this gate were height 7.75um by 7.64um in
Width
The delay characteristics as obtained from the graph are recorded as
follows

Rise Input Rise Output dx/dy (ps) dx/dy/2

(ns) (ns) (ps)
10% Voltage 4.694 4.99 295.8
90% Voltage 4.959 5.084 125.7
 fall Input fall Output
(ns) (ns)
10% Voltage 8.775 9.064 288.5
90% Voltage 8.626 8.985 358.6

From the table, the inverter rise time is 102ps and fall time is 18ps
The average delay is (43.7+28.835+30.155+44.305) /4 = 36.748ps

The power consumed by the Adder was obtained by placing two 0V

D.C. sources as passive devices in our circuit to isolate the inverters
from the remaining circuit . Using the calculator to integrate current
over one period, and multiplying by 1.8V we have
53.794fX1.8= 96.83fJ

Average power = 96.83fJ /T

= 96.83fJ /8.166n
= 11.8uW at 125MHz

The same tests were repeated using parasitic capacitances

From the output graph the following were recorded
Rise Input Rise Output dx/dy (ps) dx/dy/2
(ns) (ns) (ps)
10% Voltage 4.686 4.88 194
90% Voltage 5.205 5.309 104

fall Input fall Output

(ns) (ns)
10% Voltage 8.804 8.937 133.1
90% Voltage 8.636 8.666 30

From the table the inverter rise time is 102ps and fall time is 18ps
The average delay is (43.7+28.835+30.155+44.305) /4 = 36.748ps

he power consumed by the Adder was obtained by placing two 0V D.C.

sources as passive devices in our circuit to isolate the inverters from
the remaining circuit . Using the calculator to integrate current over
one period, and multiplying by 1.8V we have
53.808fX1.8= 96.855fJ

Average power = 96.855fJ /T

 = 96.855fJ /8n
= 12.1uW at 125MHz

THE FULL ADDER CIRCUIT

A B CARRY IN CARRY OUT SUM

0 0 0 0 0
0 0 1 0 1
0 0 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
OUTPUT
AND GATE