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DESIGN IDEAS

ADSL Line Driver Design Guide, Part 2


by Tim Regan

Part one of this article appeared in the power dissipation. In an actual and there happens to be a significant
Linear Technology X:1 (February 2000) DSL design this approach overesti- level of noise interference and/or low
and is also available on the mates the typical power dissipation line impedance conditions. Design-
Linear T echnology web site at with a DMT signal by 10% to 20% ing to handle the conservative
www.lineartech.com/ezone/dsl.html. because a data transmission is not estimate provides a margin of safety
It discusses the different DSL stan- always at the maximum output power for reliable operation.
dards, characteristics of the DSL level. The DSP intelligence built into
signals, the design of differential driv- the system automatically adjusts the The Input Variables
ers for DSL and the requirements for transmitted power level and frequency Before a design can begin, the follow-
amplifiers used in this application. spectrum for each connection made. ing information must be known:
With shorter phone-line loops, the which DSL standard is to be used,
Design Calculations, Volts, transmitted power is reduced; with Full Rate or G.Lite, whether upstream
Amps and Power Dissipation longer loops, not all of the channels (CPE) or downstream (CO). These
It is very important to consider the are used and the number of data bits same equations apply for any DSL
power requirements of the line driver per channel is reduced. The maxi- standard (HDSL and HDSL2 for
in DSL applications. Although a nomi- mum transmitted power is provided example) with some changes to the
nal power level of 100mWRMS or less when the connection loop length is in input parameters (see Table 1).
into a 100 load does not seem to be the range of 4000 feet to 10,000 feet
a lot of power, the driver must handle
large peak signals and therefore Table 1. Input variables
requires a larger than nominal power
supply voltage. This increases both Typical Values for
the power dissipation in the driver Symbol Parameter Description ADSL
package and the peak current capa- 20dBm
bility needed from the power supply. (Full Rate, CO)
This issue becomes most critical in 16.3dBm
central office designs, where many PLINE (dBm) Line Power RMS power to be put on the line (G.Lite, CO)
DSL ports are included on a single 13dBm
card powered from one supply. Addi- (Full Rate and
tionally, the heat generated by the G.Lite, CPE)
drivers must be handled properly to Peak-to-average ratio for the DMT
ensure reliable operation. PAR Crest Factor 5.3
signal
This section will provide the calcu- Line Characteristic impedance of the
lations necessary to determine the ZLINE 100
Impedance line
voltages, currents and power dissipa-
tion for an ADSL driver of either The turns ratio of the line coupling
n Turns Ratio 1:1 or higher
standard. It can be quite useful to transformer
place these equations in a spread- The power loss of the transformer
PLOSS (dBm) Insertion loss 0.2dBm to 2dBm
sheet to allow quick observation of being used
the effect of different design variables A function of the output saturation
on the overall system. Assuming that voltages (positive and negative
Headroom
a wide band, low distortion driver has VHR swing) of the driver used. Head- 2V to 5V
Voltage
been selected (the LT1795 and LT1886 room is twice the larger of the two
are excellent choices), the three most saturation voltages.
important system issues to consider Total quiescent (no input signal)
are the total supply voltage, the peak Quiescent
IQ supply current of the driver that is 10mA to 30mA
output current and the driver power Current
not diverted to the load.
dissipation required. Maximum peak-to-peak differential
For these calculations, the RMS eIN Input Voltage input voltage from the AFE (analog 1.5V to 4.5VP-P
voltages required are treated as DC front end)
levels for the purpose of estimating

26 Linear Technology Magazine May 2000


DESIGN IDEAS
Basic System Requirements determined from the next section.
This is the RMS voltage between
The following equations determine Trying to design a system with less
the two amplifier outputs. If the RBT
the essential operating requirements supply voltage or current capability
resistors are properly sized this volt-
independent of the driver amplifier using conventional transformer
age is twice the RMS voltage of the
used in the design: termination resistors will result in
transformer primary.
Line Power in Watts: clipping and transmission data errors.
Peak driver amplifier output current:
Figure 1 also compares the differ-
PLINE(dBm)
10 EPRI(RMS) PAR ent ADSL standards with the central
PLINE(W) = 10 1mW (1) IPEAK = (9) office, downstream, Full Rate ADSL,
ZPRI
example: 20dBm = 100mW. which requires the most current and
= IPRI(RMS) PAR voltage. The reduced line power
RMS Line voltage:
The peak current handling capa- requirements for the downstream
eLINE(RMS) = PLINE(W) ZLINE (2)
bility is key to selecting the driver G.Lite and the upstream Full Rate
amplifiers. and G.Lite modems produce designs
Power to the primary of the
Power supplied by the driver with lower voltage and current
transformer:
amplifiers: requirements.
PPRI(dBm) = PLINE(dBm) + PLOSS(dBm) (3)
PPRI(dBm)
POUT = eAMPLIFIERS(RMS) IPRI(RMS) (10) Important Driver
PPRI(W) = 10 10
1mW Overall line driver voltage gain: Characteristics: Headroom
Impedance of primary of the Voltage and Quiescent
eLINE(RMS) 2 PAR
transformer: AV(TOTAL) = (11) Current
eIN
To determine the required supply volt-
ZLINE Differential amplifier voltage gain:
ZPRI = (4) age, power consumption and power
n2 dissipation of the driver, the head-
AVDIFF(AMPLIFIERS) = (12)
Transformer termination resistors: room voltage and required quiescent
eAMPLIFIERS(RMS) 2 PAR current of the driver amplifier must
Z PRI
R BT 1 , R B T 2 = (5) eIN be considered.
2 Minimum total supply voltage for
Primary RMS voltage: The turns ratio of the transformer the amplifiers:
e PRI(RMS) = P PRI(W) Z PRI used is critical to the overall design.
(6)
Figure 1 illustrates the minimum total VSUPPLY(MIN) = EAMPLIFIER(RMS) (13)
Transformer primary RMS current: supply voltage across the driver and PAR + VHR
e PRI(RMS) the peak driver output current
I PRI(RMS) = ( 7 ) required as a function of the turns The actual supply voltage for the
Z PRI
ratio. These are the absolute mini- driver amplifier must be set above the
Driver amplifier RMS output voltage: mum requirements based on an ideal minimum peak-to-peak amplifier out-
e AMPLIFIER(RMS) = (8)
amplifier that has 0V headroom and put swing to provide for the headroom

) )
is therefore able to swing fully to voltage to prevent peak signal clip-
Z PRI + ( 2 R BT) either supply voltage rail, and an ideal ping. Using a supply voltage greater
e PRI(RMS) transformer, with zero insertion power than this minimum value will increase
Z PRI
loss. A practical implementation will the power dissipation in the driver
require a larger supply voltage, as amplifiers.
MINIMUM DRIVER PEAK OUTPUT CURRENT (mA)

40 800
V+
MINIMUM TOTAL SUPPLY VOLTAGE (V)

35 700 VCC VSAT+


FULL RATE VS FULLRATE IPEAK + 1
VCC VHR RL = 2k VOUT
OUTPUT SATURATION VOLTAGE (V)

30 600
G.LITE VS 2
VOUT
25 UPSTREAM VS 500 RSAT+ 3 RL = 25 RSAT+ =
G.LITE IPEAK IOUT
20 400 + 4
VSAT+ VHR VS = 15V
15 300 AMPLIFIER VEE
VOUT
OUTPUT 4 RSAT =
10 200 STAGE + IOUT
VSAT 3 RL = 25
LOAD
5 100 2 VOUT
UPSTREAM IPEAK
0 0 RSAT 1 RL = 2k
1 1.5 2 2.5 3 3.5 4 VSAT
V
TURNS RATIO (n) 50 25 0 25 50 75 100 125
VEE
TEMPERATURE (C)
Figure 1. Minimum peak-to-peak driver
output voltage and peak output current Figure 2. Typical output stage model and common data sheet curves
required, ideal amplifier and transformer are used to determine amplifier headroom voltage

Linear Technology Magazine May 2000 27


DESIGN IDEAS
30

ACTUAL AMPLIFIER QUIESCENT CURRENT (mA)


the amplifier, VHR, should be twice
ISUPPLY+ IQ (NO SIGNAL)
25 the larger of the two output satura-
tion voltages. This will ensure that
IOUTPUT STAGE 20
IBIAS SOURCING
the output will not clip at all during
15
maximum peak signal conditions.
ILOAD
INPUTS With VSUPPLY set large enough to
10 prevent signal clipping the total power
IBIAS
IOUTPUT STAGE
LOAD
IPRI(RMS) consumption from the supplies can
5
SINKING be determined with Equation 14:
ISUPPLY
0
Power consumption of the com-
500 400 300 200 100 0 100 200 300 400 500 plete line driver:
IQ = ISUPPLY+ ILOAD SINKING SOURCING
LOAD CURRENT (mA) PIN = VSUPPLY (IQ + IPRI(RMS)) (14)
Figure 3. Much of an amplifiers quiescent current is transferred to the load current = (VEXTRA + VHR + VAMPLIFIER(RMS) PAR)
(IQ + IPRI(RMS))
The headroom voltage of an ampli- around 50C. To determine the fixed
fier is determined from either the voltage part of the model for the posi- This equation introduces two new
guaranteed specification for output tive output swing, VSAT+, evaluate the terms, VEXTRA and IQ. VEXTRA is the
voltage swing or from characteristic top curve with RL = 2k. From the total additional power supply voltage
curves showing output saturation curve it can be seen that the output above VSUPPLY(MIN) that is actually used
voltage vs output current or vs tem- will swing to within 1.2V of the posi- to power the driver amplifiers. For
perature with different load currents. tive supply. Because the curve was example, if the minimum total supply
The headroom voltage is the differ- generated using supplies of 15V, the voltage for a design is determined to
ence between the supply voltage rail load current at 50C is only 13.8V/ be 20V (or 10V) but the actual sup-
and the maximum output voltage 2k or 7mA. To determine the value plies available are 12V, then the
swing, both positive and negative, for for the series resistance in the model, VEXTRA term will be 24V 20V or 4V.
a given load current. Figure 2 shows determine the change in output satu- The total power consumption of each
a simple model for determining an ration voltage with a change in load line driver is very important when
amplifiers output saturation voltages current. At the same 50C junction sizing the power supply for both volt-
and an example of a useful data sheet temperature point, evaluate the upper age and current capability to be used
curve. curve with RL = 25. With this load in the system. This becomes most
During large signal transients, the the output swings to within 1.8V of significant when multiple DSL ports
transistors in the output stage of the the positive rail and the load current are to be powered from a predesigned
amplifier will fully turn on to pull the is 13.2V/25 or 528mA. The series power supply. The power supply could
output as close as possible to the resistance is then VSAT/IOUT (0.6V/ become the limiting factor to the num-
supply voltage rails. The limitation on 521mA), which is 1.15. From these ber of ports allowable.
how close the signal can swing can be values, the positive amplifier satura- The quiescent current, IQ, is basi-
modeled as a fixed voltage drop across tion voltage will be 1.2V + 1.15 cally the operating supply current of
the transistor being driven with a IPEAK where the value of IPEAK depends the driver amplifiers. This is the cur-
resistance in series. This resistance on the particular modem design. 4500
FULL RATE CO (15V)
increases the voltage swing limitation Applying the same approach for the 4000 FULL RATE CO (12V)
in proportion to the amount of load amplifier swing towards the negative 3500 G.LITE CO (15V)
current the transistor must source or rail results in saturation voltage model 3000 G.LITE CO
sink. The combined total of the fixed parameters of 1.2V in series with a (12V)
PDISS (mW)

2500
voltage drop and the voltage across resistance of 2.2.
2000
the resistor is called the output satu- With these values modeling the
ration voltage. The values to use to output saturation characteristics of 1500

model this characteristic can be the LT1795, at any level of peak out- 1000
CPE (15V)
determined from a data sheet curve. put current the output stage will 500 CPE (12V)
G.LITE CO (12V)
CPE (12V)
Figure 2 shows the curve that appears saturate or clip when swinging 0
1 1.5 2 2.5 3 3.5 4
on the LT1795 data sheet. towards the negative supply before it TURNS RATIO (n)
This curve shows the positive and will clip on the positive swing, due to ASSUMPTIONS
negative amplifier saturation voltages the higher effective series resistance FULL RATE G.LITE CPE
vs junction temperature with two dif- voltage drop. Transmission errors can IQ 28mA 18mA 14mA
VHR 3V 2.5V 2V
ferent values of load resistance. DSL occur if either output swing excur- PLOSS 0.5dBm 0.5dBm 0.5dBm
line drivers typically run warm, so the sion clips, so when sizing the total
area of interest on the curve will be in supply voltage requirement for the Figure 4. Driver power dissipation vs
the range of junction temperature driver the total headroom voltage of turns ratio: a practical implementation

28 Linear Technology Magazine May 2000


DESIGN IDEAS
rent required to bias the internal cir- The power dissipated in the driver required. Three factors that add to
cuitry of the amplifiers. In general, package is important to consider when this power dissipation are the ampli-
high speed, high output current addressing heat management issues. fier headroom voltage, the amplifier
amplifiers that process signals with To minimize power dissipation, the quiescent operating current and the
very low distortion require signifi- driver should be powered from a power power loss of the line-coupling trans-
cantly more operating current than supply with voltages set to the former. Attention to these three factors
general-purpose amplifiers. This cur- minimum required. Most imp- when selecting an amplifier and trans-
rent adds to the power consumption lementations, however, use existing former can optimize the overall power
and power dissipation of the driver power supply voltages, typically 15V, dissipation. Analysis of the sensitivi-
package, because it must always be 12V or just the 12V rail for the line ties of the amplifier power dissipation
supplied whether there is signal driver/receiver. Figure 4 provides an (see Equation 15) for each of these
applied or not. However, the power indication of the actual power dissi- three terms is summarized in Table 2.
dissipation in the driver for the quies- pation in the line-driver amplifier This shows the effect on total package
cent current is not just a fixed DC package with commonly available dissipation for each factor taken indi-
power of IQ VSUPPLY. As seen in Figure supply voltages and a range of trans- vidually with the other two factors set
3, much of the quiescent current is former turns ratios. This is a practical to zero. The term n is the transformer
diverted to the amplifier output stage example where values have been turns ratio.
and becomes part of the load current assumed for the amplifier headroom The factors in Table 2 provide a
while processing a signal. The curve and quiescent current and some rough indication of the additional
shown is again for the LT1795 driver. transformer power loss. The lower power dissipation from these three
With no load, all of the 30mA quies- power upstream modems require less system variables. The combined effect
cent current flows from the positive operating current, which helps to on power dissipation from IQ, VHR and
supply through the amplifier to the minimize the package power dissipa- PLOSS must still be determined from
negative supply. However, when the tion. If the turns ratio is too low for Equation 15.
load is sourcing or sinking 500mA, the given supply voltage, the lines on
only 12mA flows through the ampli- the graph terminate because the sup- Optimizing Power
fier, the remaining 18mA is taken by ply voltage is not large enough to Dissipation, Adjustable
the output stage and diverted to prevent clipping of the DMT signal Quiescent Current and
become part of the load current. To peaks. Shutdown
obtain an accurate estimate of the As previously stated, the power Several high speed power amplifiers
average power dissipation of the driv- dissipation in the driver is an impor- from Linear Technology provide the
ers, this sharing of the quiescent tant concern as it generates heat in ability to externally set the operating
current should be taken into account. the system. For each of the ADSL quiescent current. For the design of
This will prevent overdesign of the standards, a certain minimum any of the DSL standards, this allows
thermal management area of con- amount of power dissipation is for fine tuning the amplifiers
cern. The IQ term in Equation 14
should be the only current that con-
tinues to flow through the amplifier at Table 2. Additional power dissipation factors
the load current level of IPRI(RMS). The Full Rate
diverted quiescent current is included ADSL Full Rate G.Lite and G.Lite Additional
in the IPRI(RMS) term. Standard Downstream Downstream Upstream Power Dissipation
Unfortunately, this curve of quies- Minimum
cent operating current vs load current Power
is not found on typical data sheets. 860mW 367mW 172mW
Dissipation,
Some characterization of the chosen PMIN
amplifier should be done. The design Amplifier
of amplifier power output stages is Per 1mA of IQ, PDISS =
Quiescent 33.5mW/n 22.14mW/n 15mW/n
varied and has a direct effect on the (FACTOR) (IQ/1mA)
Current, IQ
diversion of the total supplied operat-
ing quiescent current. Total Amplifier
Per 1V of VHR, PDISS =
Power dissipated in the line driver Headroom n 31.6mW n 20.9mW n 14.1mW
(FACTOR) (VHR /1V)
amplifiers: Voltage, VHR
Per 0.1dBm of PLOSS,
PAMPLIFIERS = PIN POUT (15) Transformer PDISS =

) )
= eAMPLIFIERS(RMS) [PAR IQ + IPRI(RMS) Insertion Loss, 2.3% 2.3% 2.3%
PLOSS(dBm)
(PAR 1)] + (VHR + VEXTRA) PLOSS in dBm PMIN 1.023
0.1dBm
1
(IQ + IPRI(RMS))

Linear Technology Magazine May 2000 29


DESIGN IDEAS
VCC
operating point for minimum power
dissipation and adequate distortion
performance. There is a direct trade- 3V OR 5V ION R2
IOFF
off between the two, however. 20mA

ISUPPLY
0V
Designing for very low quiescent cur- R1
1.4V
rent significantly reduces the power 2mA
dissipation, but obtaining the lowest
distortion performance requires
additional biasing current for the IBIAS IBIAS
ON
internal amplifier circuitry. Figure 5 3V

VLOGIC
illustrates the adjustability of the SHDNREF
OFF
operating current for the LT1795. An 0V
internal current source is pro-
TIME
grammed via a single external resistor. ISUPPLY(ON) = 115 ION

The current through this source is


Figure 6. How to reduce driver supply current in an idle channel
mirrored and scaled up to become the while maintaining the receiver function
biasing current for the two amplifi-
ers. Also shown in Figure 5 is the when there is no data transmission keeps the amplifier slightly biased
effect of adjusting the operating cur- activity and can issue a signal to the and thus allows the modem to
rent on distortion. The spectrum driver to shut down operation. Many continue to monitor the line for trans-
analyzer plots show the intermodula- drivers accept this control signal and mission signals to be received. Here,
tion components from twenty carrier completely power down the internal two resistors are carefully chosen to
tones (from 200kHz to 500kHz). With circuitry. The LT1795, for example, control the amount of operating qui-
too low of an operating current, the can be shut down to consume less escent current as well as to retain a
signal on the line is far too distorted than 200A of current when not small amount of keep-alive current
and interference with other channels required to transmit data. When com- when shut down. Resistor scaling can
is inevitable. However turning up the manded to power up, the driver accommodate a direct connection to
current drops all of the distortion requires only a few microseconds to an I/O pin from the DSP processor
products into the noise floor. This reestablish full performance, an with any logic voltage level. Shutting
adjustment should be made during insignificant time when compared to down to a quiescent current level of
the evaluation of the driver under a typical communication training-up 2mA keeps the output stage active
actual transmission conditions and interval. When powered down, how- and terminates the received signal
optimized for the highest data rates ever, the output stage of the amplifier sensing resistors, resulting in a better
obtainable. loses all bias and enters a high than 10-to-1 reduction in idle-channel
The best power and thermal man- impedance state. This essentially power consumption and dissipation.
agement technique in multiple-port opens the connection to the trans-
systems or energy efficient stand- former back-termination resistors. As Thermal Management
alone modem designs is to shut off these resistors are often used to sense Depending on the ADSL standard
the driver when the line is inactive. the received signal from the line, no being applied, the power supplies and
The digital circuitry always knows signal can be developed across them the transformer turns ratio used, the
if they are left floating. driver amplifier package will dissi-
VCC Figure 6 illustrates a power saving pate somewhere between 500mW and
function, called partial shutdown, that 2W. The average power dissipation
SHUTDOWN

BIAS CURRENT BIAS CURRENT


FOR AMPLIFIER B FOR AMPLIFIER A
I = 115 IADJ
(VCC 1.3V)

SHDNREF IADJ

RADJ

Figure 5a. Proper adjustment of the operating


current minimizes spectral components, Figure 5b. Spectrum of 20 carrier tones Figure 5c. Spectrum of 20 carrier tones
adjusting the sujpply current with IQ of 12mA/amplifier with IQ of 2.2mA/amplifier

30 Linear Technology Magazine May 2000


DESIGN IDEAS
DRIVER PACKAGE
0.7" 0.5"
TOP LAYER COPPER
INTERMEDIATE COPPER
LAYERS

0.75"
BOTTOM LAYER COPPER

0.75"
13MIL VIAS THAT FILL DURING THE PLATING PROCESS

TOP BOTTOM

Figure 7a. Using PCB copper foil for heat sinking

40
LT1795CFE
vides a continuous path for heat trans- As most of the heat is dissipated in
20-PIN TSSOP PACKAGE fer from the junction of the IC, out of the area immediately surrounding the
38 WITH EXPOSED LEAD FRAME
FOR DIRECT METALLIC the plastic encapsulation, to pins that driver amplifier package, there comes
CONTACT TO PCB FOIL are directly connected to PCB copper a point of diminishing returns where
36
planes. An exposed lead frame does more copper area does not provide
JA C/W

not plastic encapsulate the under- much additional benefit. This can be
34
side metal where the IC is attached. seen in the plot of thermal resistance
This provides a metal pad that can be in Figure 7 where, beyond a total PCB
32
connected directly to PCB copper for area of 1in2, further reduction in ther-
direct transfer of heat from the IC mal resistance is minimal. One word
30
0.5 0.7 0.9 1.4 1.8 2.3 mounting junction heat source to the of caution regarding PCB planes for
TOTAL PCB FOIL AREATOP AND BOTTOM SIDES (IN2) ambient air. An exposed lead frame heat spreading is that the fiberglass
allows for very small packages, such material (typically FR-4) is a fairly
Figure 7b. Improving Heat dissipation as that used for the LT1795CFE, a good thermal insulator. Any compo-
with increased copper foil area
20-pin TSSOP, to have thermal con- nent interconnect traces that cut
times the overall thermal resistance ductivity characteristics similar to through the plane of copper signifi-
from the junction of the driver to the much larger sized packages. Very cantly reduce the effectiveness of the
ambient air will determine the rise in small packages with good thermal lateral area. Interconnect traces
operating junction temperature above conductivity can result in very dense should be made on the inner layers of
the maximum ambient temperature. multiport ADSL systems for central multilayer boards to minimize the
Most power amplifiers have a built in office applications. distance between components. The
thermal protection mechanism that The best way to spread the heat complex interconnect of the logic cir-
will disable the output stage when the generated by the driver is to use as cuits used in DSL modems usually
junction temperature exceeds typi- many planes of copper as are avail- requires a multilayer PC board that
cally 160C. Should this temperature able and to stitch them together can be put to good use in the line
ever be reached, the amplifier will through small vias from the topside of driver area.
protect itself, but data transmission the board to the bottom, as shown in Another measure that can be taken
errors will abound and most likely Figure 7. These vias should be small is to provide some forced airflow cool-
result in a data transmission discon- enough in diameter (15 mils or less) ing. A linear flow of air across the
nect. Designing a heat-spreading that they are completely filled with driver package can significantly
system to limit the driver junction solder during the plating process. This reduce the effective thermal resis-
temperature to less than 125C at the provides a continuous thermal con- tance from junction to ambient (JA)
highest expected ambient tempera- ductivity path from the top of the of the heat-spreading system. A re-
ture will ensure continuous operation. board to the bottom for the most duction of 2C/W to 3C/W for each
Fortunately, the power dissipation exposure to the ambient environment. 100lfpm (linear feet per minute) can
levels are not so high that external There are no fixed rules for determin-
heat sinks are necessarily required, ing the lateral area of the copper DRIVER
VCC
so heat spreading can usually be planes on the PCB, other than bigger V+ PIN
+
managed through planes of PCB cop- is better, and 2oz copper is a thicker 10F 0.1F 0.1F
per foil. In addition, the packaging of and therefore better thermal conduc- +
10F
most power amplifiers uses thermal tor than 1oz copper. Figure 7 also
provides an indication of the improve- +
conduction enhancements, such as 10F 0.1F 0.1F
fused or exposed lead frames. Fused ment in the heat spreading thermal DRIVER
VEE
lead frames have several package pins resistance from junction to case with V PIN
connected directly to the metal pad various amounts of copper foil area Figure 8. Recommended power
where the IC is attached. This pro- on the top and bottom sides of a PCB. supply bypassing for any design

Linear Technology Magazine May 2000 31


DESIGN IDEAS
be achieved. This is particularly
A RBT+ C
important in a multiport system +DRIVER 0.1F
housed in an enclosed case.
1:n

A Gallery of Design eRCV


100
PHONE LINE
Recommendations
B RBT D
This section will provide examples of DRIVER
driver and receiver circuits for each of 0.1F

the ADSL standards. These circuits RC VCC

provide a good starting point for imple- 3 8


menting the line interface functions +
1 RCV+
for a DSL modem. The circuits were RB 2
designed with all of the consider-
RF1
ations mentioned so far, but other RECEIVE AFE
AND
system variables, such as available eRX
ECHO
RECEIVE
INPUTS
supply voltages or AFE output and RD
CF1
FILTER
5
input dynamic range, could mandate +
some modifications. The total voltage 7
RA
gain of each line-driver design, from 6 RCV
R B = RA 4
R C = RD
the differential input voltage to the VEE
R OR RF2
actual voltage output to the phone AV = F1 RF2
RC OR RD
line, has been scaled to a value that
requires less than 3VP-P from the AFE
providing the transmitted signal. The CF2

gain of the amplifier stage is adjusted Figure 9. Basic differential receiver (4-wire to 2-wire)
to take into account the signal boost
of the transformer used as well as the
signal loss through the back-termi- to directly pick the small received filter/AFE. Many designs still prefer
nation resistors. signals out of the noise floor after to sense the differential signal across
Common to all of the designs is a passing through the receive/echo fil- the termination resistors and provide
good power supply bypassing ter. Other designs may use a second gain to the received signal before pass-
approach. This is shown in Figure 8. transformer to process the differen- ing it through the filter to the AFE.
A large- and a small-valued bypass tial received signal directly to the This basic differential receiver circuit
capacitor at the points where the sup-
plies connect to the board provide 0.1F 12V
decoupling of noise and ripple over a eIN+
wide frequency range. Additional high RC1 3 8
267 +
frequency decoupling at the driver CC1
A1 1 A RBT1 12.4 C
1/2 LT1886
and receiver supply pins is recom- 47pF 2 0.1F
T1
mended. Another large-valued bypass 1:2
RIN1
capacitor connected directly between 12V 20k eLINE
100
PHONE LINE
the supply pins of the driver helps to
RF1 1k
reduce the 2nd harmonic component RG1
10k 187
of ripple on the supply lines. This C1 0.1F
component comes from the peak cur- 1F
DRIVER CHARACTERISTICS
eIN
rent demands from each supply, + 1F C2 eLINE
1F AV = =6
which occur twice for each input sig- 10k
RG2
eIN
187 POWER CONSUMPTION: 470mW
nal cycle due to the differential RF2 1k
POWER DISSIPATION: 425mW
amplifier topology (each amplifier PEAK DRIVER CURRENT: 159mA

sources and sinks the peak current RIN2 RECEIVER COMPONENTS


20k 6 (SEE FIGURE 9)
once each signal cycle). RBT2 12.4 RA, RB: 2k
RC2 A2 7 RC, RD: 1k
267 1/2 LT1886
5 + RF1, RF2: 4.02k
The Differential Receiver 0.1F CC2
B D
CF1, CF2: 72pF (G.Lite)
47pF 4 36pF (Full Rate)
Not all DSL modems will require a eIN
RECEIVER GAIN
receiver circuit. Some analog front T1: COILCRAFT x8390A (847) 639-6400
eRX
=1
eRCV
end ICs have sophisticated circuitry OR MIDCOM 50215 (605) 886-4385
for a very wide dynamic input range Figure 10. Full Rate or G.Lite upstream (CPE) driver

32 Linear Technology Magazine May 2000


DESIGN IDEAS
12V
be set to exactly twice the value of
17 resistors RC and RD.
eIN+
4
+
14
5
The gain of the receiver is simply
A1 18 A RBT1 34.8 C the inverting gain of the received sig-
1/2 LT1795- T1 0.1F
3

CFE 1:1.2 nal path, RF1/RC and RF2/RD. In the
RIN1
driver design examples to follow, the
10k eLINE
100
PHONE LINE
receiver input resistors connect to
RF1 1k
the driver at nodes A through D. The
recommended component values for
RG 0.1F the receiver provide for unity gain
eIN 133 DRIVER CHARACTERISTICS from the received signal appearing at
eLINE
RF2 1k AV =
eIN
=9 the line to the differential receiver
POWER CONSUMPTION: 880mW output. This takes into account the
POWER DISSIPATION: 785mW
RIN2 PEAK DRIVER CURRENT: 141mA
attenuation of the line-coupling trans-
10k 8 former. A small feedback capacitor is
A2 RBT2 34.8 RECEIVER COMPONENTS
1/2 LT1795-
13 (SEE FIGURE 9) also shown that reduces the gain at a
+ 6 RA, RB: 2k
eIN
7 CFE
20
B D
RC, RD: 1k
frequency just above the received
159k
10
11 RF1, RF2: 2.37k signal bandwidth, which varies
T1: COILCRAFT x8502-A (847) 639-6400 1 CF1, CF2: 500pF
depending on the application.
RECEIVER GAIN
eRX
12V
eRCV
=1 ADSL Full Rate or G.Lite
Figure 11. ADSL G.Lite downstream (CO) line driver
Upstream (CPE) Line Driver
This driver (Figure 10) is the lowest
powered of the ADSL standards, con-
is shown in Figure 9. Each receiver signals, leaving only the received sig- suming less than 500mW. The lower
amplifier is a summing stage that nal at the differential amplifier line power, 13dBm, and resulting
sums the received signal and the outputs. This is called local echo can- lower peak current requirement allows
attenuated transmitted signal seen cellation. In a standard line-driver the use of the LT1886, which is a high
at the primary of the transformer design, the transmit signals at nodes speed 200mA dual amplifier. The use
with a weighted, opposite-phase A and B in Figure 9 are twice the of a 2:1 transformer turns ratio allows
transmitted signal. This weighted magnitude of the signals at nodes C this driver to be powered from a single
summing of the transmitted signal and D. To cancel these signals in the 12V power supply.
ideally cancels the 180 out-of-phase receiver requires resistors RA and RB In order to obtain the highest open-
loop gain and bandwidth to minimize
12V
distortion, the LT1886 is decompen-
17 sated and is only stable with
eIN+
4 14 closed-loop gains of ten or greater. In
+ 5
A1 18 A RBT1 12.4 C this design the signal gain of each
1/2 LT1795-
3 CFE T1
0.1F amplifier is only 6.35. To remain stable
1:2 with this low value of gain requires
RIN1
10k eLINE
100 the addition of gain-compensation
PHONE LINE
components RC1, CC1, RC2 and CC2.
RF1 1k
These components, which come into
RG 0.1F play only at frequencies greater than
eIN 169
DRIVER CHARACTERISTICS 15MHz, parallel the gain-setting
RF2 1k AV =
eLINE
= 12
resistances, RG1 and RG2, to make the
eIN
POWER CONSUMPTION: 1.88W
feedback factor of each amplifier a
RIN2
POWER DISSIPATION: 1.66W value of 0.9, which is the same as
PEAK DRIVER CURRENT: 355mA
10k 8 having a closed-loop gain of ten; thus,
A2
1/2 LT1795-
13
RBT2 12.4 RECEIVER COMPONENTS
(SEE FIGURE 9)
stability is ensured.
eIN
7 + CFE
20
6 B D RA, RB: 2k The LT1886 is a 700MHz gain band-
RC, RD: 1k
11 97.6k
RF1, RF2: 4.02k width amplifier. The combination of
10
T1: COILCRAFT x8390A
OR MIDCOM 50215
(847) 639-6400 1
(605) 886-4385
CF1, CF2: 270pF gain at such high frequencies and not
RECEIVER GAIN being unity gain stable requires that
eRX
12V
eRCV
=1 the gain-setting resistors be returned
to a low impedance at all frequencies.
Figure 12 ADSL Full Rate downstream (CO) line driver For this reason, the two gain setting

Linear Technology Magazine May 2000 33


DESIGN IDEAS
12V reduces the amount of received sig-
17
nal developed across these sensing
+ 4 14 resistors. Although it is powered by
eIN +
A1
5
18 A RBT1 13.3 C 12V supplies, the circuit of Figure
3
1/2 LT1795-
CFE
T1
1:1.5
0.1F 13 achieves 300mW of power savings.
The driver current is substantially
RIN1
100 reduced by using a transformer turns
10k eLINE PHONE LINE ratio of only 1.5:1. Normally, this
RF1 1k would require a higher supply voltage
RP1 2.49k
of 14V and RBT resistors of 22.2.
0.1F
RG However, although the RBT resistors
eIN DRIVER CHARACTERISTICS
226
RP2 2.49k eLINE are reduced to 13.3, the circuit still
AV = = 12
eIN maintain the proper line-impedance
RF2 1k
POWER CONSUMPTION: 1.5W
POWER DISSIPATION: 1.33W
termination of 100 and operates
PEAK DRIVER CURRENT: 266mA from 12V supplies. It is not suitable
RIN2 RECEIVER COMPONENTS for every application, however,
10k 8 (SEE FIGURE 9) because it still reduces the amount of
A2 RBT2 13.3 RA, RB: 1.62k
1/2 LT1795-
13 RC, RD: 1.02k received signal. It is most applicable
+ CFE 20 6 B RF1, RF2: 5.11k
eIN
7 D
CF1, CF2: 240pF for systems that use a sensitive
97.6k
10
11 RECEIVER GAIN receiver AFE that can still detect the
T1: COILCRAFT x8505-A (847) 639-6400 1 eRX
=1 reduced received signal.
eRCV
The approach is termed active ter-
12V
mination. A small amount of positive
Figure 13. Reduced power dissipation ADSL Full Rate downstream (C) line driver feedback in each amplifier is obtained
ADSL Full Rate Downstream from the opposite amplifier output.
This feedback makes the effective
resistors are connected to ground (CO) Line Driver output impedance seen looking into
rather than using a single resistor Figure 12 is the highest powered DSL the circuit at nodes C and D the
connected to the other amplifiers line driver application, used in cen- proper value even though the RBT
inverting input. Capacitors C1 and tral office applications to obtain up to resistor has been reduced by 40%
C2 are included to prevent applying 8Mbps data rates throughout the from what is should be. The design
gain to the DC offset voltages of the Internet. This design uses standard equations for this topology are as
amplifiers. The different values of feed- back termination and can be powered follows.
back capacitors for the receiver from 12V supplies by using a 2:1 Instead of using the standard value
amplifier account for the frequency turns ratio transformer. This results of RBT resistance, it can be reduced to
spectrum of the downstream infor- in a fairly high, 355mA peak output any value desired, with attendant
mation from the CO modem in either current demand from the amplifiers. received-signal loss. A factor called K
the Full Rate (1104kHz) or G.Lite The LT1795, with a 500mA output can be used to define the new RBT
(552kHz) implementation. current rating, once again is capable resistance:
of the task.
ADSL G.Lite Downstream (CO) K ZLINE
RBT = (16)
Line Driver Reduced Power Dissipation 2 n2
This moderate power (16.4dBm) driver ADSL Full Rate Downstream With standard termination and a
requires less than 1W and is shown in (CO) Line Driver 1:1.5 turns ratio transformer, the
Figure 11. This design is biased from To address the power consumption value of RBT should be 22.2. In the
12V supplies and uses a transformer and dissipation issues for Full Rate design of Figure 13, this resistor is
with a turns ratio of only 1:1.2. ADSL drivers, a slightly modified reduced by 40% to 13.3, therefore
Although the peak current is only topology can be used, as shown in the factor K = 0.6.
140mA, the LT1886 cannot be used Figure 13. Recognizing that one-half The normal forward path circuit
due to its limited operating supply of the power provided by the amplifi- gain from the noninverting input of
voltage of 13.2V total. Instead the ers is lost in the transformer each amplifier to the output nodes A
LT1795CFE, which is in a very small back-termination resistors, an obvi- and B is a term called G where G = 1+
TSSOP power package, is used. This ous approach to reduce power is to RF/RG.
small package is ideal for central office, simply reduce the value of these The gain of the positive feedback
multiple DSL port designs for com- resistors. Doing so, however, modifies signal path for each side (from node D
pacting a high number of drivers on a to A and from node C to B, is called P
the output impedance of the modem
single PC card. where P = RF/RP.
as seen from the phone line and also

34 Linear Technology Magazine May 2000


DESIGN IDEAS

Table 3. Driver and receiver amplifier characteristics

Line Drivers
Part LT1795 LT1207 LT1886 LT1497 LT1206 LT1210
Single/Dual Dual Dual Dual Dual Single Single
Output Current 500mA 250mA 200mA 125mA 250mA 1.1A
Supply Voltage 10V to 30V 10V to 30V 5V to 13V 5V to 30V 10V to 30V 10V to 30V
Gain Bandwidth
50MHz 60MHz 75MHz 50MHz 60MHz 35MHz
Product
Slew Rate 900V/s 900V/s 200V/s 900V/s 900V/s 900V/s
IQ/Amplifier 1mA to 30mA 1mA to 30mA 7mA 10mA 1mA to 30mA 1mA to 50mA
+
VSAT 1.2V 1.2V 0.75V 1.2V 1.2V 1.2V

VSAT 1.2V 1.2V 0.9V 1.15V 1.2V 1.25V
RSAT +
1.2 3.2 3.1 14 3.2 0.9
RSAT 2 5.3 2.3 10 5.3 1.7
Dual-Amplifier Receivers
Part LT1355 LT1358 LT1361 LT1364 LT1813 LT1253
Supply Voltage 5V to 30V 5V to 30V 5V to 30V 5V to 30V 5V to 12V 10V to 24V
Gain Bandwidth 12MHz 25MHz 50MHz 70MHz 100MHz 90MHz
Slew Rate 400V/s 600V/s 800V/s 1000V/s 750V/s 250V/s
Noise Voltage 10nV/Hz 8nV/Hz 9nV/Hz 9nV/Hz 8nV/Hz 3nV/Hz
IQ/Amplifier 1.25mA 2.5mA 5mA 7.5mA 3mA 6mA

Conclusion
Using these abbreviations: account the turns ratio and trans- Following the design procedures
For proper impedance matching: P = former insertion loss. described in this article should make
1 K. The use of a high performance the design and implementation easy
To obtain a desired voltage gain amplifier such as the LT1795 does and accurate. At the very least, it will
from the AFE output to the line, AV, not result in any degradation of dis- ensure that power and heat issues
the term G is set to: tortion performance when modifying receive proper consideration.
the closed-loop gain by positive feed- Linear Technology offers a variety
A e
G = V PRI (1 + K P) P (17) back. Significant power savings can of high speed, low distortion power
eLINE be obtained but the design may not be amplifiers and low noise dual ampli-
where ePRI and eLINE are the voltages suitable for all applications as previ- fiers that can be used to implement
at the transformer primary and on ously mentioned. the driver/receiver functions of the
the line, determined by taking into DSL modem (see Table 3).

Authors can be contacted For more information on parts featured in this issue, see
at (408) 432-1900 http://www.linear-tech.com/go/ltmag

Linear Technology Magazine May 2000 35

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