PD- 91317C

IRLR/U2705
HEXFET Power MOSFET
l Logic-Level Gate Drive D
l Ultra Low On-Resistance VDSS = 55V
l Surface Mount (IRLR2705)
l Straight Lead (IRLU2705) RDS(on) = 0.040
l Advanced Process Technology G
l Fast Switching ID = 28A
l Fully Avalanche Rated S

Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.

The D-PAK is designed for surface mounting using vapor phase, infrared, or D-Pak I-Pak
wave soldering techniques. The straight lead version (IRFU series) is for TO-252AA TO-251AA
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25C Continuous Drain Current, VGS @ 10V 28
ID @ TC = 100C Continuous Drain Current, VGS @ 10V 20 A
IDM Pulsed Drain Current 110
PD @TC = 25C Power Dissipation 68 W
Linear Derating Factor 0.45 W/C
VGS Gate-to-Source Voltage 16 V
EAS Single Pulse Avalanche Energy 110 mJ
IAR Avalanche Current 16 A
EAR Repetitive Avalanche Energy 6.8 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RJC Junction-to-Case 2.2
RJA Case-to-Ambient (PCB mount)** 50 C/W
RJA Junction-to-Ambient 110
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
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Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 V VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient 0.065 V/C Reference to 25C, ID = 1mA
0.040 VGS = 10V, ID = 17A
RDS(on) Static Drain-to-Source On-Resistance 0.051 W VGS = 5.0V, ID = 17A
0.065 VGS = 4.0V, ID = 14A
VGS(th) Gate Threshold Voltage 1.0 2.0 V VDS = VGS, ID = 250A
gfs Forward Transconductance 11 S VDS = 25V, ID = 16A
25 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current A
250 VDS = 44V, VGS = 0V, TJ = 150C
Gate-to-Source Forward Leakage 100 VGS = 16V
IGSS nA
Gate-to-Source Reverse Leakage -100 VGS = -16V
Qg Total Gate Charge 25 ID = 16A
Qgs Gate-to-Source Charge 5.2 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge 14 VGS = 5.0V, See Fig. 6 and 13
td(on) Turn-On Delay Time 8.9 VDD = 28V
tr Rise Time 100 ID = 16A
ns
td(off) Turn-Off Delay Time 21 RG = 6.5, VGS = 5.0V
tf Fall Time 29 RD = 1.8, See Fig. 10
Between lead, D
LD Internal Drain Inductance 4.5 nH
6mm (0.25in.)
G
from package
LS Internal Source Inductance 7.5
and center of die contact S

Ciss Input Capacitance 880 VGS = 0V

Coss Output Capacitance 220 pF VDS = 25V
Crss Reverse Transfer Capacitance 94 = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
28
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

110
(Body Diode) p-n junction diode. S

VSD Diode Forward Voltage 1.3 V TJ = 25C, IS = 17A, VGS = 0V

trr Reverse Recovery Time 76 110 ns TJ = 25C, IF = 16A
Qrr Reverse RecoveryCharge 190 290 nC di/dt = 100A/s
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25C, L = 610H
RG = 25, IAS = 16A. (See Figure 12)
ISD 16A, di/dt 270A/s, VDD V(BR)DSS,
TJ 175C
Pulse width 300s; duty cycle 2%.
Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
Uses IRLZ34N data and test conditions.

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 IRLR/U2705

1000 1000
VGS VGS
TOP 15V TOP 15V
12V 12V
10V 10V
8.0V 8.0V
ID , Drain-to-Source Current (A)

ID , Drain-to-Source Current (A)

6.0V 6.0V
4.0V 4.0V
100 3.0V 100 3.0V
BOTTOM 2.5V BOTTOM 2.5V

10 10

2.5V

1 2.5V 1

20s PULSE WIDTH 20s PULSE WIDTH

T J = 25C T J = 175C
0.1 A 0.1 A
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
I D = 27A
R DS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

2.5

100
TJ = 25C
2.0
TJ = 175C
(Normalized)

10 1.5

1.0

0.5

V DS = 25V
20s PULSE WIDTH VGS = 10V
0.1 0.0 A
A
2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature

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1400 15
V GS = 0V, f = 1MHz I D = 16A
C iss = Cgs + C gd , Cds SHORTED

VGS , Gate-to-Source Voltage (V)

1200 C rss = C gd V DS = 44V
Ciss C oss = Cds + C gd 12 V DS = 28V
C, Capacitance (pF)

1000

9
800

Coss
600
6

400
Crss 3
200
FOR TEST CIRCUIT
SEE FIGURE 13
0 A 0 A
1 10 100 0 4 8 12 16 20 24 28 32
VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
ISD , Reverse Drain Current (A)

I D , Drain Current (A)

100 100

10s

TJ = 175C

TJ = 25C 100s
10 10

1ms

TC = 25C
TJ = 175C
10ms
VGS = 0V Single Pulse
1 A 1 A
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100
VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage

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30
RD
VDS
LIMITED BY PACKAGE
VGS
25 D.U.T.
RG
+
ID , Drain Current (A)

-VDD
20
5V
Pulse Width 1 s
15
Duty Factor 0.1 %

10 Fig 10a. Switching Time Test Circuit

VDS
5
90%

0
25 50 75 100 125 150 175
TC , Case Temperature ( C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

D = 0.50
1

0.20

0.10
0.05 PDM
0.1 0.02 SINGLE PULSE
0.01 (THERMAL RESPONSE) t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U2705

250
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 6.6A
11A
15V
200 BOTTOM 16A

L DRIVER
VDS
150

RG D.U.T +
V
- DD 100
IAS A
20V
tp 0.01

50
Fig 12a. Unclamped Inductive Test Circuit

VDD = 25V
0 A
25 50 75 100 125 150 175

V(BR)DSS Starting TJ , Junction Temperature (C)

tp

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

I AS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms Same Type as D.U.T.

50K

12V .2F
QG .3F

10 V +
V
QGS QGD D.U.T. - DS

VGS
VG
3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T
Low Stray Inductance
Ground Plane

Low Leakage Inductance
Current Transformer
-

+


- +
-

RG dv/dt controlled by RG +
Driver same type as D.U.T. VDD
-
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test

Driver Gate Drive

P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS

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IRLR/U2705

Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)

2.38 (.094)
6.73 (.265) 2.19 (.086)
6.35 (.250) 1.14 (.045)
0.89 (.035)
-A-
5.46 (.215) 1.27 (.050) 0.58 (.023)
5.21 (.205) 0.88 (.035) 0.46 (.018)

6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235) 10.42 (.410)
1.02 (.040) 9.40 (.370) LEAD ASSIGNMENTS
1.64 (.025) 1 2 3
1 - GATE
0.51 (.020) 2 - DRAIN
-B- MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)
0.89 (.035)
3X
0.64 (.025) 0.58 (.023)
1.14 (.045) 0.46 (.018)
2X 0.25 (.010) M A M B
0.76 (.030)

2.28 (.090) NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

Part Marking Information

TO-252AA (D-PARK)

EXAMPLE : THIS IS AN IRFR120

WITH ASSEMBLY A
LOT CODE 9U1P INTERNATIONAL
FIRST PORTION
RECTIFIER
IRFR OF PART NUMBER
LOGO
120
9U 1P
ASSEMBLY SECOND PORTION
LOT CODE OF PART NUMBER

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 IRLR/U2705

Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)

6.73 (.265) 2.38 (.094)

6.35 (.250) 2.19 (.086)
-A-
1.27 (.050) 0.58 (.023)
5.46 (.215)
0.88 (.035) 0.46 (.018)
5.21 (.205)
LEAD ASSIGNMENTS
4 1 - GATE
6.45 (.245) 2 - DRAIN
5.68 (.224) 3 - SOURCE
1.52 (.060) 6.22 (.245) 4 - DRAIN
1.15 (.045) 5.97 (.235)

1 2 3

-B- NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090) 9.65 (.380) 2 CONTROLLING DIMENSION : INCH.
1.91 (.075) 8.89 (.350) 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

1.14 (.045) 1.14 (.045)

3X 0.89 (.035)
0.76 (.030) 3X 0.89 (.035)
0.64 (.025)

2.28 (.090) 0.25 (.010) M A M B 0.58 (.023)

0.46 (.018)
2X

Part Marking Information

TO-251AA (I-PARK)

EXAMPLE : THIS IS AN IRFU120

WITH ASSEMBLY
LOT CODE 9U1P INTERNATIONAL
FIRST PORTION
RECTIFIER
IRFU OF PART NUMBER
LOGO
120
9U 1P
ASSEMBLY SECOND PORTION
LOT CODE OF PART NUMBER

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IRLR/U2705

Tape & Reel Information

TO-252AA
Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

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http://www.irf.com/ Data and specifications subject to change without notice. 4/03
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