Professional Documents
Culture Documents
• Classification
• FPGA
• Basic logic cells
• Routing strategies
• Configuration methods
• PLA/PAL
• Design flow
• eFPGA
• Examples
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 1
Classification of digital integrated circuits (see Section 2.2.3 )
µP
Semi
custom Full
µC custom
DSP
(E)EPROM
gate standard
(P)ROM FPGA array cells
PAL/PLA CPLD
RAM
Advantages
• fast and cheap procedure for implementing hardware
• fast functional verification
• low cost of low-volume production
• improved time-to-market
• re-configurability in the field
Disadvantages
• non-optimal utilisation of silicon area
• signal delay and power consumption are high
• routing problems could limit flexibility
• potential clock-skew problems
Re-programmable architectures
• prototyping and functional development on standard platforms
• in-field customisation and updating
• multiple-application hardware
Logic blocks
(CLB)
Memory blocks
(configuration)
Wiring and
interconnect
Interface blocks
Logic
module
Row of cells (b)
(c) (d)
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 6
Basic elements of Configurable Logic Cells (CLC)
Logic elements
• Transistors
• Basic gates (NAND, XOR, ... )
• Flip-flops
• Multiplexers
• Look-up tables (LUTs)
• AND-OR arrays (sum-of-products)
The term granularity refers to a quantification of the complexity of the CLC and
can depend on the following:
• Number of logical functions which may be implemented by each CLC
• Number of equivalent NAND2 gates of each CLC
• Total number of transistors that physically constitute the CLC
depending on the
combination of the input
words, a predefined
output value is assigned
Memory implementation:
input values =
address of memory
predefined values =
content of memory
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 10
Registered output based CLB
LUT based
Multiplexer to decrease
LUT size
registers selectable
large combinational
function with two outputs
Simple
programmable logic
devices (SPLD) are
used to implement
the logic functions
Logic Synthesis
(VHDL, verilog, schematic)
Floorplanning
(VHDL, verilog, schematic)
Layout Verification
(VHDL, verilog, schematic)
Macro Integration
(VHDL, verilog, schematic)
Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003 Page 20
Routing strategies for FPGAs (see Section 2.3)
Routing hierarchy:
• global lines
• double length lines
• local lines
switching nodes to
connect
neighbouring
modules
FPGA devices allow the configuration of all CLCs, I/O cells and interconnect resources.
The gate of each configurable transistor is controlled by the contents of a 1-bit memory
cell, with a logic '0' or logic '1' determining whether the gate is off or on. To reduce the
wiring required for configuration, the memory cells can be connected in a chain and the
configuration is then loaded using a shift operation. Depending on the physical
configuration mechanism, it is possible to classify FPGAs into three classes:
8-bit microcontroller
various peripheral
units
Hierarchical routing
scheme
various circuits and Max. I/O Lines Available to User 224 320 352 448
Process Parameter (2l) 0.18m 0.18m 0.18m 0.18m
applications
Metallisation Layers 5 5 5 5
Supply Voltage 1.8 V 1.8 V 1.8 V 1.8 V
eFPGA array can be Max. Clock Frequency 250 MHz 250 MHz 250 MHz 250 MHz
adapted in Typ. Core Power Consumption 2.4 mW / 2.4 mW/ 2.4 mW/ 2.4 mW/
• configuration RAM
• BIST interface (build in
self-test)
• JTAG interface for test
access and programming
Basic configuration of
CLB for DSP-like
applications
split LUT
selectable register
FPGA are taking market shares from the ASIC business for low volume
products
Embedded FPGAs allow to build systems with the best from all worlds:
• general purpose processor cores
• optimised and adapted µP/µC cores for special applications
• flexible hardware modules (eFPGA) for time critical tasks
• area and speed optimised ASIC parts for certain time critical tasks