Dynamic gates use clock for their normal operation as opposed to the static gates, which dont

use clocks.

Dynamic gates use NMOS or PMOS logic. It doesnt use CMOS logic like regular static gates.
Because it uses either NMOS or PMOS logic and not CMOS logic, it usually has fewer
transistors compared to static gates. Although there are extra transistors given that it uses clocks.

Figure : NMOS pull down logic for NOR gate.

The figure shows the pull down NMOS logic for a NOR gate. This pull down structure is used in
the dynamic gates.

How dynamic gates work :

In static gates, inputs switch and after a finite input to output delay, output possibly switches to
the expected state.
 Figure : Dynamic NOR gate.

As you can see in the figure above, dynamic gate is made using NMOS pull down logic along
with clock transistors on both pull up and pull down paths.

We know that clock has two phases, the low phase and the high phase. Dynamic gate has two
operating phases based on the clock phases. During the low clock phase, because of the
pmos gate on the pull up network, the output of dynamic gate is pre-charged to high phase. This
is the pre-charge state of dynamic gate.

When the clock is at high phase, the output of dynamic gate may change based on the inputs, or it
may stay pre-charged depending on the input. The phase of the dynamic gates, when the clock is
high, is called the evaluate phase. As it is essentially evaluating what the output should be during
this phase.

Figure : Dynamic NOR waveforms when input A is high.

As seen in the waveforms above, as soon as CLK goes low, it pre-charges output node Out
high. While in the pre-charge state, NOR input A goes high. When CLK goes high, and
evaluation phase begins, Out is discharged to low as input A is high. Input B is not shown in
the waveform as it is not relevant to this case.

If both inputs A and B were to remain low, output node would be held high during the pre-
charge.

This technique of always priming or pre-charging output to be with, is a way to

minimize switching of the output node, because if with a new set of inputs, output was supposed
to be high, it wouldnt have to switch, as it is already pre-charged. Output only has to switch in
the case where it has to be low.

But obviously such reduction in output switching doesnt come free, as it means introducing the
clocks and the extra pre-charge face, where output is not ready to be sampled.
One of the biggest concerns with dynamic gates, is the crowbar current. It needs to be ensured
that the clock input to the pull up and pull down is the same node, because of pull up and pull
down clocks are coming from different sources, there is a higher likelihood of both pull up and
pull down transistors to be on at the same time and hence the crowbar current.

Dynamic gates burn more power because of the associated clocks. Clock signal switches
continuously, hence there is more dynamic power dissipated.

The biggest benefit of dynamic gates is that they can be cascaded together and their pull down
only property can be leveraged to have a very fast delay through a chain of multiple stage
dynamic gates.
Posted in Circuits, CMOS theory | Leave a reply

NMOS and PMOS logic

Posted on August 16, 2012
CMOS is the short form for the Complementary Metal Oxide Semiconductor. Complementary
stands for the fact that in CMOS technology based logic, we use both p-type devices and n-type
devices.

Logic circuits that use only p-type devices is referred to as PMOS logic and similarly circuits
only using n-type devices are called NMOS logic. Before CMOS technology became prevalent,
NMOS logic was widely used. PMOS logic had also found its use in specific applications.

Lets understand more how NMOS logic works. As per the definition, we are only allowed to use
the n type device as building blocks. No p-type devices are allowed. Lets take an example to
clarify this. Following is the truth table for a NOR gate.

Figure : NOR truth table.

We need to come up the a circuit for this NOR gate, using n-mos only transistors. From our
understanding of CMOS logic, we can think about the pull down tree, which is made up of only
n-mos gates.
 Figure : NOR pulldown logic.

Here we can see that when either of the inputs A or B is high, the output is pulled down to the
ground. But this circuit only reflects the negative logic, or the partial functionality of NOR gate
when at least one of the inputs is high. This doesnt represent the case where both input area low,
the first row of the truth table. For an equivalent CMOS NOR gate, there would be pull up tree
made up of p-mos devices.

But here we are referring to NMOS logic and we are not allowed to have p-mos devices. How
could we come up with the pull up logic for our NOR gate ? The answer is a resistor. Essentially
when both n-mos transistor are turned off, we want out node to be pulled up and held at VDD.
A resistor tied between VDD and out node would achieve this. There could be other possible
elaborate schemes to achieve the same using n-mos transistors for pulling up purpose, but an n-
mos as a resistor is used to pull up the output node.
Of course you see some immediate drawbacks. You can see that when at least one of the pull
down n-mos is on, there is a static bias current flowing from VDD to the ground even in the
steady state. Which is why such circuits dissipate almost an order of magnitude more power
compared to CMOS equivalent. Not only that, this type of circuit is very susceptible to the input
noise glitches.

Any n-mos device can be made into a resistor by making it permanently on. N-mos device has
inherent resistance and we can achieve the desired resistance by modulating the width of n-mos
transistor.

Figure : NMOS logic NOR gate.

The above figure shows the NOR gate made using NMOS logic. Similarly any gate can also be
made using PMOS logic.

Posted in CMOS theory | Leave a reply

Verilog Races
Posted on July 27, 2012
In Verilog certain type of assignments or expression are scheduled for execution at the same time
and order of their execution is not guaranteed. This means they could be executed in any order
and the order could be change from time to time. This non-determinism is called the race
condition in Verilog.
For the purpose of refreshing your memory here is the Verilog execution order again, which we
had discussed in a prior post.

Figure : Verilog execution order.

If you look at the active event queue, it has multiple types of statements and commands with
equal priority, which means they all are scheduled to be executed together in any random order,
which leads to many of the races..

Lets look at some of the common race conditions that one may encounter.
1) Read-Write or Write-Read race condition.

Take the following example :

always @(posedge clk)

x = 2;

always @(posedge clk)

y = x;

Both assignments have same sensitivity ( posedge clk ), which means when clock rises, both will
be scheduled to get executed at the same time. Either first x could be assigned value 2 and
then y could be assigned x, in which case y would end up with value 2. Or it could be other
way around, y could be assigned value of x first, which could be something other than 2 and
then x is assigned value of 2. So depending on the order final value of y could be different.

How can you avoid this race ? It depends on what your intention is. If you wanted to have a
specific order, put both of the statements in that order within a beginend block inside a
single always block. Lets say you wanted x value to be updated first and then y you can do
following. Remember blocking assignments within a begin .. end block are executed in the
order they appear.

always @(posedge clk)

begin
x = 2;
y = x;
end

2) Write-Write race condition.

always @(posedge clk)

x = 2;

always @(posedge clk)

x = 9;

Here again both blocking assignments have same sensitivity, which means they both get
scheduled to be executed at the same time in active event queue, in any order. Depending on the
order you could get final value of x to be either 2 or 9. If you wanted a specific order, you
can follow the example in previous race condition.

3) Race condition arising from a forkjoin block.

always @(posedge clk)

fork
x = 2;
y = x;
join

Unlike beginend block where expressions are executed in the order they appear, expression
within forkjoin block are executed in parallel. This parallelism can be the source of the race
condition as shown in above example.

Both blocking assignments are scheduled to execute in parallel and depending upon the order of
their execution eventual value of y could be either 2 or the previous value of x, but it can not
be determined beforehand.

4) Race condition because of variable initialization.

reg clk = 0

initial
clk = 1

In Verilog reg type variable can be initialized within the declaration itself. This initialization is
executed at time step zero, just like initial block and if you happen to have an initial block that
does the assignment to the reg variable, you have a race condition.

There are few other situations where race conditions could come up, for example if a function is
invoked from more than one active blocks at the same time, the execution order could become
non-deterministic.