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assign F = E ? Y : 'bz;
endmodule
y0 y1 y2 y3
2-to-4 decoder
w1 w0 En
Q1 Q0
Clock
Up-counter
Clear Reset
y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3
1 1 1
Clock
Function Register
FR in
f1 f0 Rx 1 Rx 0 Ry 1 Ry 0
Function
endmodule
S1
LB
0
0 1
s s
1
S2 S3
EA Done
1
EB z
0
a0
Figure 7.19. ASM chart for the bit counter control circuit.
Please see portrait orientation PowerPoint file for Chapter 7
P = 0;
for i = 0 to n 1 do
if bi = 1 then
P = P+ A;
end if;
Left-shift A ;
end for;
(b) Pseudo-code
(c) Pseudo-code
LR L L
Left-shift w Left-shift E
ER E EA E Register
register register
n n n
an 1 B
A
n n
Clock
Q R
Clock cycle R rr 0 A/ Q
Load A, B 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0
0 Shift left 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0
1 Shift left, Q 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0
2 Shift left, Q 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0
3 Shift left, Q 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
4 Shift left, Q 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0
5 Subtract, Q 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1
6 Subtract, Q 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1
7 Subtract, Q 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1
8 Subtract, Q 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1
Figure 7.33. ASM chart for the enhanced divider control circuit.
Please see portrait orientation PowerPoint file for Chapter 7
Figure 7.39. ASM chart for the mean operation control circuit.
for i = 0 to k 2 do
A = Ri ;
for j = i + 1 to k 1 do
B = Rj ;
if B < A then
Ri = B ;
Rj = A ;
A = Ri ;
end if ;
end for;
end for;
0 1 WrInit
n RData
R0 R1 R2 R3
0 1 2 3 Imux
ABData
Ain E Bin E Rd
Clock n
DataOut
1 0 Bout <
A B
BltA
Figure 7.42. A part of the datapath circuit for the sort operation.
0
2
2
LI L R LJ L R
EI E Counter EJ E Counter
Q Q
Ci Cj
Clock 2
= k2 zi
2
Csel 0 1
= k1 zj
Cmux
2
2
RAdd
Int 0 1
Imux 2 y0 Rin0
w0, w1 y1 Rin1
y2 Rin2
WrInit
En y3 Rin3
Wr
2-to-4 decoder
Figure 7.43. A part of the datapath circuit for the sort operation.
Please see portrait orientation PowerPoint file for Chapter 7
ff ff
ff ff
ff ff
Clock
ff ff
ff ff
ff ff
ff ff
Data
A
D Q Out
B
Clock
t Clock t od
Clock Q Q
R
VDD
S
Data
R
Data
4 8
Ra
Clock 3 7
(output) 555
Rb
Timer
2 6
C1
1 5
0.01 F