LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
LIBRARY altera_mf;
USE altera_mf.all;

entity fpga_mmwave is
PORT (resetn: IN STD_LOGIC;
clk_50MHz: IN STD_LOGIC;
EN_computer: IN STD_LOGIC;
DATA_computer: IN STD_LOGIC;
TRUCO_SW: IN STD_LOGIC;
READMEM_SW: IN STD_LOGIC;
data_from_tx: IN STD_LOGIC;
data_from_rx: IN STD_LOGIC;
RX_serial : IN STD_LOGIC;
ENC_A: IN STD_LOGIC;
ENC_B: IN STD_LOGIC;
TX_serial : OUT STD_LOGIC := '1';
data_to_tx : OUT STD_LOGIC := '0';
data_to_rx : OUT STD_LOGIC := '0';
config_en_tx : OUT STD_LOGIC := '1';
config_en_rx : OUT STD_LOGIC := '1';
config_clk_out_tx : OUT STD_LOGIC;
config_clk_out_rx : OUT STD_LOGIC;
config_reset_tx : OUT STD_LOGIC := '0';
config_reset_rx : OUT STD_LOGIC := '0';
CONF_TXADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
CONF_RXADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
TX_COMADDR : OUT STD_LOGIC := '0';
RX_COMADDR : OUT STD_LOGIC := '0';
tx_ok_led : OUT STD_LOGIC := '0';
rx_ok_led : OUT STD_LOGIC := '0';
LED_RxBusy : OUT STD_LOGIC := '0';
LED_TxBusy : OUT STD_LOGIC := '0';
AWG_TRIG : OUT STD_LOGIC := '0';
DAQ_TRIG : OUT STD_LOGIC := '0';
sync : OUT STD_LOGIC := '0';
SW_TADDR : OUT STD_LOGIC_VECTOR(3 downto 0);
SW_RADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
TEST_SIG : OUT STD_LOGIC_VECTOR(1 downto 0);
stateC,stateSB : OUT STD_LOGIC := '0';
-- LCD_RS : OUT STD_LOGIC;
-- LCD_E : OUT STD_LOGIC;
-- LCD_ON : OUT STD_LOGIC;
-- LCD_RW : BUFFER STD_LOGIC;
-- LCDDATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
led_EN, led_DATA : OUT STD_LOGIC;
ENC_Tick_C: OUT integer range 0 to 10000 :=0;
ENC_Tick_SB: OUT integer range 0 to 10000 :=0);

end;

architecture arch_fpga_mmwave of fpga_mmwave is

SIGNAL reset : STD_LOGIC := '0';

SIGNAL EN_temp : STD_LOGIC := '0';
SIGNAL DATA_temp : STD_LOGIC := '0';
SIGNAL EN_serial : STD_LOGIC := '0';
SIGNAL DATA_serial : STD_LOGIC := '0';
SIGNAL wren_UART : STD_LOGIC := '0';
SIGNAL address_UART : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL address_encoder : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL data_to_RAM : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL data_from_DPRAM : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL data_dpram_tx : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL data_dpram_rx : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL internal_sync : STD_LOGIC;
SIGNAL internal_stateC : STD_LOGIC;
SIGNAL internal_stateSB : STD_LOGIC;
SIGNAL config_en : STD_LOGIC;
SIGNAL config_clk_out : STD_LOGIC;
SIGNAL clk_500kHz : STD_LOGIC;
SIGNAL clk_neg_500kHz : STD_LOGIC;
SIGNAL clk_2MHz : STD_LOGIC;
SIGNAL tx_ok : STD_LOGIC_VECTOR(47 downto 0);
SIGNAL rx_ok : STD_LOGIC_VECTOR(47 downto 0);

COMPONENT PLL
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
END COMPONENT ;

COMPONENT multiradar
PORT (reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
clk_neg: IN STD_LOGIC;
EN_computer: IN STD_LOGIC;
DATA_computer: IN STD_LOGIC;
ENC_A : IN STD_LOGIC;
ENC_B : IN STD_LOGIC;
data_from_tx: IN STD_LOGIC;
data_to_tx : OUT STD_LOGIC;
data_from_rx: IN STD_LOGIC;
data_to_rx : OUT STD_LOGIC;
EN : OUT STD_LOGIC := '1';
clk_out : OUT STD_LOGIC;
CONF_TXADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
CONF_RXADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
TX_COMADDR : OUT STD_LOGIC := '0';
RX_COMADDR : OUT STD_LOGIC := '0';
rdclk : IN STD_LOGIC;
rdaddr_rcfg : IN STD_LOGIC_VECTOR(9 downto 0);
data_ram_tx : OUT STD_LOGIC_VECTOR(7 downto 0);
data_ram_rx : OUT STD_LOGIC_VECTOR(7 downto 0);
tx_ok : OUT STD_LOGIC_VECTOR(47 downto 0);
rx_ok : OUT STD_LOGIC_VECTOR(47 downto 0);
TEST_SIG : OUT STD_LOGIC_VECTOR(1 downto 0);
AWG_TRIG : OUT STD_LOGIC := '0';
 DAQ_TRIG : OUT STD_LOGIC := '0';
SW_TADDR : OUT STD_LOGIC_VECTOR(3 downto 0);
SW_RADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
sync : OUT STD_LOGIC;
stateC, stateSB : OUT STD_LOGIC;
ENC_Tick_C: OUT integer range 0 to 10000 :=0;
ENC_Tick_SB: OUT integer range 0 to 10000 :=0);
END COMPONENT ;

COMPONENT UART
PORT (reset: IN STD_LOGIC;
CLOCK_50: IN STD_LOGIC;
READMEM_SW: IN STD_LOGIC;
wren : OUT STD_LOGIC := '0';
EN_serial : OUT STD_LOGIC := '0';
DATA_serial : OUT STD_LOGIC := '0';
address : OUT STD_LOGIC_VECTOR(9 downto 0);
DATA_from_RAM : in STD_LOGIC_VECTOR(15 downto 0);
LED_RxBusy : OUT STD_LOGIC;
LED_TxBusy : OUT STD_LOGIC;
-- TEST_SIG : OUT STD_LOGIC_VECTOR(1 downto 0);
UART_TXD:OUT STD_LOGIC;
UART_RXD:IN STD_LOGIC);
END COMPONENT ;

--COMPONENT lcd_control
-- PORT
-- (reset, clk : IN STD_LOGIC;
-- stateC,stateSB,truco : IN STD_LOGIC;
-- LCD_RS, LCD_E, LCD_ON : OUT STD_LOGIC;
-- LCD_RW : BUFFER STD_LOGIC;
-- DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
--END COMPONENT ;

begin

pll_inst: pll PORT MAP(

inclk0 => clk_50MHz,
c0 => clk_500kHz,
c1 => clk_neg_500kHz,
c2 => clk_2MHz
);
multiradar_inst : multiradar PORT MAP(
reset => reset,
clk => clk_500kHz,
clk_neg => clk_neg_500kHz,
EN_computer => EN_temp,
DATA_computer => DATA_temp,
ENC_A => ENC_A,
ENC_B => ENC_B,
data_from_tx => data_from_tx,
data_to_tx => data_to_tx,
data_from_rx => data_from_rx,
data_to_rx => data_to_rx,
EN => config_en,
clk_out => config_clk_out,
CONF_TXADDR => CONF_TXADDR,
CONF_RXADDR => CONF_RXADDR,
 TX_COMADDR => TX_COMADDR,
RX_COMADDR => RX_COMADDR,
rdclk => clk_50MHz,
rdaddr_rcfg => address_UART,
data_ram_tx => data_dpram_tx,
data_ram_rx => data_dpram_rx,
tx_ok => tx_ok,
rx_ok => rx_ok,
TEST_SIG => TEST_SIG,
AWG_TRIG => AWG_TRIG,
DAQ_TRIG => DAQ_TRIG,
sync => internal_sync,
stateC => internal_stateC,
stateSB => internal_stateSB,
ENC_Tick_C => ENC_Tick_C,
ENC_Tick_SB => ENC_Tick_SB
);

UART_inst : UART PORT MAP(

reset => reset,
CLOCK_50 => clk_50MHz,
READMEM_SW => READMEM_SW,
wren => wren_UART,
EN_serial => EN_serial,
DATA_serial => DATA_serial,
address => address_UART,
DATA_from_RAM => data_from_DPRAM,
LED_RxBusy => LED_RxBusy,
LED_TxBusy => LED_TxBusy,
-- TEST_SIG => TEST_SIG,
UART_TXD => TX_serial,
UART_RXD => RX_serial);

--lcd_control_inst: lcd_control PORT MAP(

-- reset => reset,
-- clk => clk_50MHz,
-- stateC => internal_stateC,
-- stateSB => internal_stateSB,
-- truco => TRUCO_SW,
-- LCD_RS => LCD_RS,
-- LCD_E => LCD_E,
-- LCD_ON => LCD_ON,
-- LCD_RW => LCD_RW,
-- DATA_BUS => LCDDATA_BUS
-- );

reset <= not resetn;

config_reset_tx <= not resetn;
config_reset_rx <= not resetn;
EN_temp <= EN_computer or EN_serial;
DATA_temp <= DATA_computer or DATA_serial;
data_from_DPRAM <= data_dpram_rx & data_dpram_tx;
config_en_tx <= config_en;
config_en_rx <= config_en;
config_clk_out_tx <= config_clk_out;
config_clk_out_rx <= config_clk_out;
led_EN <= EN_temp;
led_DATA <= DATA_temp;
tx_ok_led <= '0' when tx_ok = 0 else '1';
rx_ok_led <= '0' when rx_ok = 0 else '1';
sync <= internal_sync;
stateC <= internal_stateC;
stateSB <= internal_stateSB;

end arch_fpga_mmwave;