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CHAPTER 2
ARCHITECTURES OF OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER
2.1 INTRODUCTION
substrate and power lines. Hence, in this work, a high performance CMOS
fully differential OTA has been proposed using the folded cascode
architecture to achieve high gain, high output swing and a good slew rate. The
proposed OTA structures use an NMOS transistor in its input differential
stage to achieve high transconductance gain. The Selection criterion is
based on various parameters like transconductance gm, DC gain, gain
bandwidth product (GBW), Common Mode Rejection Ratio (CMRR) and
average power.
for a two stage OTA and its alternative structures are discussed. This gives
insight into improving performance parameters like voltage gain, Common
mode rejection ratio and Power supply rejection ratio etc. However, the
design considerations for the fully differential circuits have not been detailed
in it. The basic architectures of various single ended and fully differential
structures are described along with their design complexities, limitations and
disadvantages by Gregorian and Razavi (1999). This helps in choosing a
specific category of OTA for a particular application. It also details about the
various advantages of fully differential structure over the single ended
structures. Hernes and Sansen (2005) discuss the classification of single stage,
two stage and three stage structures based on harmonic distortion. A
performance comparison of single stage amplifier and two stage amplifier
shows that single stage amplifier works well at high frequency while two
stage amplifier is good at mid frequency range. The study also assures that
noise level is maintained low for differential amplifiers with an increasing in
common mode rejection ratio and power supply rejection ratio. The input
stage transistors affect the overall operation of a circuit at high frequencies
and output transistors at low frequencies. Thus, the choice of transistor made
at the input and output stage also decides the amount of nonlinearity present
in the circuit. Jakbson et al (1992) give a clear explanation about flicker (1/f)
noise in MOS transistors. The usage of p-channel transistors as the input
differential stage in an amplifier reduces the third order and total harmonic
distortion. This enhances the choice of OTA, based not only on gain and gain
bandwidth product but also on noise performance. A two-stage OTA for
digital audio applications is designed by Dessouky and Kaiser (2001). This
OTA is used in delta sigma modulator, where the first stage is a folded
cascode stage and the second stage is a common source amplifier. There is a
limitation on slew rate in both the stages. Furthermore, there is an increase in
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power dissipation as large bias current is drawn from the second stage due to
large load capacitance. This inhibits the use of OTA in low power
applications.
I = g (V V ) (2.1)
Io +
V+ +
Io
gm
Io -
-
V-
Slew rate
Slew rate (SR) defines the fastest possible rate of change of OTAs
output voltage, whose rate of change is limited due to the electronic circuitry
inside the OTA. It supplies small current to charge and discharge the
capacitor C.
= = v (2.3)
SR = = (2.4)
| = SR = V (2.5)
SR = i| (2.6)
where t = gm/C is the unity gain frequency. The above equation shows that
slew rate increases with increasing t and power supply current.
20
Gain
Vdd
Vi +
+ Vo+
+ +
gm
Vi - Vo- CL
- -
-
-
CL
+ Vss
Power dissipation
it is easy to calculate the total dissipation and then subtract the load
dissipation to obtain the device dissipation. When the load capacitance is
increased, both the slew rate and the unity gain frequency of the OTA circuit
are reduced. To maintain a constant settling behavior, the power consumption
of the OTA must be increased linearly with an increase in the load
capacitance.
A
CMRR = (2.8)
A
Where ADM is the differential mode gain and ACM is the common mode gain.
Ideally ADM should be large and ACM should be zero. The higher the value of
CMRR, better is the performance of OTA. Ideally, changes in the common
mode input should have no effect on the differential gain of the amplifier. As
it is practically not possible, Common-Mode Rejection Ratio is defined as the
ratio of differential mode gain to common mode gain. The circuit setup for
calculation of Common-Mode Rejection Ratio (CMRR) is given in
Figure 2.3.
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Vdd
Vi +
+ Vo+
+ +
gm
Vo-
- Vi - - CL
-
-
CL
+
Vss
+
VCM
-
( )
PSRR(s) = 20log dB (2.9)
( )
If the OTA involves two power supplies namely positive power supply V DD
and negative power supply VSS, a power supply gain for each power node can
be defined separately. In this case Ap, Vdd (Ap, Vss) is called the transfer
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function from the Vdd (Vss) node to the output node where by the Vss (Vdd) is
ac grounded. The PSRR of each power supply can be defined as
VDD
-
Vdd
+
Vi +
+ Vo+
+ +
gm
Vo -
- Vi - - CL
-
-
- CL
+
Vss
+
VSS
Small-signal bandwidth
the unity-gain frequency, fu, which exceeds 1GHz in today CMOS OTAs.
The 3-dB frequency, f3-dB, may also be specified to allow easier prediction of
closed loop frequency response.
20 log(AV)
0
f 3-dB
fu f (log scale)
Where Vf is the amplitude of the fundamental and Vhi is the amplitude of the
ith harmonic component.THD is presented as a percentage value.
25
HD3 = (2.12)
where HD1 and HD3, are the amplitudes of the fundamental and third-
harmonic terms respectively. The above said performance parameters were
obtained for various OTAs using CMOS 0.35 m technology and were
simulated using H-Spice, Synopsys EDA tool.
VDD
M3 M4
Vb2
M8 M6
Rz Rz
Vout+ Vout-
Cc Cc
M1 M2
V+ V-
Vb1
M9 M5 M7
Parameters Values
Vdd (V) 3.3
Channel Length ( m) 0.35
RZ (k ) 1
CC (pF) 0.1
W1,2 m) 20
W3,4 m) 6
W5 m) 4
W6,8 m) 10
W7,9 ( m) 5
Vb1 (mV) 500
Vb2 (mV) 233.6
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Since two stages are present, the stability of the OTA is maintained
using a compensation capacitor (Cc) and a resistor (Rz) or a MOSFET during
feedback operation. This reduces the unity gain bandwidth and the speed of
operation. Also, the structure requires two Common Mode Feedback (CMFB)
Circuits vb1, vb2 for the four current branches M3, M4, M5, M7 and M9
present in the circuit. Hence, the power consumption of the OTA increases
with a increase in area. This inhibits the performance of the two stage OTA.
In order to achieve high gain and large bandwidth with less power
consumption, the telescopic topologies are used in building OTA.
VDD VDD
M7 M8 M7 M8
M5 M6 M5 M6
Vout Vout
IBIAS IBIAS
CL CL
M3 M4 M3 M4
V1 V1
M1 M2 M1 M2
V+ V- V+ V-
M10 M9 M10 M9
VSS VSS
(a) OTA with Cascode Current Load (b) OTA with Wilson Current Load
The operation of the circuit requires only two current branches and
thus, the power consumption is improved. The slew rate depends upon the
bias currents and the output load capacitance and is better than the two stage
amplifier. The cascode device in the circuit helps to achieve high gain and
reduces the noise contributed by the bias transistors. The circuit gain is given as
Av = g [ (g r ) (g r )] (2.13)
OTA OTA
Parameters With Cascode With Wilson
Current mirror Current mirror
CL (pF) 0.1 0.1
Ibias ( A) 15 30
Vdd/Vss (V) 2 2
Channel Length ( m) 1 1
W1,2 m) 35 35
W3,4,9,10 m) 6 6
W5,6,7,8 m) 18 18
V1 (mV) 600 600
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VDD
M7 M8
M11
M5 M6
M12
Vout- Vout+
CL CL
M3 M4
Ibias
Vbias Ibias
M1 M2
V+ V-
M10 M9
VSS
Parameters Values
CL (pF) 0.1
Ibias ( A) 15
Vdd/Vss (V) 2
Channel Length ( m) 1
W1,2 m) 35
W3,4,9,10 m) 6
W5,6,7,8 m) 18
W11,12 m) 33.5
Vbias (mV) 600
mirror has a limited output swing. So, the OTA circuit has been modified to
improve the output swing using a Cascode current mirror. In a folded cascode
OTA using a Wilson current mirror, the maximum output voltage was set to a
value lower than: Vdd+VT+2Vds,sat. Thus, in order to restore this fall to
+2Vds,sat, a cascode current mirror is used. The folded Cascode OTA with
Wilson and Cascode current mirror is shown in Figure 2.9. The folded
cascode OTA has a PMOS differential input stage with transistors M9 and
M10 to charge the Wilson/Cascode current mirror transistors M1-M4.
Transistors M11 and M12 provide the DC bias voltages to M5, M6, M7, M8
transistors (Houda et al 2006).
VDD VDD
M1 M2 M1 M2
Ibias Ibias
M3 M4 M3 M4
M9 M10 M9 M10
V- V+ Vout V- V+ Vout
Ibias Ibias
CL CL
M5 M6 M5 M6
M11 M11
M7 M8 M7 M8
M12 M12
VSS VSS
(a) OTA with Wilson Current Load (b) OTA with Cascode Current Load
The specifications of the circuit are as in Table 2.4. The open loop
DC gain of single stage single ended folded cascode OTA with Wilson
current mirror load is 84 dB and unity gain bandwidth is 84.02 dB MHz. A
transconductance of 102.9 s is achieved using folded cascode OTA. The
CMRR and PSRR values found to be 187.5 dB and of 104 dB are achieved
using a Wilson current mirror in the folded cascode OTA.
Parameters Values
CL (pF) 0.1
Ibias ( A) 30
Vdd/Vss (V) 2
Channel Length ( m) 1
W1,2,3,4 m) 18
W5,6,7,8,11,12 m) 6
W9,10 ( m) 35
VDD
M1 M2
M12
M3 M4
Vout+ Vout-
V1
CL CL
M5 M6
M9 M10
V+ V- Ibias
V2
Ibias M7 M8
M11
VSS
A = (2.15)
( )
GBW = . (2.16)
Where, gm4, gm6 and gm9 are the transconductance of transistors M4, M6 and
M9 respectively. ID is the bias current flowing through transistors M9, M4,
and M6 and CL is the output node capacitance. N and P are the channel
length modulation parameters of NMOS and PMOS devices. The gain
expression is given as shown in Equation (2.17).
.
A = (2.17)
( )
Parameters Values
CL (pF) 0.1
Ibias ( A) 69
Vdd/Vss (V) 2
Channel Length ( m) 1
W1,2,12 m) 10.8
W3,4 m) 5.4
W5,6,7,8 m) 2
W9,10 ( m) 14
W11 m) 4
V1 = V2 (mV) 318
VDD
M1 M2
Ibias1
M15
M3 M4
V+ V-
M9 M10 M16
Vout+ Vout-
CL
CL
M5 M6
M14 M11
Ibias2
M7 M8
M13 M12
VSS
F A f CMRR + (2.18)
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where
PSRR + + (2.19)
,
The open-loop voltage gain and gain bandwidth product are given
in Equation (2.20) and Equation (2.21) respectively
A =g (g r r g r (r r )) (2.20)
GBW = (2.21)
where, gm3, gm5 and gm9 are respectively the transconductance of transistors
M3, M5 and M9. The drain to source resistances of transistors M1, M3, M5,
M7 and M9 are r01, r03, r05, r07 and r09 respectively. CL is the capacitance at the
output node.
( )( )
PSSR = (2.22)
( )
=R r g (2.23)
=r g (R +r ) (2.24)
R = r (2.25)
R =r r g (2.26)
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Parameters Values
CL (pF) 0.1
Ibias1 ( A) 60
Ibias2 ( A) 90
Vdd/Vss (V) 1.8
Channel Length ( m) 1
W1,2,15,16 m) 34.85
W3,4 m) 23
W5,6,7,8, 11,12,13,14 m) 47.15
W9,10 ( m) 49.9
Atot = g r (g r (A + 1) + 1) + g r (2.28)
Vx
Parameters Values
Vdd (V) 3.3
Channel Length ( m) 1
W1,2 m) 600
W3,4 m) 100
W5,6 m) 200
W7,8,11 m) 80
W9,10 m) 40
V1 (m V) 600
Bias (V) 0.8
Vcmfbp (V) 2
Vcmfbn (V) 0.7
Offset 0.9
45
The Table 2.9 lists all the performance parameters calculated for
the NMOS and PMOS boosting stages individually along with the folded
cascode gain boosted OTA. The gain boosted OTA has a maximum gain
when compared to all the other OTAs in literature but with increased power
consumption. As the objective is to design an OTA for low power
applications, gain boosted OTAs are utilized only for certain unique
application where there is a trade off for power. Hence, fully differential high
performances OTA has been proposed using folded cascode architecture as it
can operate at reduced supply voltage and yields low power with gain
comparable to telescopic structure with large unity gain bandwidth.
Vref
P1 P2 P2 P1
Vout+ Vout-
VSS
signals applied to the MOS transistors in the CMFB circuit which act as
switches. By varying the Itune, the tuning range of the OTA is varied to
accommodate a wider frequency range in the filter. The MOSFET design
specifications are given in Table 2.10.
Parameters Values
CS (pF) 0.01
Ca (pF) 0.1
Itune ( A) 15
Vdd /Vss (V) 2
Vref (V) 0.65
Channel Length ( m) 0.5
W1,2,3,4 m) 6
W5,6,7,8,9 m) 6
The major part art in the design of OTA lies in the choice of input
transistors as it is the first stage that provides the largest gain. Since, an
NMOS transistor exhibits a higher transconductance than a PMOS transistor,
an NMOS pair is chosen in the input differential pair to provide gain of the
OTA. This is due to the fact that the mobility of NMOS device is larger than a
PMOS device for a comparable device dimensions and bias currents. Here, a
fully differential folded cascode OTA has been proposed with NMOS as the
input differential stage because of its greater mobility and higher
transconductance.
51
A =g (g r r (g r (r r )) (2.30)
GBW = (2.31)
Where, gm3, gm5 and gm9 are the transconductances of transistors M3, M5 and
M9 and CL is the output node capacitance respectively.
VDD
M1 M2
M12
M3 M4
M13
Vout+
Vout-
Ibias
CL
CL
M5 M6
M9 M10
V+ V-
M14
Ibias M7 M8
M11
VSS
( )
PSSR = (2.32)
where
= (R +R +r R r g ) (2.33)
=r g (R +r ) (2.34)
R = r (2.35)
R =r r g (2.36)
Where r01, r03, r05, r07 and r09 are the drain-source resistances of transistors
M1, M3, M5, M7 and M9 respectively. The slew rate (SR) can be written as
SR = (2.37)
t = , (2.38)
gm9 and gm9/ID yield the bias current ID and furthermore gm9/ID
gives I', Where I'= ID/(W /L).
g I
w (2.39)
I W
L
54
g I
A (2.40)
I W
L
Parameters Values
CL (pF) 0.1
Ibias ( A) 15
Vdd/Vss (V) 2
Channel Length ( m) 1
W1,2,12 m) 10.8
W3,4 m) 5.4
W5,6,7,8 m) 2
W9,10 ( m) 14
W11 ( m) 4
57
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and implemented with the single second order section in this chapter, using
the proposed folded cascode OTA. The circuit realization proposed by Uwe et
nd
al (2003) is used for implementation of the 2 order low pass filter because of
its advantages in design and layout. Four OTA blocks are used to develop the
nd
2 order low pass filter, as shown in Figure 2.26. All filter stages operate with
one common bias generating circuit, which improves the matching between
the filter stages over the tuning range.
2C 1 2C 2
+Vo
+Vi
+ - + - + - + -
gm1 g m2 g m3 g m4
-Vi - + - + - + - +
-Vo
2C 1 2C 2
H(s) = = (2.41)
H(s) = (2.42)
.
60
H(s) = (2.43)
= Q= (2.44)
= Q= (2.45)
Where g = 2K I (2.46)
Now the transconductance g of the 2nd order filter from (2.42) and (2.43)
is
g = 1.848 g (2.47)
Parameters Performance
Technology 0.35m
Supply Voltage 2V
THD @fc=2.5MHz -50.7dB
Power 1mW
Tuning Range 50KHZ-2.5MHz
The 2nd order Gm- C Bi-quad Low Pass Filter implemented with
the proposed fully differential Folded Cascode OTA exhibits a wide tuning
range from 50 kHz to 2.5 MHz and supports wireless standards like GSM,
UMTS and WCDMA.
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2.13 CONCLUSION