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The Cadence Spectre circuit simulation platform, built on an advanced infrastructure, combines
industry-leading simulation engines to deliver a complete design and verification solution. It meets
the changing simulation needs of designers by preserving design intent as they progress through
the design cyclefrom architectural exploration, to analog and RF block-level development with
flexible and reliable abstraction, to final analog and mixed-signal full-chip verification for increased
productivity and throughput.
Virtuoso Multi-Mode
Simulation Spectre
The Virtuoso Multi-Mode Simulation
release delivers an industry-leading
Spectre circuit simulation platform for Spectre APS Spectre RF Spectre XPS
a comprehensive design and verifi- Accurate, high- Analog and RF-IC High-speed, high-
cation solution that provides SPICE, performance noise analysis capacity full-chip
simulation analysis
radio frequency (RF), FastSPICE, and
mixed-signal simulators in a unique
shared licensing package. This unified Spectre Infrastructure
solution preserves the design intent Common infrastructure, advanced simulation database,
and delivers scalable performance and versatile front-end parser, robust device library
capacity through reliable abstraction,
providing robust verification of analog, Spectre Applications
RF, memory, custom digital, and Comprehensive coverage, integrated with Virtuoso, LEA,
mixed-signal silicon realization. Liberate, Allegro, and Encounter Timing System technologies
Features tight integration with the combination of performance and capacity The Spectre simulation platform provides
Virtuoso Analog Design Environment, for verification of analog/RF and mixed- a full-chip native reliability simulation
with common use-model, cross- signal design without sacrificing accuracy and analysis solution, enabling designers
probing, and back-annotation of results. to consider reliability effects in the early
capabilities Language and netlist support stages of design and ensure silicon
realization that has sufficient margins
Features tight integration into the The Spectre simulation platform supports to function correctly over the products
Incisive Logic Design Environment, a variety of design abstraction methods. entire lifetime.
with common-use model, It is compatible with most commonly
debugging, waveform viewing, and used SPICE input decks for both pre- and Advanced analog and RF circuit
languagesupport post-layout. It can natively read Spectre, analysis techniques
Provides a proven, comprehensive suite SPICE, and Verilog-A netlist formats The advanced architecture of the Spectre
of high-precision analyses with a simple and device models. It also supports simulation platform uses proprietary
use model, delivering accurate results standard language inputs in Verilog-AMS, techniquesincluding adaptive time step
VHDL-AMS, Verilog-A, Verilog, and control, sparse matrix solving, and multi-
Offers post-layout simulation and VHDLformats. core processingto provide high perfor-
signoff analysis to ensure first-pass
Post-layout simulation mance while maintaining signoff accuracy.
silicon realization success
It bridges the gap between manufactur-
Scalability in performance Verification for post-layout designs has ability and time to market at advanced
become increasingly important with process nodes by providing a compre-
Delivers simulation performance for advanced nanometer processes. For hensive set of statistical analysis tools
complex and large analog/RF, custom larger designs such as analog subsystems tailored to IC design. Tight integration
digital, and mixed-signal designs and full chips, the post-layout parasitics with the Virtuoso Analog Design
Offers high-performance parallel data is growing exponentially at 65nm Environment offers a user-friendly inter-
simulation by harnessing the power andbelow. active setup and advanced visualization of
of clusters of multi-core compute statistical results.
The Spectre simulation platform offers
platforms to deliver peak performance a flexible solution for SPICE-level post- The Spectre simulation platform provides
layout simulations of complex and large the flexibility to combine design IP from
designswith tens of thousands of circuit the different sources and abstraction
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Virtuoso Multi-Mode Simulation with Spectre Platform
levels necessary for the design and verifi- Bipolar junction transistor (BJT) models,
cation of todays advanced mixed-signal including latest versions of VBIC,
SoCs. It accepts designs in combina- HICUM L0, HICUM L2, Mextram, HBT,
tions of various hardware description and Gummel-Poon models
languages, allowing analog bottom-up
GaAS MESFET models, includes latest
and digital top-down design methodol-
versions of GaAs, TOM2, TOM3,
ogies to link and enable complete analog/
andAngelov
mixed-signal full-chip verification.
Rensselaer Polytechnic Institute
Specifications (RPI)s Poly and Amorphous Silicon
Thin-Filmmodels
Comprehensive device models
Diode, JFET, FinFET, and flash
MOSFET models, including latest
cellmodels
versions of BSIM3, BSIM4, PSP, HISIM,
MOS9, MOS11, and EKV Verilog-A compact device models
Sun Solaris 10
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Virtuoso Multi-Mode Simulation with Spectre Platform
Benefits
Provides high-performance,
high-capacity SPICE-level analog and RF
simulation with out-of-the-box tuning
for accuracy and faster convergence Figure 2: Spectre Circuit Simulator delivers significant performance and capacity for accurate analog
simulation.
Facilitates the tradeoff between
accuracy and performance through
Delivers fast interactive simulation Comprehensive statistical analysis
user-friendly simulation setup
setup, cross-probing, visualization, and
applicable to the most complex analog The Spectre Circuit Simulator bridges the
post-processing of simulation results
and custom-digital ICs gap between manufacturability and time
through tight integration with the
to market at advanced process nodes by
Enables accurate and efficient Virtuoso Analog Design Environment
providing a comprehensive set of statis-
post-layout simulation
Ensures higher design quality using tical analysis tools tailored to IC design.
Supports out-of-the-box S-Parameter silicon-accurate, industry-standard, Advanced Monte Carlo algorithms enable
models, enabling simulation of complex foundry-certified device models shared smart selection of process and design
n-port devices across the simulation engines parameters to characterize the yield with
significantly reduced simulation runs. The
Delivers signal integrity analysis
Features DC Match capability efficiently analyzes
capability with an advanced local process mismatch effects and
transmission line library and graphical Production-proven circuit simulation identifies the yield-limiting devices and
editor techniques parameters. Tight integration between
Provides a platform to measure and The Spectre Circuit Simulator uses propri- the Spectre Circuit Simulator and the
analyze system-level performance etary techniquesincluding adaptive Virtuoso Analog Design Environment
metric time step control, sparse matrix solving, offers user-friendly interactive setup
and multi-processing of MOS models and advanced visualization of statistical
Performs application-specific analysis results.
to provide high performance while
of RF performance parameters (spectral
maintaining signoff accuracy. It includes
response, gain compression, inter- Transient noise analysis
native support for both Spectre and
modulation distortion, impedance
SPICE syntax, giving users the flexibility The Spectre Circuit Simulator provides
matching, stability, and isolation)
to use Spectre technology for any design transient noise analysis for accurate
Offers advanced statistical analysis flow without worrying about the design calculation of the large signal noise in
to help design companies improve format. Additionally, it converges to nonlinear non-periodic circuits. All noise
the manufacturability and yield of ICs results that are silicon-accurate by types are supported, including thermal,
at advanced process nodes without modeling extensive physical effects in shot, and flicker.
sacrificing time to market devices for deep sub-micron processes.
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Virtuoso Multi-Mode Simulation with Spectre Platform
Built-in Verilog-A and MDL Rapid IP2 and IP3 calculation based on netic simulations and include state-of-
perturbation technology the-art descriptions of dielectric and
The Spectre Circuit Simulator offers
conductor losses, delivering accurate
design abstraction for faster convergence Periodic noise analysis for the accurate
models, tightly integrated into Virtuoso
on results, including behavioral modeling calculation of noise in non-linear time
ADE. An intuitive and easy-to-use
capabilities in full compliance with variant circuits with detailed analysis
graphical editor gives the user the ability
Verilog-A 2.0. The compiled Verilog-A options including modulated noise,
to accurately define and graphically
implementation is optimized for compact sampled noise, and jitter
capture the substrates.
device models offering comparable
Full spectrum periodic noise provides a
performance to built-in device models. Wireless Analysis
fast and silicon-accurate Pnoise analysis
In addition to supporting standard SPICE for circuits with sharp transitions The modern mobile platform with
measurement functions (.measure), exponentially evolving wireless standards
Noise and distortion summary to
it offers a measurement description is increasing the complexity of wireless
identify the contribution of each device
language (MDL) to automate cell and RFIC designs. To meet specification
to the total output noise, harmonic, or
library characterization. Spectre MDL requirements and productivity goals,
inter-modulation distortion
enables the designer to post-process the designers must evaluate the system-level
results and tune the simulator to provide Small signal analysis includes AC, performance metrics in an integrated,
the best performance/accuracy tradeoff transfer function, S-Parameters, and automated, and easy-to-use simulation-
for a specific measurement. stability based on a periodic or quasi- based flow.
periodic operating point
Advanced device modeling and Spectre RF wireless analysis feature
support Monte Carlo, corner-case, and provides a fully automated flow integrated
parametric sweep analysis in Virtuoso ADE, enabling the designer
The Spectre Circuit Simulator supports
to easily apply the standard-compliant
MOS, BJT, specialty transistor models, Advanced Transmission Line Library
modulation sources and measure the
resistors, capacitors, inductors, trans-
Signal-integrity issues can be very difficult output to calculate system-level perfor-
formers and magnetic cores, lossy and
and time consuming to identify, analyze, mance. The simulation is based on an
lossless transmission lines, independent
and resolve for high-speed designs. The advanced, accurate, and fast envelope-
and controlled voltage and current
Spectre RF rftline (RF transmission line) following algorithm in Spectre RF.
sources, and Z and S domain sources.
library enables the designer to perform The wire analysis is designed with the
The Spectre Circuit Simulator provides a signal-integrity analysis of the design in RFIC designer in mind. It provides an
user-defined compiled model interface context of the package and PCB trace. automated setup of simulation parameters
(CMI). It allows for the rapid inclusion of Spectre rfTlineLib provides a compre- and standard-specific post-processing,
user-defined models for a model once, hensive set of multi-layer transmission eliminating the hassle and tedious nature
use everywhere capability. It offers a lines and models. Spectre rftline models of working with changing wireless
curve tracer analysis capability for rapid are based on rigorous 2-D electromag- standard sources. Spectre RF wireless
model development and debugging.
RF simulation
Spectre RF, an option to the Spectre
Circuit Simulator, provides a set of
comprehensive RF analyses built on two
production-proven simulation engines:
harmonic balance and shooting-Newton.
Spectre RF supports all industry-standard
models.
Shooting-Newton-based
analysis, optimized for strongly
non-linearcircuits
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Virtuoso Multi-Mode Simulation with Spectre Platform
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Virtuoso Multi-Mode Simulation with Spectre Platform
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Virtuoso Multi-Mode Simulation with Spectre Platform
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Virtuoso Multi-Mode Simulation with Spectre Platform
Stitching
D Timing
design intent. It uses true hierarchical PM
Designer
a
simulation and a patented isomorphic and and
D Power
adaptive partitioning algorithms. Parasitics UltraSim
Analog
DSPF, SPEF
Reliability
Benefits
Accelerates pre-and post-layout
simulation for a wide range of Electromigration/
applications from blocks to full-chip IR Drop Analysis
SoCs (see Figure 5)
Figure 5: Virtuoso UltraSim post-layout verification and analysis for silicon realization
Provides a comprehensive set of
transistor-level analysis covering
Features Specifications
electrical rule check (ERC), power,
timing, and nodal activity Compatible with SPICE, Spectre, Design inputs/outputs
Handles large post-layout designs using
Verilog-A, and SPEF
Spectre netlist
a combination of unique hierarchical The UltraSim Full-Chip Simulator is
parasitic stitching techniques and an SPICE netlist format
compatible with most types of SPICE
accurate frequency-based parasitic input decks for both pre- and post-layout. DSPF/SPEF parasitic formats
reduction algorithm Natively reads Spectre format netlists and
Verilog-A
models, and uses the same views within
Supports multiple simulation
Virtuoso Analog Design Environment, SST2 waveform format
abstraction modes (SPICE, analog,
making it easy to adopt in Spectre-based
mixed-signal, and digital), enabling the PSF and PSF XL waveform format
design flows.
user to locally tune performance and
accuracy settings for different blocks in FSDB format
Post-layout simulation
the design Veritools waveform format
When used in conjunction with Cadence
Includes flexible, easy-to-use controls post-layout products, the UltraSim UltraSim/Verilog
for providing adequate tradeoff Full-Chip Simulator provides a means Verilog-HDL IEEE 1364
between accuracy and simulation speed for exploration and validation of such PLI 1.0, VPI (PLI 2.0)
Plugs smoothly into design and verifi- effects as electromigration, IR drop, signal SDF
cation flows through integration integrity, and substrate degradation.
AMS-UltraSim
with the Virtuoso Analog Design It also has built-in, state-of-the-art,
Verilog-AMS 2.0
Environment and command-line S-Parameter-based parasitic reduction
VHDL-AMS 1076.1
environments for faster simulation with minimal loss in
Verilog (IEEE 1364-1995, IEEE
accuracy.
1364-2001 extensions)
Design reliability simulation VHDL (IEEE 1076-1987, IEEE
1076-1993, IEEE 1076.4-2000 [VITAL
The UltraSim Full-Chip Simulator provides
2000])
a robust set of analyses capable of
PLI 1.0, VPI (PLI 2.0)
predicting and validating timing, power,
SDF
and reliability. It is the only FastSPICE
SystemC, SystemVerilog
simulator capable of simulating HCI and
NBTIkey stress effects that must be
taken into account for high-performance
advanced node designs.
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Virtuoso Multi-Mode Simulation with Spectre Platform
Benefits
Features is configured using the hierarchy editor,
Ensures design quality with proven which facilitates the viewing and design
Spectre and Incisive digital simulation Methodology-independent design preparation of a complex mixed-signal
technologies convergence design. Automatically inserted interface
The AMS Designer provides the flexibility elements are used to translate signals
Supports both analog design flow use
to combine IP from different sources from one domain to the next, leaving
models in Virtuoso Analog Design
and in different formats for todays the user free to simulate with different
Environment as well as digital-verifi-
SoC designs. It does more than just design configurations to easily tradeoff
cation use models in the Incisive
co-simulate analog and digital blocks. simulation speed for simulation accuracy.
environment
By treating Virtuoso Schematic Editor The AMS Designer also supports IP
Supports both top-down and blocks and textual descriptions equally, encryption using RSA technology, which
bottom-up methodologies to quickly the AMS Designer allows different allows the user to establish both IP reuse
detect and fix design failures early points of data entry. It accepts descrip- and virtual-prototyping methodologies.
in the design cycle, helping to meet tions in the standard language formats
tapeout schedules of Verilog-AMS, VHDL-AMS, Verilog-A, Integrated with proven Spectre and
Extensive language support allows Verilog, VHDL, and SystemC, as well as Incisive simulation technologies
a higher level of abstraction and SPICE, and performs simulation on any
The AMS Designer is a single executable
accelerates simulation to achieve faster combination of these languages. This
mixed-signal simulator based on the
turnaround time allows bottom-up and top-down design
proven technology of Spectre, Specre
methodologies to converge into a fully
Supports simulation of RF circuits at full APS, and UltraSim Full-Chip Simulator,
functional design.
SPICE accuracy by combining envelope and the Incisive digital simulation capabil-
analysis of RF transceivers with Different levels of abstraction, such as ities.
digital baseband simulation for faster Verilog-AMS or VHDL-AMS behavioral
Analog-centric flow with Virtuoso
convergence of results models and schematic representation, are
easily interchangeable to allow the design The AMS Designer is tightly integrated
to change over time from full behav- with the Virtuoso Analog Design
ioral to full transistor. The entire design Environment for mixed-signal block
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Virtuoso Multi-Mode Simulation with Spectre Platform
design. It uses native Analog Design The SimVision multi-language Common mixed-signal waveform
Environment netlisting technologies to debugging environment allows users database
combine schematics and behavioral views, to view analog and digital signals in a
Incisive environment
enabling users to independently manage single waveform environment
the level of abstraction of each block. Mixed-signal debugger
AMS Designer Verification Option
The entire design is configured using
the hierarchy editor, which facilitates Breakpoints on time, position, and
The AMS Designer Verification Option
the viewing and design preparation of a condition
provides a complete solution for advanced
complex mixed-signal design. mixed-signal silicon realization. Debug stepping through behavioral
Using AMS Designer with Spectre code, analog, and digital
Enables cross-domain connectivity
ensures that the user gets golden between testbenches and design Schematic tracer
simulation results for performance IP blocks from multiple vendors by
measurements Signal flow and error browser
providing native connectivity between
VHDL or SystemVerilog and SPICE Digital transaction support
Advanced circuit analysis such as
Monte Carlo can be performed with Supports assertion-based verifi- AMS Designer Verification Option
the AMS/Spectre interface, leveraging cation for analog and digital designs
the performance benefits of behavioral by extending the syntax of PSL and Native VHDL-SPICE connectivity
models and using the same setup as SVA languages, providing an efficient Native SystemVerilog to SPICE and AMS
the Spectre tool and effective methodology for connectivity
capturing design intent and verification
Advanced-model validation capabilities
automation PowerSmart connect modules for
allow users to verify their circuit
low-power support
design against a behavioral model Extends mature digital verification
automatically by comparing simulation methodologies, such as low-power Design inputs
waveforms verification, to the analog domain.
Cadence CDBA database or
Supports capturing power intent
Digital-centric flow with Incisive OpenAccess database
with CPF and automatically inserting
The AMS Designer works natively in the PowerSmart connect modules on key Verilog-AMS 2.0
Incisive environment for digital-centric interfaces
VHDL-AMS 1076.1
verification. A single control file is used to
define how analog blocks are integrated Specifications Verilog (IEEE 1364-1995, IEEE
into the digital SoC. Analog and RTL 1364-2001 extensions)
blocks can be easily interchanged to trade Virtuoso environment
VHDL (IEEE 1076-1987, IEEE 1076-1993,
off accuracy and performance. It supports Direct Verilog-AMS netlisting IEEE 1076.4-2000 [VITAL 2000])
all features in the Incisive environment like
testbench analysis, Specman technology, Hierarchy editor AMS plug-in Spectre and SPICE netlist formats
and verification planning. Hierarchy editor configuration SystemVerilog (IEEE 1800)
Automatically inserted interface Support for global design variables and Common Power Format (CPF)
elements are used to translate signals global signals
from one domain to the next, leaving Within Incisive platform: SystemC (OSCI
the user free to simulate with different Inherited connections SystemC v2.01), SystemC Verification
design configurations to easily trade
AMS Simulator Library (OSCI SCV 1.0), and Specman e
off simulation speed for simulation
accuracy Single executable mixed-signal/mixed- Design outputs
language simulator SST2 waveform format analog and
In the verification flow, the UltraSim
Full-Chip Simulator is used as the Built-in Spectre APS and Spectre RF and digital data
built-in analog simulation engine. This Incisive digital engines PSF waveform format for analog data
enables final verification of the largest
Digital and real number-modeling Verilog-AMS netlist format
mixed-signal SoCs. The Incisive digital
capabilities
simulation engine inside AMS Designer
delivers high-performance native System-level simulations with links to
Verilog, SystemVerilog, VHDL, SystemC, Simulink from MathWorks
and e simulation
Save/restart
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Virtuoso Multi-Mode Simulation with Spectre Platform
Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of todays electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify todays mobile, cloud, and connectivity applications. www.cadence.com
2013 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Incisive, Specman, Spectre, and Virtuoso are registered
trademarks of Cadence Design Systems, Inc. SystemC is a trademark of the Open SystemC Initiative, Inc. in the US and other countries and are used
with permission. All others are properties of their respective holders. 1078 09/13 SA/DM/PDF