AP5151- ADVANCED DIGITAL SYSTEM DESIGN 13.

13. (a) Perform the design of a vending machine controller with state and reduction
table,statediagram. (13)
Class: I Yr / I Sem (M.E VLSI DESIGN) Time: 9.30 to 12.30 PM
Date: Total Marks: 100 (Or)
Part A (5X2=10 Marks)
(b) Elaborate on design of Asynchronous sequential circuit and the
1. Differentiate sequential circuit from combinational circuit. various hazards encountered in its design process (13)
2. What is the significance of ASM charts? 14. (a) consider the design of a 4 bit BCD Counter that counts in the following
3. Distinguish between positive logic and negative logic way: 0000,0001, 0010, 0011 1001 and back to 0000.
4. What is a race condition in ASC? a. Draw the state diagram (4).
5. Define the phrase Asynchronous sequential circuits. b. list the next state table (4)
6. What are Iterative circuits?list the major steps used foriterative circuit c. Draw the logic diagram of the circuit (8)
design. (Or)
7. What is a ASM chart? Draw the ASM chart for a mod-4 binary counter. (b) Design a MOD-10 synchronous counter using JK Flipflop .write
8. Define the state assignment problem in the Asynchronous sequential excitation table and state table (16)
circuit design. What are the possible solutions?
9. What is Mixed operating mode Asynchronous sequential circuit? State 15. (a) Design a clocked sequential circuit for the state diagram shown in
its significance figure below using J-K Flipflop.
10. How will you convert a JK flip flop into a D flip flop (Or)
(b). convert SR Flipflop into T Flipflop and JK Flipflop into T flipflop. (16)
Part B ( 5x13=65 Marks)
11. (a) Perform an analysis of clocked synchronous mealey machine with a
D-flip flop with an assumed example. (13)
(Or)
(b) Design a clocked sequential synchronous state machine with two
inputs X and Y and output Z. The output should be on if the number
of one input on X and Y since reset is a multiple of 4 and 0
otherwise. (13) Prepared by Academic coordinator Approved by
HOD/ECE
12. (a) Explain how the behavior of a clocked synchronous sequential network is
described by a state table and discuss the method of state table reduction
example (13)

(Or)

(b) Implement the following Boolean function with a 8:1

multiplexer:
i).F(w,x,y,z)= m(0,1,3,4,5,8,9,15) (8)
ii).F(A,B,C) = m(2,4,5,7) (8)