Unidad 2: Paso 3 - Disea circuitos combinacionales de forma correcta, a

travs del uso apropiado de los conceptos bsicos y utilizando VHDL

(Parte infividual)

Presentado por:
Francisco Javier Chvez Flrez
Cdigo: 1080262056

Grupo 243004_33

Curso ELECTRONICA DIGITAL

Tutor:
Mario Ricardo Arbulu

Universidad Nacional Abierta y a Distancia UNAD

Escuela de Ciencias Bsicas, Tecnologa e Ingeniera -ECBTI
Octubre 2017
Actividades:
1. Describa en VDHL un multiplexor 8 a 1. Las lneas de entrada del
multiplexor tienen 7 bits cada una. El diseo debe contener:

Resumen de la descripcion en vhdl

---------------------------------------------------------------------------------
-- Company: UNAD
-- Engineer: FRANCISCO JAVIER CHAVEZ FLOREZ
-- Create Date: 15.10.2017 07:22:34
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplexor8a1 is
Port ( E0 : in STD_LOGIC_VECTOR (6 downto 0);
E1 : in STD_LOGIC_VECTOR (6 downto 0);
E2 : in STD_LOGIC_VECTOR (6 downto 0);
E3 : in STD_LOGIC_VECTOR (6 downto 0);
E4 : in STD_LOGIC_VECTOR (6 downto 0);
E5 : in STD_LOGIC_VECTOR (6 downto 0);
E6 : in STD_LOGIC_VECTOR (6 downto 0);
E7 : in STD_LOGIC_VECTOR (6 downto 0);
SELECTOR : in STD_LOGIC_VECTOR (3 downto 0);
SALIDA : out STD_LOGIC_VECTOR (6 downto 0));
end multiplexor8a1;
architecture Behavioral of multiplexor8a1 is
begin
with SELECTOR select
SALIDA <= E0 WHEN "000",
E1 WHEN "001",
E2 WHEN "010",
E3 WHEN "011",
E4 WHEN "100",
E5 WHEN "101",
E6 WHEN "110",
E7 WHEN OTHERS;
end Behavioral;
a. Un pantallazo de la descripcin en VHDL.
b. Un pantallazo de la simulacin, en el cual se debe evidenciar el correcto
funcionamiento del diseo.

Resumen simulacion:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simul1 is
-- Port ( );
end simul1;

architecture Behavioral of simul1 is

component multiplexor8a1
Port ( E0 : in STD_LOGIC_VECTOR (6 downto 0);
E1 : in STD_LOGIC_VECTOR (6 downto 0);
E2 : in STD_LOGIC_VECTOR (6 downto 0);
E3 : in STD_LOGIC_VECTOR (6 downto 0);
E4 : in STD_LOGIC_VECTOR (6 downto 0);
E5 : in STD_LOGIC_VECTOR (6 downto 0);
E6 : in STD_LOGIC_VECTOR (6 downto 0);
E7 : in STD_LOGIC_VECTOR (6 downto 0);
SELECTOR : in STD_LOGIC_VECTOR (3 downto 0);
 SALIDA : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;

-- Seales de las entradas

signal E0 : std_logic_vector(6 downto
signal E1 : std_logic_vector(6 downto
signal E2 : std_logic_vector(6 downto
signal E3 : std_logic_vector(6 downto
signal E4 : std_logic_vector(6 downto
signal E5 : std_logic_vector(6 downto
signal E6 : std_logic_vector(6 downto
signal E7 : std_logic_vector(6 downto
signal SELECTOR : std_logic_vector(3
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
0) := (others => '0');
downto 0) := (others => '0');

-- Seales de salidas
signal SALIDA : std_logic_vector(6 downto 0)

begin
UO: multiplexor8a1
Port map (
E0 => E0,
E1 => E1,
E2 => E2,
E3 => E3,
E4 => E4,
E5 => E5,
E6 => E6,
E7 => E7,
SELECTOR => SELECTOR,
SALIDA => SALIDA
);
process
begin

--- Estmulos de la simulacin

wait for 100 ns;
E0 <= "0000001";
E1 <= "0000010";
E2 <= "0000100";
E3 <= "0001000";
E4 <= "0010000";
E5 <= "0100000";
E6 <= "1000000";
E7 <= "0000000";
SELECTOR <= "000"
wait for 100 ns;
SELECTOR <= "001"
wait for 100 ns;
SELECTOR <= "010"
wait for 100 ns;
SELECTOR <= "011"
wait for 100 ns;
SELECTOR <= "100"
wait for 100 ns;
SELECTOR <= "101"
wait for 100 ns;
SELECTOR <= "110"
wait for 100 ns;
SELECTOR <= "111"
wait for 100 ns;

wait;
end process;

end Behavioral;
 2. Describa en VDHL un decodificador de 3 entradas.
Nota en la tabla de verdad se debe tomar los 8 bit como queda como
decodificador de 3 a 8. Tomoanfo como partida que un decodificador de N
entradas es capa de direccionar 2 espacios de memorias. Para el ejercicio
empleare 3 a 6

Resumen de la descripcion en vhdl

----------------------------------------------------------------------------------
-- Company: UNAD
-- Engineer: FRANCISCO JAVIER CHAVEZ FLOREZ
-- Create Date: 15.10.2017 10:45:28
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decodificador3a6 is
Port ( E0 : in STD_LOGIC;
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_LOGIC;
S4 : out STD_LOGIC;
S5 : out STD_LOGIC;
S6 : out STD_LOGIC;
S7 : out STD_LOGIC
);
end decodificador3a6;

architecture Behavioral of decodificador3a6 is

signal ENTRADAS : std_logic_vector(2 downto 0);
signal SALIDAS : std_logic_vector(7 downto 0);

begin
ENTRADAS <= E2 & E1 & E0;
with ENTRADAS select
 SALIDAS <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
S7 <= SALIDAS (7);
S6 <= SALIDAS (6);
S5 <= SALIDAS (5);
S4 <= SALIDAS (4);
S3 <= SALIDAS (3);
S2 <= SALIDAS (2);
S1 <= SALIDAS (1);
S0 <= SALIDAS (0);

end Behavioral;

El diseo debe contener:

a. Un pantallazo de la descripcin en VHDL.
b. Un pantallazo de la simulacin, en el cual se debe evidenciar el correcto funcionamiento del
diseo.

Resumen simulacion:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PRUEBA1 is
-- Port ( );
end PRUEBA1;

architecture Behavioral of PRUEBA1

component decodificador3a6
Port ( E0 : in STD_LOGIC;
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_LOGIC;
S4 : out STD_LOGIC;
S5 : out STD_LOGIC;
S6 : out STD_LOGIC;
S7 : out STD_LOGIC
);
-- Seales de las entradas
signal E0 : std_logic := '0';
signal E1 : std_logic := '0';
signal E2 : std_logic := '0';

-- Seales de salidas
signal S0 : std_logic;
signal S1 : std_logic;
signal S2 : std_logic;
signal S3 : std_logic;
signal S4 : std_logic;
signal S5 : std_logic;
signal S6 : std_logic;
signal S7 : std_logic;

begin
UTT: decodificador3a6
Port map (
E0 => E0,
E1 => E1,
E2 => E2,
S0 => S0,
S1 => S1,
S2 => S2,
S3 => S3,
S4 => S4,
S5 => S5,
S6 => S6,
S7 => S7
);

stim_proc: process

begin
wait for 100 ns;

E0 <= '0';
E1 <= '0';
E2 <= '0';
wait for 100 ns;

E0 <= '1';
E1 <= '0';
E2 <= '0';
wait for 100 ns;

E0 <= '0';
E1 <= '1';
E2 <= '0';
wait for 100 ns;

E0 <= '1';
E1 <= '1';
E2 <= '0';
wait for 100 ns;

E0 <= '1';
E1 <= '1';
E2 <= '0';
wait for 100 ns;

E0 <= '0';
E1 <= '0';
E2 <= '1';
wait for 100 ns;

E0 <= '1';
E1 <= '0';
E2 <= '1';
wait for 100 ns;
E0 <= '1';
E1 <= '1';
E2 <= '1';
wait for 100 ns;

wait;
end process;
end Behavioral;
3. Describa en VDHL un codificador de 4 entradas, sin prioridad.

Resumen de la descripcion en vhdl

---------------------------------------------------------------------------------
-- Company: UNAD
-- Engineer: FRANCISCO JAVIER CHAVEZ FLOREZ
-- Create Date: 15.10.2017 14:20:55

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity codificador4E is
Port ( E3 : in STD_LOGIC;
E2 : in STD_LOGIC;
E1 : in STD_LOGIC;
E0 : in STD_LOGIC;
S2 : out STD_LOGIC;
S1 : out STD_LOGIC;
S0 : out STD_LOGIC);
end codificador4E;

architecture Behavioral of codificador4E is

signal ENTRADAS : std_logic_vector(3 downto 0);
signal SALIDAS : std_logic_vector(2 downto 0);

begin
ENTRADAS <= E3 & E2 & E1 & E0;
with ENTRADAS select
SALIDAS <= "000" when "0000",
"001" when "0001",
"010" when "0010",
"011" when "0100",
"100" when "1000",
"000" when others;
S2 <= SALIDAS (2);
S1 <= SALIDAS (1);
S0 <= SALIDAS (0);

end Behavioral;
El diseo debe contener:
a. Un pantallazo de la descripcin en VHDL.
 b. Un pantallazo de la simulacin, en el cual se debe evidenciar el correcto
funcionamiento del diseo.
Resumen simulacion:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PRUEBA2 is
-- Port ( );
end PRUEBA2;
architecture Behavioral of PRUEBA2
component codificador4E
Port ( E3 : in STD_LOGIC;
E2 : in STD_LOGIC;
E1 : in STD_LOGIC;
E0 : in STD_LOGIC;
S2 : out STD_LOGIC;
S1 : out STD_LOGIC;
S0 : out STD_LOGIC
);
-- Seales de las entradas
signal E3 : std_logic := '0';
signal E2 : std_logic := '0';
signal E1 : std_logic := '0';
signal E0 : std_logic := '0';
-- Seales de salidas
signal S2 : std_logic;
signal S1 : std_logic;
signal S0 : std_logic;
begin
UTT: codificador4E
Port map (
E3 => E3,
E2 => E2,
E1 => E1,
E0 => E0,
S2 => S2,
S1 => S1,
S0 => S0
);
stim_proc: process
begin
wait for 10 ns;

E3 <= '0';
E2 <= '0';
E1 <= '0';
E0 <= '0';
wait for 10 ns;
E3 <= '0';
E2 <= '0';
E1 <= '0';
E0 <= '1';
wait for 10 ns;

E3 <= '0';
E2 <= '0';
E1 <= '1';
E0 <= '0';
wait for 10 ns;

E3 <= '0';
E2 <= '1';
E1 <= '0';
E0 <= '0';
wait for 10 ns;

E3 <= '1';
E2 <= '0';
E1 <= '0';
E0 <= '0';
wait for 10 ns;
wait;
end process;
end Behavioral;
4. Describa en VDHL un codificador de 4 entradas, con prioridad a la entrada
menor.

Resumen de la descripcion en vhdl

----------------------------------------------------------------------------------
-- Company: UNAD
-- Engineer: FRANCISCO JAVIER CHAVEZ FLOREZ
-- Create Date: 15.10.2017 15:28:21
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity codificador_prioridad is
Port ( E3 : in STD_LOGIC;
E2 : in STD_LOGIC;
E1 : in STD_LOGIC;
E0 : in STD_LOGIC;
S2 : out STD_LOGIC;
S1 : out STD_LOGIC;
S0 : out STD_LOGIC);
end codificador_prioridad;
architecture Behavioral of codificador_prioridad is
signal SALIDAS : std_logic_vector(2 downto 0);

begin
-- se debe usar la sentencia when / else...
SALIDAS <= "100" when E3 = '1' else
"011" when E2 = '1' else
"010" when E1 = '1' else
"001" when E0 = '1' else
"000";
S2 <= SALIDAS (2);
S1 <= SALIDAS (1);
S0 <= SALIDAS (0);

end Behavioral;
El diseo debe contener:
a. Un pantallazo de la descripcin en VHDL.
 b. Un pantallazo de la simulacin, en el cual se debe evidenciar el correcto
funcionamiento del diseo.
Resumen simulacion
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PRUEBA3 is
-- Port ( );
end PRUEBA3;

architecture Behavioral of PRUEBA3

component codificador_prioridad
Port ( E3 : in STD_LOGIC;
E2 : in STD_LOGIC;
E1 : in STD_LOGIC;
E0 : in STD_LOGIC;
S2 : out STD_LOGIC;
S1 : out STD_LOGIC;
S0 : out STD_LOGIC
);
-- Seales de las entradas
signal E3 : std_logic := '0';
signal E2 : std_logic := '0';
signal E1 : std_logic := '0';
signal E0 : std_logic := '0';
-- Seales de salidas
signal S2 : std_logic;
signal S1 : std_logic;
signal S0 : std_logic;
begin
UTT: codificador_prioridad
Port map (
E3 => E3,
E2 => E2,
E1 => E1,
E0 => E0,
S2 => S2,
S1 => S1,
S0 => S0
);
stim_proc: process
begin
wait for 10 ns;
E3 <= '0';
E2 <= '0';
E1 <= '0';
E0 <= '0';
wait for 10 ns;
E3 <= '0';
E2 <= '1';
E1 <= '0';
E0 <= '1';
wait for 10 ns;
E3 <= '0';
E2 <= '0';
E1 <= '1';
E0 <= '0';
wait for 10 ns;
E3 <= '0';
E2 <= '1';
E1 <= '1';
E0 <= '0';
wait for 10 ns;
E3 <= '1';
E2 <= '0';
E1 <= '0';
E0 <= '1';
wait for 10 ns;

wait;
end process;
end Behavioral;
5. Describa en VDHL el circuito que se muestra en la siguiente figura. El diseo
debe contener tres mdulos diferentes y un archivo de alto nivel, tal como se
muestra en la siguiente figura.

SELECTOR

Resumen archivo de alto nivel en VDHL

----------------------------------------------------------------------------------
-- Company: UNAD
-- Engineer: FRANCISCO JAVIER CHAVEZ FLOREZ
-- Create Date: 15.10.2017 16:48:39
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity alto_nivel is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
SELECTOR : in STD_LOGIC;
F : out STD_LOGIC_VECTOR (3 downto 0));
end alto_nivel;

architecture Behavioral of alto_nivel is

component MULTIPLEXOR
Port (
I0_M : in STD_LOGIC_VECTOR (3 downto 0);
I1_M : in STD_LOGIC_VECTOR (3 downto 0);
SEL : in STD_LOGIC;
S_M : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component SUMA
Port (
E_1_S : in STD_LOGIC_VECTOR (3 downto 0);
E_2_S : in STD_LOGIC_VECTOR (3 downto 0);
S_S : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

component RESTA
Port (
E_1_R : in STD_LOGIC_VECTOR (3 downto 0);
E_2_R : in STD_LOGIC_VECTOR (3 downto 0);
S_R : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

-- Seales de conexion...
signal C1 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal C2 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');

begin

MULTIPLEXOR1: MULTIPLEXOR
Port map(
I0_M => C1,
I1_M => C1,
SEL => SELECTOR,
S_M => F
);

SUMADOR1: SUMA
Port map(
E_1_S => A,
E_2_S => B,
S_S => C1
);

RESTADOR1: RESTA
Port map(
E_1_R => A,
E_2_R => B,
S_R => C2
);

end Behavioral;
El diseo debe contener:
a. Un pantallazo de la descripcin en VHDL.
b. Un pantallazo con el RTL del alto nivel.

b. Un pantallazo de la simulacin, en el cual se debe evidenciar el correcto

funcionamiento del diseo.

Resumen Simulacion
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prueba4 is
-- Port ( );
end prueba4;

architecture Behavioral of prueba4

component multiplexor
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
SELECTOR : in STD_LOGIC;
F : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- Seales de las entradas
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal SELECTOR : std_logic;

-- Seales de salidas
signal F : std_logic_vector(3 downto 0)
begin
UO: multiplexor8a1
Port map (
A => A,
B => B,
SELECTOR => SELECTOR,
F => F
);
process
begin
--- Estmulos de la simulacin
wait for 10 ns;
A <= "0000001";
B <= "0000010";
SELECTOR <= "00"
wait for 10 ns;
SELECTOR <= "01"
wait for 10 ns;
SELECTOR <= "10"
wait for 10 ns;
SELECTOR <= "11"
wait for 10 ns;

wait;
end process;

end Behavioral;
Sitios web:

1. Muoz, J. (2012). Introduccin a los Sistemas Digitales: Un enfoque usando

Lenguajes de Descripcin de Hardware. (Captulos 4, 5 y 6, pp. 77-134). Madrid.
Recuperado de https://openlibra.com/es/book/introduccion-a-los-sistemas-digitales
2. Fajardo, C. (2012, diciembre 20), Introduccin a VHDL, circuitos combinacionales
(Parte 1) [Archivo de video], Recuperado de https://youtu.be/OIj59kyR7wU
3. Fajardo, C. (2012, diciembre 21), Introduccin a VHDL, circuitos combinacionales
(Parte 2) [Archivo de video], Recuperado de https://youtu.be/dK545R-YT58
4. Fajardo, C. (2017, Julio 9), Diseo de un multiplexor en VHDL en Vivado [Archivo
de video]. Recuperado de http://youtu.be/tFykKHLwLCw?hd=1
5. Fajardo, C. (2017, julio 13), Diseo jerrquico en VHDL. [Archivo de video],
Recuperado de https://youtu.be/fiLkRDRif4Y

Otros sitios web

6. Chu, P. P. (2006). RTL Hardware Design Using VHDL : Coding for Efficiency,
Portability, and Scalability. Hoboken, N.J.: Wiley-IEEE Press (Chapter 4, pp. 69-95)).
Recuperado de:
http://bibliotecavirtual.unad.edu.co:2051/login.aspx?direct=true&db=e000xww&AN
=158127&lang=es&site=ehost-live

Sitios web:

7. Muoz, J. (2012). Introduccin a los Sistemas Digitales: Un enfoque usando

Lenguajes de Descripcin de Hardware. (Captulos 4, 5 y 6, pp. 77-134). Madrid.
Recuperado de https://openlibra.com/es/book/introduccion-a-los-sistemas-digitales
8. Fajardo, C. (2012, diciembre 20), Introduccin a VHDL, circuitos combinacionales
(Parte 1) [Archivo de video], Recuperado de https://youtu.be/OIj59kyR7wU
9. Fajardo, C. (2012, diciembre 21), Introduccin a VHDL, circuitos combinacionales
(Parte 2) [Archivo de video], Recuperado de https://youtu.be/dK545R-YT58
10. Fajardo, C. (2017, Julio 9), Diseo de un multiplexor en VHDL en Vivado [Archivo
de video]. Recuperado de http://youtu.be/tFykKHLwLCw?hd=1
11. Fajardo, C. (2017, julio 13), Diseo jerrquico en VHDL. [Archivo de video],
Recuperado de https://youtu.be/fiLkRDRif4Y

Otros sitios web

12. Chu, P. P. (2006). RTL Hardware Design Using VHDL : Coding for Efficiency,
Portability, and Scalability. Hoboken, N.J.: Wiley-IEEE Press (Chapter 4, pp. 69-95)).
Recuperado de:
http://bibliotecavirtual.unad.edu.co:2051/login.aspx?direct=true&db=e000xww&AN
=158127&lang=es&site=ehost-live