Low-power bottom-plate sampling 5/4Vcm1/2Vip 7/4Vcm1/2Vip

capacitor-splitting DAC for SAR ADCs Vcm

C C C C
Vcm Vcm Vcm
C C C C
B0 = 0 or 1? B0 = 0 or 1?
Vcm Vcm V V > 3/4V ?
B. Yazdani, A. Khorami and M. Sharifkhani
Vip Vin > 1/4Vref ? ip in ref
Vcm Vcm
C C C C C C C C

A highly energy-efcient switching method for capacitor-splitting Vcm1/2Vin Vcm1/2Vin

digital-to-analogue converter (DAC) in successive approximation reg-
ister (SAR) analogue-to-digital converters (ADCs) is presented. In the E = 1/16CV 2ref no E = 1/16CV 2ref yes

proposed DAC, a bottom-plate sampling method is introduced which 3/2Vcm1/2Vip

requires only one reference voltage (Vcm = 1/2Vref ) during the entire Vcm Vcm
C C C C
DAC switching steps. Therefore, in addition to the switching energy B1 = 0 or 1?
Vcm Vip Vin > 1/2Vref ?
reduction, the precision of the DAC is increased since only one refer-
Vcm
ence voltage is used. The DAC average switching energy and the area C C C C
are reduced by 98.44% and 50% compared with the conventional
binary weighted DAC. Vcm1/2Vin

E=0 yes
DACP
3/2Vcm1/2Vip
Introduction: Digital-to-analogue converter (DAC) switching energy is Vip Vip Vcm Vcm
the dominant portion of the total energy consumption in the new gener- C3,2=C C3,1=C C2=C C1=C E=0 C C C C
B2 = 0 or 1?
ation of the successive approximation register analogue-to-digital con- Vcm Vcm
Vip>Vin?
verters (ADCs). Recently, several methods have been introduced to Vcm Vcm
C3,2=C C3,1=C C2=C C1=C C
C C C
reduce the DAC power consumption [16]. The conventional binary Vin Vin Vcm Vcm
weighted DAC offers a simple switching procedure, however, it is not 3/2Vcm1/2Vin
DACN
energy efcient, since it consumes a large amount of energy during E = 0 no
and after the sampling phase (especially during the ADC rst bit deter-
Vcm1/2Vip
mination) [1]. As a remedy, the capacitor-splitting method was intro-
duced to reduce the energy consumption of some switching steps [1]. C C C C
B1 = 0 or 1?
Using the capacitor-splitting DAC, the average switching energy was Vcm V V > 1/2V ?
ip in ref

reduced by 37.84% [1]. The capacitor-splitting DAC also consumes a Vcm

C C C C
large amount of energy during the rst step of ADC conversion. In Vcm Vcm
order to further reduce the switching energy, some methods with 3/2Vcm1/2Vin
more than one reference voltage (Vref ) are proposed [26]. These E = 1/16CV 2ref no E = 1/16CV 2ref yes
methods reduce the average switching energy by 96.89, 97.66, 87.52,
Vcm1/2Vip Vcm1/2Vip
93.7 and 96.91%, respectively, compared with the conventional
binary weighted DAC. The precision of the methods proposed in [2, C C C C C C C C
B0 = 0 or 1?
B0 = 0 or 1?
3] is highly dependent on the precision of the second voltage reference Vcm Vip Vin > 3/4Vref ?
Vcm V V > 1/4V ?
ip in ref

(Vcm). The methods reported in [5, 6] are proposed to mitigate the effect Vcm Vcm
C C C C C C C C
of the Vcm voltage precision on the DAC INL/DNL, although the Vcm Vcm Vcm Vcm Vcm
dependency remains to some extent. In the proposed switching
7/4Vcm1/2Vin 5/4Vcm1/2Vin
method, Vcm is used as the only reference voltage along with a new
sampling method. As a result, the average switching energy reduces sig-
nicantly while the precision of Vcm do not affect the precision of the Fig. 2 Proposed switching scheme of 3-bit SAR ADC
DAC (since only one reference voltage is used). Moreover, the proposed
switching method offers a simple control circuit which results in a low In this step, the output voltages of DACP and DACN are (3/2Vcm1/
power consumption in comparison to those methods which use more 2Vip) and (3/2Vcm1/2Vin), respectively. The comparator determines
than one reference voltage. whether B2 = 1 or B2 = 0. If Vip > Vin then, B2 is 1, otherwise B2
is 0. In this step, the switching energy is zero as proven in the follow-
ing derivations.
Proposed switching method: Fig. 1 presents the implementation of the
proposed DAC for a 10-bit ADC during the sampling phase. The binary E = EDACP + EDACN
splitted MSB capacitors are shown in the shaded region. In the

 E = 2C Vcm VCP,MSP2 VCP,MSP1 + 2C Vcm (VCN,MSP2 VCN,MSP1 )
sampling-phase, the top-plates of all the capacitors are connected to
Vcm ( = 1/2Vref ) while the bottom-plates of the MSB capacitors are con- (1)
nected to the input signals. The bottom-plates of other capacitors are  
Vin + Vip
connected to GND to be charged to Vcm. E = 2C Vcm Vcm , Vin = Vref Vip (2)
2
 
Vref
DACP
E = 2C Vcm Vcm =0 (3)
Vip
Vcm
2
7
2C 2C C C
7
2C 2C C C EDACN and EDACP are the switching energy of DACN and DACP. The
voltage of the MSB capacitors before and after the rst switching step is
Vcm SAR
Vcm logic shown in Fig. 3.
7 7
2C 2C C C 2C 2C C C
3/2Vcm1/2Vip
VCP,MSP1 = VipVcm VCP,MSP2 = 1/2Vip1/2Vcm
Vin Vcm
Vip Vip Vcm Vcm
+ C
VCP,MSP1 C C C VCP,MSP2+ C C C C
DACN
Vcm E=0 Vcm
Vcm Vcm
Fig. 1 Proposed 10-bit SAR ADC at the sampling phase VCN,MSP1
+ C C C C
VCN,MSP2
+ C C C C
Vin Vin Vcm Vcm
VCN,MSP1 = VinVcm VCN,MSP2 = 1/2Vin1/2Vcm
Fig. 2 presents an example of a 3-bit DAC using the proposed switch- 3/2Vcm1/2Vin

ing method. In each step, the switching energy and the output voltage of
DACN and DACP are shown in red and blue colours. In the sampling
phase, the input signals are sampled on the bottom-plates of the MSB
capacitors (C3,2, C3,1). Then, the sampling switches are disconnected
and the bottom-plates of the MSB capacitors are connected to Vcm.
Fig. 3 Proposed energy-efcient switching sequence after sampling phase
In the second step of the switching procedure, if Vip > Vin the bottom-
plates of the MSB capacitor in DACN are connected to GND, then the

ELECTRONICS LETTERS 26th May 2016 Vol. 52 No. 11 pp. 913915

comparator determines the second bit (B1) by comparing 1/2Vcm and (1/ Table 1: Comparison of several methods for a 10-bit DAC
2Vip1/2Vin). Otherwise, (Vip < Vin) the bottom-plates of MSB capaci- Average switching Energy Dependency on the
tors in DACP are connected to GND and B1 is determined by comparing Scheme 2
energy (CVref ) saving accuracy of Vcm
(1/2Vip1/2Vin) and 1/2Vcm. In this step, there is no switching energy. Conventional [1] 1363.33 Reference
In fact, during the switching, one of the capacitor banks (DACP or Capacitor-splitting
DACN) is left unchanged and in the other bank the capacitors are con- 852.33 37.48%
[1]
nected to GND while Vcm is disconnected. The third step of the switch- Tri-level [2] 42.41 96.89% Very high
ing procedure depends on B2. If B2 = 1 only the DACP experiences a Vcm-based monotonic
31.88 97.66% Very high
switching. In this case, if B1 = 1 the bottom-plate of C2 in DACP is [3]
connected to Vcm, otherwise, the bottom-plates of C3,2 are connected Vcm-based [4] 170.16 87.52% no
to GND. If B2 = 0 only the DACN experiences a switching. In this Rahimi and Yavari
84.90 93.70% Very low
case, if B1 = 1 the bottom-plates of C3,2 in DACN are connected to [5]
GND, otherwise the bottom-plate of C2 is connected to Vcm. Xie et al. [6] 42.17 96.91% Very low
Following the mentioned switching, the third bit (B0) is determined. This work 21.20 98.44% no
Generally, the next switching steps of the switching method for an
N-bit DAC is the same as the mentioned switching step. Conclusion: A DAC with a low energy switching method is presented.
In the proposed switching method, a division by two of the input In this method, the MSB capacitor is splitted into smaller binary
signals is used. The division by two let us use only one reference weighted parts and only one reference voltage is used to perform the
voltage of Vcm = 1/2Vref. Therefore, the switching energy is reduced sig- switching steps. The proposed switching procedure reduces the
nicantly and the effect of Vcm precision on the DAC linearity is elimi- average switching energy and the area by 98.44% and 50% compared
nated. Moreover, the control circuit of the proposed switching procedure with the conventional binary weighted DAC. Unlike previous works,
is simpler than the methods that use both Vcm and Vref, since less number the precision of the DAC is independent the precision of Vcm. As a
of switches are used to implement the DAC (so less control signals). In result, the proposed switching procedure is a suitable choice for high-
fact, in the methods that use more than one reference voltage, there are resolution low-power applications.
multiple switches for every DAC capacitor to connect them to all the
voltage references. The Institution of Engineering and Technology 2016
Submitted: 21 January 2016 E-rst: 26 April 2016
Switching energy simulations: Behavioural simulation of a 10-bit DAC doi: 10.1049/el.2016.0087
considering the high-precision methods was performed to draw a com- One or more of the Figures in this Letter are available in colour online.
parison. Fig. 4 presents the switching energy for the proposed and high-
precision methods (which use Vcm). The proposed switching method B. Yazdani, A. Khorami and M. Sharifkhani (Department of Electrical
offers the smallest switching energy over the entire range of the Engineering, Sharif University of Technology, Tehran, Iran)
output codes. E-mail: khorami@alum.sharif.ir

250 References
1 Ginsburg, B.P., and Chandrakasan, A.P.: 500-MS/s 5-bit ADC in 65-nm
200
CMOS with split capacitor array DAC, IEEE J. Solid-State Circuits,
switching energy, CV 2ref

Vcm-based [4]
Rahimi and Yavari [5]
2007, 42, (4), pp. 739747
150
Xie et al. [6] 2 Yuan, C., and Lam, Y.: Low-energy and area-efcient tri level switching
proposed
scheme for SAR ADC, Electron. Lett., 2012, 48, (9), pp. 482483
100
3 Zhu, Z., Xiao, Y., and Song, X.: Vcm-based monotonic capacitor switch-
50
ing scheme for SAR ADC, Electron. Lett., 2013, 49, (5), pp. 327329
4 Zhu, Y., Chan, C.-H., Chiu, U.-F., Sin, C.-W., U., S.-P., Martins, R.P.,
0
and Maloberti, F.: A 10-bit 100-MS/s reference-free SAR ADC in
0 200 400 600 800 1000 90 nm CMOS, IEEE J. Solid-State Circuits, 2010, 45, (6),
output code
pp. 11111121
5 Rahimi, E., and Yavari, M.: Energy-efcient high-accuracy switching
Fig. 4 Switching energy against output code method for SAR ADCs, Electron. Lett., 2014, 50, (7), pp. 499501
6 Xie, L., Su, J., Liu, J., and Wen, G.: Low-power high precision
The comparison between the proposed and other switching pro- capacitor-splitting DAC for SAR ADCs, Electron. Lett., 2015, 51, (6),
cedures are presented in Table 1. The average switching energy of the pp. 460462
2
proposed switching procedure is 21.20CVref . The energy reduction is
98.44% compared with the conventional binary weighted DAC. In
fact, in the rst two steps of the proposed DAC there is no switching
energy and in other steps in only one bank (DACP or DACN) there is
switching with the magnitude of Vcm. The average switching energy
of the proposed DAC is calculated using the following equation.
1
Eavg (2N 3 0.625) (4)
6

ELECTRONICS LETTERS 26th May 2016 Vol. 52 No. 11 pp. 913915