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inverters K WOhI
1. INTRODUCTION =
IF min
V'O,
aw
m o
192
V,O.i.+N(+0.5K, if O5v,, K,
V,(0%24=m v,omin+nji+Ki+0.5K2 if K1<VigK1+K2(2) C. The maximum offset SVPWM
rOmin+P +K, +K2 +0.5Kj if K, +K2 <v,, < This SVPWM method generates function v,),,vm as closest
to the maximum offset function defined as
where VrO = 0.5(n - 1)- max as shown in Fig.3b. Substituting
the function v,( into (2)-(3), the output offset can be deduced.
Vr1 = VrO,ref Vro min nO
-
'..007s$,
-1-- 21
t1-2 2
1 ,22Ne r
Vr,0, = 0
V rm if
if
V rimin
VrOm
r>ma
0 VrOmin *(6)
-2-2--12 21-12-1m 0>2-2
0
-1-2- .2 2-2-2 c) ~~~~.2-1
a) 0 5 I0
11 20
Figure 2: Minimum offset SVPWM: a) vector diagram and locations of active From the analysis described in [4], the locations of active
redundant vectors and corresponding areas; diagrams of zero sequence redundant states and the limited boundaries are drawn in Fig.4.
function and modulating signal of b)minimum offset CPWM and c) For m=0.8, there are 3 extra switchings while reference vector
minimum offset SVPWM (m=0.8). goes through the first hexagon sector. There are totally 3x6=18
extra switchings per a fundamental period and each
To investigate the number of the additional switchings, the modulating signal contributes 6 extra switchings. As a result,
area of the first hexagon sector is divided by several boundaries the A-phase modulating signal passes the carrier boundaries at
(the bold lines), which clarify additional switchings while the levels of 1,0 and -1 six times as shown in Fig.4c.
reference voltage vector crosses over them. In Fig.2a, for
m=0.8, there are 4 extra switchings while reference vector E. The medium common mode SVPWM
goes through the first hexagon sector. There are totally 4x6=24 The reference zero sequence function of medium CM
extra switchings per a fundamental period and each PWM (SFO-PWM) is defined as average value from two
modulating signal adds an amount of 8 extra switchings. As a extreme zero sequence functions and determined for an odd
result, the A-phase modulating signal passes the carrier level inverter as follows:
boundaries at levels of 1,0 and -1 eight times as shown in
Fig.2b,c. VrO,rej' = (VrOmax + VrOmin) / 2 = -(max + min) / 2. (7)
193
The location of the active centered redundant vectors in the 22-2 2 m oe
medium zero sequence PWM method are marked by the small 2- / \/
dashed circles in Fig.5. Being different from the previous / 2-2
methods, a dotted line appears and indicates that two \ b)
additional switchings occur while the reference voltage vector 22ot2
the A-phase modulating
For the modulating
crosses it.
over
signal for m=0.8 are drawn in Fig.5b.
index range of (0,5-0,577), there are totally
The diagrams of
194
C^QDbseld PWM TABLE 11. NUMBER OF EXTRA SWITCHINGS IN A FUNDAMENTAL
PERIOD FOR SEVEN-LEVEL INVERTER
1,5 Modulation index Minimum CMV Medium zero
SVPWM sequence SVPWM
1.0
0-0.288 6 6
0.i 0.288-0.33 18 6
0.0
0.U- 0.33-0.3849 18 30
f 0.3849-0.577 18 18
0.577-0.666 30 18
0.666-0.7698 30 42
0.7698-1 30 30
195
SVPWM appears preferable if reference vector appears in the
"high priority" areas (i.e. approximately m<0.66). For K,<Kp 101
(V1Vk)2
(reference vector moves in "low priority" areas ), the THD THD )2
factor situation of SVPWM becomes less convenient than the k J (Vk Ik I (0)
DPWM [7]. Similar results can be observed from the three- k=2 k=2
level inverter study [8]. The minimum/maximum offset
SVPWM ("two-level SVPWM") method achieves a good where Vk is the value of the effective k-th harmonics voltage,
THD factor for low modulation index range (Fig.9a) if the deduced from Fourier analysis. The results of Fourier analysis
reference vector appears in the "high priority" areas and a of the line voltage have been computed for fundamental
worse THD performance in the remaining triangle area of the
smallest hexagon. In the contrary, the medium CM SVPWM
frthenc oltand cave been o for Hamonics
frequency of 50Hzand carrier frequency of .5kHz. Harmonics
("three-level SVPWM") becomes advantageous for outer of orders 2 to 101 have been summed up in the obtained
triangle area of the smallest hexagon, since for its active results. The obtained diagrams for five level inverter are drawn
vectors the mentoned
vectors,
the mentioned areas are of
ares are "high priority" (Fig 9b).
of"highprority"ig9b in Fig. I I a. offset
minimum
From the diagrams, the THD of thelow
SVPWM are the same for
maximum and
modulation
By applying the previous considerations to five-level index of m<0.25 and superior in the range of (O<m<O. 15). The
inverter, the diagrams of "high/low priority" areas can be THD of the medium and minimum CM SVPWM are the same
drawn in Fig.lOa,b,c and d. It can be clearly seen that, the for m<0.42, their characteristics are appropriately most
minimum/maximum offset SVPWM could be superior in the superior in the range of (0.15<m<0.43). For the remaining
lowest modulation index range, i.e. for m<0. 15 for the best range, the minimum CM SVPWM would give a lowest THD
THD performance. The medium CM SVPWM would get an values for around values of m=0.5, 0.65,0.75 and 0.85, while
inconvenient harmonics distortion for around of m=0.5 while the medium CM SVPWM shows be advantageous around
voltage vector passes the low priority areas the most. An m=0.45, 0.55, 0.6,0.7,0.8 and in the range of (0.9,1). The
improved THD factor can be supposed at the highest THD factor values of minimum CM SVPWM diagram are
modulation index, close to a unit value. Above the value of particular worsen compared to medium CM SVPWM at some
m=0. 15, the lower THD factor values would be alternated narrow range of 0.45,0.55 and 0.6. It should be noticed that in
between minimum and medium CM SVPWM. the range of 0.43<m<cl, the minimum/maximum offset
SVPWM can be competitive to minimum/medium CM
SVPWM for several modulation ranges.
a) f/' ""\ b) ,,'-'. Since the difference between THD factors of minimum and
medium CM SVPWM methods are small for 0. 73<m<1 and
A KI3K2; B A'nx B under switching loss consideration in section 1I, from both
4,,, 3, ,KKj\/ y > < methods, the minimum CM SVPWM could be a good choice in
Ul
K1^K2>K3 |K2KI>K3
C U'
/;
C
FBa
U2
the range of 0.J5<m<C0.43 and 0. 73<m<1.
The similar conclusions have been shown in Fig. II b and c
for 7- and 9-level inverters. For full comparison, the diagrams
C) of SFO-PWM method have also been included.
M \ K1>K2 /
V. CONCLUSIONS
In the paper, several carrier based SVPWM methods have
been graphically compared. The number of switchings can be
UXlv tu urdefinitely determined in relation to modulation index. It has
been shown that regarding to number of additional switchings,
Figure 8: a) Balancing of switching time duties in a tnangle, b) locations of not any from carrier SVPWM methods can be superior in the
active redundant states and related priority areas, c) active redundant states in entire modulation range. Each SVPWM method can be
two-level inverters (no redundancy at vectors U2 and U3, d) two possible optimized in some defined ranges. Similar situation happens
. .(no redundancy of vector
active redundant states and related priority areas ~~~~~for
SVW theshe THD factors. While minimum/maximum
absolutele inithe/lower odulatoffset
~~~~~~~~~~~~~~SVPWM
show be absolutely superior in the lower modulation
U3) u index range for low THD factor and minimum number of
From mathematical opinion, the graphical explanation switchings. For the remaining range and under consideration of
using "high/low priority" areas would not be exact enough to THD factor, each from considered SVPWM methods can be
evaluate the THD factor but it could be a useful starting point optimized only for certain ranges. From them, the minimum
for considering the performance of a SVPWM method, CM and medium CM SVPWM alternately show be more
particularly its validity can properly clarify the THD factor advantageous. From all SVPWM methods, the minimum CM
balance for 2 and 3-level inverters. If number of levels is high, SVPWM has shown be more advantageous for better
the graphical approach becomes complicated. An exact balancing ofthe switching loss. In cascade multilevel inverters,
evaluating of the harmonics performances should be the balancing of switching loss can be solved by altemating the
implemented by calculating the THD factor, defined as, switching roles of switching pairs for several fundamental
periods.
196
THD
308
LOW Lwi- 0
pnosily L 10-1 Lowr , 10-1 t- M CM
1- 1 - 1~~~1 - -1 Mi,,--e
.\
1v4
h,. 1 t MCM M Oft
Figure 9: Explanation of high/low priority areas in 3-level inverter for a) two- 01
level SVPWM and b) three-level SVPWM M.d CM
O 0.1 0.2 O.3 0.4 0.8 0.8 0.7 0.5 0 1.0
-7
A~~~~~~~~~~~~~~1,3 T b)
22-5~ ~ ~ ~ ~~0
a- M.M
li Ia lo-I-s4N5sf M
-I-i~~~~~~~~~~~~~~~~~~~~0
0.0 01 0.2 0.3 0.4 0.5 0.8 0.7 0.9 0.9 1.0
V b) Figure II: Diagrams of the THD factors for a) 5-level inverter, b) 7-level
A 5-Z inveter and c) 9-level inverter.
i1
22/-
1 \/ 2
11q , 1-5n-
REFERENCES
w_;\202
H I
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llsO: 2i \ / aPo1
/ nx new multilevel PWM method- A theoretical analysis," IEEE Trans.
-11A4°,
on2 \ {/ \,[>t, \ \ 122S/ ) / J \
Power Electronics. vol.7, pp.497-505 1992
[2] J.Rodriguez.I.S.Lai, and F. Z. Peng,"Multilevel Inverters: A Survey of
Topologies, Controls, and Applications", IEEE Transactions on
-s-s
Od-s 2 OBF2 F20-2 Industrial Electronics, Vol. 49, No. 4, AUGUST 2002
[3] McGrath, B.P.; Holmes, D.G.; Lipo, T., "Optimized space vector
switching sequences for multilevel inverters", IEEE Transactions on
Figure 10: Actve redundant states and related areas for a) minimum CM Power Electronics, Vol.18, No.6, Nov. 2003, pp. 1293 -1301
SVPWM, b) medium CM SVPWM, c)minimum offset and d) maximum [4] N.V.Nho, G.W.Moon, M.J.Youn, "An analysis of CPWM methods in
offset SVPWM. relation
to common mode voltage for multilevel inverters', CD ROM
Conf. Proc. IECON 2004
[5] N.V.Nho, M.J.Youn," A Comprehensive study on SVPWM-carrier
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[6] V. Blasko, "Analysis of a hybrid PWM based on modified space vector
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[7] A.M. Hava,RJ. Kerkman, T.A.Lipo "A high performance generalized
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[8] Thomas Brucker, D.G. Holmes, "Optimal Pulse Width modulation for
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197