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A Carrier-Based PWM Strategy with Zero-Sequence
Voltage Injection for a Three-Level Neutral-Point-
Clamped Converter
Josep Pou, Member, IEEE, Jordi Zaragoza, Student Member, IEEE, Salvador Ceballos, Student Member, IEEE,
Maryam Saeedifard, Senior Member, IEEE, Dushan Boroyevich, Fellow, IEEE
Abstract— Performance of a Carrier-Based Pulse Width
Modulation (CB-PWM) strategy can be improved by inclusion of
a zero sequence voltage in the modulation reference signal. This
paper proposed a new CB-PWM strategy for a three-level
neutral-point-clamped (NPC) converter, which is based on a
zero-sequence voltage injection. By inclusion of the zero
sequence voltage, the sinusoidal modulation reference is
modified to (i) carry out the voltage balancing task of the dc-link
capacitors, with no additional control effort, (ii) reduce the
switching losses, and (iii) reduce the low-frequency voltage
oscillations of the neutral point. The proposed strategy is an
alternative approach to the Nearest Three Vector (NTV) Space
Vector Modulation (SVM) strategy and is obtained by the
analysis of the NTV-SVM strategy and establishing a co-relation
with and the CB-PWM strategy. The salient features of the
proposed scheme as compared with the NTV-SVM strategy are:
(i) its computational efficiency since it does not require NTV-
SVM calculations and reduces the required processing time for
digital implementation, and (ii) its reduced switching losses
because the four-step switching sequences are avoided.
Comparing the proposed scheme and the existing CB-PWM
strategies, not only the switching losses are reduced but it also
has superior capability to balance the capacitor voltages.
Performance of the proposed CB-PWM strategy for a three-level
NPC based on time-domain simulation studies in the
MATLAB/SIMULINK environment, is evaluated and also
experimentally verified.
Index Terms— Carrier-based PWM, SVM strategy, three-level
neutral-point-clamped converter.
I. INTRODUCTION
T HE multilevel converters have attracted significant
interest for medium- and high- power/voltage
applications[1]-[12]. The most known multilevel
topologies are the neutral-point clamped (NPC), flying
capacitor, and separated dc source, presented for the first time
in [13], [14], and [15], respectively. Among them, the three-
level NPC converter has widely been accepted for various
applications [11],[12].
Several Pulse Width Modulation (PWM) strategies have
been proposed and extensively investigated for the three-level
NPC converter to achieve the following main objectives:
• To carry out the voltage balancing task of the dc-link
capacitors which is the main technical challenge of the
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NPC converter.
• To eliminate the low-frequency oscillations of the
Neutral Point (NP) voltage which appear under certain
operating conditions and if not mitigated, impose
stress on the converter components.
The proposed PWM strategies for a three-level NPC
converter are mainly classified into the Carrier-Based (CB-
PWM) strategies and the SVM strategies. The CB-PWM
strategies are mostly based on pure Sinusoidal PWM
(SPWM) or a SPWM strategy in conjunction with a zero-
sequence voltage injection [16]-[19]. Compared with the
SPWM strategy, inclusion of a zero-sequence voltage extends
the linear modulation range of the converter. The existing
CB-PWM strategies do not provide natural voltage balancing;
therefore, additional control effort is required to achieve the
voltage balancing [16],[17]. The additional control effort
imposes relatively high switching frequencies in the switching
devices and also distorts the AC-side voltage spectra [20]-
[23]. In the technical literature, a CB-PWM strategy with a
proper zero-sequence voltage that (i) autonomously carries
out the voltage balancing task, with no requirement for
additional control effort, (ii) reduces the switching frequency,
and (iii) mitigates the low-frequency voltage oscillations of
the NP, has been neither proposed nor investigated.
This paper proposes a CB-PWM strategy for a three-level
NPC converter with a zero-sequence voltage injection. The
proposed strategy explores and exploits the duality between
the Nearest Three-Vector (NTV)-SVM strategy [24],[25] and
the CB-PWM strategy with a zero-sequence voltage injection
to (i) achieve voltage balancing task, (ii) reduce the switching
frequency and consequently switching losses, and (iii) to
mitigate the voltage oscillations of the NP. A theoretical basis
for the proposed CB-PWM strategy is developed based on the
analysis of the NTV-SVM strategy. Salient features of the
proposed strategy are the following:
• It operates at a switching frequency lower than that of
the existing CB-PWM strategies. As a result, the
power losses are reduced.
• It provides inherent capability to achieve voltage
balancing without any requirement to additional
control effort.
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• It mitigates the low-frequency oscillation of the NP [24],[25] and are not repeated here. Subsequent to that, the
voltage. next step is to identify the appropriate switching states and
Performance of the proposed CB-PWM strategy for a generate the switching sequence to control voltages of the
three-level NPC converter, based on time-domain simulation capacitors.
studies in the MATLAB/SIMULINK environment, is By proper selection of short vectors, i.e., 0-1-1/100, 00-
evaluated and experimentally verified. 1/110, -10-1/010, -100/011, -1-10/001, and 0-10/101, the
voltage balancing task of the dc-link capacitors is carried out.
1
The short vectors provide redundant switching states and
sa4 sb4 sc4
generate the same line-to-line ac-side voltage. However, they
C
vC2 provide currents with opposite direction flowing into the NP.
sa3 sb3 sc3
For instance, Vector 0-1-1 imposes current ia to the NP
ia a
i0 ib
(i0=ia), while Vector 100 imposes the same current in the NP
0 b
Vdc
(NP) ic
Load but in the opposite direction (i0=–ia). Adding one level to all
c
sa2 sb2 sc2 three integer numbers that define the “low” short vectors, i.e.,
C 0-1-1, 00-1, -10-1, -100, -1-10, and 0-10, results in the “high”
vC1
short vectors, i.e., 100, 110, 010, 011, 001, and 101,
sa1 sb1 sc1 respectively. Note that applying the “low” vectors results in
-1 having one or two phases connected to the lower dc-link rail,
while the “high” vectors connect one or two phases to the
Fig. 1. Schematic representation of a NPC converter.
higher dc-link rail. In any case, the line-to-line voltages do
vb0 Sector 2 not depend on the specific vector which is applied from a set
-11-1 of redundant vectors.
11-1 11-1
To analyze the NTV-SVM in details and to explore a co-
relation between that and the CB-PWM with a zero-sequence
Sector 3 010 110 Sector 1 voltage injection, only Sector 1 is considered and then based
-10-1 00-1 Region 3
-110 10-1 on minor adjustments, the analysis is generalized for all
111 Region 2
sectors.
011
000 Table I shows all possible switching sequences in Sector 1
100
-1-1-1 Region 4 for the NTV strategy. Over each sampling period, the NTVs
-111 -100 0-1-1 Region 1 1-1-1
are selected and based on the voltage balancing criteria, the
va0
appropriate short vector/vectors are selected. Then, the
optimal switching sequences, with the objective of switching
frequency minimization, are determined. For the same
-101 001 101 1-10 objective, the switching sequences are flipped afterwards so
Sector 4 -1-10 0-10 that there are no switching events in the sequence transitions.
Sector 6
In Table I, the so-called “Increasing Sequences” are the ones
in which the indices of the vectors increase throughout the
-1-11 0-11 1-11
sequence, and for the following sequences “Decreasing
vc0 Sector 5 Sequences” the indices decrease. Based on the various
(b) switching sequences presented in Table I, in most cases, one
Fig. 2. SV diagram of a NPC converter. phase does not change its switching state. This is a salient
feature of the NTV strategy which, in comparison with the
other SVM strategies, reduces the switching frequency of the
II. PROPOSED CB-PWM STRATEGY BASED OF THE DUALITY switching devices.
OF THE CB-PWM AND THE NTV-SVM STRATEGY In a CB-PWM strategy of a three-level NPC converter, two
carrier waveforms are displaced symmetrically with respect to
The three-level NPC converter of Fig. 1 has 27 switching
the zero axis. The switching signals are generated by
states in the αβ frame. In the αβ frame, a two-layer hexagon,
comparing the sinusoidal modulating waveform with the
centered at the origin of the plane, identifies the space voltage
carrier waveforms as shown in Fig. 3. When one phase does
vectors, Fig. 2. The switching states are illustrated by -1, 0,
not switch in SVM strategy, it is equivalent to maintaining the
and 1, which denote the corresponding voltage levels of -
corresponding modulation reference signal clamped to one,
Vdc/2, 0, and Vdc/2 with respect to the NP, as shown in Fig. 1.
zero, or minus one (1, 0, -1) throughout the entire PWM
At any sampling instant the tip of the voltage vector Vref is
cycle. For example, to clamp phase a to one (the higher dc-
located in a triangle formed by the NTV adjacent to the
link rail), the corresponding modulation signal should be
voltage vector, Fig. 2. The three adjacent switching vectors
maintained as equal to one. To clamp the ac-side voltages to a
constitute the best choice for synthesizing the reference
particular voltage level, a zero-sequence signal can be added
voltage vector.
to the sinusoidal modulation reference signals. As an
The determination of the adjacent switching vectors and
example, Fig. 3 shows a zero-sequence signal, voff, is added to
calculation of their corresponding duty cycles are explained in

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the sinusoidal modulation reference signals and as a result, The relationship between the locally-averaged NP current
the modulation signals are clamped at one during some and the modulation signals is as follows:
intervals. Thus, each phase during the corresponding interval
does not switch. Since only a zero-sequence signal is added to ( ) ( ) (
i0 = 1 − va, ia + 1 − vb, ib + 1 − vc, ic , ) (1)
the sinusoidal waveforms, the line-to-line voltages are where the modulation signals v x, for x={a, b, c}
preserved sinusoidal. However, the NP current is affected by
the injection of the zero-sequence signal. Therefore, a proper are vx, = vx + voff .
injected signal can assist to carry out the voltage balancing vx is the sinusoidal modulation reference signal.
task.

TABLE I
VECTOR SEQUENCES IN SECTOR 1

Short Sequences of Vectors Switching No Switching

Region Vectors (Increasing and Decreasing Sequences) Steps Phases
0-1-1 0-1-1/1-1-1/10-1 // 10-1/1-1-1/0-1-1 2 // 2 c clamped to -1
1
100 1-1-1/10-1/100 // 100/10-1/1-1-1 2 // 2 a clamped to 1
0-1-1/00-1 0-1-1/00-1/10-1 // 10-1/00-1/0-1-1 2 // 2 c clamped to -1
0-1-1/110 0-1-1/10-1/110 // 110/10-1/0-1-1 4 // 4 None
2
100/00-1 00-1/10-1/100 // 100/10-1/00-1 2 // 2 b clamped to 0
100/110 10-1/100/110 // 110/100/10-1 2 // 2 a clamped to 1
00-1 00-1/10-1/11-1 // 11-1/10-1/00-1 2 // 2 c clamped to -1
3
110 10-1/11-1/110 // 110/11-1/10-1 2 // 2 a clamped to 1
0-1-1/00-1 0-1-1/00-1/000 // 000/00-1/0-1-1 2 // 2 a clamped to 0
0-1-1/110 0-1-1/000/110 // 110/000/0-1-1 4 // 4 None
4
100/00-1 00-1/000/100 // 100/000/00-1 2 // 2 b clamped to 0
100/110 000/100/110 // 110/100/000 2 // 2 c clamped to 0

va vb vc Phase a at 1 Phase b at 1 Phase c at 1 Phase a at 1

1 1 v, vb, vc,
a

0 0

-1 -1
voff (Zero Sequence)
Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6

0 T/2 T 0 T/2 T
(a) (b)
Fig. 3. Modulation signals: (a) sinusoidal references, and (b) addition of a positive zero-sequence signal.

In the NTV-SVM strategy, the short vectors are chosen
based on the knowledge of phase currents and impacts of the
short vectors on the NP. For instance, if during a sampling
cycle, the tip of the reference vector is located within Region
1 and the lower dc-link capacitor of the NPC converter of Fig.
1 has a higher voltage level than the upper one, vC1>vC2, the
NP current must be positive (i0>0) to decrease the NP
voltage. Therefore, Vector 0-1-1 should be selected if ia is
positive. Otherwise, Vector 100 is selected. If Vector 0-1-1 is
selected, the sequence of vectors in Region 1 would be 0-1-
1/1-1-1/10-1 and as a result phase c is clamped to minus one.
Otherwise, if Vector 100 is chosen, the sequence of vectors
would be 1-1-1/10-1/100 and subsequently phase a is
clamped to one.

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If the tip of the reference vector is located within Region 2, 1; thus, the sequence of vectors is 00-1/10-1/100. In this case,
two short vectors should be selected, one from the pair of the NP current is expressed by:

vectors 0-1-1 and 100, and the other one from the pair 00-1
and 110.
Fig. 4 shows an example in which the vmax (va) is clamped
to +1. In this case, the sequence of vectors generated would
be 10-1/100/110, that is to say, the short vectors 100 and 110
are selected. The phase a current does not have any effect on
the NP current, since it is defined by
( ) ( )
i0 = 1 − va, ia + ib + 1 − vc, ic . (3)
In Fig. 6, the modulation signal vmin (vc) is clamped to -1.
As a result, the short vectors 0-1-1 and 00-1 are selected and
the switching sequence is 0-1-1/00-1/10-1. In this case, the
phase c current does not affect the NP current, as the current

( ) ( )
is expressed by:
i0 = 1 − vb, ib + 1 − vc, ic .
)
(2)

Fig. 5 shows an example in which the vmid (vb) is clamped

( ) (
i0 = 1 − va, ia + 1 − vb, ib . (4)

to zero. In this case, the selected short vectors are 100 and 00-
10-1 100 110 110 100 10-1
11-1
va, (va = vmax )
1
0.8
0.6 3
0.4
vb, (vb = vmid ) 110
00-1 10-1
0.2
0 2
-0.2 vc, (vc = vmin ) 4
-0.4 VREF
-0.6 1
111
-0.8 1-1-1
000
-1 -1-1-1 100
0-1-1
0 0.25 0.5 0.75 1
Time/Ts
(b)
(a)
Fig. 4. Co-relation between the CB-PWM and NTV-SVM strategy when phase a is clamped to+1: (a) CB-PWM switching sequence, and (b) NTV-SVM strategy.

00-1 10-1 100 100 10-1 00-1

11-1

1
0.8 va, (va = vmax )
0.6 3
0.4
110
00-1 10-1
0.2
vb, (vb = vmid )
0 2
-0.2 4
-0.4
VREF
vc, (vc = vmin )
-0.6
111 1
-0.8 000 1-1-1
-1 -1-1-1 100
0-1-1
0 0.25 0.5 0.75 1
Time/Ts
(b)
(a)
Fig. 5. Co-relation between the CB-PWM and NTV-SVM strategy when phase b is clamped to 0: (a) CB-PWM switching sequence, and (b) NTV-SVM strategy.

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0-1-1 00-1 10-1 10-1 00-1 0-1-1

11-1

1
0.8
0.6 3
0.4 va, (va = vmax ) 110
00-1 10-1
0.2
0 2
-0.2 vb, (vb = vmid ) 4
-0.4
VREF
-0.6
111 1
-0.8
vc, (vc = vmin ) 000 1-1-1
-1 -1-1-1 100
0-1-1
0 0.25 0.5 0.75 1
Time/Ts
(b)
(a)
Fig. 6. Co-relation between the CB-PWM and NTV-SVM strategy when phase c is clamped to -1: (a) CB-PWM switching sequence, and (b) NTV-SVM strategy.

The remaining combination to consider for Region 2 is the
case when the short vectors 0-1-1 and 110 are selected. In this
case, the optimal sequence of vectors is 0-1-1/10-1/110. As it
is observed from the switching sequence, none of the
converter phases is clamped. Furthermore, two converter
phases switch one level at the same time. This means that the
modulation signals should jump within a PWM cycle. Since
implementation of this case from a carrier-based standpoint is
difficult and unpractical, a different criterion will be applied
for this particular case to achieve the voltage balancing.
Based on the analysis of all possibilities for large
modulation indices, in which the tip of reference vector is
located in one of the Regions 1, 2, or 3, and exploring the co-
relations between the modulation signals corresponding to the
NTV-SVM and the CB-PWM strategy, the following
conclusions can be made:
• Only a maximal modulation signal (vmax) can be clamped
to +1. Similarly, a minimal modulation signal (vmin) can
be clamped to -1. The median modulation signal (vmid)
can be clamped to 0, provided no signal escapes from the
margin [+1, -1].
• If the sign of one ac-side current is not appropriate to
achieve the voltage balancing, the modulation signal of
that phase should be clamped to +1 or -1 if it corresponds
to vmax or vmin, respectively.
• When one output phase current has the proper
direction to help for voltage balance, the
corresponding modulation signal should be clamped
to 0 if it is vmid, but not to +1 or -1 if it is vmax or vmin,
respectively.
• If the two ac-side currents corresponding to the
modulation signals vmax and vmin help to achieve
voltage balance, the ac-side current associated to vmid
carries a current that is not appropriate for voltage
balancing. Therefore, vmid should be shift the farthest
as possible from zero. This is usually achieved by
clamping vmax to +1 or vmin to -1, for vmid>0 or vmid≤0,
respectively. This resolution is the only one which is
determined different than with NTV SP-PWM.
Because of this, the sequences that require four
switching steps in Table I are avoided.
The above mentioned conclusions are mathematically
summarized in Table II, where ∆vNP is the voltage difference
vC1-vC2. State conditions 1 and 0 indicate true and false,
respectively.

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TABLE II
ACTIONS TO HELP FOR VOLTAGE BALANCE

Sector 1 and [Sector 4]

∆vNP ia>0 ∆vNP ic>0 Action Offset
0 0 b Clamped to 0 −vb
0 1 a Clamped to +1 [−1] +1−va [−1−va]
1 0 c Clamped to −1 [+1] −1− vc [+1−vc ]
For vb>0: a Clamped to +1
[c Clamped to +1] For vb>0: +1−va [+1−vc]
1 1 For vb≤0: c Clamped to −1 For vb≤0: −1−vc [−1−va]
[a Clamped to −1]

Sector 2 and [Sector 5]

∆vNP ib>0 ∆vNP ic>0 Action Offset
0 0 a Clamped to 0 −va
0 1 b Clamped to +1 [−1] +1−vb [−1−vb]
1 0 c Clamped to −1 [+1] −1− vc [+1−vc]
For va>0: b Clamped to +1
[c Clamped to +1] For va>0: +1−vb [+1−vc]
1 1 For va≤0: c Clamped to −1 For va≤0: −1−vc [−1−vb]
[b Clamped to −1]

Sector 3 and [Sector 6]

∆vNP ib>0 ∆vNP ia>0 Action Offset
0 0 c Clamped to 0 −vc
0 1 b Clamped to +1 [−1] +1−vb [−1−vb]
1 0 a Clamped to −1 [+1] −1− va [+1−va]
For vc>0: b Clamped to +1
[a Clamped to +1] For vc>0: +1−vb [+1−va]
1 1 For vc≤0: a Clamped to −1 For vc≤0: −1−va [−1−vb]
[b Clamped to −1]

minimum. For Sector 2, vb is the maximum and vc is the

minimum. The different cases for the whole sectors are shown
TABLE III in Table III.
DETERMINATION OF THE SECTOR A different clamping criterion is applied when the reference
vector is in located in Region 4 (low modulation index). In
vmax vmin Sector that case, only the NP is considered for clamping (see Table
va vc 1 I). From a carrier-based point of view, the amplitude of the
vb vc 2 modulation signals is so small that any of them can be
vb va clamped to the NP without compromising linear operation
3
mode because of the other two modulation signals.
vc va 4 Furthermore, under low modulation indices, clamping the
vc vb 5 modulation signals to zero requires less zero sequence (voff)
va vb 6 amplitude and fewer carriers crossing events compared to
clamping them to +1 or -1.
The decision of which modulation signal should be
clamped to zero is made evaluating the product ∆vNP ix for the
Specifying the maximum and minimum values of the three output currents (x={a,b,c}). The maximum calculated
modulating signals, the corresponding sector in which the tip of value defines the modulation signal that has to be clamped to
the reference vector is located within is simply determined as the NP for optimal voltage balance. For example, if at a
shown in Fig. 3. For example, if the reference vector is in specific sampling instant the product ∆vNP ia is larger than ∆vNP
Sector 1, the modulating signal va is the maximum and vc is the ib and ∆vNP ic, then the modulation signal va should be clamped

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to zero because phase a carries the best balancing current for
the NP.
Notice that the four-step sequence in Region 4 (see Table I)
is avoided with this strategy.
The procedure to implement the proposed CB-PWM with
the zero sequence modulation signal is summarized in the
diagram of Fig. 7. The process outlined in this section
determines the required zero sequence signal that needs to be
added to the sinusoidal reference waveforms of the CB-PWM
strategy to generate the equivalent of the NTV-SVM strategy.
III. PERFORMANCE EVALUATION
This section evaluates performance of the three-level NPC
converter of Fig. 1 under the proposed CB-PWM strategy.
Three performance indices, i.e., power losses, the amplitude
of the NP voltage oscillations, and capability to achieve
voltage balancing are considered as performance evaluation
criteria.
The conventional SPWM strategy with the following zero-
sequence signal voff is the most popular CB-PWM strategy
used for the three-level NPC converter:
v max + v min
voff = − . (7)
2 off switching transitions of the power devices and are directly
Unlike the proposed CB-PWM, none of the modulation
signals is clamped to -1, 0, or +1 over a switching period.
Hereinafter, for the sake of compactness, the conventional
SPWM strategy with the zero-sequence injection given in (7)
is referred to the SPWM strategy.
To have a clear understanding of the performance of the
proposed CB-PWM strategy, the results are compared with
those of from the SPWM and the NTV-SVM strategies.
A. POWER LOSSES
A MATLAB/SIMULINK model of the NPC converter of
Fig. 1 is developed to calculate the power losses of the
converter which are mainly conduction and switching losses.
The rated power of the studied converter is 2.8 MVA and the
ac-side currents are assumed to be constant at their rated
values. The sampling frequency is fs=5 kHz. IGBT module
DIM1200NSM17-E000 are used for the converter switches.
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This IGBT module features a maximum collector-emitter
voltage VCES of 1700V and a DC-collector current IC of
1200A. On the basis of the on-state and switching
characteristics given in the data sheet, it is possible, to
calculate the conduction and switching losses.
The conduction losses of the IGBTs are obtained from
linearization of the static characteristics of the power
switches. The model of the switches in the on-state is
represented by a voltage source and a series resistor.
Consequently, the mean value of the conduction losses in a
power device can be approximated by the following equation:
T
1
Pcl =
T ∫ (V
0
F0 + Ron iF ) iF dt , (5)
where VF0 is the threshold voltage, Ron is the dynamic
resistance of the model, iF is the forward current in the
device, and T is the period of the fundamental frequency. The
values were obtained drawing a straight line tangent to the
characteristic curves of the device taking into account the
current magnitude in this application. The resistance Ron
corresponds to the inverse slope of this line and VF0 to the
voltage for which iF = 0 in this linearized model.
Switching losses are generated during the turn-on and turn-
related to the switching frequency.
In this paper, switching losses are calculated using the
characteristics of the energy losses from the data sheet of the
power devices. These curves are approximated by a second
order equation. The specific range of current values in this
application was taken into account in the approximation.
The mean value of the switching losses is expressed by:
∑ [E (i )+ Eoff (iF , voff )] ,
n
1
Psl = on j F , voff j
(6)
n j =1
where n is the number of transitions within one period of the
ac-side voltage, and Eon and Eoff are the energy dissipated
during the turn-on and turn-off process, respectively, and
depend on the voltage in the off-state (voff) and the current in
the on-state (iF) through the power devices. The curves
provided in the data sheets usually show energy versus
current for a specific constant voltage. The dependency of
energy on voltage is assumed to be proportional.
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Fig. 7. Modification of the modulation signals by adding the proposed zero-sequence signal to achieve the voltage balancing.
proposed CB-PWM avoids the use of the four-step sequences
from NTV-SVM (Table I); thus, it produces lower switching
losses.

B. NP VOLTAGE OSCILLATION AMPLITUDES

This section analyses and investigates the low-frequency

NP voltage oscillations of the converter of Fig. 1 for various
operating conditions.
The normalized amplitude of the ripple ( ∆VNPn 2 ) is
defined as follows:
(a)
∆V NPn ∆V NP 2
= , (8)
2 I RMS f C

(b)
Fig. 8. The ratio of the resultant total losses of the proposed CB-PWM to (a)
the SPWM and (b) the NTV-SVM strategies.
(a)

Fig. 8 shows the ratio of the total losses of the converter

when it operates based on the proposed CB-PWM strategy to
those of based on the SPWM and NTV-SVM strategies. As
Fig. 8(a) shows, the resultant total losses of the proposed CB-
PWM strategy are smaller than those produced by SPWM for
all operating points. This is reasonable because none of the
modulation signals is clamped under the SPWM scheme;
therefore, the switching losses are significantly higher.
Fig. 8(b) compares power losses on the proposed CB-
PWM strategy to those of based on the NTV-SVM strategy.
Observe that the ratio CB-PWM versus NTV-SVM is
(b)
practically the unity for some operating conditions, which
means they produce equal losses. However, for some other Fig. 9. Normalized amplitude of the low-frequency NP voltage oscillations
produced by: (a) the SPWM and (b) the proposed CB-PWM strategy.
operating conditions this ratio is lower. This is because the

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where IRMS is the RMS value of the ac-side currents, f is the voltages of the dc capacitors of the converter are VC1=73 V
fundamental frequency, and C is the value of a the dc-link and VC2=47 V. Nevertheless, after a short period, the capacitor
capacitors, Fig. 1. The low-frequency oscillations on the NP voltages converge and set at their nominal values. This shows
voltage impose stress on the converter components which in the capability of the proposed modulation strategy to achieve
turn leads to oversize design of the converter. voltage balance fairly quickly, with no requirement to
Fig. 9 illustrates and compares the low-frequency additional control effort.
oscillations of the NP voltage for both the SPWM and the
proposed CB-PWM strategy. Fig. 9(a) shows the NP voltage VI. CONCLUSION
amplitude when the NPC converter operates based on the This paper proposes a CB-PWM strategy in conjunction
SPWM strategy. As it is shown, under any operating with a zero-sequence voltage injection for a three-level NPC
condition, there exist low-frequency oscillations on the NP converter. The injected zero-sequence voltage is obtained
voltage. In contrast, the proposed CB-PWM strategy obviates based on exploring a duality between the CB-SPWM and the
the oscillations for an extensive range of operating NTV-SVM strategies. The proposed CB-PWM strategy is an
conditions, as shown in Fig. 9(b). As expected, these results alternative to the NTV-SVM strategy. Nevertheless, the main
are similar to those obtained from the NTV-SVM strategy feature of this strategy, as compared with the NTV-SVM
[25]. The main difference is that the proposed CB-PWM strategy, is its simplicity for digital implementation and the
cannot completely cancel the low-frequency voltage lower switching power losses.
oscillation when operating under low modulation indices. The salient features of the proposed CB-PWM strategy, as
However, the oscillation amplitudes are very small, and the compared to the existing CB-PWM strategies, are as follows:
benefit of lowering switching losses under those conditions is • It can operate at lower switching frequencies.
remarkable.
• It guarantees to achieve voltage balancing with no
requirement for additional control effort.
V. EXPERIMENTAL RESULTS • It mitigates the voltage oscillations of the NP
voltage.
The experimental evaluation of the proposed CB-PWM
strategy for the three-level NPC converter of Fig. 1 is
performed using a 5-kVA scaled-down prototype, with an
averaged switching frequency of around 5 kHz, which is
connected to a three-phase series connected RL load with
R=10 Ω and L=12 mH at the ac side. The dc-side of the
converter is supplied by a constant 120-V dc source. The
proposed CB-PWM strategy is implemented in a fully digital
system using a TMS320F2812 DSP.
Fig. 10 shows the ac-side currents and line-to-line ac-side
voltage of the converter for both low and high modulation
indices, i.e., ma=0.4 and ma=1.1. As Figs. 10(a) and (b) show,
the ac-side currents are sinusoidal and are not distorted by the
injected zero-sequence voltage signal.
The capability of the proposed CB-PWM strategy to 5 ms / div
mitigate the low-frequency oscillations of the NP voltage is (a)
investigated and depicted in Fig. 11. Initially the NPC
converter of Fig. 1 operates based on the SPWM strategy. At
t = 34 ms, the converter modulator is subjected to switch from
the SPWM strategy to the proposed CB-PWM strategy which
lasts for 30 ms. At t = 64 ms, the modulator switches back to
the SPWM strategy. Note that for this operating point the low-
frequency voltage oscillations on the dc-link capacitors
disappear when the proposed CB-PWM strategy is activated.
Fig. 11 highlights capability of the CB-PWM to mitigate the
NP voltage oscillations, as compared with the SPWM strategy.
This obviates the need to oversize the NPC converter
components. Fig. 11 also proves the co-relation between the
proposed strategy and the NTV-SVM strategy since the
mitigation of the NP voltage oscillations happens for the NTV-
SVM strategy as well [24],[25]. 5 ms / div
The effectiveness of the proposed CB-PWM strategy to (b)
achieve the voltage balancing is shown in Fig. 12. Fig. 12 Fig. 10. Ac-side currents and line-to-line voltage for: (a) ma=0.4, and (b)
shows the converter waveforms at for ma = 0.8. The initial ma=1.1.

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10 ms / div
Fig. 11. Response of the NPC converter to the activation of the proposed
CB-PWM strategy (ma=0.8).
10 ms / div
Fig. 12. NPC waveforms for operating condition of ma=0.8.
Simulation and experimental results conclude the
capability of the proposed strategy in (i) reducing the
switching losses of the converter, (ii) mitigating the low-
frequency oscillations of the NP voltage, and (iii) balancing
dc capacitor voltages.
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 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
Josep Pou (S’97-M’03) received the B.S.,
M.S., and Ph.D. degrees in electrical
engineering from the Technical University of
Catalonia (UPC), Catalonia, Spain, in 1989,
1996, and 2002, respectively.
During 1989, he was the Technical Director of
Polylux S.A. In 1990, he joined the faculty of
UPC as an Assistant Professor. He became an
Associate Professor in 1993. From February
2001 to January 2002, and from February
2005 to January 2006, he was a Researcher in
the Center for Power Electronics Systems,
Virginia Polytechnic Institute and State
University (Virginia Tech), Blacksburg. He has authored more than 90
published technical papers and has been involved in several industrial
projects and educational programs in the fields of power electronics and
systems. His research interests include modeling and control of power
converters, multilevel converters, power quality, renewable energy systems,
and motor drives.
Dr. Pou is a member of the IEEE Industrial Electronics, IEEE Power
Electronics, and IEEE Industrial Applications Societies.
Jordi Zaragoza (S’08) received the B.S.
degree in electronic engineering and the M.S.
degree in automatic and electronic industrial
engineering from the Technical University of
Catalonia (UPC), Barcelona, Spain, in 2001
and 2004, respectively. He is currently
working toward the Ph.D. degree in the
Terrassa Industrial Electronics Group,
Department of Electronic Engineering, UPC,
Terrassa, Spain.
In 2003, he was a member of the faculty at
UPC as an Assistant Professor. From
September 2006 to September 2007, he was a
Researcher with the Energy Unit, Robotiker–Tecnalia Technology Center,
Zamudio, Spain. He has authored more than 30 published technical papers.
His research interests include modeling and control of power converters,
multilevel converters, wind energy, and power quality.
Mr. Zaragoza is a Student Member of the IEEE Power Electronics and IEEE
Industrial Electronics Societies.
Salvador Ceballos (S’07) received the B.Sc
degree in physics from the University of
Cantabria, Santander, Spain, in 2001, and the
B.Eng. and Ph.D. degrees in electronic
engineering from the University of the Basque
Country, Bilbao, Spain, in 2002 and 2008
respectively.
Since 2002 he has been with the Robotiker-
Tecnalia Research Centre, Zamudio, Spain,
where he is currently a development engineer
in the Energy Unit. From May 2008 to May
2009 he was a visiting researcher at the
Hydraulic and Maritime Research Centre
(HMRC) University College Cork (UCC), Cork, Ireland. He has authored
more than 40 published technical papers. His research interests include
multilevel converters, fault-tolerant power electronic topologies, and
renewable energy systems.
Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
Maryam Saeedifard (M’08) received the
Ph.D. degree in electrical engineering from
the University of Toronto, Toronto, Canada,
in 2008. From September 2007 to August
2008, she was a Visiting Research Associate
with the Power Electronic Systems Group,
ABB Corporate Research Center, D¨attwil-
Baden, Switzerland. Subsequent to her
graduation, she joined the Center for Applied
Power Electronics (CAPE) in the Department
of Electrical and Computer Engineering at the
University of Toronto, as a postdoctoral
fellow.
She is currently an Assistant Professor with the Department of Electrical and
Computer Engineering, Purdue University, West Lafayette, IN, U.S.A. Her
research interests include power electronics and applications of power
electronics in power systems.
Dushan Boroyevich (S’83–M’85–SM’03–
F’06) received the Dipl. Ing. degree from the
University of Belgrade, Belgrade, Serbia, in
1976, the M.S. degree from the University of
Novi Sad, Novi Sad, Serbia, in 1982, and the
Ph.D. degree from Virginia Polytechnic
Institute and State University (Virginia Tech),
Blacksburg, in 1986.
From 1986 to 1990, he was an Assistant
Professor and the Director of the Power and
Industrial Electronics Research Program,
Institute for Power and Electronic
Engineering, University of Novi Sad, where
he later became the Head. He then joined the Bradley Department of
Electrical and Computer Engineering, Virginia Tech, as an Associate
Professor, where he is currently the American Electric Power Professor and
the Co-Director of the National Science Foundation (NSF) Engineering
Research Center for Power Electronics Systems (CPES). His research
interests include multiphase power conversion, electronic power distribution
systems, power electronics systems modeling and control, and
multidisciplinary design optimization.
Prof. Boroyevich is a recipient of the IEEE William E. Newell Power
Electronics Technical Field Award.