JUNCTION FIELD EFFECT TRANSISTOR (JFET):

The Junction Field Effect Transistor (JFET) has narrow piece of high resistivity
semiconductor material forming a Channel of either N-type or P-type silicon for the majority
carriers to flow through with two ohmic electrical connections at either end commonly called
the Drain and the Source respectively.
There are two basic configurations of junction field effect transistor, the N-channel JFET and the
P-channel JFET. The N-channel JFETs channel is doped with donor impurities meaning that the
flow of current through the channel is negative (hence the term N-channel) in the form of
electrons. Likewise, the P-channel JFETs channel is doped with acceptor impurities meaning
that the flow of current through the channel is positive (hence the term P-channel) in the form of
holes.
N-channel JFETs have a greater channel conductivity (lower resistance) than their equivalent P-
channel types, since electrons have a higher mobility through a conductor compared to holes.
This makes the N-channel JFETs a more efficient conductor compared to their P-channel
counterparts.
There are two ohmic electrical connections at either end of the channel called the Drain and
the Source. But within this channel there is a third electrical connection which is called
the Gate terminal and this can also be a P-type or N-type material forming a PN-junction with
the main channel.
COMMON DRAIN OR SOURCE FOLLOWER CONFIGURATION:
In a Common drain or a source follower configuration of a JFET, the output is taken off the source
terminal and when the dc supply is replaced by its short circuit equivalent, the drain gets grounded

Hence it is also called a source follower configuration.

Fig1: Common drain/source follower configuration.

Fig 2(a,b): ac equivalent model of the circuit

From the figure it is clear that input impedance Zi is defined by

Zi = RG

When Vi is kept 0, the gate terminal is connected directly to the ground

From the above figure it is clear that Vgs = -Vo or Vgs = |Vo|

Applying Kirchhoffs current law at node S, we obtain

Io + gmVgs = Ird + IRs
= (Vo/rd) + (Vo/RS)
the result is

Io = Vo [1/rd + 1/Rs] gmVgs

=Vo [1/rd + 1/Rs] gm[-Vo]

=Vo [1/rd + 1/Rs +gm]

Also,

Zo =Vo/ Io
=Vo/ {Vo [1/rd + 1/Rs +gm]}

=1/ [1/rd + 1/Rs +gm]

Zo=1/ [1/rd + 1/Rs +1/(1/gm)]

From the above equation, Zo appears to be a parallel combination of rd, Rs and 1\gm.

Zo=rd||Rs||1\gm

For rd <= 10 RS,

Zo=Rs||1\gm

The output voltage Vo is determined by

Vo= gmVgs(rd||RS)

and applying KVL around the perimeter of the network, we get,

Vi = Vgs + Vo and,

Vgs = Vi Vo

Vo = gm(Vi - Vo)(rd||RS)

Vo =gmVi(rd ||RS) - gmVo(rd||RS)

Vo[1 + gm(rd ||RS)] = gmVi(rd ||RS)

Amplication Factor Av:

Av =Vo /Vi
=gm(rd RS)/[1 + gm(rd RS)]

If rd is not there or rd >= 10Rs

Av =Vo /Vi
=gm(RS)/[1 + gm(RS)]