1.

A combinational circuit takes two 2-bit binary numbers A = A1A0 and B = B1B0 as
inputs, and outputs a 1-bit signal F indicating whether A is no less than B (namely, =
1 if , and = 0 if < ) and only needs to be correct when A is non-zero.

a) Create a truth table for output F as a function of inputs A1, A0, B1, and B0.

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b) Use a Karnaugh map to find a minimal sum-of-products expression (SOP) for F,
and draw the corresponding gate-level circuit using NAND gates only.

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c) Use a Karnaugh map to find a minimal product-of-sums expression (POS) for F,
and draw the corresponding gate-level circuit using NOR gates only.

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2. The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR
(XOR) gate. Table 1 shows the truth table for a 2-input XNOR gate.

Table 1
inputs output
A B F
0 0 1
0 1 0
1 0 0
1 1 1

a) Write down the Boolean expression for F as a function of A and B in SOP form.

b) Prove the following property of the XNOR gate, using Boolean algebra theorems.

XNOR(, XNOR(, )) = XNOR(, XNOR(, ))

Note that a, b, and c are inputs; XNOR(a, b) denotes a 2-input XNOR gate.

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3. Figure 1 shows an incomplete static CMOS circuit.

Figure 1

a) Please determine the Boolean expression for output Y as a function of inputs A, B,

C, and D by inspecting the pull-up (PMOS) network.

b) Can you draw the pull-down (NMOS) network to complete the CMOS circuit for
output Y ?

c) Can you draw the pull-up and pull-down networks to complete the CMOS circuit
for output Y (inverting the output you completed in Part B)?

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4. A demultiplexer (demux) can be viewed as the inverse of multiplexer. A 1-to-2
demux connects the input signal to one of the 2n outputs based on the -bit select
signal. Figure 2 illustrates a 1-to-4 demux, whose corresponding truth table is shown
in Table 2.

Table 2
1-to-4 demux inputs outputs
s1 s0 d q3 q2 q1 q0
q0 0 0 0 0 0 0 0
d q1 0 0 1 0 0 0 1
q2 0 1 0 0 0 0 0
q3 0 1 1 0 0 1 0
s1 s0
1 0 0 0 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 0 0
Figure 2
1 1 1 1 0 0 0

Now, consider a 1-to-4 demux with input d, select signals s0 and s1, and output signals
q0, q1, q2 and q3.

a) Derive Boolean expressions for outputs q0, q1, q2 and q3 as functions of d, s0 and s1.

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b) Can you implement a 1-to-4 demux using only one 3-to-8 decoder? Please
complete the circuit diagram in Figure 3 by properly labeling the input pins of the
decoder with s0, s1 and d, and also connecting appropriate decoder outputs to q0, q1,
q2 and q3.

Figure 3

c) Can you implement a 1-to-4 demux using one 2-to-4 decoder and a minimal
number of additional 2-input AND gates? Please draw the circuit diagram and
clearly label all the input and output signals.

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5. Figure 4a shows a simple sequential logic circuit that uses a D flip-flop. Please
complete the timing diagram for signals Q and QN in Figure 4b. Assume initially that
Q = 0 and QN = 1.

Figure 4

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6. Two very similar Verilog code snippets are shown in Figure 5, where non-blocking
assignments are used in Figure 5a, and blocking assignments are used in Figure 5b.

reg a, b, c, d; reg a, b, c, d;

always @(posedge clk) always @(posedge clk)

begin begin
a <= IN; a = IN;
b <= a; b = a;
c <= b; c = b;
d <= c; d = c;
end end

(a) (b)

Figure 5

a) Can you identify the functionality of the Verilog code in Figure 5a?

b) Please draw the corresponding circuit for the code snippet shown in Figure 5b.
You should clearly label the names of signal(s) and flip-flop(s).

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c) Please concisely explain why the code snippet in Figure 5a, with its non-blocking
statements, is different than the snippet in Figure 5b, which uses blocking
statements. Support your explanation with an example.

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