Master Learning Maps

Cadence Training Services learning maps provide a comprehensive visual overview of the
learning opportunities for Cadence customers. They provide recommended course flows as well
as tool experience and knowledge levels to guide students through a complete learning plan.
Learning Maps cover all Cadence Technologies and reference courses available worldwide. For
course names, descriptions, and schedules, please select the Browse Catalog button at
https://www.cadence.com/training.
Contents
PCB Design and Analysis
IC Package Design and Analysis
Custom Design with Virtuoso Technology
Digital Design and Signoff
System Design and Analysis
Tensilica Processor IP
V14.0 2017 Cadence Design Systems, Inc. All rights reserved

Learning Map for
PCB Design and Analysis
Library
Logic Design PCB Design SI/PI Analysis
Development
EE
Allegro AMS PSpice Advanced
Simulator Adv. Analysis (1)
Analog
Focus
Analysis (1)
Analog Simulation
Allegro AMS with PSpice (3)
Simulator (3)
NEW Allegro Sigrity System Allegro PCB Editor
Allegro FPGA Allegro PCB
Master
Serial Link Analysis (1) SKILL Language (3)

System Planner (2) Editor Advanced
Methodologies (1) Sigrity PowerSI for Model Allegro Design Entry HDL
Generation and Analysis (2) SKILL Language (3)
EE
Allegro Allegro Design Allegro Sigrity Power-Aware Allegro Design
Experienced
Design Reuse (1) Workbench for Parallel Bus Analysis (2) Workbench for
Engineers and Administrators (2)
Designers (1)
Allegro System Allegro Team Allegro PCB Sigrity PowerDC and
Architect (1) Design Router Basics (2) OptimizePI (1)
Authoring (1)
Allegro High-Speed Constraint Management (2) EE

Allegro Tool Setup and Configuration (2)
Allegro Sigrity PI (1)
Allegro Design Allegro Design Entry Allegro PCB Allegro PCB
Entry HDL Using OrCAD Editor Intermediate Allegro Sigrity SI Librarian (2)
Basics (1) Capture (2) Techniques (2) Foundations (2)
Core
PCB Design at RF - multi-Gigabit

Allegro Design OrCAD CIS (1) Allegro PCB Transmission, EMI Control, and Allegro Design
Entry HDL Front- Editor Basic PCB Materials(2) Workbench for
to-Back Flow (3) Techniques (3) Librarians (2)
Essential High-speed PCB Design
for Signal Integrity(3)
Also available online. Online only. EE Denotes Advance with Engineer Explorer course. L, XL, GXL denotes tiers of Cadence products used in course (not applicable if no legend).
(#) Denotes number of days for instructor-led training. Several self-paced courses are only available in our Online Training Collection. NEW New course (see course catalog at cadence.com
for a complete course listing).
Learning Map for
IC Package Design and Analysis
IC Package
SI/PI Analysis
Design
Analog
Focus
Allegro Sigrity System Serial Link

Master
Analysis (1)
Sigrity PowerSI for Model Generation

and Analysis (2)
Allegro Sigrity Power-Aware Parallel

Experienced
Bus Analysis (2) OrbitIO System Planner (1)
Sigrity PowerDC and OptimizePI (1) Allegro Sigrity Package Assessment and
Model Extraction (1)
Allegro High-Speed Constraint Management (2) EE

Allegro Tool Setup and Configuration (2)
Allegro Sigrity PI (1) Allegro Package Designer (4)

Core
Allegro Sigrity SI Foundations (2) SiP Layout (5)
Learning Map for 1 of 2 see next page
Custom Design with Virtuoso Technology Custom IC, Analog and RF Design
Circuit Design, Simulation, Modeling and RF Design Library
NEW EE NEW EE
Transistor Level Power Signoff with Spectre RF Analysis Using XL, GXL
Characterization
Voltus-Fi (1.5) Shooting Newton or Harmonic Balance (2)
NEW
EE EE
Master
Virtuoso Spectre Pro

NEW EE Real Modeling with
Variation Analysis Using the Virtuoso (0.5-1.0-day short courses)
SystemVerilog or Verilog-AMS (2)
ADE Assembler (1) S5: Transient Noise
S4: Accurate Fourier Transform
EE S3: Transient Algorithm
NEW Behavioral Modeling with S2: AC, XF, STB, and Noise Analyses
Virtuoso ADE Verifier (1) Verilog-AMS or VHDL-AMS (2) S1: DC Algorithm
Analog Modeling with Verilog-A (3) Virtuoso Electrically-Aware Design with

Layout Dependent Effects (1)
NEW NEW
Mixed-Signal Simulations Using AMS Simulation and Analysis
Virtuoso ADE Assembler
Experienced
Designer (3) Using OCEAN (2)

(0.5-day short courses)
S3: Circuit Checks, Device Asserts, and NEW
Reliability Analysis Spectre Accelerated Parallel Simulator (1)

Cadence Variety
S2: Sweeping Variables, Simulating Virtuoso Analog Simulation XL, GXL
Statistical Library
Corners, and Creating Run Plans (0.5-1.0-day short courses)
Characterization (1)
S1: Introducing the Assembler T4: Sensitivity Analysis and Circuit High-Performance Simulation Using
Environment Optimization Using ADE GXL Spectre APS (1)/Spectre XPS (1)
T3: Monte Carlo Simulation Using ADE XL Virtuoso Liberate MX
T2: Creating Sweeps and Running Corners Memory
T1: Introduction to the Virtuoso ADE XL Env. Spectre Simulations Using Virtuoso ADE
Characterization (2.5)
(1)
NEW NEW
Virtuoso ADE Explorer Virtuoso Analog Design Environment (3) L
Spectre Simulator Fundamentals Cadence Library
(0.5-day short courses) (0.5-day short courses) Characterization and
S4: Real-Time Tuning, Checks/Asserts, S4: Spectre Measurement Description Validation (2)
Core
and Reliability Analysis Language

L, XL
S3: Corner Analysis & Monte Carlo Sim. Virtuoso Schematic Editor (2) S3: Small-Signal Analyses
S2: Analyzing Simulations Using ViVA XL S2: Large-Signal Analyses
S1: Set Up and Run Analog Simulations S1: Spectre Basics
Using the Spectre Simulator
Learning Map for 2 of 2 see prior page
Custom Design with Virtuoso Technology Custom IC, Analog and RF Design
IC CAD Layout Design and Advanced Nodes Layout Verification and Extraction
EE
Analog-on-Top (AoT) Mixed-Signal NEW
EE
Implementation (2) Uses IC and Virtuoso Layout for
Innovus Advanced Nodes T2:
Electromigration (0.5)
NEW ICADV
Virtuoso Space-Based Router Express
Master
NEW
(0.5) GXL EE
Virtuoso Layout for NEW
Advanced Nodes T1: Place Quantus QRC

Virtuoso Space-Based Router (2) GXL Transistor-Level T3:
and Route (1) ICADV
EE NEW EE
Extracted View
Advanced SKILL Virtuoso Abstract Generator (1) GXL EE Flows and
Language Virtuoso Layout for Advanced Features
Programming (3) EE Advanced Nodes (2) ICADV (0.5)
Virtuoso Floorplanner (1) GXL
SKILL Programming
EE Using Virtuoso Constraints Effectively (2)
for IC Layout Design
(2) Virtuoso Layout Pro (0.5 day short courses)
T8: Debugging Layout Issues L, XL NEW
Experienced
T7: Module Generator and Floorplanner XL, GXL Assura Physical Quantus QRC
SKILL Development T6: Constraint-Driven Flow & Power Routing XL,GXL Rules- Verification Transistor-Level T2:
of Parameterized T5: Interactive Routing XL Writer (4) Language Parasitic Extraction
Cells (2) T4: Advanced Commands XL Rules-Writer (2) (1)
T3: Basic Commands XL
SKILL Language T2: Create and Edit Commands L
Programming (5) T1: Environment and Basic Commands L
Virtuoso Connectivity-Driven Layout Transition (2)
L to XL
NEW
SKILL Language Assura Physical Quantus QRC
Programming Virtuoso Layout Design Basics (1) L Verification Verification Transistor-Level T1:
Core
Introduction (2) (DRC/LVS) System (PVS) Overview and

(3) (2) Technology Setup
(0.5)
Learning Map for
Digital Design and Signoff
Synthesis Implementation Silicon Signoff Equivalence Checking
EE
Master
Advanced Synthesis with

Genus Synthesis Solution (1)
Modus Test Solution (1)XL Analog-on-Top Mixed- EE

Signal Implementation (2)
Conformal ECO (1)
Test Synthesis Using Genus

Synthesis Solution (2) Low-Power Flow with EE
Experienced
EE Innovus Implementation
Low-Power Synthesis System (1) EE Low-Power Verification
Flow with Genus Synthesis Voltus Power-Grid XL
with Conformal (1)
Solution (1) Analysis and Signoff (2)
EE Innovus Clock Concurrent
Fundamentals of IEEE 1801 Optimization Technology for
Low-Power Specification Clock Tree Synthesis (1)
Format (1)
EE
Innovus Implementation
Joules Power Calculator (1) System (Hierarchical) (1)
Innovus Implementation Tempus Signoff Timing XL

System (Block) (3) Analysis and Closure (2)
Logic Equivalence
Checking with Conformal EC
Genus Synthesis Solution (2) (2)
Virtuoso Digital Basic Static Timing
Core
Implementation (2) Analysis (2)
Cadence RTL-to-GDSII Flow (2)
Learning Map for 1 of 2 see next page
System Design and Verification Languages, Methodologies, and Tools
HDL Design and Verification with Incisive SystemC Specman
NEW EE NEW EE NEW EE
XL XL
Real Modeling with vManager
SystemVerilog Register
SystemVerilog (2) Tool Usage in Batch
Verification Using UVM (2) EE
Mode (0.5)
Master
XL
Specman Advanced
Verification (4)
EE EE NEW EE
XL Metric-Driven XL
SystemVerilog XL
Real Modeling with Incisive Functional
Advanced / Accelerated Verification Using
Verilog-AMS (2) Safety Simulator (1)
Verification Using UVM (5) Incisive vManager (3)
NEW EE EE
XL Foundations of Metric-
XL Low-Power XL
JasperGold Formal Simulation with
Driven Verification (1)
Fundamentals (3) IEEE1801 UPF (2)
NEW EE
XL
EE
SystemC Synthesis
EE
Incisive XL Low-Power XL with Stratus HLS (3)
Experienced
EE Comprehensive Simulation with CPF (2)

L
SystemVerilog Coverage with IMC (2)
Assertions (2)
EE
L
Verification L
Indago Debug
XL SystemC Transaction-XL
Perl for EDA
with PSL (2) Analyzer App Level Modelling
Engineering (3)
EE (TLM2.0) (2)
SystemVerilog for L NEW
Design and Incisive Simulation XL L

Tcl Scripting for EDA
Verification (5) Performance
(2)
Optimization
L L XL
Verilog for Verilog Language SystemC
VHDL Users (2) and Application (4) Fundamentals (3)
XL Specman Fundamentals XL
Core
Incisive SystemC,
VHDL, and Verilog for Block-Level Environment
L L Simulation (2) C++ Fundamentals L Developers (5)
VHDL for VHDL Language
for Design and
Verilog Users (3) and Application (5)
Verification (2)
Learning Map for 2 of 2 see prior page
System Design and Verification Acceleration and Emulation
Acceleration Emulation
NEW EE
XL
SystemVerilog
Experienced
Advanced Register
Verification Using UVM (2)
EE
EE
XL Power-Aware Emulation
SystemVerilog Advanced with DPA and CPF (2)
Verification Using UVM (5)
EE EE EE
Acceleration with In Circuit Emulation with Protium Rapid
Core
Palladium XP (4) Palladium XP (3) Prototyping Platform (1.5)
Learning Map for
Tensilica Processor IP
ConnX Fusion HiFi Vision
NEW
Tensilica ConnX BBE16EP Tensilica ConnX BBE16 Tensilica Fusion F1 DSP (1) Tensilica HiFi 3 Audio Tensilica Vision P5 DSP (2)
Baseband Engine (2) Baseband Engine (2) Engine ISA (1)
NEW
NEW
Tensilica ConnX BBE32EP Tensilica Fusion G3 DSP (2) Tensilica HiFi 2/EP/Mini
DSP
Tensilica Vision P6 DSP (2)

Baseband Engine (2) Audio Engine ISA (1)
NEW
Tensilica ConnX BBE64EP Tensilica Fusion G6 DSP (2) Tensilica Audio Codec API
Baseband Engine (2) (1/2)
Introduction to System Modeling Tensilica Xtensa Hardware

Experienced
with Tensilica Processor Cores (1) Verification and EDA (1)
Tensilica Instruction Extension (TIE) Tensilica Xtensa

Language and Design (1) Processor Interfaces (1)
Core
Tensilica Processor
Fundamentals (2)

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Master Learning Maps

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Cadence Training Services learning maps provide a comprehensive visual overview of the

V14.0 2017 Cadence Design Systems, Inc. All rights reserved

Serial Link Analysis (1) SKILL Language (3)

Allegro High-Speed Constraint Management (2) EE

PCB Design at RF - multi-Gigabit

Allegro Sigrity System Serial Link

Sigrity PowerSI for Model Generation

Allegro Sigrity Power-Aware Parallel

Bus Analysis (2) OrbitIO System Planner (1)

Allegro High-Speed Constraint Management (2) EE

Allegro Sigrity PI (1) Allegro Package Designer (4)

Allegro Sigrity SI Foundations (2) SiP Layout (5)

Virtuoso Spectre Pro

Analog Modeling with Verilog-A (3) Virtuoso Electrically-Aware Design with

Designer (3) Using OCEAN (2)

Reliability Analysis Spectre Accelerated Parallel Simulator (1)

and Reliability Analysis Language

Advanced Nodes T1: Place Quantus QRC

Introduction (2) (DRC/LVS) System (PVS) Overview and

Advanced Synthesis with

Modus Test Solution (1)XL Analog-on-Top Mixed- EE

Test Synthesis Using Genus

Innovus Implementation Tempus Signoff Timing XL

Implementation (2) Analysis (2)

Cadence RTL-to-GDSII Flow (2)

EE Comprehensive Simulation with CPF (2)

Design and Incisive Simulation XL L

Palladium XP (4) Palladium XP (3) Prototyping Platform (1.5)

ConnX Fusion HiFi Vision

Tensilica Vision P6 DSP (2)

Introduction to System Modeling Tensilica Xtensa Hardware

with Tensilica Processor Cores (1) Verification and EDA (1)

Tensilica Instruction Extension (TIE) Tensilica Xtensa

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