Notes by Sir Arsalan

EE380 SSUET Fall 2010

EE380 Integrated Electronics

MOSFETs
Today’s field of microelectronics is dominated by a type of device called the metal-oxide
semiconductor field-effect transistor (MOSFET). Conceived in the 1930s but first
realized in the 1960s,MOSFETs (also called MOS devices) offer unique properties that
have led to the revolution of the semiconductor industry. This revolution has culminated
in microprocessors having100 million transistors, memory chips containing billions of
transistors, and sophisticated communication circuits providing tremendous signal
processing capability.

There are two basic types of MOSFETs:

• Depletion MOSFETs, or D-MOSFETs, can be operated in either the depletion

mode or the enhancement mode.
• Enhancement MOSFETs, or E-MOSFETs, can be operated only in the
enhancement mode.

The differences between the two are a result of the physical construction of each.
MOSFET construction can be represented as shown in Figure 1

Figure 1: Construction of D-MOSFET and E-MOSFET.

The D-MOSFET has a physical channel that connects the source and drain materials. The
E-MOSFET has source and drain materials that are separated by the substrate (which is
made of p-type material in the component shown).

Both MOSFETs represented in Figure1 have a metal gate. Between the gate and the
semiconductor material is an insulating layer made up of silicon dioxide SiO2. Going
from the gate to the substrate, the component has a metal-oxide-semiconductor
configuration, which is the source of the component’s name.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

D-MOSFETs
D-MOSFETs can operate in the depletion and enhancement modes. These modes of operation
are illustrated in Figure 2. (The zero bias condition is included for comparison.)

Figure 2: D-MOSFET operation.

Here is a summary of the operating states shown in Figure 2:

• Zero bias: The gate is shorted to the source, so drain current (by definition)
equals the rating of the component. (Remember: is the shorted-gate
drain current.)
• Depletion mode: The negative gate-source voltage forces free electrons away
from the gate, forming a depletion layer that cuts into the channel. As a
result, .
• Enhancement mode: The positive gate-source voltage attracts free electrons in
the substrate toward the channel while driving valence-band holes (in the
substrate) away from the channel. As a result, the material to the right of the
channel effectively becomes n-type material. This results in a wider channel,
and .

These operating relationships are represented by the transconductance curve shown in the
figure.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

E-MOSFETs
E-MOSFETs are restricted to enhancement-mode operation. This mode of operation is
illustrated in Figure 3.

Figure 3: E-MOSFET operation.

When an E-MOSFET is zero biased, there is no channel between the source and drain
materials, and ID = 0A. When VGS exceeds the threshold voltage rating for the component
VTH, a channel is formed as shown in Figure 3. This allows a current to pass through the
component. The operation of the E-MOSFET is represented by the transconductance
curve shown in Figure 3. Note that the IDSS rating for the component is, by definition, the
value of drain current when VGS = VTH. Since the channel is just beginning to form when
VGS = VTH , IDSS ≈ 0A

Note:
Due to the superior nature of E- MOSFETs in terms of their switching characteristics and
current handling, they are the transistors of choice for the semiconductor industry.
Therefore from here onwards the transistor in focus will be E-MOSFET and will only be
called ‘MOSFET’.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

MOSFET Quantitative Analysis

In order to arrive at the structure of the MOSFET, we begin with a simple geometry
consisting of a conductive (e.g., metal) plate, an insulator (“dielectric”), and a doped
piece of silicon. Illustrated in Figure 4(a), such a structure operates as a capacitor because
the p-type silicon is somewhat conductive, “mirroring” any charge deposited on the top
plate. What happens if a potential difference is applied as shown in Figure 4(b)? As
positive charge is placed on the top plate, it attracts negative charge, e.g., electrons, from
the piece of silicon.(Even though doped with acceptors, the p-type silicon does contain a
small number of electrons.) We therefore observe that a “channel” of free electrons may
be created at the interface between the insulator and the piece of silicon, potentially
serving as a good conductive path if the electron density is sufficiently high. The key
point here is that the density of electrons in the channel varies with V1, as evident from
Q = CV, where C denotes the capacitance between the two plates.

Figure 4: (a) Hypothetical semiconductor device, (b) operation as a capacitor, (c) current flow as a result of
potential difference.

The dependence of the electron density upon V1 leads to an interesting property: if, as
depicted in Figure 4(c), we allow a current to flow from left to right through the silicon
material, V1 can control the current by adjusting the resistivity of the channel. (Note that
the current prefers to take the path of least resistance, thus flowing primarily through the
channel rather than through the entire body of silicon.) This will serve our objective of
building a voltage-controlled current source.

Equation Q = CV suggests that, to achieve a strong control of Q by V, the value of C

must be maximized, for example, by reducing the thickness of the dielectric layer
separating the two plates. The ability of silicon fabrication technology to produce
extremely thin but uniform dielectric layers (with thicknesses below 20 Å today) has
proven essential to the rapid advancement of microelectronic devices.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

The foregoing thoughts lead to the MOSFET structure shown in Figure 5(a) as a
candidate for an amplifying device. Called the “gate” (G), the top conductive plate
resides on a thin dielectric (insulator) layer, which itself is deposited on the underlying p-
type silicon “substrate.” To allow current flow through the silicon material, two contacts
are attached to the substrate through two heavily-doped n-type regions because direct
connection of metal to the substrate would not produce a good “ohmic” contact. These
two terminals are called “source” (S) and “drain” (D) to indicate that the former can
provide charge carriers and the latter can absorb them. Figure 5(a) reveals that the device
is symmetric with respect to S and D; i.e., depending on the voltages applied to the
device, either of these two terminals can drain the charge carriers from the other. With n-
type source/drain and p-type substrate, this transistor operates with electrons rather than
holes and is therefore called an n-type MOS (NMOS) device. We draw the device as
shown in Figure 5(b) for simplicity. Figure 5(c) depicts the circuit symbol for an NMOS
transistor, wherein the arrow signifies the source terminal.

Figure 5: (a) Structure of MOSFET, (b) side view, (c) circuit symbol.

Before delving into the operation of the MOSFET, let us consider the types of materials
used in the device. The gate plate must serve as a good conductor and was in fact realized
by metal (aluminum) in the early generations of MOS technology. However, it was
discovered that non crystaline silicon (“polysilicon” or simply “poly”) with heavy doping
(for low resistivity) exhibits better fabrication and physical properties. Thus, today’s
MOSFETs employ polysilicon gates. The dielectric layer sandwiched between the gate
and the substrate plays a critical role in the performance of transistors and is created by
growing silicon dioxide (or simply “oxide”) on top of the silicon area.

The n+ regions are sometimes called source/drain “diffusion,” referring to a fabrication

method used in early days of microelectronics. We should also remark that these regions
in fact form diodes with the p-type substrate (Figure 6). Proper operation of the transistor
requires that these junctions remain reverse-biased. Thus, only the depletion region
capacitance associated with the two diodes must be taken into account. Figure 6 shows
some of the device dimensions in today’s state-of-the-art MOS technologies. The oxide
thickness is denoted by tox.
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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Figure 6: Typical dimensions of today’s MOSFETs.

Our study of the simple structures shown in Figures 4 and 5 suggests that the MOSFET
may conduct current between the source and drain if a channel of electrons is created by
making the gate voltage sufficiently positive. Moreover, we expect that the magnitude of
the current can be controlled by the gate voltage. Our analysis will indeed confirm these
conjectures while revealing other subtle effects in the device. Note that the gate terminal
draws no (low-frequency) current as it is insulated from the channel by the oxide.

Since the MOSFET contains three terminals, we may face many combinations of
terminal voltages and currents. Fortunately, with the (low-frequency) gate current being
zero, the only current of interest is that flowing between the source and the drain. We
must study the dependence of this current upon the gate voltage (e.g., for a constant drain
voltage) and upon the drain voltage (e.g., for a constant gate voltage). These concepts
become clearer below.

Figure 7: (a) MOSFET with gate voltage, (b) formation of depletion layer, (c) formation of channel.

Let us first consider the arrangement shown in Figure 7(a), where the source and drain
are grounded and the gate voltage is varied. This circuit does not appear particularly
useful but it gives us a great deal of insight. Recall from Figure 4(b) that, as VG rises, the
positive charge on the gate must be mirrored by negative charge in the substrate.

While electrons are attracted to the interface, in reality, another phenomenon precedes the
formation of the channel. As VG increases from zero, the positive charge on the gate repel

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

the holes in the substrate, thereby exposing negative ions and creating a depletion region
[Figure 7(b)]. Note that the device still acts as a capacitor—positive charge on the gate is
mirrored by negative charge in the substrate—but no channel of mobile charge is created
yet. Thus, no current can flow from the source to the drain. We say the MOSFET is off.

Can the source-substrate and drain-substrate junctions carry current in this mode? To
avoid this effect, the substrate itself is also tied to zero, ensuring that these diodes are not
forward biased. For simplicity, we do not show this connection in the diagrams.

What happens as VG increases? To mirror the charge on the gate, more negative ions are
exposed and the depletion region under the oxide becomes deeper. Does this mean the
transistor never turns on?! Fortunately, if VG becomes sufficiently positive, free electrons
are attracted to the oxide-silicon interface, forming a conductive channel [Figure 7(c)].
We say the MOSFET is on. The gate potential at which the channel begins to appear is
called the “threshold voltage,” VTH, and falls in the range of 300 mV to 500 mV. Note
that the electrons are readily provided by the n+ source and drain regions, and need not
be supplied by the substrate.

It is interesting to recognize that the gate terminal of the MOSFET draws no (low-
frequency) current. Resting on top of the oxide, the gate remains insulated from other
terminals and simply operates as a plate of a capacitor.

Figure 8: (a) MOSFET with gate and drain voltages, (b) ID-VG characteristics.

In the arrangement of Figure 7(c), no current flows between S and D because the two
terminals are at the same potential. We now raise the drain voltage as shown in Figure
8(a) and examine the drain current (= source current). If VG < VTH, no channel exists, the
device is off, and ID = 0 regardless of the value of VD. On the other hand, if VG > VTH,
then ID > 0 [Figure 8(b)]. In fact, the source-drain path may act as a simple resistor,
yielding the ID-VD characteristic shown in Figure 8(c). The slope of the characteristic is
equal to 1 / Ron, where Ron denotes the “on-resistance” of the transistor.

Figure 8: (c) ID-VD characteristics, (d) ID-VD characteristics for various gate voltages.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Derivation of I/V Characteristics

In order to obtain the relationship between the drain current of a MOSFET and its
terminal voltages, we make two observations.

First, consider a semiconductor bar carrying a current I. If the charge density along the
direction of current is Qd coulombs per meter and the velocity of the charge is v meters
per second, then

To understand why, we measure the total charge that passes through a cross section of the
bar in unit time. With a velocity v, all of the charge enclosed in v meters of the bar must
flow through the cross section in one second. Since the charge density is Qd, the total
charge in v meters equals Qd v. This lemma proves useful in analyzing semiconductor
devices.

Figure 9: (a) A semiconductor bar carrying a current I, (b) snapshot of the carriers one second apart.

Second, consider an NFET whose source and drain are connected to ground. What is the
charge density in the inversion layer? Since we assume the onset of inversion occurs at
VGS = VTH , the inversion charge density produced by the gate oxide capacitance is
proportional to VGS - VTH . For VGS ≥ VTH, any charge placed on the gate must be mirrored
by the charge in the channel, yielding a uniform channel charge density (charge per unit
length) equal to

where COX is multiplied by W to represent the total capacitance per unit length.

Figure 10: Channel charge with equal source and drain voltages.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Figure 11: Channel charge with unequal source and drain voltages.

Now suppose, as depicted in figure 11, the drain voltage is greater than zero. Since the
channel potential varies from zero at the source to VD at the drain, the local voltage
difference between the gate and the channel varies from VG to VG – VD. Thus, the charge
density at a point x along the channel can be written as

where V(x) is the channel potential at x.

Now the current is given by

where the negative sign is inserted because the charge carriers are negative and v denotes
the velocity of the electrons in the channel. For semiconductors, v = µE, where u is the
mobility of charge carriers and E is the electric field. Noting that E(x) = - dV / dx and
representing the mobility of electrons by µn, we have

subject to boundary conditions V(0) = 0 and V(L) = VDS. While V(x) can be easily found
from this equation, the quantity of interest is in fact ID. Multiplying both sides by dV and
performing integration, we obtain

Since ID is constant along the channel,

Note that the L is the effective channel length.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Figure 12: Drain current versus drain-source voltage in the triode region (Linear region).

Figure 12 plots the parabolas for different values of VGS, indicating that the “current
capability” of the device increases with VGS. Calculating ∂ID / ∂VDS, the reader can show
that the peak of each parabola occurs at VDS = VGS - VTH and the peak current is

We call VGS - VTH the “overdrive voltage” and W/L the “aspect ratio.” If VDS ≤ VGS -
VTH we say the device operates in the “triode region.”

The above equations describe the dependence of ID upon the constant of the technology
µn COX , the device dimensions W and L, and the gate and drain potentials with respect to
the source.

If VDS << 2(VGS - VTH), we have

that is, the drain current is a linear function of VDS . This is also evident from the
characteristic of Fig 12 for small VDS each parabola can be approximated by a straight
line. The linear relationship implies that the path from the source to the drain can be
represented by a linear resistor equal to

A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive
voltage [as long as VDS << 2(VGS - VTH)]. This is conceptually illustrated in Fig. Note that
in contrast to bipolar transistors, a MOS device may be on even if it carries no current.
With the condition VDS << 2(VGS - VTH), we say the device operated in deep triode
region.
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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Figure 13: Linear operation in deep triode region.

Figure 14: MOSFET as a controlled linear resistor.

What happens if in Fig 12 the drain-source voltage exceed VGS - VTH ? In reality, the
drain current does not follow the parabolic behavior for VDS > VGS - VTH . In fact, as
shown in Figure 15, ID becomes relatively constant and we say the device operates in the
“saturation region.”

Figure 15: Saturation of drain current.

To understand this phenomenon, recall that the local density of inversion layer charge is
proportional to VGS - V(x) - VTH . Thus, if V(x) approaches V(x) - VTH , then Qd drops to
zero. In other words, as depicted in fig , if VDS is slightly greater than V(x) - VTH then the
inversion layer stops at x ≤ L , and we say the channel is “pinched off.”

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Figure 16: Pinch-off behavior.

With the above observations, we re-examine the current equation for a saturated device.
Since Qd is the density of mobile charge, the integral on the left – hand side must be
taken from x = 0 to x = L' , where L' is the potential at which Qd drops to zero, and that
on the right from V(x) = 0 to V(x) = VGS - VTH . As a result,

Figure 17: Overall MOS characteristic.

For PMOS devices, equations are respectively written as

and

The negative sign appears here because we assume ID flows from the drain to the source,
whereas holes flow in the reverse direction. Since the mobility of holes is about one-half
of the mobility of electrons, PMOS devices suffer from lower “current drive” capability.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

With the approximation L ≈ L' , a saturated MOSFET can be used as a current source
connected between the drain and the source (Figure 18), an important component in
circuit design. Note that the current sources inject current into ground or draw current
from VDD. In other words, only one terminal of each current source is “floating.”

Figure 18: Saturated MOSFET’s operating as current sorces.

Since a MOSFET operating in saturation produces a current in response to its gate-source

overdrive voltage, we may define a figure of merit that indicates how well a device
converts a voltage to a current. More specifically, since in processing signals we deal
with the changes in voltages and currents, we define the figure of merit as the change in
the drain current divided by the change in the gate-source voltage. Called the
“transconductance” and denoted by gm, this quantity is expressed as,

In a sense, gm represents the sensitivity of the device: for a high gm , a small change in
VGS results in a large change in ID. Interestingly, gm in the saturation region is equal to
the inverse of Ron in deep triode region.

gm can also be written as,

Figure 19: MOS transconductance as a function of overdrive voltage and drain current.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Channel length modulation

In our study of the pinch-off effect, we observed that the point at which the channel
vanishes in fact moves toward the source as the drain voltage increases. In other words,
the value of L' in Figure 16 varies with VDS to some extent. Called “channel-length
modulation” and illustrated in Figure 20.

Figure 20: Variation of ID in saturation region.

To account for channel-length modulation, we assume L is constant, but multiply the

right hand side of MOS current equation by a corrective term:

where λ is called the “channel-length modulation coefficient.” While only an

approximation, this linear dependence of ID upon VDS still provides a great deal of insight
into the circuit design implications of channel-length modulation.

Unlike the Early effect in bipolar devices, the amount of channel-length modulation is
under the circuit designer’s control. This is because λ is inversely proportional to L: for a
longer channel, the relative change in L (and hence in ID) for a given change in VDS is
smaller (Figure 21). (By contrast, the base width of bipolar devices cannot be adjusted by
the circuit designer, yielding a constant Early voltage for all transistors in a given
technology.)

Figure 21: Channel – length modulation.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

MOS device layout

The layout of a MOSFET is determined by both the electrical properties required of the
device in the circuit and the “design rules” imposed by the technology. For example W/L
is chosen to set the transconductance or other circuit parameter, while the minimum L is
dictated by the process. In addition to the gate, the source and drain areas must be defined
properly as well.

Shown in Figure 22 are the “bird eye’s view” and the top view of a MOSFET. The gate
polysilicon and the source and drain terminals are typically tied to metal (aluminum)
wires that serve as interconnects with low resistance and capacitance. To accomplish this,
one or more “contact windows” must be opened in each region, filled with metal, and
connected to the upper metal wires. Note that the gate poly extends beyond the channel
area by some amount to ensure reliable definition of the “edge” of the transistor.

The source and drain junctions play an important role in the performance. To minimize
the capacitance of S and D, the total area of each junction must be minimized. We see
from fig that one dimension of the junctions is equal to W. The other dimension must be
large enough to accommodate the contact windows and is specified by the technology
design rules.

Figure 22: Bird’s eye and vertical views of a MOS device.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Numericals
Question 1:

Sketch the ID-VG and ID-VD characteristics for (a) different channel lengths, and (b)
different oxide thicknesses.

Solution:

As the channel length increases, so does the on-resistance. Thus, for VG > VTH, the drain
current begins with lesser values as the channel length increases [Figure 23(a)]. Similarly,
ID exhibits a smaller slope as a function of VD [Figure 23(b)]. It is therefore desirable to
minimize the channel length so as to achieve large drain currents—an important trend in
the MOS technology development.

Figure 23: (a) ID -VG characteristics for different channel lengths, (b) ID -VD characteristics for different
channel lengths, (c) ID -VG characteristics for different oxide thicknesses, (d) ID -VD characteristics for
different oxide thicknesses.

How does the oxide thickness, tox, affect the I-V characteristics? As tox increases, the
capacitance between the gate and the silicon substrate decreases. Thus, from Q = CV, we
note that a given voltage results in less charge on the gate and hence a lower electron
density in the channel. Consequently, the device suffers from a higher on-resistance,
producing less drain current for a given gate voltage [Figure 23(c)] or drain voltage
[Figure 23(d)]. For this reason, the semiconductor industry has continued to reduce the
gate oxide thickness.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Question 2:

Draw the layout of the circuit shown in Figure 24(a)

Figure 24: (a) Circuit schematic

Solution:

Noting that transistors M1 and M2 share the same S/D junctions at node C and transistors
M2 and M3 also do so at node N, we surmise that the three transistors can be laid out as
shown in Figure 24(b). Connecting the remaining terminals, we obtain the layout in
Figure 24(c). Note that the gate poly-silicon of transistor M3 cannot be directly tied to the
source material of transistor M1, thus requiring a metal interconnect.

Figure 24: (b) Rough sketch, (c) layout for given circuit.

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 Notes by Sir Arsalan
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Question 3

Calculate the bias current of transistor M1 in Figure 25. Assume µn COX = 100 µA / V2
and VTH = 0.4 V. If the gate voltage increases by 10 mV, what is the change in the drain
voltage?

Figure 25: Circuit schematic

Solution:

It is unclear at first in which region M1 operates. So let us assume that M1 is saturated

and proceed. Since VGS = 1 V,

= 200 µA

We must check our assumption by calculating the drain potential:

VX = VDD - IDRD

= 0.8 V

Thus VDS > VGS – VTH therefore M1 indeed operates in saturation.

If the gate voltage increases to 1.01 V, then

ID = 206.7 µA

lowering VX to

VX = 0.766 V

Fortunately, transistor M1 is still saturated. The 34-mV change in VX reveals that the
circuit can amplify the input.

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 Notes by Sir Arsalan
EE380 SSUET Fall 2010

Question 4:

Determine the value of W/L in Figure 26 that places transistor M1 at the edge of
saturation.

Figure 26: Circuit schematic

Solution:

With VGS = 1 V, the drain voltage must fall to VGS - VTH = 0.6 V for transistor M1 to
enter the triode region. That is,

Question 5:

A MOSFET carries a drain current of 1 mA with VDS = 0:5 V in saturation. Determine

the change in ID if VDS rises to 1V and λ = 0.1 V -1

Solution:

We write,

and hence,

With ID1 = 1 mA, VDS1 = 0:5 V, VDS2 = 1 V, and λ = 0.1 V -1,

ID2 = 1.048 mA

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