Professional Documents
Culture Documents
Methodology
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in
the Graduate School of The Ohio State University
By
Yueh-Ching Teng
2011
2011
ABSTRACT
Modern analog integrated circuit design is mainly based on CMOS technology and is
wildly used in different applications. Analog circuit designs are often complicated by
the choice of design parameters such as channel length, channel width, drain current
and biasing voltage that show up in every MOSFET in the circuits. In this thesis, we
will focusing on an new interpretation of MOS modeling for analog design problems
motivated by the traditional square law models. The design procedure for analog
building blocks are based on gm /Id ratio of the device characterization data. The
design problem and trade-offs can be synthesized by program functions then later
ii
To my parents, Ying-Mou Teng and Yu-Yeh Lin
iii
ACKNOWLEDGMENTS
Mohammed Ismail for his guidance and patience. His kindness for letting me use
Analog VLSI Lab. and being a teaching assistance for the mixed signal course were
invaluable.
they have in me. I would like to thank Pei-Chun Hsieh for providing me love and
courage.
iv
VITA
FIELDS OF STUDY
v
TABLE OF CONTENTS
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Chapters:
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
vi
2.2.3 Transconductance Efficiency as Design Parameter . . . . . . 18
2.2.4 Define V* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.5 How to choose V* . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.6 Design Driven Device Characterization . . . . . . . . . . . . . 25
2.2.7 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 Signle Stage Deisgn Example . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.1 Signle Stage Deisgn Flow . . . . . . . . . . . . . . . . . . . . . 28
2.3.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Appendices:
A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
vii
B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
viii
LIST OF TABLES
Table Page
ix
LIST OF FIGURES
Figure Page
x
2.16 SPICE Netlist for Device Characterization . . . . . . . . . . . . . . . . 26
2.19 Circuit to Find Gate Biasing Voltage Under Constant Drain Current 30
4.9 Typical Gain and Phase Marge with Right Half Plane Zero . . . . . . 51
xi
4.12 Output Swing of Second Stage . . . . . . . . . . . . . . . . . . . . . . . . 56
4.13 Vic=Voc=Vdd/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.18 p/z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
xii
A.1 NMOS Transit Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
xiii
CHAPTER 1
INTRODUCTION
and supply voltage lowering posing challenges for circuit designers. Demand for ac-
curate device models for design using deep submicron transistors is high [1]. Unlike
digital circuit design, the level of abstraction in analog design can not be easily de-
fined and synthesized by the softwares. Analog circuit design is challenging because
the design process targets complex design specs [2]. The parameters of the transistor
models used in analog design procedure are technology dependent, therefore, migrat-
ing any existing designs to the new processing technologies is slow and costly, every
Nowadays, due to the shrinking supply voltage and other constraints, operating
transistor near moderate or weak inversion regions is attractive for low power circuit
design because it provides good trade-offs between speed and power [3]. The idea
over the drain current, a pure DC metrics that cover all the short channel effects
[4, 3, 5]. The gm /Id metric is a universal characteristics for transistors in different
1
method and gm /Id design methodology. Using V in the design process helps the
designer using pre-existing analog design instincts of square law equations to design
it is easy to learn, unlike gm /Id based on EKV modeling contains lots of equations that
can not be transferred into design intuitions, the V modeling equations are mainly
adopted from the square law equations. We can use the analogy of Vdsat , Vod , Vov to
design circuits in submicron technologies, second, as shown in the thesis, the design
charts and Matlab scripts, therefore, it is easy to maintain, modify and customize for
standing basic characteristics of modern MOSFET, a simple and new design equation
based on transconductance efficiency has been utilized in the design process. A com-
plex design problem without close form solution can be iterated efficiently by using
The following chapters of the thesis are organized as follows: a brief introduction
to the modern MOSFET devices and short channel effects will be presented in Chap-
ter2. A single transistor design example will be shown in the last part of Chapter 2.
2
In Chapter 3, we will discuss the basic building blocks of pipeline ADC and discuss
In Chapter 4, we will apply the gm /Id design method on the two-stage OTA
design. We will go trough various design considerations of the two-stage OTA and
discuss the design trade-offs that been used in the design scripts. An design flow for
two-stage OTA is shown in Chapter 4. The last part of Chapter 4 is a two-stage design
example using Matlab script based on gm /Id method. Finally, Chapter 5 concludes
the work in the thesis and discusses how to extend the usage of synthesis tool.
3
CHAPTER 2
In this chapter, we will introduce modelings of the MOSFET and the general gm /Id
design method. In the modeling section, we will discuss the reason to use new mod-
elings and will briefly discuss the short channel effects and operation regions of the
modern MOSFET. In the gm /Id design section, we will discuss gaps between design
equations and the actual implementations. A design driven small signal modeling
will be introduced. We will define a new design parameter called V* and discuss its
role in the design process. Last but not least, we will introduce the design driven
characterization of the modern MOSFET. A simple SPICE netlist was given and the
In digital circuit design, we can create some kind of margin, such as noise mar-
gin to simplified the design problems. As long as the circuit meet these constraints,
circuits will behave well within the desired specs. That is, digital circuits have larger
margin of errors to play with[5]. However, in analog circuit design, the circuit per-
formance is usually rely on precise currents, voltages, etc [5]. In other words, analog
4
circuits are more sensitive to the transistor behaviors [5]. There is no way for a cir-
cuit designer to design analog circuits consider every details in physical devices and
process parameters. A design engineer needs good abstraction and design intuitions.
Therefore, models and simulators such as SPICE provide tools for thinking/verify-
ing how circuits might behave during the design process. Doing experiments with
simulator is much cheaper and easier to do than waiting for the IC tape-out results.
Derive proper abstraction for any circuit design is crucial. The best abstraction
usually depends on what goals that the designer wants to achieve [5]. In digital circuit
design problem such as digital delay, a MOS can be treated as a current source and
a switch driving some load capacitors. We can create levels of abstraction based on
digital functionality and digital performance [5]. However, creating analog abstraction
described by models are too complicated to come up with simple abstractions for
not possible, because there is no way for designers to remember every device I-V
We can find the MOSFET square law equation in almost all microelectronics
textbooks and analog circuit design books. The square law model is well known:
1 W
ID,sat = n Cox (VGS Vth )2 (2.1)
2 L
5
the equation is based on charge and velocity assumptions. That is, the equation is base
on Q v, charge times velocity. We assumed that the charge Q is only related to the
Vgs and the velocity v is only proportional to the VDS or E. The square law model
is good approximation for long channel devices but totally inadequate to describe
short channel behaviors [5, 6]. In short channel devices, due to velocity saturation,
charge Q is not only related to the Vgs but is also a function of VDS , Q f (Vgs , VDS ).
It turns out that the velocity v is also a function of Vgs , the vertical field.
The Channel length modulation(CML) is one of the common second order ap-
proximations for MOSFET equation. The change of VDS cause the depletion region
to vary and also change the effective channel length. If the change of channel length
1 1 L(VDS ) Ids
I (1 + ) = (1 + Vds ) (2.2)
L L(VDS ) L L Ids0
One other observation from modern MOSFET device is that the Vth goes down with
the increasing of drain voltage. This is called the drain induced barrier lowering
6
(DIBL) effect. Because the drain region of the MOSFET imaged some charges on
the channel, the gate node need less voltage to mirror the charge onto the channel,
The source and substrate of the MOSFET formed a P-N diode. At high electric field,
some moving electrons may have enough energy(hot electrons) and will knock off
effect(SCBE) [5]. In other words, if we push drain voltage to high enough level, the
drain current ID (not IDS ) and substrate current will suddenly increase. In modern
devices the brake down voltage may not be high, usually between 1.5 2V [5]. If
device operated in SCBE dominated region for a long time, the electrons may be
trapped in the gate oxide and create defects and cause long term problem. From the
analog circuit designers stand point, the SCBE may lower the output resistance so
Fig. 2.1 shows the drain current and output resistance with different VDS . All
effects are active simultaneously. Regions on the Fig. 2.1 indicate what effect dominate
at that voltage range. The cure formed by circles is the drain current curve, output
resistance curve is represented by squares. As we can see from the Fig. 2.1, the
CML kicks in at relatively low fields, the DIBL dominates the high field and the
SCBE happens at very high fields. From Fig. 2.1 we can clearly see that the output
resistance is not constant after the MOSFET device left triode region. Instead of
showing sharp transition between triode region and the saturation region that square
law model predicted, Fig. 2.1 shows gradual transition for the output resistance curve
7
in different operation regions. One may suggest that in order to get more gain from
the device, we need higher output resistance. Therefore, biasing the transistor in the
region where the DIBL effect dominates seems to be a good idea. However, in most
analog circuits design require some finite swing, biasing transistor in the DIBL region
is not a good idea. In fact, most modern analog circuits design will biasing transistors
in the CML region, the output resistance has big variation in the CML region.
Every material have speed limit, compared to GaAs and other materials, the
speed limit of silicon (Si) is higher. In Fig. 2.2, we can see the drift velocity increase
8
linearly with the field in the beginning. As the filed gets higher, the carriers reach
the speed limit and the ID (VGS -Vth ) [5]. Another effect is vertical field mobility
reduction. As the gate voltage increases, it not only change the charges on the channel
but also affect how fast the channel charges can move, as a result, mobility depends
on gate (vertical) field. The reason is that the electric filed pushes carriers toward
the surface and the additional scattering lower the mobility of the charge [5]. Both
velocity saturation and mobility reduction caused by vertical field will cause gm to
9
2.1.5 Modern MOSFET
Fig. 2.3 shows cross section of modern MOS transistor. As we can see in Fig. 2.3
(a), the depth of source or drain junction is roughly equal to the length of the channel.
The p-substrate is not uniformly doped, instead, it usually uses highly non-uniform
doping called retrograde doping to reduce the body effect. The doping level near
the channel is lower. The high doping level on the substrate makes the depletion
region smaller, therefore, the device behaves better. The pocket (halo) implements
under the drain and source area prevent drain and source depletion regions to connect
together(punch trough). The increased doping level in the channel will cause output
impedance to increase, junction capacitance will increase too. The gate oxide is very
thin so that some of the electrons can tunnel directly trough the barrier, in many
cases, it is not characterized by device models. If the circuit is sensitive to the gate
input current, care must be taken to ensure that the gate leakage current will not
10
(a) A real transistor
In Fig. 2.4 (a), the transistor without halo doping has constant Vth , as the channel
length shrinks, two depletion regions eventually touch each other and cause the Vth to
go down. With halo doping, the Vth is higher when channel length is shorter. This is
11
because the effective doping level in the channel is higher, larger Vth means the device
needs more voltage to image charges on the channel. For modern process with halo
doping, if we want Vth of the transistor to be lower, we can use transistor with longer
channel length. As shown in Fig. 2.4 (b), the effective doping level in the channel of
longer device is lower, therefore, the Vth is lower than short channel devices.
In real MOSFET operation, when VGS Vth , the current does not go to zero, the
device is in the sub-threshold region. The current in or near the sub-threshold region
have exponential behavior as shown in Fig. 2.5, this is because the transistor itself
forms a lateral BJT [5]. The sub-threshold or weak inversion current is dominate by
the diffusion current. The current equation is similar to the BJT current equation:
12
W q(Vgs VT ) qVDS
Ids = Ids,0 e nkT (1 e kT ), n > 1. (2.4)
L
The base of this lateral BJT is controlled by the capacitive divider (see Fig. 2.5).
The non-ideal factor of channel control n varies with bias, the typical number for n is
about 1.5. Because tiny current driving large capacitor Cgs , operate MOS device in
weak inversion region is usually slow. However, some modern sub-micron processes,
device can get relative high speed even operate in the weak inversion region, some
low power circuits usually operate in the weak inversion region. In the weak inversion
region, the Vth matching is poor and the model is not well defined [5].
13
Operating transistors in strong inversion region cost more power, operating transistors
in weak inversion region is slow. Why cant we operate devices in the region between
weak and strong inversion regions? The region between weak and strong inversion
regions is called moderate inversion region Fig. 2.6. In moderate inversion region, the
current is composed of both drift and diffusion current. With the shrinking supply
form equation exist for the moderate inversion region [5, 6]. Some models such as
EKV uses weak and strong inversion equations to interpolate the moderate inversion
region. The EKV models or BSIM models are too complicated to generate any close
form equations for traditional hand analysis. From the designers stand point, simple
and effective hand analysis model to build design intuitions is necessary. Often times,
question such as what channel width should I use to get certain gm is what a circuit
14
2.2 gm /Id Deisgn
Once we learn some neat circuit design theories and hand analysis techniques
by taking courses and reading books. Given a set of design specifications, we may
start our design by using simple hand analysis equations such as MOSFET square law
equation. However, when we open the modern device models such as BSIM model,
usually we cant find Cox , or any parameters that we are familiar with. The
equations used in BSIM models or any other models are too complicated for hand
analysis. From a designers stand point we need something to gain useful intuitions,
not a pile of equations. Furthermore, from previous sections we already know that
there is a huge discrepancy between modern CMOS models and traditional square
law equations. All these discrepancies posing a challenge for modern circuit designer,
15
The lack of good hand analysis models to design circuits forcing many designers to
give up hand calculation/analysis, they iterate their design problem in the simulators
until they somehow meet the design specs. Even the circuit meet the design targets,
usually, the design is not guarantee to be optimal. In other words, this issue or
challenge turns many designers into SPICE Monkey, Fig. 2.8 [6]. Normally, any
simulator is just a calculator to check the design meet the specs or not.
Circuit designer, unlike layout designer care mostly about W and L, they care
about gain, bandwidth, noise, power, swing and etc [5]. We need something that
tells us critical parameters such as gm , ro , CGS , CGD without resorting to the actual
16
equations in the modern device models. The idea is simple, we want to use circuit
W 2Ids
gm = Cox (2.5a)
L Cox W
L
W
gm = 2Cox Ids Ids (2.5b)
L
1 W 1
gm = n Cox (VGS Vth )2 1 (2.5c)
2 L 2 (Vgs Vth )
2 Ids 2 Ids
gm = = (2.5d)
(Vgs Vth ) Vod
The overdrive voltage Vod or so called Vdsat found in equation (2.5d) tells us two
things, swing and transconductance efficiency. The lower the the Vod , the higher the
swing and more gm you get per unit current you spent.
The MOSFET operating in the weak inversion region have Ids and gm :
W q(Vgs VT )
Ids Ids,0 e nkT (2.6)
L
q(Vgs VT )
W
IDS L Ids,0 e
nkT
gm = = (2.7a)
VGS n kT q
IDS
gm = IDS (2.7b)
n kT
q
17
Therefore, if we simulated the MOSFET and plot gm vs. VGS . In the weak inversion
other words, for a given current, BJT has better transconductance efficiency. This is
This will cause MOSFET to operate in the sub-threshold region and give out better
gm efficiency. However, the operation speed in sub-threshold region is slow [5, 6].
the device and measure its current. To get gm , we take the derivative of that drain
current with respect to gate voltage. By using simulator, we can always determine the
gm
ID regardless of any short channel effect or complex modeling equations. As shown
gm
in Fig. 2.9, we can drive the simulator to give us the answer that we care about: ID .
We can always plot gm vs. ID of MOSFET for any process technology because it
is a pure DC metric. From Fig. 2.9 we known that before the moderate inversion
gm 2 2
or sub-threshold regions, the curve can be approximated by ID = (Vgs Vth ) = Vod . The
gm 1 gm
equation used in the sub-threshold region is ID = n kT
. Notice that the ID is limited
q
by 1
n kT
similar to the BJT device. The ideal limit of gm
ID of BJT is gm
ID = kT
1
38V 1 .
q q
gm 1
The ID of MOSFET has extra n factor in n kT
of the sub-threshold region, therefore,
q
the MOSFET can never reach the ideal 38V 1 value [5, 6]. The capacitive divider
between the oxide and depletion region as shown in Fig. 2.5 reduce the effective
18
voltage at the channel of the MOSFET. One interesting discovery is that weak and
moderate inversion regions are clearly the most efficient regions to operate in [5].
Form Fig. 2.10, we can see that the transconductance efficiency metric is mostly
19
2.2.4 Define V*
can take equation (2.8a) and define a new parameter called V* [1, 5].
gm 2 2
= = (2.8a)
ID (Vgs Vth ) Vod
2ID gm 2
V = (2.8b)
gm ID V
In square law model, V = Vdsat = Vov = Vod = VGS Vth as we can see in equation (2.8a).
We define V for modern MOSFET not because real device behave like square law
device. Because it is simple and useful. It allows us to by analogy, think about how
to pick V in the same way as to pick Vod for the square law device. We already
know that the real MOSFET do not obey square law equations [5]. So how does V
lower the V to 150mV, for the same current, we will have better transconductance
efficiency and potentially higher swing, we will have larger device, therefore, more
parasitic capacitance.
Vod V
Overdrive voltage Vod
V = 2ID /gm
Cannot be measured Measure(simulate) easily
Complex equations Complex equations
Long channel device Short Channel device
V = Vod = Vdsat All interpretation of V are approximations
Id V 2 Except V = 2I
gm (but V Vdsat )
D
20
Equation (2.9) shows figures of merits for device characterization [3, 6]. Since
we can use the analogy between V and Vod , these equations can help us determine
the V value during the design process. From equation (2.9a) we know that we want
high gm but low current. From equation (2.9b) we know that both smaller channel
length and higher V lead to higher fT . We want large gm but small Cgg . As we will
see in Fig. 2.11, the fT goes up substantially with the processing technology. For a
given 10GHz target, if we use 0.18m device to replace the 0.25m device, the V
will goes down and the operation of the transistor is faster, we also scale down the
gm 2
Transconductance efficiency = (2.9a)
ID Vod
gm 2
Intrinsic gain (2.9b)
g0 Vod
gm 3 Vod
Transit frequency (fT ) (2.9c)
Cgg 2 L2
By taking a MOSFET and connect its gate and drain and doing a voltage sweep
in the simulator, we can plot Vgs vs. fT and gm /Id , as shown in Fig. 2.12. Base on
the plot we found that if we make Vgs larger, generally we will get more gm (ignore
vertical filed degradation) and the fT will go up. Equation (2.9c) predicted these
trends. Therefore, if we want fast device, we want large Vgs and device with smaller
channel length (Fig. 2.11), but if we want a good current efficiency, we want low
Vgs (low current density region) to operate the device in moderate or weak inversion
21
region. To have higher transconductance efficiency, the Vgs is lower and the device
is larger, which means we have lower gm per unit capacitance, therefore, it is slower.
22
If we have a design target u = 1GHz, we can set our device fT = 5GHz. Now the
question is how to find the gm /Id range. If we choose high gm /Id , the device fT will
be lower than 5GHz. On the other hand, if we choose low gm /Id , we will meet the fT
target but wasting current. We can see these trade-offs in Fig. 2.13 .
Because many of the circuit performance parameters that we care about would be
times gm /Id vs. Vod shown in Fig. 2.14. As we can see in the Fig. 2.14, the peak
plot. This magic V voltage range is a nice trade-off between the device fT and
23
the current efficiency. For many applications, the biasing point of MOSFETs would
probably near or at the moderate inversion region, because in this region we get pretty
good efficiency, moderate speed(fT ) and reasonable gm /ID . Notice that the magic
voltage range is processing dependent and it is not truly optimal for any particular
circuit design. For particular circuit design, if we want high gm /ID , we are going to
increase the intrinsic capacitance of the device because the device is larger. Depending
on the load capacitance, bandwidth and the intrinsic capacitance, every design is
there is a certain ratio between the intrinsic capacitors of the transistor and the load
capacitor to get the best result. However, given any processing technology, we can
always make this composite figure of merit plots by using different channel lengths
to see what would be the magic voltage range. We can use this voltage range in the
24
2.2.6 Design Driven Device Characterization
So far we known that we can always characterize the device by measuring the
Id , gm in the simulator and choose V . Therefore, given a device modeling file (e.g
BSIM), we can generate plots of parameters in equation (2.9) with respect to the gm /Id
[6, 4]. By using simple configuration in Fig. 2.15, we can generate several useful plots
for hand analysis. A simple SPICE netlist file shown in Fig. 2.16 demonstrate how
to generate these useful plots. All plots generated by the SPICE netlist shown in
25
Figure 2.16: SPICE Netlist for Device Characterization
Fig. 2.17 shows the general design flow by using pre-simulated plots and the
gm /Id design method. Normally, our design target would require certain amount of
gain, therefore, we should determine how much gm that we need first. After we found
the range of gm that we needed, we can look at the intrinsic gain charts to find what
channel length should be used. Based on the unity gain bandwidth or current budget
26
we can determine the gm /Id or the ft of the device. Once we determine the L, gm /Id
or the ft of the device, we can determine device width based on the current density
charts. The above description is just a general design flow using gm /Id design method.
The design flow may be changed based on the actual constraints, circuit specs and
27
2.3.1 Signle Stage Deisgn Flow
Fig. 2.18 shown a simple common source amplifier configuration with Cload on
28
First we need to determine the channel length based on the gain requirement. This
can be achieved by looking at the intrinsic gain charts. Once we decided the channel
in the processing technology that we used here. Using equation (2.8b), we can found
that the drain current is equal to 314A. After we known the channel length, drain
current and V value, we can determine the width of the transistor by using the
current density charts. Based on the device characterization charts we can derived
After we determined all the parameters of common-mode stage, we can use circuit
shown in Fig. 2.19 to find the gate biasing voltage for the V that we choose. The
circuit in Fig. 2.19 allow us to sweep the drain voltage of the device under constant
basing current. The ideal amplifier form a feedback loop to generate proper gate
biasing voltage.
29
Figure 2.19: Circuit to Find Gate Biasing Voltage Under Constant Drain Current
Fig. 2.20 shows that the simulation result meet both the unity gain frequency and
the gain requirement. By using the pre-simulated device characterization charts and
gm /Id design methodology, we can bridging the gap between hand analysis and the
modern device models, as shown in Fig. 2.21 [6]. The discrepancies between gm /Id
design results and the actual simulations results are usually on the oder of 10 20%,
mostly due to the assumptions that we made during the gm /Id design procedure [6].
Even we found the discrepancies in the simulation results, we can always look back to
our gm /Id derivations to track down the root causes [6]. The square law calculations
are based on inappropriate parameters that do not exit or have no significant impacts
30
Figure 2.20: Common Source Stage Simulation Result
31
CHAPTER 3
In this Chapter, we would like to introduce the structure and basic operation of
the pipeline ADC. After we understand the basic ideas of the pipeline ADC, in the
second part of this chapter we will discuss how we come up with the basic designing
specifications for the ADC. The design specifications used in Chapter 4 are based on
The pipeline ADCs are commonly used in modern electronic applications. The
main feature of the pipeline ADC is that it trades accuracy with latency. Fig. 3.1
shows the basic pipeline ADC topology, the basic building blocks are:
32
1. Sample and Hold Circuit
DAC
Subtractor
Gain Amplifier
3. Sub-ADC Circuits
4. Synchronization Circuits
33
3.1.2 Pipeline ADC Operation
A generic pipeline ADC consists of N cascade stages, each resolve B-bit. In each
stage, the analog input signal is first sampled and held then coarsely quantized by
a sub-ADC circuit to resolve B-bit. By using a DAC, the quantized value is then
subtracted from the original input signal to generate the quantization error. The
quantization error is amplified by an amplifier with gain 2B1 . The resulting residue
signal is then feed into the next stage for further quantization on the next clock cycle.
The function of DAC, S/H, subtraction and the amplification can be combined into a
single stage called multiplying DAC (MDAC) [9], as shown in Fig. 3.1. Because each
stage has sample and hold function, each stage works concurrently to achieve high
throughput.
Fig. 3.3 and Fig. 3.2 show the circuit level implementations of the S/H and MDAC
building blocks. Notice that the main building elements in each of these blocks are
issue for any pipeline ADC design projects. Designing a high quality OTA is never
an easy task, the performance of an ADC is mainly affected by these analog building
blocks. As we will see later, the main focus of this thesis is to design these OTAs
based on systematic design procedure and also decrease the designing times.
34
(a) Single Ended S/H (b) Fully Differential S/H
35
3.2 ADC Design Specifications
The value of the capacitors used in the MDAC and the S/H circuit are determined
by:
3. Noise consideration
Because we can use various circuit techniques (bottom plate sampling, bootstrap) to
reduce the error caused by the non-ideal switches, the noise consideration determine
the lower bound value of capacitors. After we estimate the capacitance values, we
can add matching and common-mode into design considerations to adjust the final
capacitance values that we are going to use in the actual design simulations.
1. KT/C noise
We can use the equivalent model shown in Fig. 3.4 to determine the capacitance
values. During the sampling phase, 1 and 1a are high, 2 are low.The KT/C noise
36
Figure 3.4: MDAC Equivalent Model for Noise Calculation
2 K T
Vout , Camp is the total input capacitance of the amplifier. (3.1)
Cs + Cf + Camp
During the hold phase, the input signals and the noise charges sampled on the capac-
itor will be transferred to the Cf , we can derive the output noise to be:
2
Cs + Cf + Camp KT 1
Vout KT = , is the feedback factor (3.2)
Cf2 Cf
The input referred noise can be derived by dividing the total output noise with the
37
2
V2 KT 1 Cf KT (Cs + Cf + Camp )
Vin2 = out
2
= ( ) = 2 (3.3)
G Cf Cf + Cs (Cs + Cf )
The noise of the amplifier will be determined by the circuit topology and actual
implementation. The main noise source from the amplifier is generated by the drain
current noise: i2n 4 KT ( 32 gm ). We can calculate the total noise power from the
amplifier by deriving the transfer function and doing the integration. We can derived
2 2
Vout 2 1 1 Cf
2 = = KT ( )
G2 3 CLtot Cf + Cs
where CLtot = CLoad + (Cs + Camp ), CLoad is the loading of later stages (3.4)
If we assumed the KT/C noise and the noise in the amplifier are uncorrelated, we
38
3.2.2 What Are the Specs?
Suppose we want to design a 10-bit ADC with 50MS/s. We can derive the
1 1
Accuracy: wrost = (3.6a)
210 2
1
Settling time: period = = 20ns half,period = 10ns (3.6b)
50M
From equation (3.6a) we can known that the total error budget for the entire ADC.
1 1
The static error of the amplifier is equal to (DC Loop Gain) = T0. For a 0.1% accuracy
in the first stage of the 10-bit ADC, we need loop gain T0 > 60dB. Usually, we will
make the loop gain larger to get more margins for other defects in the design. From
equation (3.6b) we know that the amplifier has less than 10ns to settle within the
The close loop gain in equation (3.6d) is determine by the gain of each stage that
been used in the ADC. A large close loop gain is equivalent to the smaller feedback
39
factor, which means the loop gain must be large to achieve the desired static error.
Usually, we started the design by choosing an OTA topologies that have sufficient
gain and less noise [8]. In some circumstances such as high resolution ADC designs,
we may use some circuit techniques to compensate the finite gain errors [4, 7].
For a 10-bit resolution pipeline ADC, we can derive the input referred noise of
1
Cs = Cf = C, Camp = C, F = 6 :Two stage or folded cascode structures (3.7)
2
165 KT KT KT
Vn2in ,tot = = 4.58 6 (3.8)
36 C C C
6 KT 6 KT 1 1 1 1 11 KT
Vn2in ,ADC + (1 + 2 + 4 + 6 + 8 + ) (3.9)
2C C 2 2 2 2 C
We choose the input referred noise to be a fraction of one LSB, in other words, we
dont want the noise to degrade the SNDR of the ADC, here we choose 61 LSB to be
the design value. With full scale voltage VF S at the output to be equaled to 2 volts,
we can calculate one LSB is equal to VLSB = 2/2 1.953mV . in = Vn2in ,ADC =
10
1 11KT
6 LSB 325V . By using C = 325V , we found that C 0.5pF . We can adjust
have to derive CLoad value from the worst case loading during the circuit operations.
Once we decided the C and the Cload values, we can use them in the OTA design
process.
40
CHAPTER 4
In this chapter, we would like to introduce the basic design flow for the OTA used in
pipeline ADC. First, detail design considerations of two stage miller OTA structure
will be discussed. In the second part, we will transfer these design ideas into Matlab
codes using gm /Id method introduced in the Chapter 2. We will use the circuit
simulator to simulate the circuit based on Matlab simulation outputs and compare
A single stage amplifier have direct trade-off between swing and gain. A single
stage amplifier can be simplified with two current sources as shown in The Fig. 4.1 [5].
The more Vod we put across the current source, the more gain we get (higher output
impedance). However, higher Vod will reduce the effective swing and may degrade the
dynamic range.
41
Figure 4.1: Single Stage Amplifier
Two-stage amplifier can decouple the direct trade-off between gain and swing.
However, two-stage amplifier also have more poles associate with it so the stability
of the amplifier is crucial. Figure. 4.2 shown a two-stage configuration, the first stage
use telescopic structure to get more gain, the second stage use simple common source
differential pair to increase the output swing. Therefore, the two stage structure can
have high gain and high output ranges. With the telescopic structure, the gain is
roughly equal to (gm ro )3 . With 1.8V supply voltage, the common output swing can
42
Figure 4.2: Two Stage OTA
We can use simple two-stage amplifier shown in Fig. 4.3 [5] [4] to analyze the
stability issue. As shown in Fig. 4.3, we can use simple R and C to express total
resistance and capacitance at the output of each stage. From the simple R,C elements
shown at the output, we know that there are at least two poles in this simple two-
stage model, therefore, at least 180 degrees phase shift. If the two-stage amplifier
used in a loop configuration,the phase shift of 180 degrees from these two poles is
theoretically stable, but in reality, any tiny parasitic capacitance in the loop could
43
Figure 4.3: Simple Model for Two-Stage Amplifier
By adding two capacitors to the circuit shown in Fig. 4.3, we can derive simplified
model (Fig. 4.4) with feedback network for two-stage amplifier in Fig. 4.2. Equations
(4.1a) and (4.1b) are equivalent output resistance at outputs. The in equation
(4.1c) is the feedback factor. The total equivalent output capacitance CLtot at output
of second stage is shown in (4.1d), total equivalent output capacitance at first stage
is C1 . The equivalent input capacitance at the gate of the first stage is Cx . Notice
that the feedback factor is not just a function of Cs and Cf , is is also a function
of Cx . The Cgg values of input transistors will have large impact on the value of Cx ,
therefore, proper sizing the input transistor is crucial get the desired value.
44
R1 (gm3 ro3 ro4 ) (gm2 ro2 ro1 ) (4.1a)
Cf
(4.1c)
Cf + Cs + Cx
45
4.1.5 Loop Gain for Two-Stage Amplifier
By using the return ratio theory in reference [10], we can derive loop transfer
function of the circuit (Fig. 4.4) in equation (4.2). The loop transfer functions T (s)
consists of feedback factor and the transfer functions of each stage a1 (s) a2 (s) = a(s).
Notice that the resistance and capacitance at the output of each stage create two
poles in the loop transfer function, therefore, the circuit is potentially unstable. If
p1 and p2 are close to each other we will have small phase margin (Fig. 4.5). In
order to make sure the circuit stable and obtain more phase margin, we could make
the transfer function smaller. However, the gain accuracy requirement may require
certain amount of T (s) value. The other simple solution is narrowbanding which
makes the loop behave like first order system [10] [5]. Narrowbanding means we push
shown that by introducing the dominant pole in the system makes p2 to be much
larger than p1 . The phase margin of two-stage amplifier with extra dominant pole
is determine by the p /c ratio, where p is the pole at the higher frequency and c
is the unit gain frequency of loop transfer function. The phase margin in Fig. 4.6 is
approximately equal to p2 /c .
gm1 R1 gm5 R2
T (s) = = a1 (s)a2 (s) = a(s) (4.2a)
(1 ps1 ) (1 ps2 )
1 1
p1 = , p2 = (4.2b)
R1 C1 R2 CLtot
46
Figure 4.5: Bode Plots of Two-Stage Amplifier
[4]
47
By introducing dominant pole to the system we can make the circuit stable. In
reality, making one of the poles dominate will require large capacitance at the output
of the stage. Also, the unit gain frequency would be pretty low. From the circuit
designers stand point, both of them are undesirable. We can make our circuit stable
by purposely connect an additional capacitor between the input and output of the
second stage, this is called Miller compensation [10, 5, 6, 4, 11]. After adding the
Miller capacitor in the circuit (Fig. 4.7), two pole will split apart (pole splitting) and
the system can be treated as first order system. Due to the Miller capacitor, the total
capacitance (C1 ) at the output of the first stage is gaining larger, therefore, the pole
associate with it moves to the lower frequency. On the contrary, at high frequency,
the Miller capacitor look like a low impedance path between the input and output of
the second stage, as a result, the pole moves to higher frequency. Figure 4.8 shown
48
Figure 4.8: Pole Splitting
[10]
vo
We can derive the transfer function of vx and the result is shown in equation (4.1.5).
The result of transfer function is messy and complicated. In order to better analyzing
and designing the circuit, we can use dominant pole approximation to simplify the
results.
vo
a(s) = (4.3)
vx
gm1 R1 gm5 R2 (1 s gCm5c )
=
1 + s [(CLtot + Cc ) R2 + (C1 + Cc ) R1 + gm5 R1 R2 Cc ] + s2 R1 R2 (C1 CLtot + Cc CLtot + Cc C1 )
49
We can use dominant pole approximation and assume p2 p1 , we can write de-
s s 1 1 s2
D(s) = (1 ) (1 ) = 1 s ( + ) + (4.4a)
p1 p2 p1 p2 p1 p2
1 s2
1 s( )+ (4.4b)
p1 p1 p2
Compared coefficients in equation (4.4) with equation (4.1.5), we can find identify p1
(1 zs )
a(s) a0 (4.5a)
(1 ps1 ) (1 ps2 )
gm5
z=+ (4.5b)
Cc
1
p1 (4.5c)
gm5 R2 R1 Cc
gm5
p2 (4.5d)
C1 + CLtot + CLtot
Cc
C1
As expected, equation (4.5) shows that the circuit have a right half plane zero. Usu-
ally, connection between input and output will create zero in the circuit. Here, the
Miller compensation capacitor create a low impedance path between input and out-
put at high frequency. The right half plane zero is problematic because it can reduce
the phase margin if occurs before the cross over frequency. [10, 5, 4]. As shown in
Fig. 4.9, the right half plane zero happens before the loop cross over frequency and
50
Figure 4.9: Typical Gain and Phase Marge with Right Half Plane Zero
[10]
We may want to push the right half plane zero way higher than the cross over fre-
quency, but what can we do? We can derive loop cross over frequency (c ) as gain
gm5
z = (4.6b)
Cc
51
and we can derive the ratio between the right half plane zero and the loop cross over
frequency to be:
z 1 gm1
= (4.7)
c gm5
Since c is usually fixed and the gm1 is also fixed, the only thing we can play around is
the gm5 [6]! Besides, pushing right half plane zero beyond crossover frequency requires
There are two commonly seen methods to mitigate the right half plane issue
[6] [4]. The first one is to make the feedback path of Cc unilateral. One practical
realization is by adding source follower. However, using source follower the circuit
will consume more power and degrade the swing. The other way to create unilateral
the circuit became third order system and is difficult to design. The second method
is to use nulling resistor as shown in Fig. 4.10. We can derive new transfer function :
1
1 sCc ( gm5 Rz )
a(s) a0 (4.8)
(1 ps1 ) (1 ps2 ) (1 ps3 )
52
Figure 4.10: Miller Compensation and Nulling Resistor
From equation (4.8), we know that by adding the nulling resistor, the transfer function
now has three poles and a tuning knob to mitigate the zero. Fig. 4.11 shown the
movement of zero position as the nulling resistor changes. We can move zero to
infinity by making Rz = 1/gm5 . The nulling resistor can be realized using poly resistors
or triode region transistors [4] [5]. Some may suggest that we can set the nulling
resistor equal to cancel out the second pole. Theoretically the idea is good but not
piratical in real design. Due to process variation, the nulling resistance may not
cancel the desired pole and create the pole-zero doublet which will slow down the
53
Figure 4.11: Movement Diagram with Varying Nulling Resistor
[10]
By using the Miller capacitor and the nulling resistor, we found that the loop
crossover frequency depends on the Cc and the non-dominant pole (high frequency)
gm1
c (4.9a)
Cc
gm5
p2 (4.9b)
C1 + CLtot + CLtot
Cc
C1
that used in the Matlab design script. Notice that unlike the single stage amplifier,
the increasing of the load capacitance will cause p2 move to lower frequency and
4.1.6 Swing
The output swing of the second stage shown in Fig. 4.2 is critical to many design
specs. Often time the circuit is noise limited, therefore, the circuit require large output
swing range. For the common mode differential pair output stage, the available swing
depends on both input and output common mode. That is, we cant decouple the
54
input common mode from output swing. Generally, we would choose folded cascode
structure to avoid input common mode set the output swing. As shown in Fig. 4.12,
the out put swing is limited by the active load or the input device. We found that
[4]:
Assumed all devices operate in the edge of saturation region (long channel model),by
adjusting the overdrive voltage and the common mode range, we can get maximum
available output swing. In real life, we may not have the freedom to choose the
common mode level because it is determined by the previous stage circuits [4].
55
Figure 4.12: Output Swing of Second Stage
[4]
If both input and output common mode level are half of the supply voltage. By
assuming the output swing limited by Vminn , we found that the available output
differential peak to peak swing is around 4 Vth shown in Fig. 4.13 [4].
56
Figure 4.13: Vic=Voc=Vdd/2
[4]
Because usually the OTA is used in some feedback configuration, the large signal
gain characteristic is what we really care about. By plotting the the large signal
gain versus the output differential range, we can found the available swing at the
output. Using AV 0 = Vout /Vin we can plot Fig. 4.14. The plot shows that for a
given deviation at the input, how much deviation show on the output.
57
Figure 4.14: Low Frequency Gain and Large Signal Characteristic
[5]
We known from the early section, the transition between triode and saturation region
is gradual, not abrupt. So how can we find the exact output swing of the circuit?
We can plot the large signal characteristic and define output range as the full scale
swing (differential) that causes no more than 30% variation drop in the gain [4]. The
58
4.1.7 Settling Performance
The settling performance is about how long it take to get the right result out
of amplifier. For a switched capacitor OTA used in ADC, we care about two things:
what is the residue error you can tolerate and how much time the output take to
reach the final value. For a 10-bit ADC with 200Ms/s, the non-overlap clock period
is 5ns each and we have half clock period(2.5ns) for our circuit to settle. As shown
in Fig. 4.15, after putting in a step, the output will rise and settle. Because the step
is relatively broadband, applying input with a step and check the output response is
There are two types of settling errors, the static error and the dynamic error [5].
The static error is related to the finite gain of the amplifier and the mismatch of the
59
capacitors setting the feedback loop, no matter how long we wait, the static error is
always there. If we tie the amplifier with capacitors shown in Fig. 4.16, we can derive:
Vo c
= , T0 = Av0 (4.11a)
Vi 1 + A1 v0
Cf
, feedback factor (4.11b)
Cf + Cs + Cx
Cs
c= , closed loop gain (4.11c)
Cf
Vo c 1
= 1 c (1 ) (4.12)
Vi 1 + Av0 Av0
From equation (4.12) we found that the loop gain T0 will change the closed loop gain
c and causing gain error. The input capacitance Cx will cause the feedback factor to
change. For a given error spec, if the feedback factor deviated from the ideal value
too much, we will need large open loop gain. For example, if we want error to be
smaller than 0.1% and the close loop gain c = 4 with Cs = 500f F , Cx = 500f F and
Cs = 2pF . The feedback factor = 1/6, therefore, we need AV 0 grater than 6000 over
60
Figure 4.16: Closed Loop Amplifier
[5]
Dynamic errors are set by many dynamic effects such as: finite bandwidth, feed-
forward zero, non-dominant pole, doublets and slewing [5]. Figure. 4.17 shows a closed
loop amplifier with load capacitor. By using single time constant approximation, we
61
Figure 4.17: Closed Loop Amplifier with Cload
[5]
Notice that because the feedforward created from the feedback loop, it will create
zero in settling response. If we apply input with a step Vi,step = Vstep /s, the output
using initial and final value theorems, we can derive time domain response at the
output is [5]:
p
Vo,step (t) = Vstep c [1 (1 ) ept ] (4.14)
z
where Vstep c is the ideal response and 1 p/z is the initial error caused by feed-
forward. If p/z < 0 then there is extra swing that we need to spend as shown in
Figure. 4.18.
62
Figure 4.18: p/z
[5]
= et/ (4.16a)
ts
= ln (4.16b)
Equation (4.16b) is critical in the design process: if I have a fixed settling time ts ,
how many do I need to reach the settling error that Im interest in. In other
words, I know how fast that the circuit is going to operate (ts ), I know what value
63
that I want to settle to () then I can calculate the gain bandwidth that I need to hit
the design target. The typical number to remember is 2.3 per decade in the error
specs. Notice that the total equivalent output capacitance (Clef f ) on the output of
Fig. 4.16 is usually set by how much noise we can tolerate in the circuit. Therefore,
p
Vo,step (t) Vstep c [1 (1 ) et/ ], = 1/p (4.17)
z
p
= (1 ) et/ (4.18a)
z
ts
= ln ( ) (4.18b)
1 + Cf /Clef f
Notice that from equation (4.18b), we can decrease the feedforward by decrease Cf or
increase Cload . We know that to compensate the extra swing shown in Figure. 4.18,
the circuit needs longer times to settle. However, the extra time that we need to
spend is less than 1 . Therefore, for dynamic error budget, we can calculate the
design value by using 2.3 per decade rule plus some margin (Appendix.B, line 13).
The non-dominant pole in the circuit will impact the settling response. The
non-dominant poles can be found in cascode, gain boosting and multistage amplifiers.
Here we focus on the non-dominant poles in the multistage amplifier. The equation
(4.9) can be used to calculate the ratio of crossover frequency and non-dominant pole
64
p2 = K c (4.19)
If K is smaller than 1, then both the phase margin and bandwidth of the loop are
small. In order to lower the dynamic error settling time, we need certain amount of
bandwidths and phase margin. Fig. 4.19 shows that the optimum value of K depends
on the required dynamic (accuracy) [5] [4]. Generally, we dont want the K to be lower
than 2.
65
p2
P M tan1 ( ) (4.20)
c
p2
As shown in Fig. 4.20, if the phase margin is too low, in other words, c is too small,
the overall output response will have ripples and peaking on it. Therefore, it will take
more time to settle within the desired accuracy. In the multistage design example,
p2
Figure 4.20: PM vs. c
[10]
4.1.8 Noise
Fig. 4.21 shows the simplified equivalent circuit of two stage OTA used in noise
calculation. The total integrated noise of the circuit shown in Fig. 4.21 is [12]:
66
p2
c PM
1 45
2 63
3 72
4 76
5 79
1 KT p gm4 KT p gm6
Vo2 n (1 + )+ [1 + n (1 + )] (4.21a)
Cc n gm1 CLtot n gm5
1 KT p V1 KT p V5
n (1 + [1 + n (1 + (4.21b)
n V4 n V6
)+ )]
Cc CLtot
From equation (4.21) we found that in order to reduce the total integrated noise,
we want to choose larger V for the loading device. However, the desired swing
requirement may force us to use lower V value. We also found that the larger the
Cc and CLtot , the smaller the total integrated noise. It seems attractive to use larger
capacitors to lower down the total noise. However, there are many limitations for
integrated capacitors. Also, to drive larger capacitance means the circuit will consume
more power and the transistor is bigger and slower(parasitics, transit frequency and
etc). An integrated circuit usually face the trade-off between the design simulation
(may or may not be real) and the actual realization (practical stand point).
67
Figure 4.21: Circuit for total integrated noise
[4]
The available output swing of the second stage in OTA will determine the dy-
namic range of the circuit. The dynamic range at the output can be calculated using:
2
Psignal,max 0.5 Vod,peak
DR = = (4.22)
Pnoise Vod2
The dynamic range is simply the power of the signal at the output divide by the power
of the noise at the output. The available swing of the common source differential pair
68
1
Vo,peak (VDD VodP VodN VodN ) (4.23a)
2
2 2 2
Vod,peak (VDD ) (4.23c)
(gm /Id )P (gm /Id )N (gm /Id )N
For worst case corner, the supply voltage VDD =1.6V and the Vod,peak =1V, the total
budget for all three V would be 0.6V. If we assumed PMOS and NMOS using same
V then each V is less than or equal to 200mV. In other words, the gm /Id for
NMOS and PMOS should be 10. The above derivation are used during the Matlab
simulation setup. In order to lower the noise on the output, the V* of the load device
should be larger than the V of the gain device. However, using larger V will reduce
the effective swings at the output. Therefore, the designer must choose these ratio or
parameters carefully.
69
Figure 4.22: Dynamic Range
[4]
After we know the design considerations in the previous section, we can start
designing an OTA and keep those design equations in mind. Fig. 4.23 shows an two
stage OTA used in the 10-bit pipeline ADC. As we can see from the Fig. 4.23, we
need to choose sixteen channel lengths and widths plus the compensation capacitor
value and the lead resistance value. Obviously, if we just put this circuit in the
simulator without any initial calculation, it would be time consuming and painful
for any designers to finish it on time. We could spend a lot of time on this and the
70
design still dont meet the specs. It is impossible to find a close form solution for
such complex circuit design problem, therefore the design must be iterated several
times[4]. We can use the basic characterization circuit introduced in Chaper 2 and
plots similar charts shown in Appendix A to do our iteration. Instead of using human
brain and paper pencil to iterate this problem. We can use the Excel, Matlab or any
other software to iterate/design this circuit based on the gm /Id method introduced
before. We can use Matlab function and treat these characterization charts as lookup
table to help us iterate the circuit during the design process [5, 6, 4, 1, 3].
71
Once we setup the tool for accessing the characterization charts, we need to
analyze the design problem. We need to define primary variables and secondary
variables. Primary variables are the tuning knobs for the design, any tiny changes
variables are those parameters which will not cause serious impact on the critical
design trade-offs [4]. There are many possible ways to analyze the design targets and
define primary variables. The general design flow for complex circuits such as an
72
We choose Cgg1 and Cgg2 as main design variables and left others as secondary vari-
ables. The iteration loop is shown in Fig. 4.25, the equivalent Matlab codes and
function can be found in the Appendix B and [4]. The main calling function has
been adopted and modified from reference [4]. In order to create a loop for the de-
sign iteration, several lookup functions has been developed at the early stage of the
design. The lookup functions and the Matlab design script are crucial in the loop
iteration process because entire design method is based on the pre-simulated charts
and the Matlab codes. Therefore, the correctness of the device characterization data
is very important, we can only verify this through circuit simulators. Notice that even
we extracted the wrong data during the device characterization process, the Matlab
73
Figure 4.25: Design Flow Used in the OTA Design
[4]
The design specs for the OTA shown in Fig. 4.23 is based on 10-bit 50Ms/s
pipeline ADC. The clock period is 20ns, therefore, the settling time ts is half of the
clock period. The dynamic range requirement is 65dB. The supply voltage is 1.8V
and we want to use minimum power. The load capacitance, sampling and feedback
74
capacitance is determined by the noise requirement. The static error is set to be
1 1
8 LSB and the dynamic error is set to be around 16 LSB.
The design process started by choosing the channel length to meet the static error
process. For the secondary design parameter such as phase margin, we must choose
carefully. If we choose high phase margin(e.g 75), the gm5 , the total current consump-
tion will be significantly larger than low phase margin design. However, if we choose
the phase margin to be lower than 60, we will see ripples in the output step response
and the OTA may not meet the error specs. After we determine the secondary design
variables, we need to set the primary variables: Cgg1 and Cgg5 . We may guess some
numbers and try to iterate the problem. Since using minimum current is our design
goal, one systematic way is to use loop function to find the lower current combinations
as shown in Fig. 4.26. The capacitance ratios in the current optimization plot may
not be the optimal choice, but it shows the tendency for the design problem. Usually,
we want the Cgg1 to be small because we want its impact on feedback factor to be
smaller.
75
Figure 4.26: Current Optimization Plot
are listed in Table.4.4, the discrepancies between the Matlab simulation results and
the circuits simulator results are mainly caused by the assumptions made during the
device characterizations. We can see that the circuit simulation basically meet all the
76
design specifications. To make the design more robust against processing variations,
all we have to do is to change the design parameters in the Matlab scripts to get more
margins. After we adjust the design parameters to obtain margins, the next step is to
apply and refine the biasing network. We may choose some high swing and constant
gm biasing networks. After we finished the biasing network design, the next step is
to implement the common mode feedback network and refine the device fingers and
multipliers. The last step is to check the design using different processing corners and
77
Table 4.4: Compare Matlab and Spectre Simulation Results
m1 (knob) m2 m3
Matlab Simulation Matlab Simulation Matlab Simulation
Cgg 17f 17.033f
Cdd 9.2872f 2.012f 14.551f 3.3f 58.206f 16.88f
gm 603.15 579 716.24 704.966 716.24 700.94
ft 5.6467GHz
gm /Id 10.8228 10.432 12.8521 12.7 12.8521 12.63
Id 55.73A 55.5A 55.73A 55.5A 55.73A 55.5A
Id /W 10.708 10.673 6.3047 6.278 1.0901 1.086
W 5.2045m 5.2m 8.8394m 8.84m 51.126m 51.1m
m4 m5 (knob) m6
Matlab Simulation Matlab Simulation Matlab Simulation
Cgg 151.48f 151.389f
Cdd 33.789f 8.7f 47.991f 29.959f 215f 138.732f
gm 545.708 526.264 22.9m 22.5789m 18.291m 18.178m
ft 24.017GHz
gm /Id 9.792 9.482 9.5269 9.407 7.6215 7.574
Id 55.73A 55.5A 2.4mA 2.4mA 2.4mA 2.4mA
Id /W 2.1509 2.124 29.3545 29.375 5.664 5.674
W 25.91m 25.9m 81.738m 81.7m 423.62m 423m
78
Figure 4.27: Input Step and Output vs. Time
79
(a) Loop Phase (b) Loop Gain
80
(a) Noise vs. Frequency (b) Total Integrated Noise
81
CHAPTER 5
CONCLUSION
thesis. The proposed methodology was validated by the design of an two-stage OTA.
The results showed excellent matching between the Matlab synthesis results and the
circuit simulator results. The synthesis tool can reduce the re-design and optimization
times of the critical analog building blocks, it can also be used to synthesis the design
circuits such as pipeline ADC can be significantly reduced because the synthesis tool
can speed up the redesigning process. By changing the device characterization data
and properly modify the design script, the designer could migrate analog circuits to
different processing technologies in a short time. Last but not least, the synthesis
tool could be used for educational purpose by adding more circuit configurations and
more processing technologies. Instead of directly using circuit simulators to design the
circuits and get get frustrated, students can quickly learn the circuit design trade-offs
82
APPENDIX A
83
Figure A.2: PMOS Transit Frequency
84
Figure A.3: NMOS Intrinsic Gain
85
Figure A.5: NMOS Composite FoM
86
Figure A.7: NMOS Current Density
87
APPENDIX B
1 % design script.m
2 % tech parameters
3 tech.pcgd w = 0.657e-15; %
4 tech.ncgd w = 0.491e-15; %
5 tech.ncdb = 0.488;
6 tech.pcdb = 0.596;
7 tech.mun mup = 265/103; %
8
9 % specifications
10 spec.dr = 65; % 65dB SNR
11 spec.ts = 10e-9; % 10ns
12 spec.es = 2.4414e-004 % error, static
13 spec.ed = 0.0125e-2 % error, dynamic, 8.9872tao, 1/8 LSB
14 spec.g = 1; % close loop gain
15 spec.vodpp = 2; % Vodp-p swing
16
17
18 % design choices
19 % noise
20 choices.gm6 gm5 = 160/200;
21 choices.gm4 gm1 = 190/210;
22 choices.gm3 gm2 = 160/160;
23 choices.gm2 gm1 = 190/160;
24 choices.gm3 gm4 = 210/160;
25 choices.gm7 gm4 = 210/170;
26 choices.gm8 gm5 = 160/170;
27
28
29
30
31 choices.cs = .5e-12;
88
32 choices.cf = choices.cs;
33 choices.cl = 2.5e-12;
34 choices.cgg1 = 0.01*(choices.cf+choices.cs);
35
36 choices.pm = 60;
37 choices.vodntot = (0.5*(spec.vodpp/2)2)/(10(spec.dr/10));
38 choices.fc = -(log(spec.ed)/(2*pi*0.5*spec.ts));
39
40
41 % dc gain requirement
42 beta guess = choices.cf/(choices.cf+choices.cs+choices.cgg1);
43 a0 = 1/spec.es/beta guess;
44
45
46 % pick L to achieve the computed value of gm gds for all devices (using
47 % intrinsic gain charts)
48
49 choices.L1 = 0.45;
50 choices.L2 = 0.5;
51 choices.L3 = 0.5;
52 choices.L4 = 0.5;
53
54 choices.L5 = 0.20;
55 choices.L6 = 0.35;
56
57 choices.L7 = 0.45;
58 choices.L8 = 0.25;
59
60
61
62 % primary optimization variables
63 cgg1 cs plus cf = 0.017;
64 cgg5 cltot = .055;
65
66 % compute required current for given design choices
67 [itotal, beta, cc, c1, c2, m1, m2, m3, m4, m5, m6, m7, m8] =
68 two stage miller(cgg1 cs plus cf, cgg5 cltot, choices, tech)
89
BIBLIOGRAPHY
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