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SKEE 1063
PART A: ANSWER ALL QUESTIONS

Q.1
(a)ExplainWith
(i) the help of energy band diagram, explain the differences in energy gap
and resistivity of these materials.
I. Copper (2 marks)
II. silicon (2 marks)
III. Plastic (2 marks)

(ii) State two differences between n-type and p-type semiconductors?

(2 marks)
(iii) How is the electrical field across the pn junction created? Describe in terms
of majority carrier movement. (3 marks)

(iv) What is the difference between knee voltage and breakdown voltage in a
semiconductor diode. (2 marks)

(b) For the circuit in Figure Q1(b); Vpri is given as sine wave with a peak value of
100V and frequency of 50Hz. All diodes are silicon type with VF = 0.7 V.

(i) Plot and label Vpri and Vsec if given the turns ratio for the transformer is 5:1.
(3 marks)

(ii) Plot and label the output signal,Vout. (2 marks)

(iii) What is the PIV rating for each diode in Figure Q1(b). (2 marks)
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Vout
Vpri Vsec

C R

Figure Q1(b)

(c) Figure Q1(c) shows a voltage regulator circuit. Determine suitable voltage range
for the unregulated DC input, Vi, that will maintain the ouput voltage, VL at 8V,
and not exceeding the maximum power rating of the zener diode, PZM = 400
mW. (5 marks)

RS = 80

+
+
Unregulated
Vi RL
DC input VZ VL Regulated DC output
0.2k
-
-

Figure Q1(c)
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Q.2 (a) Describe the difference between a bipolar and a unipolar device. (2 marks)
(b) Refer to Figure Q2 (a). Redraw the circuit and by a proper marking (i.e. using the
plus and the minus signs), show the correct polarity for VBE and VBC of the
transistor if the transistor is biased and fall into the following regions:
(i) Saturation region
(ii) Active region
(iii) Cut-off region
(6 marks)

E n p n C

RE RC

B
VBE VBC

Figure Q2 (a)

(c) A test has been conducted at different temperatures on two different biasing
circuits. The collected data are shown in Table Q2(a) and Table Q2(b). Which
biasing circuit is more stable? Justify your answer. (7 marks)

: =

Table Q2(a): Q-point from Biasing Circuit 1

Temperature (oC) IBQ (A) ICQ (mA) VCEQ (V)
30 17.8 3.81 5.24
50 18.7 2.75 7.94
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Table Q2(b): Q-point from Biasing Circuit 2

Temperature (oC) IBQ (A) ICQ (mA) VCEQ (V)
30 15.1 3.24 6.70
50 21.3 3.17 6.88

(d) (i) For the fixed-bias circuit given in Figure Q2(d), determine the values for Vcc,
the resistor RB, and the resistor RC, if we require RB = 80RC, ICQ = 12mA,
and VCEQ = 8V. (6 marks)

VCC

RC
RB
ICQ 10 mF

10 mF
=50
RS
600 W

VS

Figure Q2(d)

(ii) Is the BJT in active, saturation, or cut-off mode? Justify your answer.
(3 marks)
(iii) What is the disadvantage of this circuit compared to the voltage-divider-bias
circuit? (1 mark )
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Q.3
(a) State two advantages of MOSFET over BJT. (2 marks)

(b) Table Q3 shows a structure, type and symbol of a MOSFET. Fill up the blank box
with appropriate answer. (6 marks)
Table Q3
MOSFET
Structure Type Symbol
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(c) Figure Q3(a) shows a circuit configuration of a MOSFET amplifier. Additional

information on the amplifier are as follows;
K = 0.5x10-3A/V2, VGS(Th) = 2 V
The transfer characteristic of the circuits DC bias is given in Figure Q3 (b).
Estimate the MOSFET operating point, Q via Figure Q3(b). (8 marks)

Figure Q3(a)

Figure Q3(b)
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(d) Figure Q3(c) shows the transfer characteristics of a MOSFET bias circuit. All
components and terminals have the following parameters;

VDD = 20 V, VD= 8.8 V, RG = 2 MW, RD & RS = unknown

(i) Sketch the circuit. (3 marks)

(ii) Calculate the value of RD and RS. (6 marks)

Figure Q3(c)
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PART B: ANSWER ONE (1) QUESTION ONLY

Q.1 (a) Draw and label the output voltage, vout, for the circuit in Figure Q1-B (a). Show
all your calculations.
(7 marks)
R1
vin (V)
2 k +
+ R2
+25 Si
5 k vout
vin
0 t (s)
-25 -
Si -

Figure Q1-B(a)

(b) Consider the circuit in Figure Q1-B (b). Determine the voltage V1 and current I1,
I2 and I3. Assume that D1 and D2 are silicon diodes with VF = 0.7 V.
(8 marks)

I1 R1 V1 R2

I3
4.7 k 5 k

10V D1 D2
VZ =5V
I2

Figure Q1-B(b)
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(c) The input voltage for clamping circuits in Figure Q1-B(c) and Q1-B(d) is a
square-wave with vin(p-p) = 10 V (vin(ave) = 0 V) with VF of diode = 0.7 V .
Examine both clampers and determine which one produces the output waveform
in Figure Q1-B (e). Calculate the suitable value of VDC. (10 marks)
C

+ +

vout
VDC
- -

Figure Q1-B(c)

+ +

vout
VDC
- -

Figure Q1-B(d)

vout (V)

12.3

Clamper +
vin vout 7.3
circuit
-
2.3
t (s)
0

Figure Q1-B(e)
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Q.2
(a) Create the truth table for the CMOS gate in Figure Q2-B (a). Determine the digital
representation from the truth table.
(3 marks)

VDD

(INPUT)
A

S
(OUTPUT)

Figure Q2-B(a)

(b) A two input, (VA and VB) NAND DTL gate is shown in Figure Q2-B (b). All
diodes are assumed to conduct with a voltage drop of 0.7 V.

Figure Q2-B(b)
(i) Find the current through D1 when VA = 0.2 V and VB = 4 V. Also find the
voltage at the base of the transistor Q1. (5 marks)
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(ii) If VA = VB = 4 V, find the transistor base current, IB.
If VCEsat = 0.2 V, find the value of . (6 marks)

(c) An inverter output of RTL (Resistor Transistor, BJT) switching circuit is

shown in Figure Q2-B(c) with component RB, RC and =250. The waveform
indicates IC is saturated at 10 mA.

Vc

10 V 10 V

0V
t

Figure Q2-B(c)

(i) Sketch the circuit and the input waveform. (5 marks)

(ii) Calculate RB and RC. (6 marks)

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APPENDIX 1 - LIST OF EQUATIONS

= 2( ) + 0.7 =
+1

= +
=
2
= +
= =

= 2 = 3

1 2
= = = 1
() ()
2 3

( )
( ) = =

2 3

= ( ) =

2
=
= 1
()

()
= 2
= () ()

2 = 2 ()
= ()
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SKEE 1063
PART A: ANSWER ALL QUESTIONS

Q.1
(a)ExplainWith
(i) the help of energy band diagram, explain the differences in energy gap
and resistivity of these materials.
I. Copper

Copper is a conductor. For a conductor, there is no energy gap since

the valence and conduction band overlaps and it has a low
resistivity.
II. silicon
Si is a semiconductor. The energy gap is lower than an insulator
and the resistivity is between a conductor and an insulator
III. Plastic
Plastic is an insulator. The energy gap in an insulator material is the
largest and it has the highest resistivity.
The

(ii) State two differences between n-type and p-type semiconductors?

n-type-Majority carriers are electrons, minority holes, impurity atoms are
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donor atoms such as P.
p-type Majority carriers are holes, minority electrons, impurity atoms are
acceptor atoms such as B.
(iii) How is the electrical field across the pn junction created? Describe in terms
of majority carrier movement. (3 marks)
First, majority carrier from the n-side which is electrons diffuse towards p-
1
side. Each electrons diffuse will leave positive ions. At the p-side, electrons
will lose energy and becomes valence electrons producing negative ions.
1
These positive and negative ions will be attracted at the pn junction thus
1
producing electric field.

What is the difference between knee voltage and breakdown voltage in a

semiconductor diode. (2 marks)
Cut-in voltage/knee voltage: The forward voltage at which the current
through the diode or pn junction starts rising abruptly during forward bias
(due to majority carriers).
Breakdown voltage: The reverse voltage at which diode current increases
during reverse bias due to minority carriers.

(b) For the circuit in Figure Q1(b); Vpri is given as sine wave with a peak value of
100V and frequency of 50Hz. All diodes are silicon type with VF = 0.7 V.

(i) Plot and label Vpri and Vsec if given the turn on ratio for the transformer is
Vpri (V)
5:1. (3 marks)
100 V

10 20 30 t (ms)
1.5

- 100 V
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(ii) Vsec (V)
20 V

10 20 30 t (ms)
1.5

- 20V

Plot and label the output signal,Vout. (2 marks)

Vout (V)

9.3

t (ms)
10 20 30

(iii) What is the PIV rating for each diode in Figure Q1(b). (2 marks)
-Vpsec/2 + 0.7 + PIV-Vpsec/2 = 0 1

PIV = Vpsec 0.7 = 19.3 V 1

Vout
Vpri Vsec

C R

Figure Q1(b)

(c) A voltage regulator as shown in Figure Q1(c) is added at the output of the
rectifier circuit of Figure Q1(b). Determine suitable voltage range for the
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unregulated DC input, Vi, that will maintain the ouput voltage, VL at 8V, and not
exceeding the maximum power rating of the Zener diode, PZM = 400 mW.
RS (5 marks)
40

+
+
Unregulated
Vi RL
DC input VZ VL Regulated DC output
0.2k
-
-

Figure Q1(c)
PZM = 400 mW
Iz,max = 400 m/8 = 50 mA
1
Iz,min = 0
IL = 8/0.2 k = 40 mA
Ismin = Iz,min + IL = 0 + 40 mA = 40 mA 1

Ismax = Iz,max + IL = 50 + 40 = 90 mA 1

-Vi + RsIs + Vz =0
Vi,min = Is,min(Rs) + Vz = (40m)(40) + 8 = 9.6 V 1

Vi,max = Is,max(Rs) + Vz = (90m)(40) + 8 = 11.6 V 1

Q.2 (a) Describe the difference between a bipolar and a unipolar device. (2 marks)
Bipolar devices have electrons and holes as their current carriers.
Unipolar devices have only either electrons or holes as current carrier.
(b) Refer to Figure Q2 (a). Redraw the circuit and by a proper marking (i.e. using the
plus and the minus signs), show the correct polarity for VBE and VBC of the
transistor if the transistor is biased and fall into the following regions:
(i) Saturation region
(ii) Active region
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(iii) Cut-off region
(6 marks)

E n p n C

RE RC

B
VBE VBC

Figure Q2 (a)
Saturation

E n p n C

RE RC

2
- + + -
B
VBE VBC

Active

E n p n C

RE RC

- + - +
B 2
VBE VBC
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E n p n C

RE RC

2
+ - - +
B
VBE VBC

(c) A test has been conducted at different temperatures on two different biasing
circuits. The collected data are shown in Table Q2(a) and Table Q2(b). Which
biasing circuit is more stable? Justify your answer. (7 marks)

: =

Table Q2(a): Q-point from Biasing Circuit 1

IBQ ICQ VCEQ =IC/IB IC S()

T (oC)
(A) (mA) (V)

30 17.8 3.81 5.24 214.0 1.06

66.9 0.0000158
50 18.7 2.75 7.94 147.1 mA

2.5
Table Q2(b): Q-point from Biasing Circuit 2

IBQ ICQ VCEQ =IC/IB IC S()

2.5 T (oC)
(A) (mA) (V)

30 15.1 3.24 6.70 214.6 0.07

65.8 0.0000011
50 21.3 3.17 6.88 148.8 mA

Biasing Circuit 2 is more stable than biasing Circuit 1. For a large variation of ,
biasing Circuit 2 will only cause a small variation in IC which results in low stability
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factor. The lower the stability factor, the less sensitive is the biasing circuit to
variations. 2

(d) (i) For the fixed-bias circuit given in Figure Q2(d), determine the values for Vcc,
the resistor RB, and the resistor RC, if we require RB = 80RC, ICQ = 12mA,
VCEQ = 8V and VBE = 0.7 V with = 50.
(6 marks)

VCC

RC
RB
ICQ 10 mF

10 mF
=50
RS
600

VS

Output loop: VCC = 12RC + 8 eq 1

Input loop: VCC = IBQ RB + VBE
VCC = (12/50)(80RC) + 0.7
1
VCC = 19.2RC + 0.7 . eq 2
Solving for RB using eq1 & eq2: 12RC + 8 = 19.2RC + 0.7
1
RC = 7.3V/7.2mA = 1.01 k
Then RB = 80RC = 80.8 k 2

VCC = 12(1.01) + 8 = 20.12V 2

Figure Q2(d)
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(ii) Is the BJT in active, saturation, or cut-off mode? Justify your answer.
(3 marks)
BE junction is forward biased (VBE = 0.7V) and BC junction is reverse
1
biased (VBC = VB VC = 0.7V 8V = 7.3V) confirmed that the transistor is
1 1
in active region.

(iii) What is the disadvantage of this circuit compared to the voltage-divider-bias

circuit? (1 mark )
Circuit in Figure Q2(d) is a fixed biased configuration such that the Q-point
very dependent whereas voltage divider is independent . So values for
the same transistor can vary from 100 to 300 without affecting significantly
the stability. 1

Q.3
(a) State two advantages of MOSFET over BJT. (2 marks)
1.Less noise
2. Temperature stable
3. Small size
4. High input resistance

Table Q3 shows a structure, type and symbol of a MOSFET. Fill up the blank box
(b)
with appropriate answer.
(4 marks)
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Table Q3
MOSFET
Structure Type Symbol

D-MOSFET (n channel)

E-Mosfet (n channel)

D-Mosfet (p channel)

(c)
Figure Q3(a) shows a circuit configuration of a MOSFET amplifier. Additional
information on the amplifier are as follows;

K = 0.5x10-3A/V2, VGS(Th) = 2 V, rd = , Vi = 20 mVP-P

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The drain characteristic of the circuits DC bias is given in Figure Q3 (b).
Estimate the MOSFET operating point, Q via Figure Q3(b). (8 marks)

Figure Q3(a)

Figure Q3(b)

2
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(d)
Figure Q3(c) shows the transfer characteristics of a MOSFET bias circuit. All
components and terminals have the following parameters;

VDD = 20 V, VD= 8.8 V, RG = 2 M, RD & RS = unknown

(i) Sketch the circuit. (3 marks)

3
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(ii)

(6 MARKS)

PART B: ANSWER ONE (1) QUESTION ONLY

Q.1 (a) Draw and label the output voltage, vout, for the circuit in Figure Q1-B(a). Show
all your calculations.
R1
vin (V)
2 k +
+ R2
+25 D1
Si 5 k vOut
vin
0 t (s)
-25 - D2
Si -

(7 marks)
Figure Q1-B(a)
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During positive half of cycle, Diode D1 is forward biased, Vout = 0.7 V 1

During negative half of cycle, Diode D1 is reverse biased and D2 forward biased.
Apply KVL : -25 + 0.7 +5k(I) + 2k(I) = 0 2
I = -3.47 mA
Vout = 5k (-3.47m) 0.7 = -18.05 V 2
Vout(V)

0.7 V 2

t (ms)

- 18.05V

(b) Consider the circuit in Figure Q.1-B(a). Determine the voltage V1 and current I1,
I2 and I3. Assume that D1 and D2 are silicon diodes with VF= 0.7V.
(8 marks)
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I1 R1 V1 R2

I3
4.7 k 5 k

10V D1 D2
VZ =5V
I2

Figure Q1-B(b)
Zener diode, D1 is On as DC supply > Vz
V1= Vz = 5V 2
D2 is forward biased; VD2 = 0.7V:

I1 = (10 -5)/4.7 k = 1.06 mA 2

5 k(I3) + 0.7 = 5V
I3 = 0.86 mA 2

Using KCL : I2 = I1 I3
= 1.06 0.86 = 0.2 mA 2

(c) Input voltage for clamping circuits in Figure Q1-B(c) and Q1-B(d) is square-wave
with vin(p-p) = 10 V (vin(ave) = 0 V). Examine both clampers and determine which
one produces the output waveform in Figure Q1-B (e). Show all your works.
(10 marks)
C

+ +

vout
VDC
- -

Figure Q1-B(c)
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C

+ +

vout
VDC
- -

Figure Q1-B(d)

vout (V)

12.3

Clamper +
vin vout 7.3
circuit
-
2.3
t (s)
0

Figure Q1-B(e) 1

For both clamping circuit, diode is forward biased during negative cycle of vin.
The only difference between the two circuits is the polarity of the battery.
During negative cycle, VO = 2.3V (from Figure Q1-B(e))
For Figure Q1-B(c): 1
When capacitor is charging

VO VDC VD 1
Therefore: VDC VO VD 2.3 0.7 3V
Negative value of VDC indicates that the polarity of the battery should be reversed as
shown in Figure Q1-B(d).
Applying KVL for the circuit in Figure Q1-B(d): 2
Vin VDC VD VC 0
VC Vin VDC VD
1
5 3 0.7
7.3V
During positive cycle: VO VC Vi 7.3 5 12.3V 1
Based on the analyses done on both circuits for both +ve and ve cycles of the input, it is
determined that Figure Q1-B(d) produces the output waveform shown in Figure Q1-B(e).
1
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Q.2
(a) Create the truth table for the CMOS gate in Figure Q2-B (a). Determine
the digital representation from the truth table.
(3 marks)

VDD

(INPUT)
A

S
(OUTPUT)

Figure Q2-B(a)

A B Output
0 0 1
0 1 1
1 0 1
1 1 0
2 input NAND gate
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(b) A two input, VA and VB NAND DTL gate is shown in Figure Q2-B (b). All
diodes are assumed to conduct with a voltage drop of 0.7 V.

Figure Q2-B(b)

(i) Find the current through D1 when VA = 0.2 V and VB = 4 V. Also find the
voltage at the base of the transistor Q1. (5 marks)

(ii) If VA = VB = 4 V, find the transistor base current, IB. If VCEsat = 0.2 V,

find the value of . (6 marks)
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(c)

An inverter output of RTL (Resistor Transistor, BJT) switching circuit is

shown in Figure Q2-B(c) with component RB, RC and =250. The
waveform indicates IC is saturated at 10 mA.

Vc

10 V 10 V

0V
t

Figure Q2-B(c)

(i) Sketch the circuit and the input waveform. (5 marks)

(ii) Calculate RB and RC. (6 marks)

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