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Experiment 1
Objective of the experiment: To determine the efficiency, ripple factor and voltage
regulation for Half Wave Rectifier with and without Capacitor filter.
Components:
Circuit Diagram:
DMM 1 To CRO
D
+ -
Transformer 1N4007
0-100mA +
230V, 50Hz 1.0k DMM 2
AC Input Load R 0-20V
230/9-0-9V -
DMM 1 To CRO
D
+ -
Transformer 1N4007
0-100mA +
230V, 50Hz 1.0k DMM 2
33F
AC Input Load R 0-20V
C
230/9-0-9V -
Theory:
Procedure:
2. Switch ON the AC supply and observe the output waveform across load R = 1k.
3. From the DMM1 and DMM2 note the current IoDC and voltage VoDC respectively.
4. From the CRO note the peak value of output voltage, Vom.
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Analog Electronics Lab (10ESL37)
6. Switch ON the AC supply and note the no load voltage, VNL on DMM2, and calculate the
voltage regulation with VFL = observed value of VoDC.
7. Connect the circuit as per fig. 2 for HWR with capacitor filter, and observe waveform
across 1k load.
8. From CRO note the Vom and ripple voltage VRp p, and VoDC from DMM2, and calculate
ripple factor.
Observations:
VoDC IoDC % %R
Vom Vorms Iom
Obs. Theo. Obs. Theo.
Calculation
VoDC
Vom VRp p VRrms
Obs. Theo. Obs. Theo.
Calculation
Result:
Conclusion:
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Analog Electronics Lab (10ESL37)
Experiment 2
Objective of the experiment: To determine the efficiency, ripple factor and voltage
regulation for Bridge Rectifier with and without Capacitor filter.
Components:
Circuit Diagram:
DMM1 To CRO
+ -
0-100mA
D1 D4
+
Transformer
DMM2
1.0k 0-50V
Load R -
230/9-0-9
D3 D2
Transformer +
DMM2
1.0k 33F
0-50V
Load R C -
230/9-0-9
D3 D2
Theory:
Procedure:
1. Connect the circuit as per fig. 1 for bridge rectifier without filter.
2. Switch ON the AC supply and observe the output waveform across load R = 1k.
3. From the DMM1 and DMM2 note the current IoDC and voltage VoDC respectively.
4. From the CRO note the peak value of output voltage, Vom.
Page 3 of 10
Analog Electronics Lab (10ESL37)
5. Switch OFF the AC supply and connect 1M instead of 1k.
6. Switch ON the AC supply and note the no load voltage, VNL on DMM2, and calculate the
voltage regulation with VFL = observed value of VoDC.
7. Connect the circuit as per fig. 2 for bridge rectifier with capacitor filter, and observe
waveform across 1k load.
8. From CRO note the Vom and ripple voltage VRp p, and VoDC from DMM2, and calculate
ripple factor.
Observations:
VoDC IoDC % %R
Vom Vorms Iom
Obs. Theo. Obs. Theo.
Calculation
VoDC
Vom VRp p VRrms
Obs. Theo. Obs. Theo.
Calculation
Result:
Conclusion:
Page 4 of 10
Analog Electronics Lab (10ESL37)
Experiment 3
Clipper Circuits
Objective of the experiment: To study the working of various types of series and
parallel clipper circuits.
Components:
Circuit Diagram:
Series Clippers
D 2V, DC -2V, DC
fig. 1 Positive Clipper (a) without bias (b) with positive bias (c) with negative Bias
D 2V, DC -2V, DC
fig. 2 Negative Clipper (a) without bias (b) with positive bias (c) with negative Bias
Parallel Clippers
Load R Load R
Load R 1N4007 1N4007
D
5Vp-p, 1kHz 1N4007 5Vp-p, 1kHz 5Vp-p, 1kHz
2V, DC
-2V, DC
fig. 3 Positive Clipper (a) without bias (b) with positive bias (c) with negative Bias
Load R Load R
Load R D1 1N4007 1N4007
1N4007
5Vp-p, 1kHz 5Vp-p, 1kHz 5Vp-p, 1kHz
2V, DC
-2V, DC
fig. 4 Negative Clipper (a) without bias (b) with positive bias (c) with negative Bias
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Analog Electronics Lab (10ESL37)
Theory:
Procedure:
1. Connect the circuit as per fig. 1(a) for Series Positive Clipper without bias.
3. Note the output waveform and the transfer characteristics across 1k from the CRO.
4. Connect 2V DC supply as shown in fig. 1(b) for series positive clipper with positive bias,
and repeat steps 2 and 3.
5. Connect 2V DC supply as shown in fig. 1(c) for series positive clipper with negative bias,
and repeat steps 2 and 3.
6. Repeat above procedure for Series Negative Clipper circuits shown in fig. 2.
7. Connect the circuit as per fig. 3(a) for Parallel Positive Clipper without bias.
9. Note the output waveform and the transfer characteristics across DIODE from the CRO.
10. Repeat above procedure for Parallel Positive clippers with bias, in fig. 3 and Parallel
Negative Clippers shown in fig. 4.
Result:
Conclusion:
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Analog Electronics Lab (10ESL37)
Experiment 4
Clamper Circuits
Objective of the experiment: To design clamper circuits for the given specifications,
and observe the variations in the clamping levels by changing the RC time constant and
also DC reference voltage.
Components:
Circuit Diagram:
Design: -
For appropriate working of the clamper circuit the values of R and C must to be
chosen such that the time constant RC is much greater than the period of the input
signal.
Therefore, RC >> T
Assume T = 1 ms
To satisfy the requirement for clamping R is chosen as 100 K~ and C as 1F
i.e. RC= 100ms >>1 ms
Positive clamper
1F
D
1F 100k
1kHz 100k 1kHz Vdc
D 5Vp-p R
5Vp-p R 1V
(a) (b)
fig. 1 Positive Clamper (a) without bias (b) with positive bias
Negative clamper
1F
D
1F 100k
1kHz 100k 1kHz
D 5Vp-p R
5Vp-p R -1 V
Vdc
(a) (b)
fig. 2 Negative Clamper (a) without bias (b) with negative Bias
Page 7 of 10
Analog Electronics Lab (10ESL37)
Theory:
Procedure:
1. Connect the circuit as per fig. 1(a) for Series Positive Clamper without bias.
2. Set the input signal from signal generator to 5Vp p, 1 kHz AC signal.
3. Note the output waveform and the transfer characteristics across 100k from the CRO.
4. Connect the circuit for positive clamper with positive bias as shown in fig 1(b) and repeat
steps2 and 3
5. Repeat above procedure for negative clamper shown in fig 2 (a) and (b).
Result:
Conclusion:
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Analog Electronics Lab (10ESL37)
Experiment 5
R C Coupled Amplifier
Objective of the experiment: To design clamper circuits for the given specifications,
and observe the variations in the clamping levels by changing the RC time constant and
also DC reference voltage.
Components:
Circuit Diagram:
5V
+Vcc
Rb1 Rc
To CRO
Co
Ci
SL100
Vi
1Vp-p Rb2 Re
5V
+Vcc
Rb1 Rc
To CRO
Co
Ci
SL100
Vi
1Vp-p Rb2
Re Ce
Theory:
Procedure:
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Analog Electronics Lab (10ESL37)
6. Connect the circuit as per fig. 1(a) for Series Positive Clamper without bias.
7. Set the input signal from signal generator to 5Vp p, 1 kHz AC signal.
8. Note the output waveform and the transfer characteristics across 100k from the CRO.
9. Connect the circuit for positive clamper with positive bias as shown in fig 1(b) and repeat
steps2 and 3
10. Repeat above procedure for negative clamper shown in fig 2 (a) and (b).
Result:
Conclusion:
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